118 lines
3.9 KiB
Python
118 lines
3.9 KiB
Python
import unittest
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from h8536.emulator import (
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HEARTBEAT_FRAME,
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SCI1_SCR,
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SCI1_SSR,
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SCI1_TDR,
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SCI_SCR_TE,
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SCI_SSR_FER,
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SCI_SSR_ORER,
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SCI_SSR_PER,
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SCI_SSR_RDRF,
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SCI_SSR_TDRE,
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SCI1,
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UartTiming,
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)
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class SciTimingTest(unittest.TestCase):
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def test_ssr_write_one_does_not_set_hardware_flags(self):
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sci = SCI1()
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sci.ssr = 0x00
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sci.write(SCI1_SSR, SCI_SSR_TDRE | SCI_SSR_RDRF | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER)
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self.assertEqual(sci.read(SCI1_SSR) & 0xF8, 0x00)
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def test_ssr_write_zero_clears_selected_writable_flags(self):
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sci = SCI1()
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sci.ssr = SCI_SSR_TDRE | SCI_SSR_RDRF | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER | 0x07
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sci.write(SCI1_SSR, sci.ssr & ~SCI_SSR_RDRF)
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self.assertEqual(sci.read(SCI1_SSR) & SCI_SSR_RDRF, 0x00)
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self.assertEqual(
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sci.read(SCI1_SSR) & (SCI_SSR_TDRE | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER),
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SCI_SSR_TDRE | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER,
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)
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def test_tdr_write_then_ssr_clear_delays_tdre_until_ticks(self):
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sci = SCI1(tx_ready_ticks=2)
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sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
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self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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sci.write(SCI1_TDR, 0x42)
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sci.write(SCI1_SSR, sci.read(SCI1_SSR) & ~SCI_SSR_TDRE)
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self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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sci.tick()
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self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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sci.tick()
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self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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def test_transmit_capture_requires_te_enabled(self):
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sci = SCI1()
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sci.write(SCI1_TDR, 0x33)
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self.assertEqual(sci.tx_bytes, [])
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self.assertFalse(sci.tx_events[-1].emitted)
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sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
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for byte in HEARTBEAT_FRAME:
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sci.write(SCI1_TDR, byte)
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self.assertEqual(bytes(sci.tx_bytes), HEARTBEAT_FRAME)
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self.assertEqual(sci.tx_frames, [HEARTBEAT_FRAME])
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self.assertTrue(sci.saw_heartbeat())
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def test_inject_rx_sets_overrun_if_rdrf_is_still_full(self):
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sci = SCI1()
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sci.inject_rx(0x11)
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sci.inject_rx(0x22)
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self.assertEqual(sci.read(SCI1_SSR) & (SCI_SSR_RDRF | SCI_SSR_ORER), SCI_SSR_RDRF | SCI_SSR_ORER)
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self.assertEqual(sci.rdr, 0x11)
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def test_uart_8n1_38400_byte_timing(self):
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timing = UartTiming(baud=38_400)
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self.assertEqual(timing.bits_per_character, 10)
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self.assertAlmostEqual(timing.micros_per_character(), 260.416666, places=3)
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self.assertEqual(timing.cycles_per_character(10_000_000), 2604)
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def test_uart_8e1_38400_byte_timing_matches_bench_link(self):
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timing = UartTiming.from_format("8E1", baud=38_400)
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self.assertEqual(timing.bits_per_character, 11)
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self.assertAlmostEqual(timing.micros_per_character(), 286.458333, places=3)
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self.assertEqual(timing.cycles_per_character(10_000_000), 2865)
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self.assertEqual(timing.summary(10_000_000).split()[0], "uart_8E1")
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def test_uart_timing_can_be_derived_from_sci_smr(self):
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timing = UartTiming.from_sci_smr(0x24, baud=38_400)
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self.assertEqual((timing.data_bits, timing.parity, timing.stop_bits), (8, "E", 1))
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def test_tdr_write_can_use_uart_character_time_for_tdre(self):
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sci = SCI1()
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sci.configure_tx_timing(UartTiming.from_format("8E1", baud=38_400), clock_hz=10_000_000)
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sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
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sci.write(SCI1_TDR, 0x42)
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sci.write(SCI1_SSR, sci.read(SCI1_SSR) & ~SCI_SSR_TDRE)
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self.assertTrue(sci.tx_busy())
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self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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sci.tick(2864)
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self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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sci.tick(1)
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self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
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self.assertFalse(sci.tx_busy())
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if __name__ == "__main__":
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unittest.main()
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