269 lines
8.8 KiB
Python
269 lines
8.8 KiB
Python
from __future__ import annotations
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from .model import EA
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from .tables import IO_BITFIELDS, IO_DTE_BITS, IO_PRIORITY_FIELDS, IO_REGISTERS
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def h8(value: int) -> str:
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return f"H'{value & 0xFF:02X}"
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def h16(value: int) -> str:
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return f"H'{value & 0xFFFF:04X}"
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def h24(value: int) -> str:
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return f"H'{value & 0xFFFFFF:06X}"
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def s8(value: int) -> int:
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value &= 0xFF
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return value - 0x100 if value & 0x80 else value
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def s16(value: int) -> int:
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value &= 0xFFFF
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return value - 0x10000 if value & 0x8000 else value
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def parse_int(text: str) -> int:
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return int(text.replace("H'", "0x").replace("$", "0x"), 0)
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def reg_list(mask: int) -> str:
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regs = [f"R{idx}" for idx in range(8) if mask & (1 << idx)]
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return "{" + ",".join(regs) + "}" if regs else "{}"
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def disp_text(value: int) -> str:
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if value < 0:
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return f"-{h16(-value) if value < -0xFF else h8(-value)}"
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return h16(value) if value > 0xFF else h8(value)
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def short_abs(low: int) -> str:
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return f"@BR:{h8(low)}"
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def control_reg(ccc: int, size: str) -> str:
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if size == "W":
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return "SR" if ccc == 0 else f"CR{ccc}?"
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return {
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0: "CCR",
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1: "BR",
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2: "EP",
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3: "DP",
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4: "TP",
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}.get(ccc, f"CR{ccc}?")
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def label_for(address: int) -> str:
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return f"loc_{address:04X}"
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def label_or_h(address: int, labels: dict[int, str]) -> str:
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return labels.get(address, label_for(address))
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def _bitfield_name(address: int, bit: int) -> str | None:
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priority_name = _priority_bit_name(address, bit)
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if priority_name:
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return priority_name
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dte_name = _dte_bit_name(address, bit)
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if dte_name:
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return dte_name
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return IO_BITFIELDS.get(address, {}).get(bit)
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def _bitfield_values(address: int, value: int) -> str:
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fields = IO_BITFIELDS.get(address)
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if not fields:
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return ""
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parts = [f"{name}={(value >> bit) & 1}" for bit, name in sorted(fields.items(), reverse=True)]
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return " ".join(parts)
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def _adcsr_semantics(value: int) -> str:
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channels_single = ["AN0", "AN1", "AN2", "AN3", "AN4", "AN5", "AN6", "AN7"]
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channels_scan = ["AN0", "AN0-AN1", "AN0-AN2", "AN0-AN3", "AN4", "AN4-AN5", "AN4-AN6", "AN4-AN7"]
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scan = bool(value & 0x10)
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channels = channels_scan[value & 0x07] if scan else channels_single[value & 0x07]
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mode = "scan" if scan else "single"
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state = "start" if value & 0x20 else "halt"
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interrupt = "ADI enabled" if value & 0x40 else "ADI disabled"
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conversion = "138-state max" if value & 0x08 else "274-state max"
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return f"A/D {state}, {mode} {channels}, {conversion}, {interrupt}"
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def _priority_bit_name(address: int, bit: int) -> str | None:
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for shift, source in IO_PRIORITY_FIELDS.get(address, ()):
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if shift <= bit <= shift + 2:
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return f"{source} priority bit {bit - shift}"
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if address in IO_PRIORITY_FIELDS and bit in (7, 3):
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return "reserved priority bit"
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return None
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def _dte_bit_name(address: int, bit: int) -> str | None:
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fields = IO_DTE_BITS.get(address)
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if fields is None:
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return None
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source = fields.get(bit)
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return f"{source} DTC enable" if source else "reserved DTE bit"
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def _ipr_semantics(address: int, value: int) -> str:
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parts: list[str] = []
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for shift, source in IO_PRIORITY_FIELDS[address]:
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priority = (value >> shift) & 0x07
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parts.append(f"{source} priority={priority}")
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reserved = _set_bit_numbers(value, 0x88)
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if reserved:
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parts.append(f"reserved bits {reserved} should be 0")
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return "; ".join(parts)
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def _dte_semantics(address: int, value: int) -> str:
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fields = IO_DTE_BITS[address]
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parts = [
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f"{source} {'DTC enabled' if value & (1 << bit) else 'CPU interrupt'}"
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for bit, source in sorted(fields.items(), reverse=True)
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]
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assigned_mask = 0
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for bit in fields:
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assigned_mask |= 1 << bit
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reserved = _set_bit_numbers(value, (~assigned_mask) & 0xFF)
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if reserved:
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parts.append(f"reserved bits {reserved} should be 0")
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return "; ".join(parts)
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def _set_bit_numbers(value: int, mask: int) -> str:
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bits = [str(bit) for bit in range(7, -1, -1) if value & mask & (1 << bit)]
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return ", ".join(bits)
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def _sci_smr_semantics(value: int) -> str:
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mode = "sync" if value & 0x80 else "async"
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char_len = "7-bit" if value & 0x40 else "8-bit"
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parity = "odd parity" if value & 0x10 else "even parity"
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parity = parity if value & 0x20 else "no parity"
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stop = "2 stop" if value & 0x08 else "1 stop"
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clock = ["phi", "phi/4", "phi/16", "phi/64"][value & 0x03]
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return f"SCI {mode}, {char_len}, {parity}, {stop}, clock {clock}"
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def _sci_scr_semantics(value: int) -> str:
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enabled: list[str] = []
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if value & 0x20:
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enabled.append("TX")
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if value & 0x10:
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enabled.append("RX")
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if value & 0x80:
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enabled.append("TXI")
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if value & 0x40:
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enabled.append("RXI/ERI")
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clock = "external clock" if value & 0x02 else "internal clock"
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if value & 0x01:
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clock += ", SCK output"
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return f"SCI enables {','.join(enabled) if enabled else 'none'}, {clock}"
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def _wcr_semantics(value: int) -> str:
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modes = ["programmable wait", "no wait states", "pin wait", "pin auto-wait"]
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counts = ["0 waits", "1 wait", "2 waits", "3 waits"]
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return f"{modes[(value >> 2) & 0x03]}, {counts[value & 0x03]}"
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def _wdt_semantics(value: int) -> str:
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if value <= 0xFF:
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data = value
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return _wdt_tcsr_data_semantics(data)
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password = (value >> 8) & 0xFF
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data = value & 0xFF
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if password == 0xA5:
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return f"TCSR password H'A5, {_wdt_tcsr_data_semantics(data)}"
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if password == 0x5A:
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return f"TCNT password H'5A, counter write {h8(data)}"
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return f"watchdog password {h8(password)}, data {h8(data)}"
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def _wdt_tcsr_data_semantics(value: int) -> str:
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clock = ["phi/2", "phi/32", "phi/64", "phi/128", "phi/256", "phi/512", "phi/2048", "phi/4096"][value & 0x07]
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mode = "watchdog NMI" if value & 0x40 else "interval IRQ0"
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state = "enabled" if value & 0x20 else "disabled"
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return f"WDT {state}, {mode}, clock {clock}"
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def _rstcsr_semantics(value: int) -> str:
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if value <= 0xFF:
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data = value
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password = None
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else:
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password = (value >> 8) & 0xFF
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data = value & 0xFF
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if password == 0xA5:
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return f"RSTCSR password H'A5, clear WRST with data {h8(data)}"
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if password == 0x5A:
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rstoe = "RES output enabled" if data & 0x40 else "RES output disabled"
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return f"RSTCSR password H'5A, {rstoe}"
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return "RSTCSR status/control"
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def _semantic_values(address: int, value: int) -> str:
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if address in IO_PRIORITY_FIELDS:
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return _ipr_semantics(address, value)
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if address in IO_DTE_BITS:
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return _dte_semantics(address, value)
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if address == 0xFEE8:
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return _adcsr_semantics(value)
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if address in (0xFED8, 0xFEF0):
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return _sci_smr_semantics(value)
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if address in (0xFEDA, 0xFEF2):
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return _sci_scr_semantics(value)
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if address == 0xFEFC:
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brle = "bus release pins enabled" if value & 0x08 else "P12/P13 are I/O"
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irq0 = "IRQ0 enabled" if value & 0x20 else "IRQ0 disabled"
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irq1 = "IRQ1 enabled" if value & 0x40 else "IRQ1 disabled"
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return f"{brle}, {irq0}, {irq1}"
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if address == 0xFEFD:
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enabled = [name for bit, name in ((0, "SCI2 pins"), (1, "P9 PWM"), (2, "P6 PWM"), (3, "IRQ2"), (4, "IRQ3"), (5, "IRQ4"), (6, "IRQ5")) if value & (1 << bit)]
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return "enabled " + ", ".join(enabled) if enabled else "alternate pin functions disabled"
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if address == 0xFEEC:
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return _wdt_semantics(value)
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if address == 0xFF10:
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return _wcr_semantics(value)
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if address == 0xFF11:
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return "on-chip RAM enabled" if value & 0x80 else "on-chip RAM disabled"
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if address == 0xFF12:
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return f"mode select bits MDS={value & 0x07}"
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if address == 0xFF14:
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return _rstcsr_semantics(value)
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return ""
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def write_comment(ea: EA, value: int | None) -> str:
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if ea.address is None or ea.address not in IO_REGISTERS:
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return ""
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name = IO_REGISTERS[ea.address]
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if value is None:
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return name
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text = f"{name} = {h16(value) if value > 0xFF else h8(value)}"
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fields = _bitfield_values(ea.address, value)
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semantic = _semantic_values(ea.address, value)
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details = "; ".join(part for part in (fields, semantic) if part)
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return f"{text} ({details})" if details else text
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def bit_comment(mnemonic: str, ea: EA, bit: int) -> str:
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if ea.address is None or ea.address not in IO_REGISTERS:
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return ""
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action = {"BSET": "set", "BCLR": "clear", "BNOT": "toggle", "BTST": "test"}.get(
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mnemonic.split(".")[0],
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"bit",
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)
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bit_name = _bitfield_name(ea.address, bit)
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if bit_name:
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return f"{action} {bit_name} (bit {bit}) of {IO_REGISTERS[ea.address]}"
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return f"{action} bit {bit} of {IO_REGISTERS[ea.address]}"
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