aiden/h8-536-decoder
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80819448cfe371cafc8bd4a4298194bb48ebe470
h8-536-decoder/build/rom_decompiled.json
Aiden 80819448cf DTC and SCI improvements
2026-05-25 14:22:32 +10:00

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},
{
"start": 6089,
"end": 6094,
"label": "loc_17C9",
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"unknown_cycles": 0,
"terminator": "BHI loc_17F2",
"targets": [
6130
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},
{
"start": 6096,
"end": 6100,
"label": "loc_17D0",
"instruction_count": 2,
"cycles_min": 10,
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"unknown_cycles": 0,
"terminator": "BEQ loc_17F2",
"targets": [
6130
]
},
{
"start": 6102,
"end": 6117,
"label": "loc_17D6",
"instruction_count": 5,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "BEQ loc_17EF",
"targets": [
6127
]
},
{
"start": 6119,
"end": 6123,
"label": "loc_17E7",
"instruction_count": 2,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "BEQ loc_17EF",
"targets": [
6127
]
},
{
"start": 6125,
"end": 6125,
"label": "loc_17ED",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6127,
"end": 6127,
"label": "loc_17EF",
"instruction_count": 1,
"cycles_min": 14,
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"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6130,
"end": 6138,
"label": "loc_17F2",
"instruction_count": 3,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6139,
"end": 6144,
"label": "loc_17FB",
"instruction_count": 2,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "BHI loc_1824",
"targets": [
6180
]
},
{
"start": 6146,
"end": 6150,
"label": "loc_1802",
"instruction_count": 2,
"cycles_min": 10,
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"unknown_cycles": 0,
"terminator": "BEQ loc_1824",
"targets": [
6180
]
},
{
"start": 6152,
"end": 6167,
"label": "loc_1808",
"instruction_count": 5,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "BEQ loc_1821",
"targets": [
6177
]
},
{
"start": 6169,
"end": 6173,
"label": "loc_1819",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1821",
"targets": [
6177
]
},
{
"start": 6175,
"end": 6175,
"label": "loc_181F",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6177,
"end": 6177,
"label": "loc_1821",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6180,
"end": 6188,
"label": "loc_1824",
"instruction_count": 3,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6189,
"end": 6193,
"label": "loc_182D",
"instruction_count": 2,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "BNE loc_1865",
"targets": [
6245
]
},
{
"start": 6195,
"end": 6200,
"label": "loc_1833",
"instruction_count": 2,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "BHI loc_185C",
"targets": [
6236
]
},
{
"start": 6202,
"end": 6206,
"label": "loc_183A",
"instruction_count": 2,
"cycles_min": 10,
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"unknown_cycles": 0,
"terminator": "BEQ loc_185C",
"targets": [
6236
]
},
{
"start": 6208,
"end": 6223,
"label": "loc_1840",
"instruction_count": 5,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "BEQ loc_1859",
"targets": [
6233
]
},
{
"start": 6225,
"end": 6229,
"label": "loc_1851",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1859",
"targets": [
6233
]
},
{
"start": 6231,
"end": 6231,
"label": "loc_1857",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6233,
"end": 6233,
"label": "loc_1859",
"instruction_count": 1,
"cycles_min": 14,
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"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6236,
"end": 6244,
"label": "loc_185C",
"instruction_count": 3,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6245,
"end": 6250,
"label": "loc_1865",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BHI loc_1888",
"targets": [
6280
]
},
{
"start": 6252,
"end": 6267,
"label": "loc_186C",
"instruction_count": 5,
"cycles_min": 26,
"cycles_max": 31,
"unknown_cycles": 0,
"terminator": "BEQ loc_1885",
"targets": [
6277
]
},
{
"start": 6269,
"end": 6273,
"label": "loc_187D",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1885",
"targets": [
6277
]
},
{
"start": 6275,
"end": 6275,
"label": "loc_1883",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6277,
"end": 6277,
"label": "loc_1885",
"instruction_count": 1,
"cycles_min": 14,
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"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6280,
"end": 6288,
"label": "loc_1888",
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6289,
"end": 6293,
"label": "loc_1891",
"instruction_count": 2,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "BNE loc_18BB",
"targets": [
6331
]
},
{
"start": 6295,
"end": 6300,
"label": "loc_1897",
"instruction_count": 2,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "BHI loc_18B2",
"targets": [
6322
]
},
{
"start": 6302,
"end": 6306,
"label": "loc_189E",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_18B2",
"targets": [
6322
]
},
{
"start": 6308,
"end": 6319,
"label": "loc_18A4",
"instruction_count": 4,
"cycles_min": 31,
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"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6322,
"end": 6330,
"label": "loc_18B2",
"instruction_count": 3,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6331,
"end": 6336,
"label": "loc_18BB",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BHI loc_18DE",
"targets": [
6366
]
},
{
"start": 6338,
"end": 6353,
"label": "loc_18C2",
"instruction_count": 5,
"cycles_min": 26,
"cycles_max": 31,
"unknown_cycles": 0,
"terminator": "BEQ loc_18DB",
"targets": [
6363
]
},
{
"start": 6355,
"end": 6359,
"label": "loc_18D3",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_18DB",
"targets": [
6363
]
},
{
"start": 6361,
"end": 6361,
"label": "loc_18D9",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6363,
"end": 6363,
"label": "loc_18DB",
"instruction_count": 1,
"cycles_min": 14,
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"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6366,
"end": 6374,
"label": "loc_18DE",
"instruction_count": 3,
"cycles_min": 26,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6375,
"end": 6379,
"label": "loc_18E7",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_191F",
"targets": [
6431
]
},
{
"start": 6381,
"end": 6386,
"label": "loc_18ED",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BHI loc_1916",
"targets": [
6422
]
},
{
"start": 6388,
"end": 6392,
"label": "loc_18F4",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1916",
"targets": [
6422
]
},
{
"start": 6394,
"end": 6409,
"label": "loc_18FA",
"instruction_count": 5,
"cycles_min": 26,
"cycles_max": 31,
"unknown_cycles": 0,
"terminator": "BEQ loc_1913",
"targets": [
6419
]
},
{
"start": 6411,
"end": 6415,
"label": "loc_190B",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1913",
"targets": [
6419
]
},
{
"start": 6417,
"end": 6417,
"label": "loc_1911",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6419,
"end": 6419,
"label": "loc_1913",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6422,
"end": 6430,
"label": "loc_1916",
"instruction_count": 3,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6431,
"end": 6436,
"label": "loc_191F",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BHI loc_1941",
"targets": [
6465
]
},
{
"start": 6438,
"end": 6453,
"label": "loc_1926",
"instruction_count": 5,
"cycles_min": 26,
"cycles_max": 31,
"unknown_cycles": 0,
"terminator": "BEQ loc_193F",
"targets": [
6463
]
},
{
"start": 6455,
"end": 6459,
"label": "loc_1937",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_193F",
"targets": [
6463
]
},
{
"start": 6461,
"end": 6461,
"label": "loc_193D",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6463,
"end": 6463,
"label": "loc_193F",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_19A2",
"targets": [
6562
]
},
{
"start": 6465,
"end": 6473,
"label": "loc_1941",
"instruction_count": 3,
"cycles_min": 25,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6474,
"end": 6479,
"label": "loc_194A",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 15,
"unknown_cycles": 0,
"terminator": "BHI loc_1970",
"targets": [
6512
]
},
{
"start": 6481,
"end": 6493,
"label": "loc_1951",
"instruction_count": 4,
"cycles_min": 21,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "BNE loc_195F",
"targets": [
6495
]
},
{
"start": 6495,
"end": 6502,
"label": "loc_195F",
"instruction_count": 3,
"cycles_min": 13,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BEQ loc_196A",
"targets": [
6506
]
},
{
"start": 6504,
"end": 6504,
"label": "loc_1968",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6506,
"end": 6508,
"label": "loc_196A",
"instruction_count": 2,
"cycles_min": 22,
"cycles_max": 22,
"unknown_cycles": 0,
"terminator": "BSET.B #7, @H'F76D",
"targets": []
},
{
"start": 6512,
"end": 6520,
"label": "loc_1970",
"instruction_count": 3,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6521,
"end": 6526,
"label": "loc_1979",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BHI loc_1999",
"targets": [
6553
]
},
{
"start": 6528,
"end": 6547,
"label": "loc_1980",
"instruction_count": 6,
"cycles_min": 52,
"cycles_max": 57,
"unknown_cycles": 0,
"terminator": "BEQ loc_1997",
"targets": [
6551
]
},
{
"start": 6549,
"end": 6549,
"label": "loc_1995",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 6551,
"end": 6551,
"label": "loc_1997",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_19DB",
"targets": [
6619
]
},
{
"start": 6553,
"end": 6561,
"label": "loc_1999",
"instruction_count": 3,
"cycles_min": 25,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6562,
"end": 6577,
"label": "loc_19A2",
"instruction_count": 6,
"cycles_min": 23,
"cycles_max": 28,
"unknown_cycles": 0,
"terminator": "BHI loc_19B6",
"targets": [
6582
]
},
{
"start": 6579,
"end": 6579,
"label": "loc_19B3",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'FE00, R0",
"targets": []
},
{
"start": 6582,
"end": 6589,
"label": "loc_19B6",
"instruction_count": 4,
"cycles_min": 13,
"cycles_max": 18,
"unknown_cycles": 0,
"terminator": "BLS loc_19D3",
"targets": [
6611
]
},
{
"start": 6591,
"end": 6594,
"label": "loc_19BF",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BCC loc_19D3",
"targets": [
6611
]
},
{
"start": 6596,
"end": 6599,
"label": "loc_19C4",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BCC loc_19CE",
"targets": [
6606
]
},
{
"start": 6601,
"end": 6604,
"label": "loc_19C9",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_19D7",
"targets": [
6615
]
},
{
"start": 6606,
"end": 6609,
"label": "loc_19CE",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_19D7",
"targets": [
6615
]
},
{
"start": 6611,
"end": 6611,
"label": "loc_19D3",
"instruction_count": 1,
"cycles_min": 6,
"cycles_max": 6,
"unknown_cycles": 0,
"terminator": "MOV:G.B @(H'1A25,R4), R4",
"targets": []
},
{
"start": 6615,
"end": 6617,
"label": "loc_19D7",
"instruction_count": 2,
"cycles_min": 33,
"cycles_max": 33,
"unknown_cycles": 0,
"terminator": "BRA loc_19E3",
"targets": [
6627
]
},
{
"start": 6619,
"end": 6625,
"label": "loc_19DB",
"instruction_count": 3,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "SHLL.W R3",
"targets": []
},
{
"start": 6627,
"end": 6635,
"label": "loc_19E3",
"instruction_count": 4,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BCS loc_19F9",
"targets": [
6649
]
},
{
"start": 6637,
"end": 6642,
"label": "loc_19ED",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BLS loc_1A03",
"targets": [
6659
]
},
{
"start": 6644,
"end": 6647,
"label": "loc_19F4",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_1A03",
"targets": [
6659
]
},
{
"start": 6649,
"end": 6654,
"label": "loc_19F9",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BLS loc_1A03",
"targets": [
6659
]
},
{
"start": 6656,
"end": 6656,
"label": "loc_1A00",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'FFFF, R1",
"targets": []
},
{
"start": 6659,
"end": 6663,
"label": "loc_1A03",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A14",
"targets": [
6676
]
},
{
"start": 6665,
"end": 6673,
"label": "loc_1A09",
"instruction_count": 4,
"cycles_min": 25,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "BSR loc_3E54",
"targets": [
15956
]
},
{
"start": 6676,
"end": 6676,
"label": "loc_1A14",
"instruction_count": 1,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6709,
"end": 6721,
"label": "loc_1A35",
"instruction_count": 5,
"cycles_min": 19,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A7D",
"targets": [
6781
]
},
{
"start": 6723,
"end": 6723,
"label": "loc_1A43",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_1A8D",
"targets": [
6797
]
},
{
"start": 6725,
"end": 6727,
"label": "loc_1A45",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BNE loc_1A59",
"targets": [
6745
]
},
{
"start": 6729,
"end": 6729,
"label": "loc_1A49",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, R2",
"targets": []
},
{
"start": 6731,
"end": 6737,
"label": "loc_1A4B",
"instruction_count": 3,
"cycles_min": 12,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A69",
"targets": [
6761
]
},
{
"start": 6739,
"end": 6741,
"label": "loc_1A53",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A4B",
"targets": [
6731
]
},
{
"start": 6743,
"end": 6743,
"label": "loc_1A57",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_1A6B",
"targets": [
6763
]
},
{
"start": 6745,
"end": 6745,
"label": "loc_1A59",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, R2",
"targets": []
},
{
"start": 6747,
"end": 6753,
"label": "loc_1A5B",
"instruction_count": 3,
"cycles_min": 12,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A69",
"targets": [
6761
]
},
{
"start": 6755,
"end": 6757,
"label": "loc_1A63",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A5B",
"targets": [
6747
]
},
{
"start": 6759,
"end": 6759,
"label": "loc_1A67",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_1A6B",
"targets": [
6763
]
},
{
"start": 6761,
"end": 6761,
"label": "loc_1A69",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:G.W R2, R0",
"targets": []
},
{
"start": 6763,
"end": 6767,
"label": "loc_1A6B",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_1A7C",
"targets": [
6780
]
},
{
"start": 6769,
"end": 6777,
"label": "loc_1A71",
"instruction_count": 4,
"cycles_min": 25,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "BSR loc_3E54",
"targets": [
15956
]
},
{
"start": 6780,
"end": 6780,
"label": "loc_1A7C",
"instruction_count": 1,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6781,
"end": 6781,
"label": "loc_1A7D",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #15, R0",
"targets": []
},
{
"start": 6783,
"end": 6789,
"label": "loc_1A7F",
"instruction_count": 3,
"cycles_min": 12,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BNE loc_1A8B",
"targets": [
6795
]
},
{
"start": 6791,
"end": 6793,
"label": "loc_1A87",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_1A7F",
"targets": [
6783
]
},
{
"start": 6795,
"end": 6795,
"label": "loc_1A8B",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_1A45",
"targets": [
6725
]
},
{
"start": 6797,
"end": 6797,
"label": "loc_1A8D",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'000F, R1",
"targets": []
},
{
"start": 6800,
"end": 6802,
"label": "loc_1A90",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BNE loc_1A97",
"targets": [
6807
]
},
{
"start": 6804,
"end": 6804,
"label": "loc_1A94",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "SCB/F R1, loc_1A90",
"targets": [
6800
]
},
{
"start": 6807,
"end": 6811,
"label": "loc_1A97",
"instruction_count": 3,
"cycles_min": 19,
"cycles_max": 19,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6812,
"end": 6814,
"label": "loc_1A9C",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_1AD2",
"targets": [
6866
]
},
{
"start": 6816,
"end": 6829,
"label": "loc_1AA0",
"instruction_count": 6,
"cycles_min": 21,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "BNE loc_1ABC",
"targets": [
6844
]
},
{
"start": 6831,
"end": 6840,
"label": "loc_1AAF",
"instruction_count": 4,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_1AAF",
"targets": [
6831
]
},
{
"start": 6842,
"end": 6842,
"label": "loc_1ABA",
"instruction_count": 1,
"cycles_min": 7,
"cycles_max": 7,
"unknown_cycles": 0,
"terminator": "BRA loc_1AC7",
"targets": [
6855
]
},
{
"start": 6844,
"end": 6853,
"label": "loc_1ABC",
"instruction_count": 4,
"cycles_min": 16,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_1ABC",
"targets": [
6844
]
},
{
"start": 6855,
"end": 6864,
"label": "loc_1AC7",
"instruction_count": 4,
"cycles_min": 19,
"cycles_max": 19,
"unknown_cycles": 0,
"terminator": "BRA loc_1AE0",
"targets": [
6880
]
},
{
"start": 6866,
"end": 6868,
"label": "loc_1AD2",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BNE loc_1ADC",
"targets": [
6876
]
},
{
"start": 6870,
"end": 6874,
"label": "loc_1AD6",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_1AE0",
"targets": [
6880
]
},
{
"start": 6876,
"end": 6876,
"label": "loc_1ADC",
"instruction_count": 1,
"cycles_min": 9,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "ADD:Q.B #-1, @H'F733",
"targets": []
},
{
"start": 6880,
"end": 6883,
"label": "loc_1AE0",
"instruction_count": 2,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6884,
"end": 6896,
"label": "loc_1AE4",
"instruction_count": 5,
"cycles_min": 23,
"cycles_max": 27,
"unknown_cycles": 0,
"terminator": "BNE loc_1AFC",
"targets": [
6908
]
},
{
"start": 6898,
"end": 6902,
"label": "loc_1AF2",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BLS loc_1B03",
"targets": [
6915
]
},
{
"start": 6904,
"end": 6906,
"label": "loc_1AF8",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BRA loc_1B03",
"targets": [
6915
]
},
{
"start": 6908,
"end": 6911,
"label": "loc_1AFC",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BCC loc_1B03",
"targets": [
6915
]
},
{
"start": 6913,
"end": 6913,
"label": "loc_1B01",
"instruction_count": 1,
"cycles_min": 2,
"cycles_max": 2,
"unknown_cycles": 0,
"terminator": "MOV:E.B #H'2E, R1",
"targets": []
},
{
"start": 6915,
"end": 6922,
"label": "loc_1B03",
"instruction_count": 3,
"cycles_min": 32,
"cycles_max": 32,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6923,
"end": 6929,
"label": "loc_1B0B",
"instruction_count": 3,
"cycles_min": 12,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BNE loc_1B1D",
"targets": [
6941
]
},
{
"start": 6931,
"end": 6935,
"label": "loc_1B13",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BLS loc_1B25",
"targets": [
6949
]
},
{
"start": 6937,
"end": 6939,
"label": "loc_1B19",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_1B25",
"targets": [
6949
]
},
{
"start": 6941,
"end": 6945,
"label": "loc_1B1D",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BCC loc_1B25",
"targets": [
6949
]
},
{
"start": 6947,
"end": 6947,
"label": "loc_1B23",
"instruction_count": 1,
"cycles_min": 2,
"cycles_max": 2,
"unknown_cycles": 0,
"terminator": "MOV:E.B #H'01, R0",
"targets": []
},
{
"start": 6949,
"end": 6956,
"label": "loc_1B25",
"instruction_count": 3,
"cycles_min": 32,
"cycles_max": 32,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6957,
"end": 6979,
"label": "loc_1B2D",
"instruction_count": 7,
"cycles_min": 53,
"cycles_max": 53,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 6980,
"end": 7002,
"label": "loc_1B44",
"instruction_count": 7,
"cycles_min": 57,
"cycles_max": 57,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7003,
"end": 7025,
"label": "loc_1B5B",
"instruction_count": 7,
"cycles_min": 53,
"cycles_max": 53,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7026,
"end": 7048,
"label": "loc_1B72",
"instruction_count": 7,
"cycles_min": 57,
"cycles_max": 57,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7049,
"end": 7071,
"label": "loc_1B89",
"instruction_count": 7,
"cycles_min": 53,
"cycles_max": 53,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7072,
"end": 7093,
"label": "loc_1BA0",
"instruction_count": 7,
"cycles_min": 56,
"cycles_max": 56,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7094,
"end": 7115,
"label": "loc_1BB6",
"instruction_count": 7,
"cycles_min": 56,
"cycles_max": 56,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7116,
"end": 7137,
"label": "loc_1BCC",
"instruction_count": 7,
"cycles_min": 56,
"cycles_max": 56,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7138,
"end": 7159,
"label": "loc_1BE2",
"instruction_count": 7,
"cycles_min": 56,
"cycles_max": 56,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7160,
"end": 7181,
"label": "loc_1BF8",
"instruction_count": 7,
"cycles_min": 56,
"cycles_max": 56,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 7182,
"end": 7184,
"label": "loc_1C0E",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BCC loc_1C1C",
"targets": [
7196
]
},
{
"start": 7186,
"end": 7194,
"label": "loc_1C12",
"instruction_count": 4,
"cycles_min": 46,
"cycles_max": 46,
"unknown_cycles": 0,
"terminator": "LDM.W @SP+, {R4,R5}",
"targets": []
},
{
"start": 7196,
"end": 7198,
"label": "loc_1C1C",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_1C24",
"targets": [
7204
]
},
{
"start": 7200,
"end": 7202,
"label": "loc_1C20",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_1C0E",
"targets": [
7182
]
},
{
"start": 7204,
"end": 7204,
"label": "loc_1C24",
"instruction_count": 1,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 8487,
"end": 8491,
"label": "loc_2127",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BNE loc_2135",
"targets": [
8501
]
},
{
"start": 8493,
"end": 8497,
"label": "loc_212D",
"instruction_count": 2,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "MOV:G.W R1, @H'F734",
"targets": []
},
{
"start": 8501,
"end": 8515,
"label": "loc_2135",
"instruction_count": 4,
"cycles_min": 44,
"cycles_max": 44,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 9808,
"end": 9812,
"label": "loc_2650",
"instruction_count": 2,
"cycles_min": 12,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BEQ loc_26BF",
"targets": [
9919
]
},
{
"start": 9815,
"end": 9827,
"label": "loc_2657",
"instruction_count": 5,
"cycles_min": 21,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "BNE loc_266D",
"targets": [
9837
]
},
{
"start": 9829,
"end": 9831,
"label": "loc_2665",
"instruction_count": 2,
"cycles_min": 7,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "BCC loc_2683",
"targets": [
9859
]
},
{
"start": 9833,
"end": 9835,
"label": "loc_2669",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_2683",
"targets": [
9859
]
},
{
"start": 9837,
"end": 9843,
"label": "loc_266D",
"instruction_count": 3,
"cycles_min": 13,
"cycles_max": 18,
"unknown_cycles": 0,
"terminator": "BNE loc_267D",
"targets": [
9853
]
},
{
"start": 9845,
"end": 9847,
"label": "loc_2675",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BCC loc_2683",
"targets": [
9859
]
},
{
"start": 9849,
"end": 9851,
"label": "loc_2679",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_2683",
"targets": [
9859
]
},
{
"start": 9853,
"end": 9855,
"label": "loc_267D",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BCC loc_2683",
"targets": [
9859
]
},
{
"start": 9857,
"end": 9857,
"label": "loc_2681",
"instruction_count": 1,
"cycles_min": 2,
"cycles_max": 2,
"unknown_cycles": 0,
"terminator": "MOV:E.B #H'16, R0",
"targets": []
},
{
"start": 9859,
"end": 9871,
"label": "loc_2683",
"instruction_count": 6,
"cycles_min": 21,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "BEQ loc_26BF",
"targets": [
9919
]
},
{
"start": 9873,
"end": 9886,
"label": "loc_2691",
"instruction_count": 5,
"cycles_min": 21,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "BEQ loc_26A8",
"targets": [
9896
]
},
{
"start": 9888,
"end": 9892,
"label": "loc_26A0",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_26A8",
"targets": [
9896
]
},
{
"start": 9894,
"end": 9894,
"label": "loc_26A6",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "BSET.W #14, R3",
"targets": []
},
{
"start": 9896,
"end": 9903,
"label": "loc_26A8",
"instruction_count": 3,
"cycles_min": 24,
"cycles_max": 29,
"unknown_cycles": 0,
"terminator": "BNE loc_26B9",
"targets": [
9913
]
},
{
"start": 9905,
"end": 9911,
"label": "loc_26B1",
"instruction_count": 2,
"cycles_min": 17,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BRA loc_26BF",
"targets": [
9919
]
},
{
"start": 9913,
"end": 9913,
"label": "loc_26B9",
"instruction_count": 1,
"cycles_min": 9,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "MOV:G.W #H'00C8, @H'F6F4",
"targets": []
},
{
"start": 9919,
"end": 9919,
"label": "loc_26BF",
"instruction_count": 1,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 10246,
"end": 10256,
"label": "loc_2806",
"instruction_count": 4,
"cycles_min": 20,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BNE loc_2815",
"targets": [
10261
]
},
{
"start": 10258,
"end": 10258,
"label": "loc_2812",
"instruction_count": 1,
"cycles_min": 7,
"cycles_max": 7,
"unknown_cycles": 0,
"terminator": "BRA loc_2CA6",
"targets": [
11430
]
},
{
"start": 10261,
"end": 10293,
"label": "loc_2815",
"instruction_count": 13,
"cycles_min": 58,
"cycles_max": 63,
"unknown_cycles": 0,
"terminator": "BEQ loc_289F",
"targets": [
10399
]
},
{
"start": 10295,
"end": 10305,
"label": "loc_2837",
"instruction_count": 4,
"cycles_min": 16,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10308,
"end": 10318,
"label": "loc_2844",
"instruction_count": 4,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10321,
"end": 10331,
"label": "loc_2851",
"instruction_count": 4,
"cycles_min": 16,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10334,
"end": 10344,
"label": "loc_285E",
"instruction_count": 4,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10347,
"end": 10357,
"label": "loc_286B",
"instruction_count": 4,
"cycles_min": 16,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10360,
"end": 10370,
"label": "loc_2878",
"instruction_count": 4,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10373,
"end": 10383,
"label": "loc_2885",
"instruction_count": 4,
"cycles_min": 16,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10386,
"end": 10396,
"label": "loc_2892",
"instruction_count": 4,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_2CAB",
"targets": [
11435
]
},
{
"start": 10399,
"end": 10403,
"label": "loc_289F",
"instruction_count": 2,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "JMP @R1",
"targets": []
},
{
"start": 11430,
"end": 11434,
"label": "loc_2CA6",
"instruction_count": 2,
"cycles_min": 21,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 11435,
"end": 11446,
"label": "loc_2CAB",
"instruction_count": 5,
"cycles_min": 63,
"cycles_max": 63,
"unknown_cycles": 0,
"terminator": "BRA loc_289F",
"targets": [
10399
]
},
{
"start": 14640,
"end": 14640,
"label": "loc_3930",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'0007, R0",
"targets": []
},
{
"start": 14643,
"end": 14647,
"label": "loc_3933",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_3943",
"targets": [
14659
]
},
{
"start": 14649,
"end": 14657,
"label": "loc_3939",
"instruction_count": 3,
"cycles_min": 24,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BRA loc_3947",
"targets": [
14663
]
},
{
"start": 14659,
"end": 14659,
"label": "loc_3943",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "SHLL.B @(-H'0980,R0)",
"targets": []
},
{
"start": 14663,
"end": 14668,
"label": "loc_3947",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BNE loc_3954",
"targets": [
14676
]
},
{
"start": 14670,
"end": 14674,
"label": "loc_394E",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_395F",
"targets": [
14687
]
},
{
"start": 14676,
"end": 14681,
"label": "loc_3954",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 15,
"unknown_cycles": 0,
"terminator": "BNE loc_395F",
"targets": [
14687
]
},
{
"start": 14683,
"end": 14683,
"label": "loc_395B",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BCLR.B R0, @H'F688",
"targets": []
},
{
"start": 14687,
"end": 14687,
"label": "loc_395F",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "SCB/F R0, loc_3933",
"targets": [
14643
]
},
{
"start": 14690,
"end": 14699,
"label": "loc_3962",
"instruction_count": 3,
"cycles_min": 19,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_397C",
"targets": [
14716
]
},
{
"start": 14701,
"end": 14706,
"label": "loc_396D",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BEQ loc_397F",
"targets": [
14719
]
},
{
"start": 14708,
"end": 14713,
"label": "loc_3974",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 15,
"unknown_cycles": 0,
"terminator": "BEQ loc_3983",
"targets": [
14723
]
},
{
"start": 14715,
"end": 14715,
"label": "loc_397B",
"instruction_count": 1,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 14716,
"end": 14718,
"label": "loc_397C",
"instruction_count": 2,
"cycles_min": 25,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 14719,
"end": 14722,
"label": "loc_397F",
"instruction_count": 2,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 14723,
"end": 14729,
"label": "loc_3983",
"instruction_count": 3,
"cycles_min": 35,
"cycles_max": 35,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 14730,
"end": 14734,
"label": "loc_398A",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_3994",
"targets": [
14740
]
},
{
"start": 14736,
"end": 14736,
"label": "loc_3990",
"instruction_count": 1,
"cycles_min": 9,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BSET.B #5, @ADCSR",
"targets": []
},
{
"start": 14740,
"end": 14740,
"label": "loc_3994",
"instruction_count": 1,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 14741,
"end": 14745,
"label": "loc_3995",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_3A2D",
"targets": [
14893
]
},
{
"start": 14748,
"end": 14757,
"label": "loc_399C",
"instruction_count": 3,
"cycles_min": 18,
"cycles_max": 23,
"unknown_cycles": 0,
"terminator": "BEQ loc_3A2D",
"targets": [
14893
]
},
{
"start": 14760,
"end": 14888,
"label": "loc_39A8",
"instruction_count": 34,
"cycles_min": 227,
"cycles_max": 227,
"unknown_cycles": 0,
"terminator": "MOV:G.B #H'03, @H'F720",
"targets": []
},
{
"start": 14893,
"end": 14893,
"label": "loc_3A2D",
"instruction_count": 1,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 14894,
"end": 14898,
"label": "loc_3A2E",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_3AC6",
"targets": [
15046
]
},
{
"start": 14901,
"end": 14910,
"label": "loc_3A35",
"instruction_count": 3,
"cycles_min": 19,
"cycles_max": 23,
"unknown_cycles": 0,
"terminator": "BEQ loc_3AC6",
"targets": [
15046
]
},
{
"start": 14913,
"end": 15041,
"label": "loc_3A41",
"instruction_count": 34,
"cycles_min": 197,
"cycles_max": 197,
"unknown_cycles": 0,
"terminator": "MOV:G.B #H'03, @H'F721",
"targets": []
},
{
"start": 15046,
"end": 15046,
"label": "loc_3AC6",
"instruction_count": 1,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 15047,
"end": 15053,
"label": "vec_irq4_3AC7",
"instruction_count": 3,
"cycles_min": 14,
"cycles_max": 19,
"unknown_cycles": 0,
"terminator": "BNE loc_3C2D",
"targets": [
15405
]
},
{
"start": 15056,
"end": 15062,
"label": "loc_3AD0",
"instruction_count": 3,
"cycles_min": 12,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BEQ loc_3AE0",
"targets": [
15072
]
},
{
"start": 15064,
"end": 15066,
"label": "loc_3AD8",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B62",
"targets": [
15202
]
},
{
"start": 15069,
"end": 15069,
"label": "loc_3ADD",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_3C2D",
"targets": [
15405
]
},
{
"start": 15072,
"end": 15091,
"label": "loc_3AE0",
"instruction_count": 6,
"cycles_min": 31,
"cycles_max": 36,
"unknown_cycles": 0,
"terminator": "BEQ loc_3AFD",
"targets": [
15101
]
},
{
"start": 15093,
"end": 15097,
"label": "loc_3AF5",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F69A",
"targets": []
},
{
"start": 15101,
"end": 15109,
"label": "loc_3AFD",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B0F",
"targets": [
15119
]
},
{
"start": 15111,
"end": 15115,
"label": "loc_3B07",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F698",
"targets": []
},
{
"start": 15119,
"end": 15127,
"label": "loc_3B0F",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B21",
"targets": [
15137
]
},
{
"start": 15129,
"end": 15133,
"label": "loc_3B19",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F696",
"targets": []
},
{
"start": 15137,
"end": 15145,
"label": "loc_3B21",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B33",
"targets": [
15155
]
},
{
"start": 15147,
"end": 15151,
"label": "loc_3B2B",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F694",
"targets": []
},
{
"start": 15155,
"end": 15163,
"label": "loc_3B33",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B45",
"targets": [
15173
]
},
{
"start": 15165,
"end": 15169,
"label": "loc_3B3D",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F692",
"targets": []
},
{
"start": 15173,
"end": 15181,
"label": "loc_3B45",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B57",
"targets": [
15191
]
},
{
"start": 15183,
"end": 15187,
"label": "loc_3B4F",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F690",
"targets": []
},
{
"start": 15191,
"end": 15199,
"label": "loc_3B57",
"instruction_count": 3,
"cycles_min": 22,
"cycles_max": 22,
"unknown_cycles": 0,
"terminator": "BRA loc_3C2D",
"targets": [
15405
]
},
{
"start": 15202,
"end": 15225,
"label": "loc_3B62",
"instruction_count": 7,
"cycles_min": 39,
"cycles_max": 44,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B83",
"targets": [
15235
]
},
{
"start": 15227,
"end": 15231,
"label": "loc_3B7B",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F69E",
"targets": []
},
{
"start": 15235,
"end": 15243,
"label": "loc_3B83",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3B95",
"targets": [
15253
]
},
{
"start": 15245,
"end": 15249,
"label": "loc_3B8D",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F69C",
"targets": []
},
{
"start": 15253,
"end": 15261,
"label": "loc_3B95",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3BA7",
"targets": [
15271
]
},
{
"start": 15263,
"end": 15267,
"label": "loc_3B9F",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D0",
"targets": []
},
{
"start": 15271,
"end": 15279,
"label": "loc_3BA7",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3BB9",
"targets": [
15289
]
},
{
"start": 15281,
"end": 15285,
"label": "loc_3BB1",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D1",
"targets": []
},
{
"start": 15289,
"end": 15297,
"label": "loc_3BB9",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3BCB",
"targets": [
15307
]
},
{
"start": 15299,
"end": 15303,
"label": "loc_3BC3",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D2",
"targets": []
},
{
"start": 15307,
"end": 15315,
"label": "loc_3BCB",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3BDD",
"targets": [
15325
]
},
{
"start": 15317,
"end": 15321,
"label": "loc_3BD5",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D3",
"targets": []
},
{
"start": 15325,
"end": 15333,
"label": "loc_3BDD",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3BEF",
"targets": [
15343
]
},
{
"start": 15335,
"end": 15339,
"label": "loc_3BE7",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D4",
"targets": []
},
{
"start": 15343,
"end": 15351,
"label": "loc_3BEF",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C01",
"targets": [
15361
]
},
{
"start": 15353,
"end": 15357,
"label": "loc_3BF9",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D5",
"targets": []
},
{
"start": 15361,
"end": 15369,
"label": "loc_3C01",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C13",
"targets": [
15379
]
},
{
"start": 15371,
"end": 15375,
"label": "loc_3C0B",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D6",
"targets": []
},
{
"start": 15379,
"end": 15387,
"label": "loc_3C13",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C25",
"targets": [
15397
]
},
{
"start": 15389,
"end": 15393,
"label": "loc_3C1D",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D7",
"targets": []
},
{
"start": 15397,
"end": 15401,
"label": "loc_3C25",
"instruction_count": 2,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BCLR.B #1, @H'F720",
"targets": []
},
{
"start": 15405,
"end": 15407,
"label": "loc_3C2D",
"instruction_count": 2,
"cycles_min": 20,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "RTE",
"targets": []
},
{
"start": 15408,
"end": 15414,
"label": "vec_irq3_3C30",
"instruction_count": 3,
"cycles_min": 16,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BNE loc_3D96",
"targets": [
15766
]
},
{
"start": 15417,
"end": 15423,
"label": "loc_3C39",
"instruction_count": 3,
"cycles_min": 11,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C49",
"targets": [
15433
]
},
{
"start": 15425,
"end": 15427,
"label": "loc_3C41",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_3CCB",
"targets": [
15563
]
},
{
"start": 15430,
"end": 15430,
"label": "loc_3C46",
"instruction_count": 1,
"cycles_min": 7,
"cycles_max": 7,
"unknown_cycles": 0,
"terminator": "BRA loc_3D96",
"targets": [
15766
]
},
{
"start": 15433,
"end": 15452,
"label": "loc_3C49",
"instruction_count": 6,
"cycles_min": 33,
"cycles_max": 37,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C66",
"targets": [
15462
]
},
{
"start": 15454,
"end": 15458,
"label": "loc_3C5E",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6AA",
"targets": []
},
{
"start": 15462,
"end": 15470,
"label": "loc_3C66",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C78",
"targets": [
15480
]
},
{
"start": 15472,
"end": 15476,
"label": "loc_3C70",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6A8",
"targets": []
},
{
"start": 15480,
"end": 15488,
"label": "loc_3C78",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C8A",
"targets": [
15498
]
},
{
"start": 15490,
"end": 15494,
"label": "loc_3C82",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6A6",
"targets": []
},
{
"start": 15498,
"end": 15506,
"label": "loc_3C8A",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3C9C",
"targets": [
15516
]
},
{
"start": 15508,
"end": 15512,
"label": "loc_3C94",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6A4",
"targets": []
},
{
"start": 15516,
"end": 15524,
"label": "loc_3C9C",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3CAE",
"targets": [
15534
]
},
{
"start": 15526,
"end": 15530,
"label": "loc_3CA6",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6A2",
"targets": []
},
{
"start": 15534,
"end": 15542,
"label": "loc_3CAE",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3CC0",
"targets": [
15552
]
},
{
"start": 15544,
"end": 15548,
"label": "loc_3CB8",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6A0",
"targets": []
},
{
"start": 15552,
"end": 15560,
"label": "loc_3CC0",
"instruction_count": 3,
"cycles_min": 23,
"cycles_max": 23,
"unknown_cycles": 0,
"terminator": "BRA loc_3D96",
"targets": [
15766
]
},
{
"start": 15563,
"end": 15586,
"label": "loc_3CCB",
"instruction_count": 7,
"cycles_min": 42,
"cycles_max": 46,
"unknown_cycles": 0,
"terminator": "BEQ loc_3CEC",
"targets": [
15596
]
},
{
"start": 15588,
"end": 15592,
"label": "loc_3CE4",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6AE",
"targets": []
},
{
"start": 15596,
"end": 15604,
"label": "loc_3CEC",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3CFE",
"targets": [
15614
]
},
{
"start": 15606,
"end": 15610,
"label": "loc_3CF6",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F6AC",
"targets": []
},
{
"start": 15614,
"end": 15622,
"label": "loc_3CFE",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D10",
"targets": [
15632
]
},
{
"start": 15624,
"end": 15628,
"label": "loc_3D08",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D8",
"targets": []
},
{
"start": 15632,
"end": 15640,
"label": "loc_3D10",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D22",
"targets": [
15650
]
},
{
"start": 15642,
"end": 15646,
"label": "loc_3D1A",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6D9",
"targets": []
},
{
"start": 15650,
"end": 15658,
"label": "loc_3D22",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D34",
"targets": [
15668
]
},
{
"start": 15660,
"end": 15664,
"label": "loc_3D2C",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6DA",
"targets": []
},
{
"start": 15668,
"end": 15676,
"label": "loc_3D34",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D46",
"targets": [
15686
]
},
{
"start": 15678,
"end": 15682,
"label": "loc_3D3E",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6DB",
"targets": []
},
{
"start": 15686,
"end": 15694,
"label": "loc_3D46",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D58",
"targets": [
15704
]
},
{
"start": 15696,
"end": 15700,
"label": "loc_3D50",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6DC",
"targets": []
},
{
"start": 15704,
"end": 15712,
"label": "loc_3D58",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D6A",
"targets": [
15722
]
},
{
"start": 15714,
"end": 15718,
"label": "loc_3D62",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6DD",
"targets": []
},
{
"start": 15722,
"end": 15730,
"label": "loc_3D6A",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D7C",
"targets": [
15740
]
},
{
"start": 15732,
"end": 15736,
"label": "loc_3D74",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6DE",
"targets": []
},
{
"start": 15740,
"end": 15748,
"label": "loc_3D7C",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BEQ loc_3D8E",
"targets": [
15758
]
},
{
"start": 15750,
"end": 15754,
"label": "loc_3D86",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F6DF",
"targets": []
},
{
"start": 15758,
"end": 15762,
"label": "loc_3D8E",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BCLR.B #1, @H'F721",
"targets": []
},
{
"start": 15766,
"end": 15768,
"label": "loc_3D96",
"instruction_count": 2,
"cycles_min": 18,
"cycles_max": 18,
"unknown_cycles": 0,
"terminator": "RTE",
"targets": []
},
{
"start": 15769,
"end": 15803,
"label": "vec_ad_adi_3D99",
"instruction_count": 12,
"cycles_min": 112,
"cycles_max": 117,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E08",
"targets": [
15880
]
},
{
"start": 15805,
"end": 15818,
"label": "loc_3DBD",
"instruction_count": 4,
"cycles_min": 21,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "BHI loc_3E08",
"targets": [
15880
]
},
{
"start": 15820,
"end": 15842,
"label": "loc_3DCC",
"instruction_count": 9,
"cycles_min": 75,
"cycles_max": 79,
"unknown_cycles": 0,
"terminator": "BCS loc_3DF0",
"targets": [
15856
]
},
{
"start": 15844,
"end": 15849,
"label": "loc_3DE4",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BLS loc_3DFA",
"targets": [
15866
]
},
{
"start": 15851,
"end": 15854,
"label": "loc_3DEB",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_3DFA",
"targets": [
15866
]
},
{
"start": 15856,
"end": 15861,
"label": "loc_3DF0",
"instruction_count": 3,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BLS loc_3DFA",
"targets": [
15866
]
},
{
"start": 15863,
"end": 15863,
"label": "loc_3DF7",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'FFFF, R1",
"targets": []
},
{
"start": 15866,
"end": 15870,
"label": "loc_3DFA",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E08",
"targets": [
15880
]
},
{
"start": 15872,
"end": 15876,
"label": "loc_3E00",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BSET.B #7, @H'F689",
"targets": []
},
{
"start": 15880,
"end": 15904,
"label": "loc_3E08",
"instruction_count": 9,
"cycles_min": 74,
"cycles_max": 78,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E28",
"targets": [
15912
]
},
{
"start": 15906,
"end": 15910,
"label": "loc_3E22",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E4D",
"targets": [
15949
]
},
{
"start": 15912,
"end": 15941,
"label": "loc_3E28",
"instruction_count": 11,
"cycles_min": 98,
"cycles_max": 103,
"unknown_cycles": 0,
"terminator": "BNE loc_3E49",
"targets": [
15945
]
},
{
"start": 15943,
"end": 15943,
"label": "loc_3E47",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "SHLR.W R0",
"targets": []
},
{
"start": 15945,
"end": 15945,
"label": "loc_3E49",
"instruction_count": 1,
"cycles_min": 6,
"cycles_max": 6,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @H'F68C",
"targets": []
},
{
"start": 15949,
"end": 15955,
"label": "loc_3E4D",
"instruction_count": 3,
"cycles_min": 52,
"cycles_max": 52,
"unknown_cycles": 0,
"terminator": "RTE",
"targets": []
},
{
"start": 15956,
"end": 15958,
"label": "loc_3E54",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E9A",
"targets": [
16026
]
},
{
"start": 15960,
"end": 15974,
"label": "loc_3E58",
"instruction_count": 6,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "SHLL.W R1",
"targets": []
},
{
"start": 15976,
"end": 15978,
"label": "loc_3E68",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E76",
"targets": [
15990
]
},
{
"start": 15980,
"end": 15984,
"label": "loc_3E6C",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_3E9A",
"targets": [
16026
]
},
{
"start": 15986,
"end": 15988,
"label": "loc_3E72",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_3E68",
"targets": [
15976
]
},
{
"start": 15990,
"end": 15998,
"label": "loc_3E76",
"instruction_count": 3,
"cycles_min": 25,
"cycles_max": 25,
"unknown_cycles": 0,
"terminator": "BCLR.B #7, @H'F9B0",
"targets": []
},
{
"start": 16002,
"end": 16015,
"label": "loc_3E82",
"instruction_count": 5,
"cycles_min": 23,
"cycles_max": 28,
"unknown_cycles": 0,
"terminator": "BNE loc_3E9A",
"targets": [
16026
]
},
{
"start": 16017,
"end": 16024,
"label": "loc_3E91",
"instruction_count": 4,
"cycles_min": 47,
"cycles_max": 47,
"unknown_cycles": 0,
"terminator": "BRA loc_3E82",
"targets": [
16002
]
},
{
"start": 16026,
"end": 16028,
"label": "loc_3E9A",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_3ECB",
"targets": [
16075
]
},
{
"start": 16030,
"end": 16044,
"label": "loc_3E9E",
"instruction_count": 6,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "SHLL.W R1",
"targets": []
},
{
"start": 16046,
"end": 16048,
"label": "loc_3EAE",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_3EBF",
"targets": [
16063
]
},
{
"start": 16050,
"end": 16054,
"label": "loc_3EB2",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_3ECB",
"targets": [
16075
]
},
{
"start": 16056,
"end": 16061,
"label": "loc_3EB8",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 15,
"unknown_cycles": 0,
"terminator": "BRA loc_3EAE",
"targets": [
16046
]
},
{
"start": 16063,
"end": 16071,
"label": "loc_3EBF",
"instruction_count": 3,
"cycles_min": 22,
"cycles_max": 22,
"unknown_cycles": 0,
"terminator": "BCLR.B #5, @H'F9B4",
"targets": []
},
{
"start": 16075,
"end": 16075,
"label": "loc_3ECB",
"instruction_count": 1,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16076,
"end": 16082,
"label": "loc_3ECC",
"instruction_count": 4,
"cycles_min": 29,
"cycles_max": 33,
"unknown_cycles": 0,
"terminator": "BLS loc_3ED9",
"targets": [
16089
]
},
{
"start": 16084,
"end": 16087,
"label": "loc_3ED4",
"instruction_count": 2,
"cycles_min": 21,
"cycles_max": 21,
"unknown_cycles": 0,
"terminator": "BRA loc_3F25",
"targets": [
16165
]
},
{
"start": 16089,
"end": 16093,
"label": "loc_3ED9",
"instruction_count": 3,
"cycles_min": 7,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "BEQ loc_3EE9",
"targets": [
16105
]
},
{
"start": 16095,
"end": 16097,
"label": "loc_3EDF",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_3EEE",
"targets": [
16110
]
},
{
"start": 16099,
"end": 16101,
"label": "loc_3EE3",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_3EF3",
"targets": [
16115
]
},
{
"start": 16103,
"end": 16103,
"label": "loc_3EE7",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_3EF8",
"targets": [
16120
]
},
{
"start": 16105,
"end": 16108,
"label": "loc_3EE9",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_3EFB",
"targets": [
16123
]
},
{
"start": 16110,
"end": 16113,
"label": "loc_3EEE",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_3EFB",
"targets": [
16123
]
},
{
"start": 16115,
"end": 16118,
"label": "loc_3EF3",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_3EFB",
"targets": [
16123
]
},
{
"start": 16120,
"end": 16120,
"label": "loc_3EF8",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'00D0, R5",
"targets": []
},
{
"start": 16123,
"end": 16130,
"label": "loc_3EFB",
"instruction_count": 3,
"cycles_min": 26,
"cycles_max": 26,
"unknown_cycles": 0,
"terminator": "CLR.W R1",
"targets": []
},
{
"start": 16132,
"end": 16138,
"label": "loc_3F04",
"instruction_count": 3,
"cycles_min": 16,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_3F10",
"targets": [
16144
]
},
{
"start": 16140,
"end": 16142,
"label": "loc_3F0C",
"instruction_count": 2,
"cycles_min": 19,
"cycles_max": 19,
"unknown_cycles": 0,
"terminator": "BSR loc_3F28",
"targets": [
16168
]
},
{
"start": 16144,
"end": 16150,
"label": "loc_3F10",
"instruction_count": 4,
"cycles_min": 13,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BEQ loc_3F1A",
"targets": [
16154
]
},
{
"start": 16152,
"end": 16152,
"label": "loc_3F18",
"instruction_count": 1,
"cycles_min": 7,
"cycles_max": 7,
"unknown_cycles": 0,
"terminator": "BRA loc_3F04",
"targets": [
16132
]
},
{
"start": 16154,
"end": 16163,
"label": "loc_3F1A",
"instruction_count": 3,
"cycles_min": 28,
"cycles_max": 28,
"unknown_cycles": 0,
"terminator": "BSR loc_3F40",
"targets": [
16192
]
},
{
"start": 16165,
"end": 16167,
"label": "loc_3F25",
"instruction_count": 2,
"cycles_min": 39,
"cycles_max": 39,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16168,
"end": 16176,
"label": "loc_3F28",
"instruction_count": 4,
"cycles_min": 15,
"cycles_max": 19,
"unknown_cycles": 0,
"terminator": "BEQ loc_3F38",
"targets": [
16184
]
},
{
"start": 16178,
"end": 16182,
"label": "loc_3F32",
"instruction_count": 2,
"cycles_min": 20,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BSR loc_3F40",
"targets": [
16192
]
},
{
"start": 16184,
"end": 16191,
"label": "loc_3F38",
"instruction_count": 4,
"cycles_min": 32,
"cycles_max": 32,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16192,
"end": 16198,
"label": "loc_3F40",
"instruction_count": 3,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "ORC.W #H'0600, SR",
"targets": []
},
{
"start": 16202,
"end": 16209,
"label": "loc_3F4A",
"instruction_count": 3,
"cycles_min": 18,
"cycles_max": 23,
"unknown_cycles": 0,
"terminator": "BNE loc_3F4A",
"targets": [
16202
]
},
{
"start": 16211,
"end": 16213,
"label": "loc_3F53",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BNE loc_3F6D",
"targets": [
16237
]
},
{
"start": 16215,
"end": 16217,
"label": "loc_3F57",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BNE loc_3F62",
"targets": [
16226
]
},
{
"start": 16219,
"end": 16224,
"label": "loc_3F5B",
"instruction_count": 2,
"cycles_min": 20,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BRA loc_3F72",
"targets": [
16242
]
},
{
"start": 16226,
"end": 16235,
"label": "loc_3F62",
"instruction_count": 3,
"cycles_min": 29,
"cycles_max": 29,
"unknown_cycles": 0,
"terminator": "BRA loc_3F72",
"targets": [
16242
]
},
{
"start": 16237,
"end": 16237,
"label": "loc_3F6D",
"instruction_count": 1,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "MOVFPE.B @H'F201, R4",
"targets": []
},
{
"start": 16242,
"end": 16244,
"label": "loc_3F72",
"instruction_count": 2,
"cycles_min": 19,
"cycles_max": 19,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16246,
"end": 16249,
"label": "loc_3F76",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 6,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'C350, R1",
"targets": []
},
{
"start": 16252,
"end": 16256,
"label": "loc_3F7C",
"instruction_count": 2,
"cycles_min": 12,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "SCB/F R0, loc_3F7C",
"targets": [
16252
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},
{
"start": 16259,
"end": 16263,
"label": "loc_3F83",
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"terminator": "SCB/F R1, loc_3F83",
"targets": [
16259
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},
{
"start": 16266,
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"label": "loc_3F8A",
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"terminator": "CLR.W R0",
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},
{
"start": 16268,
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"label": "loc_3F8C",
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"terminator": "BNE loc_3F8C",
"targets": [
16268
]
},
{
"start": 16287,
"end": 16302,
"label": "loc_3F9F",
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"terminator": "BSR loc_434C",
"targets": [
17228
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},
{
"start": 16305,
"end": 16337,
"label": "loc_3FB1",
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"terminator": "BRA loc_3FB1",
"targets": [
16305
]
},
{
"start": 16339,
"end": 16343,
"label": "loc_3FD3",
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"terminator": "BNE loc_3FEE",
"targets": [
16366
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},
{
"start": 16345,
"end": 16349,
"label": "loc_3FD9",
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"terminator": "BEQ loc_3FE5",
"targets": [
16357
]
},
{
"start": 16351,
"end": 16355,
"label": "loc_3FDF",
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"terminator": "BNE loc_3FEE",
"targets": [
16366
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},
{
"start": 16357,
"end": 16361,
"label": "loc_3FE5",
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"terminator": "BNE loc_3FEE",
"targets": [
16366
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},
{
"start": 16363,
"end": 16363,
"label": "loc_3FEB",
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"unknown_cycles": 0,
"terminator": "BSR loc_BAF2",
"targets": [
47858
]
},
{
"start": 16366,
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"label": "loc_3FEE",
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"cycles_min": 12,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16367,
"end": 16371,
"label": "loc_3FEF",
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"terminator": "BNE loc_4007",
"targets": [
16391
]
},
{
"start": 16373,
"end": 16385,
"label": "loc_3FF5",
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"terminator": "BEQ loc_400B",
"targets": [
16395
]
},
{
"start": 16387,
"end": 16389,
"label": "loc_4003",
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"terminator": "BRA loc_400B",
"targets": [
16395
]
},
{
"start": 16391,
"end": 16391,
"label": "loc_4007",
"instruction_count": 1,
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"unknown_cycles": 0,
"terminator": "BSET.B #7, @H'FAA5",
"targets": []
},
{
"start": 16395,
"end": 16395,
"label": "loc_400B",
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"cycles_min": 13,
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"terminator": "RTS",
"targets": []
},
{
"start": 16396,
"end": 16453,
"label": "loc_400C",
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"cycles_min": 156,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16454,
"end": 16458,
"label": "loc_4046",
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"terminator": "BNE loc_4058",
"targets": [
16472
]
},
{
"start": 16460,
"end": 16464,
"label": "loc_404C",
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"unknown_cycles": 0,
"terminator": "BEQ loc_4059",
"targets": [
16473
]
},
{
"start": 16466,
"end": 16470,
"label": "loc_4052",
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"terminator": "BEQ loc_4059",
"targets": [
16473
]
},
{
"start": 16472,
"end": 16472,
"label": "loc_4058",
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"cycles_min": 12,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16473,
"end": 16483,
"label": "loc_4059",
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"unknown_cycles": 0,
"terminator": "BNE loc_4074",
"targets": [
16500
]
},
{
"start": 16485,
"end": 16496,
"label": "loc_4065",
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"unknown_cycles": 0,
"terminator": "BCLR.B #7, @H'F9B0",
"targets": []
},
{
"start": 16500,
"end": 16500,
"label": "loc_4074",
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16501,
"end": 16501,
"label": "loc_4075",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "CLR.W R0",
"targets": []
},
{
"start": 16503,
"end": 16518,
"label": "loc_4077",
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"unknown_cycles": 0,
"terminator": "BCC loc_408C",
"targets": [
16524
]
},
{
"start": 16520,
"end": 16520,
"label": "loc_4088",
"instruction_count": 1,
"cycles_min": 9,
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"unknown_cycles": 0,
"terminator": "CLR.W @(-H'1400,R0)",
"targets": []
},
{
"start": 16524,
"end": 16529,
"label": "loc_408C",
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"cycles_min": 10,
"cycles_max": 15,
"unknown_cycles": 0,
"terminator": "BNE loc_4077",
"targets": [
16503
]
},
{
"start": 16531,
"end": 16533,
"label": "loc_4093",
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16534,
"end": 16570,
"label": "loc_4096",
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 16571,
"end": 16571,
"label": "loc_40BB",
"instruction_count": 1,
"cycles_min": 3,
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"unknown_cycles": 0,
"terminator": "MOV:I.W #H'0040, R0",
"targets": []
},
{
"start": 16574,
"end": 16606,
"label": "loc_40BE",
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"unknown_cycles": 0,
"terminator": "BNE loc_40BE",
"targets": [
16574
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},
{
"start": 16608,
"end": 16632,
"label": "loc_40E0",
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"unknown_cycles": 0,
"terminator": "BEQ loc_4103",
"targets": [
16643
]
},
{
"start": 16634,
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"label": "loc_40FA",
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"unknown_cycles": 0,
"terminator": "BEQ loc_41B0",
"targets": [
16816
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},
{
"start": 16643,
"end": 16643,
"label": "loc_4103",
"instruction_count": 1,
"cycles_min": 3,
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"unknown_cycles": 0,
"terminator": "MOV:I.W #H'0100, R0",
"targets": []
},
{
"start": 16646,
"end": 16770,
"label": "loc_4106",
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"cycles_min": 311,
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"terminator": "BNE loc_4106",
"targets": [
16646
]
},
{
"start": 16772,
"end": 16772,
"label": "loc_4184",
"instruction_count": 1,
"cycles_min": 3,
"cycles_max": 3,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'000F, R0",
"targets": []
},
{
"start": 16775,
"end": 16813,
"label": "loc_4187",
"instruction_count": 16,
"cycles_min": 96,
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"unknown_cycles": 0,
"terminator": "SCB/F R0, loc_4187",
"targets": [
16775
]
},
{
"start": 16816,
"end": 16816,
"label": "loc_41B0",
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"cycles_min": 7,
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"unknown_cycles": 0,
"terminator": "BRA loc_41D2",
"targets": [
16850
]
},
{
"start": 16850,
"end": 16850,
"label": "loc_41D2",
"instruction_count": 1,
"cycles_min": 3,
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"unknown_cycles": 0,
"terminator": "MOV:I.W #H'000F, R0",
"targets": []
},
{
"start": 16853,
"end": 16915,
"label": "loc_41D5",
"instruction_count": 26,
"cycles_min": 214,
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"terminator": "SCB/F R0, loc_41D5",
"targets": [
16853
]
},
{
"start": 16918,
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"label": "loc_4216",
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"terminator": "RTS",
"targets": []
},
{
"start": 16919,
"end": 17163,
"label": "loc_4217",
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"terminator": "RTS",
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},
{
"start": 17164,
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"label": "loc_430C",
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"terminator": "RTS",
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},
{
"start": 17188,
"end": 17227,
"label": "loc_4324",
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"terminator": "RTS",
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},
{
"start": 17228,
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"label": "loc_434C",
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"terminator": "BEQ loc_438E",
"targets": [
17294
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},
{
"start": 17288,
"end": 17288,
"label": "loc_4388",
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"terminator": "MOV:G.W #H'A53F, @WDT_TCSR_R",
"targets": []
},
{
"start": 17294,
"end": 17298,
"label": "loc_438E",
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"terminator": "RTS",
"targets": []
},
{
"start": 17299,
"end": 17299,
"label": "vec_nmi_4393",
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"terminator": "RTE",
"targets": []
},
{
"start": 17300,
"end": 17305,
"label": "loc_4394",
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"terminator": "BHI loc_4422",
"targets": [
17442
]
},
{
"start": 17308,
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"label": "loc_439C",
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"terminator": "BNE loc_4422",
"targets": [
17442
]
},
{
"start": 17315,
"end": 17319,
"label": "loc_43A3",
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"terminator": "BEQ loc_4422",
"targets": [
17442
]
},
{
"start": 17322,
"end": 17332,
"label": "loc_43AA",
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"unknown_cycles": 0,
"terminator": "BNE loc_43CF",
"targets": [
17359
]
},
{
"start": 17334,
"end": 17336,
"label": "loc_43B6",
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"unknown_cycles": 0,
"terminator": "BNE loc_43DB",
"targets": [
17371
]
},
{
"start": 17338,
"end": 17340,
"label": "loc_43BA",
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"unknown_cycles": 0,
"terminator": "BNE loc_43E7",
"targets": [
17383
]
},
{
"start": 17342,
"end": 17344,
"label": "loc_43BE",
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"cycles_min": 6,
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"unknown_cycles": 0,
"terminator": "BNE loc_43F3",
"targets": [
17395
]
},
{
"start": 17346,
"end": 17348,
"label": "loc_43C2",
"instruction_count": 2,
"cycles_min": 6,
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"unknown_cycles": 0,
"terminator": "BNE loc_43FF",
"targets": [
17407
]
},
{
"start": 17350,
"end": 17352,
"label": "loc_43C6",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BNE loc_440D",
"targets": [
17421
]
},
{
"start": 17354,
"end": 17357,
"label": "loc_43CA",
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"cycles_min": 21,
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"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17359,
"end": 17364,
"label": "loc_43CF",
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"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_43D9",
"targets": [
17369
]
},
{
"start": 17366,
"end": 17366,
"label": "loc_43D6",
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"cycles_min": 13,
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"unknown_cycles": 0,
"terminator": "BSR loc_1A35",
"targets": [
6709
]
},
{
"start": 17369,
"end": 17369,
"label": "loc_43D9",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17371,
"end": 17376,
"label": "loc_43DB",
"instruction_count": 3,
"cycles_min": 20,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_43E5",
"targets": [
17381
]
},
{
"start": 17378,
"end": 17378,
"label": "loc_43E2",
"instruction_count": 1,
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"unknown_cycles": 0,
"terminator": "BSR loc_1A9C",
"targets": [
6812
]
},
{
"start": 17381,
"end": 17381,
"label": "loc_43E5",
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"cycles_min": 8,
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"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17383,
"end": 17388,
"label": "loc_43E7",
"instruction_count": 3,
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"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_43F1",
"targets": [
17393
]
},
{
"start": 17390,
"end": 17390,
"label": "loc_43EE",
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"cycles_min": 13,
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"unknown_cycles": 0,
"terminator": "BSR loc_1AE4",
"targets": [
6884
]
},
{
"start": 17393,
"end": 17393,
"label": "loc_43F1",
"instruction_count": 1,
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"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17395,
"end": 17400,
"label": "loc_43F3",
"instruction_count": 3,
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"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_43FD",
"targets": [
17405
]
},
{
"start": 17402,
"end": 17402,
"label": "loc_43FA",
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"cycles_min": 13,
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"unknown_cycles": 0,
"terminator": "BSR loc_1B0B",
"targets": [
6923
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},
{
"start": 17405,
"end": 17405,
"label": "loc_43FD",
"instruction_count": 1,
"cycles_min": 8,
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"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17407,
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"label": "loc_43FF",
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"cycles_min": 37,
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"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17421,
"end": 17426,
"label": "loc_440D",
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"cycles_min": 20,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BEQ loc_4420",
"targets": [
17440
]
},
{
"start": 17428,
"end": 17437,
"label": "loc_4414",
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"unknown_cycles": 0,
"terminator": "BSR loc_48FA",
"targets": [
18682
]
},
{
"start": 17440,
"end": 17440,
"label": "loc_4420",
"instruction_count": 1,
"cycles_min": 7,
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"unknown_cycles": 0,
"terminator": "BRA loc_4422",
"targets": [
17442
]
},
{
"start": 17442,
"end": 17454,
"label": "loc_4422",
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 17455,
"end": 17461,
"label": "loc_442F",
"instruction_count": 3,
"cycles_min": 11,
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"unknown_cycles": 0,
"terminator": "BCC loc_4444",
"targets": [
17476
]
},
{
"start": 17463,
"end": 17465,
"label": "loc_4437",
"instruction_count": 2,
"cycles_min": 5,
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"unknown_cycles": 0,
"terminator": "BLS loc_444E",
"targets": [
17486
]
},
{
"start": 17467,
"end": 17474,
"label": "loc_443B",
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"cycles_min": 16,
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"unknown_cycles": 0,
"terminator": "BRA loc_4456",
"targets": [
17494
]
},
{
"start": 17476,
"end": 17484,
"label": "loc_4444",
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"unknown_cycles": 0,
"terminator": "BRA loc_4456",
"targets": [
17494
]
},
{
"start": 17486,
"end": 17491,
"label": "loc_444E",
"instruction_count": 2,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'0001, R4",
"targets": []
},
{
"start": 17494,
"end": 17494,
"label": "loc_4456",
"instruction_count": 1,
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"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 17495,
"end": 17500,
"label": "loc_4457",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BHI loc_44E5",
"targets": [
17637
]
},
{
"start": 17503,
"end": 17507,
"label": "loc_445F",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_44E5",
"targets": [
17637
]
},
{
"start": 17510,
"end": 17514,
"label": "loc_4466",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_44E5",
"targets": [
17637
]
},
{
"start": 17517,
"end": 17527,
"label": "loc_446D",
"instruction_count": 4,
"cycles_min": 18,
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{
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"end": 25172,
"label": "loc_6251",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BRA loc_6264",
"targets": [
25188
]
},
{
"start": 25174,
"end": 25176,
"label": "loc_6256",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BHI loc_625F",
"targets": [
25183
]
},
{
"start": 25178,
"end": 25181,
"label": "loc_625A",
"instruction_count": 2,
"cycles_min": 11,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BRA loc_6264",
"targets": [
25188
]
},
{
"start": 25183,
"end": 25185,
"label": "loc_625F",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 6,
"unknown_cycles": 0,
"terminator": "MOV:I.W #H'01FF, R5",
"targets": []
},
{
"start": 25188,
"end": 25190,
"label": "loc_6264",
"instruction_count": 2,
"cycles_min": 15,
"cycles_max": 15,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 47654,
"end": 47658,
"label": "loc_BA26",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_BA26",
"targets": [
47654
]
},
{
"start": 47660,
"end": 47716,
"label": "loc_BA2C",
"instruction_count": 15,
"cycles_min": 104,
"cycles_max": 104,
"unknown_cycles": 0,
"terminator": "MOV:G.B R0, @H'F85D",
"targets": []
},
{
"start": 47720,
"end": 47724,
"label": "loc_BA68",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BA68",
"targets": [
47720
]
},
{
"start": 47726,
"end": 47747,
"label": "loc_BA6E",
"instruction_count": 6,
"cycles_min": 52,
"cycles_max": 52,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 47748,
"end": 47752,
"label": "vec_sci1_txi_BA84",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BAA9",
"targets": [
47785
]
},
{
"start": 47754,
"end": 47758,
"label": "loc_BA8A",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BAA9",
"targets": [
47785
]
},
{
"start": 47760,
"end": 47764,
"label": "loc_BA90",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BAA9",
"targets": [
47785
]
},
{
"start": 47766,
"end": 47783,
"label": "loc_BA96",
"instruction_count": 5,
"cycles_min": 44,
"cycles_max": 44,
"unknown_cycles": 0,
"terminator": "BRA loc_BAF1",
"targets": [
47857
]
},
{
"start": 47785,
"end": 47816,
"label": "loc_BAA9",
"instruction_count": 10,
"cycles_min": 57,
"cycles_max": 61,
"unknown_cycles": 0,
"terminator": "BNE loc_BAF1",
"targets": [
47857
]
},
{
"start": 47818,
"end": 47826,
"label": "loc_BACA",
"instruction_count": 3,
"cycles_min": 19,
"cycles_max": 23,
"unknown_cycles": 0,
"terminator": "BNE loc_BAE8",
"targets": [
47848
]
},
{
"start": 47828,
"end": 47832,
"label": "loc_BAD4",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_BAE1",
"targets": [
47841
]
},
{
"start": 47834,
"end": 47839,
"label": "loc_BADA",
"instruction_count": 2,
"cycles_min": 17,
"cycles_max": 17,
"unknown_cycles": 0,
"terminator": "BRA loc_BAED",
"targets": [
47853
]
},
{
"start": 47841,
"end": 47846,
"label": "loc_BAE1",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_BAED",
"targets": [
47853
]
},
{
"start": 47848,
"end": 47848,
"label": "loc_BAE8",
"instruction_count": 1,
"cycles_min": 9,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "MOV:G.B #H'F0, @H'F9C0",
"targets": []
},
{
"start": 47853,
"end": 47853,
"label": "loc_BAED",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "CLR.B @H'F9C1",
"targets": []
},
{
"start": 47857,
"end": 47857,
"label": "loc_BAF1",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "RTE",
"targets": []
},
{
"start": 47858,
"end": 47868,
"label": "loc_BAF2",
"instruction_count": 4,
"cycles_min": 20,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BNE loc_BB00",
"targets": [
47872
]
},
{
"start": 47870,
"end": 47870,
"label": "loc_BAFE",
"instruction_count": 1,
"cycles_min": 7,
"cycles_max": 7,
"unknown_cycles": 0,
"terminator": "BRA loc_BB56",
"targets": [
47958
]
},
{
"start": 47872,
"end": 47953,
"label": "loc_BB00",
"instruction_count": 27,
"cycles_min": 150,
"cycles_max": 150,
"unknown_cycles": 0,
"terminator": "MOV:G.B #H'80, @H'FAA3",
"targets": []
},
{
"start": 47958,
"end": 47958,
"label": "loc_BB56",
"instruction_count": 1,
"cycles_min": 12,
"cycles_max": 12,
"unknown_cycles": 0,
"terminator": "RTS",
"targets": []
},
{
"start": 47959,
"end": 47971,
"label": "vec_sci1_eri_BB57",
"instruction_count": 4,
"cycles_min": 32,
"cycles_max": 32,
"unknown_cycles": 0,
"terminator": "BCLR.B #3, @SCI1_SSR",
"targets": []
},
{
"start": 47975,
"end": 47989,
"label": "vec_sci1_rxi_BB67",
"instruction_count": 5,
"cycles_min": 35,
"cycles_max": 40,
"unknown_cycles": 0,
"terminator": "BNE loc_BB7D",
"targets": [
47997
]
},
{
"start": 47991,
"end": 47995,
"label": "loc_BB77",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_BB8A",
"targets": [
48010
]
},
{
"start": 47997,
"end": 48002,
"label": "loc_BB7D",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BLS loc_BB8A",
"targets": [
48010
]
},
{
"start": 48004,
"end": 48008,
"label": "loc_BB84",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_BBA3",
"targets": [
48035
]
},
{
"start": 48010,
"end": 48028,
"label": "loc_BB8A",
"instruction_count": 7,
"cycles_min": 33,
"cycles_max": 37,
"unknown_cycles": 0,
"terminator": "BNE loc_BBA3",
"targets": [
48035
]
},
{
"start": 48030,
"end": 48030,
"label": "loc_BB9E",
"instruction_count": 1,
"cycles_min": 9,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "MOV:G.B #H'14, @H'F9C5",
"targets": []
},
{
"start": 48035,
"end": 48042,
"label": "loc_BBA3",
"instruction_count": 3,
"cycles_min": 36,
"cycles_max": 36,
"unknown_cycles": 0,
"terminator": "RTE",
"targets": []
},
{
"start": 48043,
"end": 48048,
"label": "loc_BBAB",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BNE loc_BE6F",
"targets": [
48751
]
},
{
"start": 48051,
"end": 48083,
"label": "loc_BBB3",
"instruction_count": 9,
"cycles_min": 53,
"cycles_max": 58,
"unknown_cycles": 0,
"terminator": "BNE loc_BE29",
"targets": [
48681
]
},
{
"start": 48086,
"end": 48112,
"label": "loc_BBD6",
"instruction_count": 8,
"cycles_min": 47,
"cycles_max": 51,
"unknown_cycles": 0,
"terminator": "BNE loc_BE29",
"targets": [
48681
]
},
{
"start": 48115,
"end": 48147,
"label": "loc_BBF3",
"instruction_count": 11,
"cycles_min": 62,
"cycles_max": 67,
"unknown_cycles": 0,
"terminator": "BNE loc_BC3A",
"targets": [
48186
]
},
{
"start": 48149,
"end": 48157,
"label": "loc_BC15",
"instruction_count": 3,
"cycles_min": 17,
"cycles_max": 22,
"unknown_cycles": 0,
"terminator": "BNE loc_BD0B",
"targets": [
48395
]
},
{
"start": 48160,
"end": 48162,
"label": "loc_BC20",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_BC69",
"targets": [
48233
]
},
{
"start": 48164,
"end": 48166,
"label": "loc_BC24",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_BCD7",
"targets": [
48343
]
},
{
"start": 48169,
"end": 48171,
"label": "loc_BC29",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BD04",
"targets": [
48388
]
},
{
"start": 48174,
"end": 48176,
"label": "loc_BC2E",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_BE05",
"targets": [
48645
]
},
{
"start": 48179,
"end": 48183,
"label": "loc_BC33",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48186,
"end": 48188,
"label": "loc_BC3A",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_BC5C",
"targets": [
48220
]
},
{
"start": 48190,
"end": 48194,
"label": "loc_BC3E",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BNE loc_BE27",
"targets": [
48679
]
},
{
"start": 48197,
"end": 48199,
"label": "loc_BC45",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BD0E",
"targets": [
48398
]
},
{
"start": 48202,
"end": 48204,
"label": "loc_BC4A",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_BD80",
"targets": [
48512
]
},
{
"start": 48207,
"end": 48209,
"label": "loc_BC4F",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDDB",
"targets": [
48603
]
},
{
"start": 48212,
"end": 48214,
"label": "loc_BC54",
"instruction_count": 2,
"cycles_min": 5,
"cycles_max": 9,
"unknown_cycles": 0,
"terminator": "BEQ loc_BE05",
"targets": [
48645
]
},
{
"start": 48217,
"end": 48217,
"label": "loc_BC59",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48220,
"end": 48224,
"label": "loc_BC5C",
"instruction_count": 2,
"cycles_min": 12,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BEQ loc_BE6F",
"targets": [
48751
]
},
{
"start": 48227,
"end": 48231,
"label": "loc_BC63",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_BC15",
"targets": [
48149
]
},
{
"start": 48233,
"end": 48235,
"label": "loc_BC69",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BNE loc_BC8B",
"targets": [
48267
]
},
{
"start": 48237,
"end": 48265,
"label": "loc_BC6D",
"instruction_count": 9,
"cycles_min": 62,
"cycles_max": 62,
"unknown_cycles": 0,
"terminator": "BRA loc_BCB0",
"targets": [
48304
]
},
{
"start": 48267,
"end": 48295,
"label": "loc_BC8B",
"instruction_count": 9,
"cycles_min": 47,
"cycles_max": 52,
"unknown_cycles": 0,
"terminator": "BEQ loc_BCAD",
"targets": [
48301
]
},
{
"start": 48297,
"end": 48297,
"label": "loc_BCA9",
"instruction_count": 1,
"cycles_min": 6,
"cycles_max": 6,
"unknown_cycles": 0,
"terminator": "MOV:G.W R0, @(-H'0C00,R1)",
"targets": []
},
{
"start": 48301,
"end": 48301,
"label": "loc_BCAD",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_BE70",
"targets": [
48752
]
},
{
"start": 48304,
"end": 48340,
"label": "loc_BCB0",
"instruction_count": 10,
"cycles_min": 75,
"cycles_max": 75,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48343,
"end": 48385,
"label": "loc_BCD7",
"instruction_count": 12,
"cycles_min": 90,
"cycles_max": 90,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48388,
"end": 48392,
"label": "loc_BD04",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48395,
"end": 48395,
"label": "loc_BD0B",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48398,
"end": 48400,
"label": "loc_BD0E",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BNE loc_BD2B",
"targets": [
48427
]
},
{
"start": 48402,
"end": 48425,
"label": "loc_BD12",
"instruction_count": 8,
"cycles_min": 56,
"cycles_max": 56,
"unknown_cycles": 0,
"terminator": "BRA loc_BD67",
"targets": [
48487
]
},
{
"start": 48427,
"end": 48451,
"label": "loc_BD2B",
"instruction_count": 8,
"cycles_min": 41,
"cycles_max": 46,
"unknown_cycles": 0,
"terminator": "BEQ loc_BD64",
"targets": [
48484
]
},
{
"start": 48453,
"end": 48461,
"label": "loc_BD45",
"instruction_count": 3,
"cycles_min": 15,
"cycles_max": 20,
"unknown_cycles": 0,
"terminator": "BEQ loc_BD64",
"targets": [
48484
]
},
{
"start": 48463,
"end": 48482,
"label": "loc_BD4F",
"instruction_count": 8,
"cycles_min": 65,
"cycles_max": 65,
"unknown_cycles": 0,
"terminator": "LDM.W @SP+, {R0,R4,R5}",
"targets": []
},
{
"start": 48484,
"end": 48484,
"label": "loc_BD64",
"instruction_count": 1,
"cycles_min": 13,
"cycles_max": 13,
"unknown_cycles": 0,
"terminator": "BSR loc_BE70",
"targets": [
48752
]
},
{
"start": 48487,
"end": 48491,
"label": "loc_BD67",
"instruction_count": 2,
"cycles_min": 9,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BD75",
"targets": [
48501
]
},
{
"start": 48493,
"end": 48497,
"label": "loc_BD6D",
"instruction_count": 2,
"cycles_min": 16,
"cycles_max": 16,
"unknown_cycles": 0,
"terminator": "BCLR.B #7, @H'F9B5",
"targets": []
},
{
"start": 48501,
"end": 48509,
"label": "loc_BD75",
"instruction_count": 3,
"cycles_min": 24,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BRA loc_BE6F",
"targets": [
48751
]
},
{
"start": 48512,
"end": 48515,
"label": "loc_BD80",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDBF",
"targets": [
48575
]
},
{
"start": 48517,
"end": 48520,
"label": "loc_BD85",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDBF",
"targets": [
48575
]
},
{
"start": 48522,
"end": 48525,
"label": "loc_BD8A",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDBF",
"targets": [
48575
]
},
{
"start": 48527,
"end": 48530,
"label": "loc_BD8F",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDBF",
"targets": [
48575
]
},
{
"start": 48532,
"end": 48536,
"label": "loc_BD94",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDC2",
"targets": [
48578
]
},
{
"start": 48538,
"end": 48541,
"label": "loc_BD9A",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDB5",
"targets": [
48565
]
},
{
"start": 48543,
"end": 48546,
"label": "loc_BD9F",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDB5",
"targets": [
48565
]
},
{
"start": 48548,
"end": 48551,
"label": "loc_BDA4",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDB5",
"targets": [
48565
]
},
{
"start": 48553,
"end": 48556,
"label": "loc_BDA9",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 10,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDB5",
"targets": [
48565
]
},
{
"start": 48558,
"end": 48561,
"label": "loc_BDAE",
"instruction_count": 2,
"cycles_min": 6,
"cycles_max": 11,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDB5",
"targets": [
48565
]
},
{
"start": 48563,
"end": 48563,
"label": "loc_BDB3",
"instruction_count": 1,
"cycles_min": 8,
"cycles_max": 8,
"unknown_cycles": 0,
"terminator": "BRA loc_BDC2",
"targets": [
48578
]
},
{
"start": 48565,
"end": 48573,
"label": "loc_BDB5",
"instruction_count": 3,
"cycles_min": 24,
"cycles_max": 24,
"unknown_cycles": 0,
"terminator": "BRA loc_BDC2",
"targets": [
48578
]
},
{
"start": 48575,
"end": 48575,
"label": "loc_BDBF",
"instruction_count": 1,
"cycles_min": 14,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BSR loc_BE70",
"targets": [
48752
]
},
{
"start": 48578,
"end": 48582,
"label": "loc_BDC2",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"terminator": "BEQ loc_BDD0",
"targets": [
48592
]
},
{
"start": 48584,
"end": 48588,
"label": "loc_BDC8",
"instruction_count": 2,
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"instruction_count": 2,
"cycles_min": 9,
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"terminator": "BEQ loc_C069",
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},
{
"start": 49217,
"end": 49224,
"label": "loc_C041",
"instruction_count": 4,
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49211
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},
{
"start": 49226,
"end": 49230,
"label": "loc_C04A",
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49211
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},
{
"start": 49232,
"end": 49241,
"label": "loc_C050",
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"targets": [
49211
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},
{
"start": 49243,
"end": 49254,
"label": "loc_C05B",
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"terminator": "BSR loc_C142",
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49474
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},
{
"start": 49257,
"end": 49257,
"label": "loc_C069",
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},
{
"start": 49258,
"end": 49265,
"label": "loc_C06A",
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"terminator": "BCC loc_C07E",
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},
{
"start": 49267,
"end": 49276,
"label": "loc_C073",
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"terminator": "BRA loc_C08A",
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49290
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},
{
"start": 49278,
"end": 49287,
"label": "loc_C07E",
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"terminator": "OR.B #H'E0, R3",
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},
{
"start": 49290,
"end": 49290,
"label": "loc_C08A",
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"cycles_min": 12,
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{
"start": 49291,
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"label": "loc_C08B",
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"cycles_min": 3,
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"terminator": "MOV:I.W #H'0007, R1",
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},
{
"start": 49294,
"end": 49296,
"label": "loc_C08E",
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"cycles_min": 5,
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"terminator": "BCC loc_C098",
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49304
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},
{
"start": 49298,
"end": 49302,
"label": "loc_C092",
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"terminator": "BRA loc_C09C",
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49308
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},
{
"start": 49304,
"end": 49304,
"label": "loc_C098",
"instruction_count": 1,
"cycles_min": 9,
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"terminator": "BCLR.B #7, @P9DR",
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},
{
"start": 49308,
"end": 49324,
"label": "loc_C09C",
"instruction_count": 5,
"cycles_min": 39,
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"terminator": "SCB/F R1, loc_C08E",
"targets": [
49294
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},
{
"start": 49327,
"end": 49344,
"label": "loc_C0AF",
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"terminator": "BEQ loc_C0CF",
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49359
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},
{
"start": 49346,
"end": 49357,
"label": "loc_C0C2",
"instruction_count": 4,
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"terminator": "BRA loc_C0DA",
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49370
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},
{
"start": 49359,
"end": 49368,
"label": "loc_C0CF",
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"terminator": "MOV:E.B #H'01, R0",
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},
{
"start": 49370,
"end": 49370,
"label": "loc_C0DA",
"instruction_count": 1,
"cycles_min": 12,
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"terminator": "RTS",
"targets": []
},
{
"start": 49371,
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"label": "loc_C0DB",
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"cycles_min": 12,
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"terminator": "MOV:I.W #H'0007, R1",
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},
{
"start": 49379,
"end": 49391,
"label": "loc_C0E3",
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49397
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},
{
"start": 49393,
"end": 49395,
"label": "loc_C0F1",
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"terminator": "BRA loc_C0F7",
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49399
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{
"start": 49397,
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"label": "loc_C0F5",
"instruction_count": 1,
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"terminator": "BCLR.B R1, R5",
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{
"start": 49399,
"end": 49411,
"label": "loc_C0F7",
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49379
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},
{
"start": 49414,
"end": 49419,
"label": "loc_C106",
"instruction_count": 2,
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"terminator": "RTS",
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{
"start": 49420,
"end": 49440,
"label": "loc_C10C",
"instruction_count": 6,
"cycles_min": 57,
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"terminator": "RTS",
"targets": []
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{
"start": 49441,
"end": 49473,
"label": "loc_C121",
"instruction_count": 9,
"cycles_min": 77,
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"terminator": "RTS",
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{
"start": 49474,
"end": 49506,
"label": "loc_C142",
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"terminator": "RTS",
"targets": []
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"end": 6741,
"label": "loc_1A4B",
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{
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{
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"has_call": false,
"kind": "delay_loop_candidate"
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{
"start": 6844,
"end": 6853,
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"has_call": false,
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{
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"has_call": true,
"kind": "loop_with_call"
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{
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"end": 11446,
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 14643,
"end": 14687,
"label": "loc_3933",
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"back_edge_text": "SCB/F R0, loc_3933",
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"cycles_min": 87,
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"has_call": false,
"kind": "counter_delay_loop"
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{
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{
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{
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{
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"back_edge_text": "BRA loc_3F04",
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{
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{
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{
"start": 16259,
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"label": "loc_3F83",
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"has_call": false,
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{
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{
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"back_edge_text": "BSR loc_2806",
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{
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"back_edge_text": "BSR loc_3930",
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"kind": "loop_with_call"
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{
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"label": "loc_15E0",
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"back_edge_text": "BSR loc_15E0",
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{
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"label": "loc_3FB1",
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"back_edge_text": "BRA loc_3FB1",
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{
"start": 16503,
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"label": "loc_4077",
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"kind": "delay_loop_candidate"
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{
"start": 16574,
"end": 16606,
"label": "loc_40BE",
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"has_call": false,
"kind": "delay_loop_candidate"
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{
"start": 16646,
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"label": "loc_4106",
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"back_edge_text": "BNE loc_4106",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 16775,
"end": 16813,
"label": "loc_4187",
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"back_edge_text": "SCB/F R0, loc_4187",
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"cycles_min": 96,
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"has_call": true,
"kind": "counter_loop"
},
{
"start": 16853,
"end": 16915,
"label": "loc_41D5",
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"back_edge_text": "SCB/F R0, loc_41D5",
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"has_call": true,
"kind": "counter_loop"
},
{
"start": 16076,
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"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"has_call": true,
"kind": "loop_with_call"
},
{
"start": 16076,
"end": 17148,
"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 16076,
"end": 17154,
"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 16076,
"end": 17160,
"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"kind": "loop_with_call"
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{
"start": 16076,
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"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 16076,
"end": 17203,
"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 16076,
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"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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{
"start": 16076,
"end": 17221,
"label": "loc_3ECC",
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"back_edge_text": "BSR loc_3ECC",
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"kind": "loop_with_call"
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{
"start": 4302,
"end": 17224,
"label": "loc_10CE",
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"back_edge_text": "BSR loc_10CE",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 6562,
"end": 17354,
"label": "loc_19A2",
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"back_edge_text": "BSR loc_19A2",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 6709,
"end": 17366,
"label": "loc_1A35",
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"back_edge_text": "BSR loc_1A35",
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 6812,
"end": 17378,
"label": "loc_1A9C",
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"back_edge_text": "BSR loc_1A9C",
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"cycles_min": 7288,
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"has_call": true,
"kind": "loop_with_call"
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{
"start": 6884,
"end": 17390,
"label": "loc_1AE4",
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"back_edge_text": "BSR loc_1AE4",
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"kind": "loop_with_call"
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{
"start": 6923,
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"label": "loc_1B0B",
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"back_edge_text": "BSR loc_1B0B",
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"kind": "loop_with_call"
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{
"start": 6562,
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"label": "loc_19A2",
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"back_edge_text": "BSR loc_19A2",
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"kind": "loop_with_call"
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{
"start": 6709,
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"label": "loc_1A35",
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"back_edge_text": "BSR loc_1A35",
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"kind": "loop_with_call"
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{
"start": 6812,
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"label": "loc_1A9C",
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"back_edge_text": "BSR loc_1A9C",
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"kind": "loop_with_call"
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{
"start": 6884,
"end": 17585,
"label": "loc_1AE4",
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"back_edge_text": "BSR loc_1AE4",
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"kind": "loop_with_call"
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{
"start": 6923,
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"label": "loc_1B0B",
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"back_edge_text": "BSR loc_1B0B",
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"cycles_max": 8304,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 6562,
"end": 17744,
"label": "loc_19A2",
"back_edge": 17744,
"back_edge_text": "BSR loc_19A2",
"instruction_count": 1289,
"cycles_min": 8560,
"cycles_max": 9429,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 6709,
"end": 17756,
"label": "loc_1A35",
"back_edge": 17756,
"back_edge_text": "BSR loc_1A35",
"instruction_count": 1249,
"cycles_min": 8387,
"cycles_max": 9223,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 6812,
"end": 17768,
"label": "loc_1A9C",
"back_edge": 17768,
"back_edge_text": "BSR loc_1A9C",
"instruction_count": 1210,
"cycles_min": 8217,
"cycles_max": 9008,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 6884,
"end": 17780,
"label": "loc_1AE4",
"back_edge": 17780,
"back_edge_text": "BSR loc_1AE4",
"instruction_count": 1187,
"cycles_min": 8115,
"cycles_max": 8888,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 6923,
"end": 17792,
"label": "loc_1B0B",
"back_edge": 17792,
"back_edge_text": "BSR loc_1B0B",
"instruction_count": 1176,
"cycles_min": 8075,
"cycles_max": 8839,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 15956,
"end": 18726,
"label": "loc_3E54",
"back_edge": 18726,
"back_edge_text": "BSR loc_3E54",
"instruction_count": 634,
"cycles_min": 4572,
"cycles_max": 4982,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 47654,
"end": 47658,
"label": "loc_BA26",
"back_edge": 47658,
"back_edge_text": "BNE loc_BA26",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"has_call": false,
"kind": "delay_loop_candidate"
},
{
"start": 47720,
"end": 47724,
"label": "loc_BA68",
"back_edge": 47724,
"back_edge_text": "BEQ loc_BA68",
"instruction_count": 2,
"cycles_min": 10,
"cycles_max": 14,
"unknown_cycles": 0,
"has_call": false,
"kind": "delay_loop_candidate"
},
{
"start": 25094,
"end": 47886,
"label": "loc_6206",
"back_edge": 47886,
"back_edge_text": "BSR loc_6206",
"instruction_count": 110,
"cycles_min": 630,
"cycles_max": 704,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 47654,
"end": 47939,
"label": "loc_BA26",
"back_edge": 47939,
"back_edge_text": "BSR loc_BA26",
"instruction_count": 87,
"cycles_min": 548,
"cycles_max": 584,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 25131,
"end": 48129,
"label": "loc_622B",
"back_edge": 48129,
"back_edge_text": "BSR loc_622B",
"instruction_count": 169,
"cycles_min": 1021,
"cycles_max": 1112,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 48149,
"end": 48231,
"label": "loc_BC15",
"back_edge": 48231,
"back_edge_text": "BRA loc_BC15",
"instruction_count": 30,
"cycles_min": 124,
"cycles_max": 176,
"unknown_cycles": 0,
"has_call": false,
"kind": "unconditional_loop"
},
{
"start": 47654,
"end": 48333,
"label": "loc_BA26",
"back_edge": 48333,
"back_edge_text": "BSR loc_BA26",
"instruction_count": 207,
"cycles_min": 1264,
"cycles_max": 1393,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 47654,
"end": 48378,
"label": "loc_BA26",
"back_edge": 48378,
"back_edge_text": "BSR loc_BA26",
"instruction_count": 219,
"cycles_min": 1354,
"cycles_max": 1483,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 47654,
"end": 48674,
"label": "loc_BA26",
"back_edge": 48674,
"back_edge_text": "BSR loc_BA26",
"instruction_count": 313,
"cycles_min": 1938,
"cycles_max": 2140,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 47654,
"end": 48746,
"label": "loc_BA26",
"back_edge": 48746,
"back_edge_text": "BSR loc_BA26",
"instruction_count": 333,
"cycles_min": 2085,
"cycles_max": 2296,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 48768,
"end": 48783,
"label": "loc_BE80",
"back_edge": 48783,
"back_edge_text": "BRA loc_BE80",
"instruction_count": 7,
"cycles_min": 30,
"cycles_max": 38,
"unknown_cycles": 0,
"has_call": false,
"kind": "unconditional_loop"
},
{
"start": 47654,
"end": 48853,
"label": "loc_BA26",
"back_edge": 48853,
"back_edge_text": "BSR loc_BA26",
"instruction_count": 369,
"cycles_min": 2304,
"cycles_max": 2543,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 18671,
"end": 49000,
"label": "loc_48EF",
"back_edge": 49000,
"back_edge_text": "BSR loc_48EF",
"instruction_count": 479,
"cycles_min": 2952,
"cycles_max": 3296,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49125,
"end": 49143,
"label": "loc_BFE5",
"back_edge": 49143,
"back_edge_text": "BRA loc_BFE5",
"instruction_count": 9,
"cycles_min": 57,
"cycles_max": 67,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49170,
"end": 49183,
"label": "loc_C012",
"back_edge": 49183,
"back_edge_text": "BEQ loc_C012",
"instruction_count": 6,
"cycles_min": 42,
"cycles_max": 51,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49170,
"end": 49189,
"label": "loc_C012",
"back_edge": 49189,
"back_edge_text": "BEQ loc_C012",
"instruction_count": 9,
"cycles_min": 61,
"cycles_max": 75,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49170,
"end": 49197,
"label": "loc_C012",
"back_edge": 49197,
"back_edge_text": "BEQ loc_C012",
"instruction_count": 13,
"cycles_min": 84,
"cycles_max": 103,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49170,
"end": 49203,
"label": "loc_C012",
"back_edge": 49203,
"back_edge_text": "BEQ loc_C012",
"instruction_count": 16,
"cycles_min": 103,
"cycles_max": 127,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49211,
"end": 49224,
"label": "loc_C03B",
"back_edge": 49224,
"back_edge_text": "BEQ loc_C03B",
"instruction_count": 6,
"cycles_min": 41,
"cycles_max": 50,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49211,
"end": 49230,
"label": "loc_C03B",
"back_edge": 49230,
"back_edge_text": "BEQ loc_C03B",
"instruction_count": 9,
"cycles_min": 59,
"cycles_max": 72,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49211,
"end": 49241,
"label": "loc_C03B",
"back_edge": 49241,
"back_edge_text": "BEQ loc_C03B",
"instruction_count": 14,
"cycles_min": 93,
"cycles_max": 111,
"unknown_cycles": 0,
"has_call": true,
"kind": "loop_with_call"
},
{
"start": 49294,
"end": 49324,
"label": "loc_C08E",
"back_edge": 49324,
"back_edge_text": "SCB/F R1, loc_C08E",
"instruction_count": 10,
"cycles_min": 69,
"cycles_max": 78,
"unknown_cycles": 0,
"has_call": false,
"kind": "counter_delay_loop"
},
{
"start": 49379,
"end": 49411,
"label": "loc_C0E3",
"back_edge": 49411,
"back_edge_text": "SCB/F R1, loc_C0E3",
"instruction_count": 11,
"cycles_min": 64,
"cycles_max": 75,
"unknown_cycles": 0,
"has_call": false,
"kind": "counter_delay_loop"
}
]
},
"sci": {
"clock_hz": null,
"formulas": {
"async": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
"sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))"
},
"manual_references": [
"Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source",
"Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source",
"Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator",
"Manual/0900766b802125d0.md:16303 asynchronous BRR formula",
"Manual/0900766b802125d0.md:16379 synchronous BRR formula",
"Manual/0900766b802125d0.md:16410 SCI clock source selection tables"
],
"channels": {
"SCI1": {
"writes": [
{
"address": 4245,
"instruction": "MOV:G.B #H'24, @SCI1_SMR",
"channel": "SCI1",
"register": "SMR",
"register_address": 65240,
"operation": "MOV:G",
"value": 36,
"value_hex": "H'24"
},
{
"address": 4250,
"instruction": "MOV:G.B #H'3C, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "MOV:G",
"value": 60,
"value_hex": "H'3C"
},
{
"address": 4255,
"instruction": "MOV:G.B #H'07, @SCI1_BRR",
"channel": "SCI1",
"register": "BRR",
"register_address": 65241,
"operation": "MOV:G",
"value": 7,
"value_hex": "H'07"
},
{
"address": 17258,
"instruction": "BSET.B #6, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BSET",
"value": 124,
"value_hex": "H'7C"
},
{
"address": 47743,
"instruction": "BSET.B #7, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BSET",
"value": 252,
"value_hex": "H'FC"
},
{
"address": 47774,
"instruction": "BCLR.B #7, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BCLR",
"value": 124,
"value_hex": "H'7C"
},
{
"address": 47818,
"instruction": "BCLR.B #7, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BCLR",
"value": 124,
"value_hex": "H'7C"
}
],
"configurations": [
{
"channel": "SCI1",
"mode": "async",
"mode_summary": "async 8-bit even parity 1 stop",
"smr": 36,
"smr_hex": "H'24",
"brr": 7,
"brr_hex": "H'07",
"scr": 60,
"scr_hex": "H'3C",
"cks_n": 0,
"cks_divisor": 1,
"denominator": 512,
"clock_source": "internal",
"formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
"baud_bps": null,
"confidence": "partial",
"reason": "clock_hz_missing",
"comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
"address": 4255,
"instruction": "MOV:G.B #H'07, @SCI1_BRR"
}
]
},
"SCI2": {
"writes": [
{
"address": 4260,
"instruction": "MOV:G.B #H'24, @SCI2_SMR",
"channel": "SCI2",
"register": "SMR",
"register_address": 65264,
"operation": "MOV:G",
"value": 36,
"value_hex": "H'24"
},
{
"address": 4265,
"instruction": "MOV:G.B #H'0C, @SCI2_SCR",
"channel": "SCI2",
"register": "SCR",
"register_address": 65266,
"operation": "MOV:G",
"value": 12,
"value_hex": "H'0C"
},
{
"address": 4270,
"instruction": "MOV:G.B #H'07, @SCI2_BRR",
"channel": "SCI2",
"register": "BRR",
"register_address": 65265,
"operation": "MOV:G",
"value": 7,
"value_hex": "H'07"
}
],
"configurations": [
{
"channel": "SCI2",
"mode": "async",
"mode_summary": "async 8-bit even parity 1 stop",
"smr": 36,
"smr_hex": "H'24",
"brr": 7,
"brr_hex": "H'07",
"scr": 12,
"scr_hex": "H'0C",
"cks_n": 0,
"cks_divisor": 1,
"denominator": 512,
"clock_source": "internal",
"formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
"baud_bps": null,
"confidence": "partial",
"reason": "clock_hz_missing",
"comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
"address": 4270,
"instruction": "MOV:G.B #H'07, @SCI2_BRR"
}
]
}
}
},
"peripheral_access": {
"manual_references": [
"Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access",
"Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte",
"Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP",
"Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP",
"Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte"
],
"warnings": []
},
"instructions": [
{
"address": 4096,
"address_region": "program_or_external",
"bytes": "5FFE80",
"text": "MOV:I.W #H'FE80, R7",
"mnemonic": "MOV:I.W",
"operands": "#H'FE80, R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4099,
"address_region": "program_or_external",
"bytes": "0C070088",
"text": "LDC.W #H'0700, SR",
"mnemonic": "LDC.W",
"operands": "#H'0700, SR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4103,
"address_region": "program_or_external",
"bytes": "15FE8006FF",
"text": "MOV:G.B #H'FF, @P1DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @P1DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65152,
"name": "P1DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P1DDR = H'FF",
"valid": true
},
{
"address": 4108,
"address_region": "program_or_external",
"bytes": "15FE820600",
"text": "MOV:G.B #H'00, @P1DR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @P1DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65154,
"name": "P1DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P1DR = H'00",
"valid": true
},
{
"address": 4113,
"address_region": "program_or_external",
"bytes": "15FE8906F9",
"text": "MOV:G.B #H'F9, @P6DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'F9, @P6DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65161,
"name": "P6DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P6DDR = H'F9",
"valid": true
},
{
"address": 4118,
"address_region": "program_or_external",
"bytes": "15FE8B06F1",
"text": "MOV:G.B #H'F1, @P6DR",
"mnemonic": "MOV:G.B",
"operands": "#H'F1, @P6DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65163,
"name": "P6DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P6DR = H'F1",
"valid": true
},
{
"address": 4123,
"address_region": "program_or_external",
"bytes": "15FE8C0600",
"text": "MOV:G.B #H'00, @P7DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @P7DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65164,
"name": "P7DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P7DDR = H'00",
"valid": true
},
{
"address": 4128,
"address_region": "program_or_external",
"bytes": "15FE8E0600",
"text": "MOV:G.B #H'00, @P7DR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @P7DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P7DR = H'00",
"valid": true
},
{
"address": 4133,
"address_region": "program_or_external",
"bytes": "15FEFE0693",
"text": "MOV:G.B #H'93, @P9DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'93, @P9DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65278,
"name": "P9DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DDR = H'93",
"valid": true
},
{
"address": 4138,
"address_region": "program_or_external",
"bytes": "15FEFF0600",
"text": "MOV:G.B #H'00, @P9DR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DR = H'00",
"valid": true
},
{
"address": 4143,
"address_region": "program_or_external",
"bytes": "15FEFC0687",
"text": "MOV:G.B #H'87, @SYSCR1",
"mnemonic": "MOV:G.B",
"operands": "#H'87, @SYSCR1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65276,
"name": "SYSCR1",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled)",
"valid": true
},
{
"address": 4148,
"address_region": "program_or_external",
"bytes": "15FEFD0684",
"text": "MOV:G.B #H'84, @SYSCR2",
"mnemonic": "MOV:G.B",
"operands": "#H'84, @SYSCR2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65277,
"name": "SYSCR2",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM)",
"valid": true
},
{
"address": 4153,
"address_region": "program_or_external",
"bytes": "15FE900602",
"text": "MOV:G.B #H'02, @FRT1_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'02, @FRT1_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65168,
"name": "FRT1_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)",
"valid": true
},
{
"address": 4158,
"address_region": "program_or_external",
"bytes": "15FE910601",
"text": "MOV:G.B #H'01, @FRT1_TCSR",
"mnemonic": "MOV:G.B",
"operands": "#H'01, @FRT1_TCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65169,
"name": "FRT1_TCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)",
"valid": true
},
{
"address": 4163,
"address_region": "program_or_external",
"bytes": "1DFE920600",
"text": "MOV:G.W #H'00, @FRT1_FRC_H",
"mnemonic": "MOV:G.W",
"operands": "#H'00, @FRT1_FRC_H",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65170,
"name": "FRT1_FRC_H",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT1_FRC_H = H'00",
"valid": true,
"peripheral_access": [
{
"address": 4163,
"instruction": "MOV:G.W #H'00, @FRT1_FRC_H",
"register": "FRT1_FRC",
"high_address": 65170,
"low_address": 65171,
"referenced_address": 65170,
"referenced_address_hex": "H'FE92",
"byte": "high",
"size": "W",
"direction": "write"
}
]
},
{
"address": 4168,
"address_region": "program_or_external",
"bytes": "1DFE9407009C",
"text": "MOV:G.W #H'009C, @FRT1_OCRA_H",
"mnemonic": "MOV:G.W",
"operands": "#H'009C, @FRT1_OCRA_H",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65172,
"name": "FRT1_OCRA_H",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT1_OCRA_H = H'9C",
"valid": true,
"peripheral_access": [
{
"address": 4168,
"instruction": "MOV:G.W #H'009C, @FRT1_OCRA_H",
"register": "FRT1_OCRA",
"high_address": 65172,
"low_address": 65173,
"referenced_address": 65172,
"referenced_address_hex": "H'FE94",
"byte": "high",
"size": "W",
"direction": "write"
}
]
},
{
"address": 4174,
"address_region": "program_or_external",
"bytes": "15FEA00602",
"text": "MOV:G.B #H'02, @FRT2_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'02, @FRT2_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65184,
"name": "FRT2_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)",
"valid": true
},
{
"address": 4179,
"address_region": "program_or_external",
"bytes": "15FEA10601",
"text": "MOV:G.B #H'01, @FRT2_TCSR",
"mnemonic": "MOV:G.B",
"operands": "#H'01, @FRT2_TCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65185,
"name": "FRT2_TCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)",
"valid": true
},
{
"address": 4184,
"address_region": "program_or_external",
"bytes": "1DFEA20600",
"text": "MOV:G.W #H'00, @FRT2_FRC_H",
"mnemonic": "MOV:G.W",
"operands": "#H'00, @FRT2_FRC_H",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65186,
"name": "FRT2_FRC_H",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT2_FRC_H = H'00",
"valid": true,
"peripheral_access": [
{
"address": 4184,
"instruction": "MOV:G.W #H'00, @FRT2_FRC_H",
"register": "FRT2_FRC",
"high_address": 65186,
"low_address": 65187,
"referenced_address": 65186,
"referenced_address_hex": "H'FEA2",
"byte": "high",
"size": "W",
"direction": "write"
}
]
},
{
"address": 4189,
"address_region": "program_or_external",
"bytes": "1DFEA4077A12",
"text": "MOV:G.W #H'7A12, @FRT2_OCRA_H",
"mnemonic": "MOV:G.W",
"operands": "#H'7A12, @FRT2_OCRA_H",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65188,
"name": "FRT2_OCRA_H",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT2_OCRA_H = H'7A12",
"valid": true,
"peripheral_access": [
{
"address": 4189,
"instruction": "MOV:G.W #H'7A12, @FRT2_OCRA_H",
"register": "FRT2_OCRA",
"high_address": 65188,
"low_address": 65189,
"referenced_address": 65188,
"referenced_address_hex": "H'FEA4",
"byte": "high",
"size": "W",
"direction": "write"
}
]
},
{
"address": 4195,
"address_region": "program_or_external",
"bytes": "15FEB00600",
"text": "MOV:G.B #H'00, @FRT3_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @FRT3_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65200,
"name": "FRT3_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0)",
"valid": true
},
{
"address": 4200,
"address_region": "program_or_external",
"bytes": "15FEB10600",
"text": "MOV:G.B #H'00, @FRT3_TCSR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @FRT3_TCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65201,
"name": "FRT3_TCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0)",
"valid": true
},
{
"address": 4205,
"address_region": "program_or_external",
"bytes": "15FED00600",
"text": "MOV:G.B #H'00, @TMR_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @TMR_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65232,
"name": "TMR_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0)",
"valid": true
},
{
"address": 4210,
"address_region": "program_or_external",
"bytes": "15FED10610",
"text": "MOV:G.B #H'10, @TMR_TCSR",
"mnemonic": "MOV:G.B",
"operands": "#H'10, @TMR_TCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65233,
"name": "TMR_TCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0)",
"valid": true
},
{
"address": 4215,
"address_region": "program_or_external",
"bytes": "15FEC00638",
"text": "MOV:G.B #H'38, @PWM1_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'38, @PWM1_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65216,
"name": "PWM1_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)",
"valid": true
},
{
"address": 4220,
"address_region": "program_or_external",
"bytes": "15FEC106FF",
"text": "MOV:G.B #H'FF, @PWM1_DTR",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @PWM1_DTR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65217,
"name": "PWM1_DTR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "PWM1_DTR = H'FF",
"valid": true
},
{
"address": 4225,
"address_region": "program_or_external",
"bytes": "15FEC40638",
"text": "MOV:G.B #H'38, @PWM2_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'38, @PWM2_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65220,
"name": "PWM2_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)",
"valid": true
},
{
"address": 4230,
"address_region": "program_or_external",
"bytes": "15FEC506FF",
"text": "MOV:G.B #H'FF, @PWM2_DTR",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @PWM2_DTR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65221,
"name": "PWM2_DTR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "PWM2_DTR = H'FF",
"valid": true
},
{
"address": 4235,
"address_region": "program_or_external",
"bytes": "15FEC8063B",
"text": "MOV:G.B #H'3B, @PWM3_TCR",
"mnemonic": "MOV:G.B",
"operands": "#H'3B, @PWM3_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65224,
"name": "PWM3_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1)",
"valid": true
},
{
"address": 4240,
"address_region": "program_or_external",
"bytes": "15FEC9067D",
"text": "MOV:G.B #H'7D, @PWM3_DTR",
"mnemonic": "MOV:G.B",
"operands": "#H'7D, @PWM3_DTR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65225,
"name": "PWM3_DTR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "PWM3_DTR = H'7D",
"valid": true
},
{
"address": 4245,
"address_region": "program_or_external",
"bytes": "15FED80624",
"text": "MOV:G.B #H'24, @SCI1_SMR",
"mnemonic": "MOV:G.B",
"operands": "#H'24, @SCI1_SMR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65240,
"name": "SCI1_SMR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)",
"valid": true,
"sci": {
"writes": [
{
"address": 4245,
"instruction": "MOV:G.B #H'24, @SCI1_SMR",
"channel": "SCI1",
"register": "SMR",
"register_address": 65240,
"operation": "MOV:G",
"value": 36,
"value_hex": "H'24"
}
]
}
},
{
"address": 4250,
"address_region": "program_or_external",
"bytes": "15FEDA063C",
"text": "MOV:G.B #H'3C, @SCI1_SCR",
"mnemonic": "MOV:G.B",
"operands": "#H'3C, @SCI1_SCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65242,
"name": "SCI1_SCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock)",
"valid": true,
"sci": {
"writes": [
{
"address": 4250,
"instruction": "MOV:G.B #H'3C, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "MOV:G",
"value": 60,
"value_hex": "H'3C"
}
]
}
},
{
"address": 4255,
"address_region": "program_or_external",
"bytes": "15FED90607",
"text": "MOV:G.B #H'07, @SCI1_BRR",
"mnemonic": "MOV:G.B",
"operands": "#H'07, @SCI1_BRR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65241,
"name": "SCI1_BRR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI1_BRR = H'07",
"valid": true,
"sci": {
"writes": [
{
"address": 4255,
"instruction": "MOV:G.B #H'07, @SCI1_BRR",
"channel": "SCI1",
"register": "BRR",
"register_address": 65241,
"operation": "MOV:G",
"value": 7,
"value_hex": "H'07"
}
],
"inferences": [
{
"channel": "SCI1",
"mode": "async",
"mode_summary": "async 8-bit even parity 1 stop",
"smr": 36,
"smr_hex": "H'24",
"brr": 7,
"brr_hex": "H'07",
"scr": 60,
"scr_hex": "H'3C",
"cks_n": 0,
"cks_divisor": 1,
"denominator": 512,
"clock_source": "internal",
"formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
"baud_bps": null,
"confidence": "partial",
"reason": "clock_hz_missing",
"comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
"address": 4255,
"instruction": "MOV:G.B #H'07, @SCI1_BRR"
}
]
}
},
{
"address": 4260,
"address_region": "program_or_external",
"bytes": "15FEF00624",
"text": "MOV:G.B #H'24, @SCI2_SMR",
"mnemonic": "MOV:G.B",
"operands": "#H'24, @SCI2_SMR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65264,
"name": "SCI2_SMR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)",
"valid": true,
"sci": {
"writes": [
{
"address": 4260,
"instruction": "MOV:G.B #H'24, @SCI2_SMR",
"channel": "SCI2",
"register": "SMR",
"register_address": 65264,
"operation": "MOV:G",
"value": 36,
"value_hex": "H'24"
}
]
}
},
{
"address": 4265,
"address_region": "program_or_external",
"bytes": "15FEF2060C",
"text": "MOV:G.B #H'0C, @SCI2_SCR",
"mnemonic": "MOV:G.B",
"operands": "#H'0C, @SCI2_SCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65266,
"name": "SCI2_SCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock)",
"valid": true,
"sci": {
"writes": [
{
"address": 4265,
"instruction": "MOV:G.B #H'0C, @SCI2_SCR",
"channel": "SCI2",
"register": "SCR",
"register_address": 65266,
"operation": "MOV:G",
"value": 12,
"value_hex": "H'0C"
}
]
}
},
{
"address": 4270,
"address_region": "program_or_external",
"bytes": "15FEF10607",
"text": "MOV:G.B #H'07, @SCI2_BRR",
"mnemonic": "MOV:G.B",
"operands": "#H'07, @SCI2_BRR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65265,
"name": "SCI2_BRR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI2_BRR = H'07",
"valid": true,
"sci": {
"writes": [
{
"address": 4270,
"instruction": "MOV:G.B #H'07, @SCI2_BRR",
"channel": "SCI2",
"register": "BRR",
"register_address": 65265,
"operation": "MOV:G",
"value": 7,
"value_hex": "H'07"
}
],
"inferences": [
{
"channel": "SCI2",
"mode": "async",
"mode_summary": "async 8-bit even parity 1 stop",
"smr": 36,
"smr_hex": "H'24",
"brr": 7,
"brr_hex": "H'07",
"scr": 12,
"scr_hex": "H'0C",
"cks_n": 0,
"cks_divisor": 1,
"denominator": 512,
"clock_source": "internal",
"formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
"baud_bps": null,
"confidence": "partial",
"reason": "clock_hz_missing",
"comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
"address": 4270,
"instruction": "MOV:G.B #H'07, @SCI2_BRR"
}
]
}
},
{
"address": 4275,
"address_region": "program_or_external",
"bytes": "15FEE80619",
"text": "MOV:G.B #H'19, @ADCSR",
"mnemonic": "MOV:G.B",
"operands": "#H'19, @ADCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65256,
"name": "ADCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled)",
"valid": true
},
{
"address": 4280,
"address_region": "program_or_external",
"bytes": "15FEE9067F",
"text": "MOV:G.B #H'7F, @H'FEE9",
"mnemonic": "MOV:G.B",
"operands": "#H'7F, @H'FEE9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65257,
"name": null,
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 4285,
"address_region": "program_or_external",
"bytes": "15FF1006F0",
"text": "MOV:G.B #H'F0, @WCR",
"mnemonic": "MOV:G.B",
"operands": "#H'F0, @WCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65296,
"name": "WCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits)",
"valid": true
},
{
"address": 4290,
"address_region": "program_or_external",
"bytes": "15FF1106FF",
"text": "MOV:G.B #H'FF, @RAMCR",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @RAMCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65297,
"name": "RAMCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "RAMCR = H'FF (RAME=1; on-chip RAM enabled)",
"valid": true
},
{
"address": 4295,
"address_region": "program_or_external",
"bytes": "15FE82D7",
"text": "BCLR.B #7, @P1DR",
"mnemonic": "BCLR.B",
"operands": "#7, @P1DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65154,
"name": "P1DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 7 of P1DR",
"valid": true
},
{
"address": 4299,
"address_region": "program_or_external",
"bytes": "302EA8",
"text": "BRA loc_3F76",
"mnemonic": "BRA",
"operands": "loc_3F76",
"kind": "jump",
"targets": [
16246
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4302,
"address_region": "program_or_external",
"bytes": "5C0040",
"text": "MOV:I.W #H'0040, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0040, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4305,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4308,
"address_region": "program_or_external",
"bytes": "1E2DF5",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4311,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4314,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4317,
"address_region": "program_or_external",
"bytes": "1E2DEC",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4320,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4323,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4326,
"address_region": "program_or_external",
"bytes": "1E2DE3",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4329,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4332,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4335,
"address_region": "program_or_external",
"bytes": "1E2DDA",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4338,
"address_region": "program_or_external",
"bytes": "5C0207",
"text": "MOV:I.W #H'0207, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0207, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4341,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4344,
"address_region": "program_or_external",
"bytes": "1E2DD1",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4347,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4350,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4353,
"address_region": "program_or_external",
"bytes": "1E2DC8",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4356,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4359,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4362,
"address_region": "program_or_external",
"bytes": "1E2DBF",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4365,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4368,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4371,
"address_region": "program_or_external",
"bytes": "1E2DB6",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4374,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4377,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4380,
"address_region": "program_or_external",
"bytes": "1E2DAD",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4383,
"address_region": "program_or_external",
"bytes": "5C0048",
"text": "MOV:I.W #H'0048, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0048, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4386,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4389,
"address_region": "program_or_external",
"bytes": "1E2DA4",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4392,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4395,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4398,
"address_region": "program_or_external",
"bytes": "1E2D9B",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4401,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4404,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4407,
"address_region": "program_or_external",
"bytes": "1E2D92",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4410,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4413,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4416,
"address_region": "program_or_external",
"bytes": "1E2D89",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4419,
"address_region": "program_or_external",
"bytes": "5C021B",
"text": "MOV:I.W #H'021B, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'021B, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4422,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4425,
"address_region": "program_or_external",
"bytes": "1E2D80",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4428,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4431,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4434,
"address_region": "program_or_external",
"bytes": "1E2D77",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4437,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4440,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4443,
"address_region": "program_or_external",
"bytes": "1E2D6E",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4446,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4449,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4452,
"address_region": "program_or_external",
"bytes": "1E2D65",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4455,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4458,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4461,
"address_region": "program_or_external",
"bytes": "1E2D5C",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4464,
"address_region": "program_or_external",
"bytes": "5C0050",
"text": "MOV:I.W #H'0050, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0050, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4467,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4470,
"address_region": "program_or_external",
"bytes": "1E2D53",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4473,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4476,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4479,
"address_region": "program_or_external",
"bytes": "1E2D4A",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4482,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4485,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4488,
"address_region": "program_or_external",
"bytes": "1E2D41",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4491,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4494,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4497,
"address_region": "program_or_external",
"bytes": "1E2D38",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4500,
"address_region": "program_or_external",
"bytes": "5C021C",
"text": "MOV:I.W #H'021C, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'021C, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4503,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4506,
"address_region": "program_or_external",
"bytes": "1E2D2F",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4509,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4512,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4515,
"address_region": "program_or_external",
"bytes": "1E2D26",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4518,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4521,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4524,
"address_region": "program_or_external",
"bytes": "1E2D1D",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4527,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4530,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4533,
"address_region": "program_or_external",
"bytes": "1E2D14",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4536,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4539,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4542,
"address_region": "program_or_external",
"bytes": "1E2D0B",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4545,
"address_region": "program_or_external",
"bytes": "5C0058",
"text": "MOV:I.W #H'0058, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0058, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4548,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4551,
"address_region": "program_or_external",
"bytes": "1E2D02",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4554,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4557,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4560,
"address_region": "program_or_external",
"bytes": "1E2CF9",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4563,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4566,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4569,
"address_region": "program_or_external",
"bytes": "1E2CF0",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4572,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4575,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4578,
"address_region": "program_or_external",
"bytes": "1E2CE7",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4581,
"address_region": "program_or_external",
"bytes": "5C0207",
"text": "MOV:I.W #H'0207, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0207, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4584,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4587,
"address_region": "program_or_external",
"bytes": "1E2CDE",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4590,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4593,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4596,
"address_region": "program_or_external",
"bytes": "1E2CD5",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4599,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4602,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4605,
"address_region": "program_or_external",
"bytes": "1E2CCC",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4608,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4611,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4614,
"address_region": "program_or_external",
"bytes": "1E2CC3",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4617,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4620,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4623,
"address_region": "program_or_external",
"bytes": "1E2CBA",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4626,
"address_region": "program_or_external",
"bytes": "5C0060",
"text": "MOV:I.W #H'0060, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0060, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4629,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4632,
"address_region": "program_or_external",
"bytes": "1E2CB1",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4635,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4638,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4641,
"address_region": "program_or_external",
"bytes": "1E2CA8",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4644,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4647,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4650,
"address_region": "program_or_external",
"bytes": "1E2C9F",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4653,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4656,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4659,
"address_region": "program_or_external",
"bytes": "1E2C96",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4662,
"address_region": "program_or_external",
"bytes": "5C021B",
"text": "MOV:I.W #H'021B, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'021B, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4665,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4668,
"address_region": "program_or_external",
"bytes": "1E2C8D",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4671,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4674,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4677,
"address_region": "program_or_external",
"bytes": "1E2C84",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4680,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4683,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4686,
"address_region": "program_or_external",
"bytes": "1E2C7B",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4689,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4692,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4695,
"address_region": "program_or_external",
"bytes": "1E2C72",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4698,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4701,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4704,
"address_region": "program_or_external",
"bytes": "1E2C69",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4707,
"address_region": "program_or_external",
"bytes": "5C0068",
"text": "MOV:I.W #H'0068, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0068, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4710,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4713,
"address_region": "program_or_external",
"bytes": "1E2C60",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4716,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4719,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4722,
"address_region": "program_or_external",
"bytes": "1E2C57",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4725,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4728,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4731,
"address_region": "program_or_external",
"bytes": "1E2C4E",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4734,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4737,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4740,
"address_region": "program_or_external",
"bytes": "1E2C45",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4743,
"address_region": "program_or_external",
"bytes": "5C021C",
"text": "MOV:I.W #H'021C, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'021C, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4746,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4749,
"address_region": "program_or_external",
"bytes": "1E2C3C",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4752,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4755,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4758,
"address_region": "program_or_external",
"bytes": "1E2C33",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4761,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4764,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4767,
"address_region": "program_or_external",
"bytes": "1E2C2A",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4770,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4773,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4776,
"address_region": "program_or_external",
"bytes": "1E2C21",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4779,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4782,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4785,
"address_region": "program_or_external",
"bytes": "1E2C18",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4788,
"address_region": "program_or_external",
"bytes": "5C0070",
"text": "MOV:I.W #H'0070, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0070, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4791,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4794,
"address_region": "program_or_external",
"bytes": "1E2C0F",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4797,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4800,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4803,
"address_region": "program_or_external",
"bytes": "1E2C06",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4806,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4809,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4812,
"address_region": "program_or_external",
"bytes": "1E2BFD",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4815,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4818,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4821,
"address_region": "program_or_external",
"bytes": "1E2BF4",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4824,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4827,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4830,
"address_region": "program_or_external",
"bytes": "1E2BEB",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4833,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4836,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4839,
"address_region": "program_or_external",
"bytes": "1E2BE2",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4842,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4845,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4848,
"address_region": "program_or_external",
"bytes": "1E2BD9",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4851,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4854,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4857,
"address_region": "program_or_external",
"bytes": "1E2BD0",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4860,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4863,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4866,
"address_region": "program_or_external",
"bytes": "1E2BC7",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4869,
"address_region": "program_or_external",
"bytes": "5C0078",
"text": "MOV:I.W #H'0078, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0078, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4872,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4875,
"address_region": "program_or_external",
"bytes": "1E2BBE",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4878,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4881,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4884,
"address_region": "program_or_external",
"bytes": "1E2BB5",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4887,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4890,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4893,
"address_region": "program_or_external",
"bytes": "1E2BAC",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4896,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4899,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4902,
"address_region": "program_or_external",
"bytes": "1E2BA3",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4905,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4908,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4911,
"address_region": "program_or_external",
"bytes": "1E2B9A",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4914,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4917,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4920,
"address_region": "program_or_external",
"bytes": "1E2B91",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4923,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4926,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4929,
"address_region": "program_or_external",
"bytes": "1E2B88",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4932,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4935,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4938,
"address_region": "program_or_external",
"bytes": "1E2B7F",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4941,
"address_region": "program_or_external",
"bytes": "5C0204",
"text": "MOV:I.W #H'0204, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0204, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4944,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4947,
"address_region": "program_or_external",
"bytes": "1E2B76",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 4950,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5600,
"address_region": "program_or_external",
"bytes": "1E106D",
"text": "BSR loc_2650",
"mnemonic": "BSR",
"operands": "loc_2650",
"kind": "call",
"targets": [
9808
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5603,
"address_region": "program_or_external",
"bytes": "15F689D7",
"text": "BCLR.B #7, @H'F689",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F689",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63113,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5607,
"address_region": "program_or_external",
"bytes": "2710",
"text": "BEQ loc_15F9",
"mnemonic": "BEQ",
"operands": "loc_15F9",
"kind": "branch",
"targets": [
5625
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5609,
"address_region": "program_or_external",
"bytes": "1DF68E81",
"text": "MOV:G.W @H'F68E, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F68E, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63118,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5613,
"address_region": "program_or_external",
"bytes": "1DE90291",
"text": "MOV:G.W R1, @H'E902",
"mnemonic": "MOV:G.W",
"operands": "R1, @H'E902",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 59650,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 5617,
"address_region": "program_or_external",
"bytes": "5280",
"text": "MOV:E.B #H'80, R2",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5619,
"address_region": "program_or_external",
"bytes": "5B0081",
"text": "MOV:I.W #H'0081, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'0081, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5622,
"address_region": "program_or_external",
"bytes": "1E285B",
"text": "BSR loc_3E54",
"mnemonic": "BSR",
"operands": "loc_3E54",
"kind": "call",
"targets": [
15956
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5625,
"address_region": "program_or_external",
"bytes": "15F6F016",
"text": "TST.B @H'F6F0",
"mnemonic": "TST.B",
"operands": "@H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5629,
"address_region": "program_or_external",
"bytes": "273E",
"text": "BEQ loc_163D",
"mnemonic": "BEQ",
"operands": "loc_163D",
"kind": "branch",
"targets": [
5693
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5631,
"address_region": "program_or_external",
"bytes": "15F6F0D7",
"text": "BCLR.B #7, @H'F6F0",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5635,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_1608",
"mnemonic": "BEQ",
"operands": "loc_1608",
"kind": "branch",
"targets": [
5640
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5637,
"address_region": "program_or_external",
"bytes": "184394",
"text": "JSR @loc_4394",
"mnemonic": "JSR",
"operands": "@loc_4394",
"kind": "call",
"targets": [
17300
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5640,
"address_region": "program_or_external",
"bytes": "15F6F0D6",
"text": "BCLR.B #6, @H'F6F0",
"mnemonic": "BCLR.B",
"operands": "#6, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5644,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_1611",
"mnemonic": "BEQ",
"operands": "loc_1611",
"kind": "branch",
"targets": [
5649
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5646,
"address_region": "program_or_external",
"bytes": "184457",
"text": "JSR @loc_4457",
"mnemonic": "JSR",
"operands": "@loc_4457",
"kind": "call",
"targets": [
17495
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5649,
"address_region": "program_or_external",
"bytes": "15F6F0D5",
"text": "BCLR.B #5, @H'F6F0",
"mnemonic": "BCLR.B",
"operands": "#5, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5653,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_161A",
"mnemonic": "BEQ",
"operands": "loc_161A",
"kind": "branch",
"targets": [
5658
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5655,
"address_region": "program_or_external",
"bytes": "18451A",
"text": "JSR @loc_451A",
"mnemonic": "JSR",
"operands": "@loc_451A",
"kind": "call",
"targets": [
17690
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5658,
"address_region": "program_or_external",
"bytes": "15F6F0D4",
"text": "BCLR.B #4, @H'F6F0",
"mnemonic": "BCLR.B",
"operands": "#4, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5662,
"address_region": "program_or_external",
"bytes": "15F6F0D3",
"text": "BCLR.B #3, @H'F6F0",
"mnemonic": "BCLR.B",
"operands": "#3, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5666,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_1627",
"mnemonic": "BEQ",
"operands": "loc_1627",
"kind": "branch",
"targets": [
5671
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5668,
"address_region": "program_or_external",
"bytes": "181705",
"text": "JSR @loc_1705",
"mnemonic": "JSR",
"operands": "@loc_1705",
"kind": "call",
"targets": [
5893
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5671,
"address_region": "program_or_external",
"bytes": "15F6F0D2",
"text": "BCLR.B #2, @H'F6F0",
"mnemonic": "BCLR.B",
"operands": "#2, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
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},
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{
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{
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{
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},
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{
"address": 5787,
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"bytes": "181B44",
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"references": [],
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"valid": true
},
{
"address": 5790,
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"text": "BCLR.B #5, @H'F6F2",
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"operands": "#5, @H'F6F2",
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"address": 63218,
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"address": 5794,
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"bytes": "2703",
"text": "BEQ loc_16A7",
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},
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{
"address": 5796,
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{
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},
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{
"address": 5805,
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}
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},
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{
"address": 5814,
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"kind": "call",
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{
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"kind": "ram"
}
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{
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},
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"valid": true
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{
"address": 5823,
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"valid": true
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{
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"address": 63218,
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}
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{
"address": 5830,
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},
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"valid": true
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{
"address": 5832,
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7026
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"valid": true
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{
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},
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}
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{
"address": 5839,
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},
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{
"address": 5841,
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},
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"valid": true
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{
"address": 5844,
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"address": 63219,
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}
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{
"address": 5848,
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"taken": 7,
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},
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"valid": true
},
{
"address": 5850,
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}
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{
"address": 5854,
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}
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},
{
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}
],
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},
{
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}
],
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},
{
"address": 5866,
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},
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},
{
"address": 5868,
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"kind": "call",
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},
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{
"address": 5871,
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},
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}
],
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{
"address": 5875,
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},
"references": [],
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},
{
"address": 5877,
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},
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{
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},
"references": [
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"region": "on_chip_ram",
"kind": "ram"
}
],
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"valid": true
},
{
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},
"references": [
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}
],
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},
{
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},
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}
],
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},
{
"address": 5892,
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},
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},
{
"address": 5893,
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},
"references": [
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}
],
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},
{
"address": 5898,
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},
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},
{
"address": 5900,
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"references": [
{
"address": 57678,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 5904,
"address_region": "program_or_external",
"bytes": "2624",
"text": "BNE loc_1736",
"mnemonic": "BNE",
"operands": "loc_1736",
"kind": "branch",
"targets": [
5942
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5906,
"address_region": "program_or_external",
"bytes": "15F730F6",
"text": "BTST.B #6, @H'F730",
"mnemonic": "BTST.B",
"operands": "#6, @H'F730",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63280,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5910,
"address_region": "program_or_external",
"bytes": "261E",
"text": "BNE loc_1736",
"mnemonic": "BNE",
"operands": "loc_1736",
"kind": "branch",
"targets": [
5942
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5912,
"address_region": "program_or_external",
"bytes": "15FB03C7",
"text": "BSET.B #7, @H'FB03",
"mnemonic": "BSET.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5916,
"address_region": "program_or_external",
"bytes": "2608",
"text": "BNE loc_1726",
"mnemonic": "BNE",
"operands": "loc_1726",
"kind": "branch",
"targets": [
5926
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5918,
"address_region": "program_or_external",
"bytes": "1DF73281",
"text": "MOV:G.W @H'F732, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F732, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5922,
"address_region": "program_or_external",
"bytes": "1DF73491",
"text": "MOV:G.W R1, @H'F734",
"mnemonic": "MOV:G.W",
"operands": "R1, @H'F734",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63284,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5926,
"address_region": "program_or_external",
"bytes": "1DF732071C07",
"text": "MOV:G.W #H'1C07, @H'F732",
"mnemonic": "MOV:G.W",
"operands": "#H'1C07, @H'F732",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5932,
"address_region": "program_or_external",
"bytes": "15FB020614",
"text": "MOV:G.B #H'14, @H'FB02",
"mnemonic": "MOV:G.B",
"operands": "#H'14, @H'FB02",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5937,
"address_region": "program_or_external",
"bytes": "1E31C6",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5940,
"address_region": "program_or_external",
"bytes": "200E",
"text": "BRA loc_1744",
"mnemonic": "BRA",
"operands": "loc_1744",
"kind": "jump",
"targets": [
5956
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5942,
"address_region": "program_or_external",
"bytes": "1DF69684",
"text": "MOV:G.W @H'F696, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F696, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63126,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5946,
"address_region": "program_or_external",
"bytes": "1DF6B634",
"text": "SUB.W @H'F6B6, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6B6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63158,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5950,
"address_region": "program_or_external",
"bytes": "5B00A9",
"text": "MOV:I.W #H'00A9, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00A9, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5953,
"address_region": "program_or_external",
"bytes": "1E025E",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5956,
"address_region": "program_or_external",
"bytes": "1DF69684",
"text": "MOV:G.W @H'F696, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F696, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63126,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5960,
"address_region": "program_or_external",
"bytes": "1DF6B694",
"text": "MOV:G.W R4, @H'F6B6",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6B6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63158,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5964,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5965,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5970,
"address_region": "program_or_external",
"bytes": "2238",
"text": "BHI loc_178C",
"mnemonic": "BHI",
"operands": "loc_178C",
"kind": "branch",
"targets": [
6028
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5972,
"address_region": "program_or_external",
"bytes": "15F730F7",
"text": "BTST.B #7, @H'F730",
"mnemonic": "BTST.B",
"operands": "#7, @H'F730",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63280,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5976,
"address_region": "program_or_external",
"bytes": "2732",
"text": "BEQ loc_178C",
"mnemonic": "BEQ",
"operands": "loc_178C",
"kind": "branch",
"targets": [
6028
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5978,
"address_region": "program_or_external",
"bytes": "1DE16EFD",
"text": "BTST.W #13, @H'E16E",
"mnemonic": "BTST.W",
"operands": "#13, @H'E16E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57710,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 5982,
"address_region": "program_or_external",
"bytes": "261E",
"text": "BNE loc_177E",
"mnemonic": "BNE",
"operands": "loc_177E",
"kind": "branch",
"targets": [
6014
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5984,
"address_region": "program_or_external",
"bytes": "15FB03C7",
"text": "BSET.B #7, @H'FB03",
"mnemonic": "BSET.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5988,
"address_region": "program_or_external",
"bytes": "2608",
"text": "BNE loc_176E",
"mnemonic": "BNE",
"operands": "loc_176E",
"kind": "branch",
"targets": [
5998
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 5990,
"address_region": "program_or_external",
"bytes": "1DF73281",
"text": "MOV:G.W @H'F732, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F732, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5994,
"address_region": "program_or_external",
"bytes": "1DF73491",
"text": "MOV:G.W R1, @H'F734",
"mnemonic": "MOV:G.W",
"operands": "R1, @H'F734",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63284,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 5998,
"address_region": "program_or_external",
"bytes": "1DF732071C06",
"text": "MOV:G.W #H'1C06, @H'F732",
"mnemonic": "MOV:G.W",
"operands": "#H'1C06, @H'F732",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6004,
"address_region": "program_or_external",
"bytes": "15FB020614",
"text": "MOV:G.B #H'14, @H'FB02",
"mnemonic": "MOV:G.B",
"operands": "#H'14, @H'FB02",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6009,
"address_region": "program_or_external",
"bytes": "1E317E",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6012,
"address_region": "program_or_external",
"bytes": "200E",
"text": "BRA loc_178C",
"mnemonic": "BRA",
"operands": "loc_178C",
"kind": "jump",
"targets": [
6028
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6014,
"address_region": "program_or_external",
"bytes": "1DF69484",
"text": "MOV:G.W @H'F694, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F694, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63124,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6018,
"address_region": "program_or_external",
"bytes": "1DF6B434",
"text": "SUB.W @H'F6B4, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6B4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63156,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6022,
"address_region": "program_or_external",
"bytes": "5B00C5",
"text": "MOV:I.W #H'00C5, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00C5, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6025,
"address_region": "program_or_external",
"bytes": "1E0216",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6028,
"address_region": "program_or_external",
"bytes": "1DF69484",
"text": "MOV:G.W @H'F694, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F694, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63124,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6032,
"address_region": "program_or_external",
"bytes": "1DF6B494",
"text": "MOV:G.W R4, @H'F6B4",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6B4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63156,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6036,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6037,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6042,
"address_region": "program_or_external",
"bytes": "2224",
"text": "BHI loc_17C0",
"mnemonic": "BHI",
"operands": "loc_17C0",
"kind": "branch",
"targets": [
6080
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6044,
"address_region": "program_or_external",
"bytes": "1DE172FD",
"text": "BTST.W #13, @H'E172",
"mnemonic": "BTST.W",
"operands": "#13, @H'E172",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57714,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6048,
"address_region": "program_or_external",
"bytes": "2605",
"text": "BNE loc_17A7",
"mnemonic": "BNE",
"operands": "loc_17A7",
"kind": "branch",
"targets": [
6055
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6050,
"address_region": "program_or_external",
"bytes": "1E0982",
"text": "BSR loc_2127",
"mnemonic": "BSR",
"operands": "loc_2127",
"kind": "call",
"targets": [
8487
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6053,
"address_region": "program_or_external",
"bytes": "2019",
"text": "BRA loc_17C0",
"mnemonic": "BRA",
"operands": "loc_17C0",
"kind": "jump",
"targets": [
6080
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6055,
"address_region": "program_or_external",
"bytes": "1DE220FF",
"text": "BTST.W #15, @H'E220",
"mnemonic": "BTST.W",
"operands": "#15, @H'E220",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57888,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6059,
"address_region": "program_or_external",
"bytes": "2705",
"text": "BEQ loc_17B2",
"mnemonic": "BEQ",
"operands": "loc_17B2",
"kind": "branch",
"targets": [
6066
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6061,
"address_region": "program_or_external",
"bytes": "1E0977",
"text": "BSR loc_2127",
"mnemonic": "BSR",
"operands": "loc_2127",
"kind": "call",
"targets": [
8487
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6064,
"address_region": "program_or_external",
"bytes": "200E",
"text": "BRA loc_17C0",
"mnemonic": "BRA",
"operands": "loc_17C0",
"kind": "jump",
"targets": [
6080
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6066,
"address_region": "program_or_external",
"bytes": "1DF69284",
"text": "MOV:G.W @H'F692, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F692, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63122,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6070,
"address_region": "program_or_external",
"bytes": "1DF6B234",
"text": "SUB.W @H'F6B2, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6B2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63154,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6074,
"address_region": "program_or_external",
"bytes": "5B00BC",
"text": "MOV:I.W #H'00BC, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00BC, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6077,
"address_region": "program_or_external",
"bytes": "1E01E2",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6080,
"address_region": "program_or_external",
"bytes": "1DF69284",
"text": "MOV:G.W @H'F692, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F692, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63122,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6084,
"address_region": "program_or_external",
"bytes": "1DF6B294",
"text": "MOV:G.W R4, @H'F6B2",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6B2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63154,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6088,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6089,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6094,
"address_region": "program_or_external",
"bytes": "2222",
"text": "BHI loc_17F2",
"mnemonic": "BHI",
"operands": "loc_17F2",
"kind": "branch",
"targets": [
6130
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6096,
"address_region": "program_or_external",
"bytes": "1DE126FC",
"text": "BTST.W #12, @H'E126",
"mnemonic": "BTST.W",
"operands": "#12, @H'E126",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57638,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6100,
"address_region": "program_or_external",
"bytes": "271C",
"text": "BEQ loc_17F2",
"mnemonic": "BEQ",
"operands": "loc_17F2",
"kind": "branch",
"targets": [
6130
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6102,
"address_region": "program_or_external",
"bytes": "1DF6AE84",
"text": "MOV:G.W @H'F6AE, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AE, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63150,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6106,
"address_region": "program_or_external",
"bytes": "1DF6CE34",
"text": "SUB.W @H'F6CE, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6CE, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63182,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6110,
"address_region": "program_or_external",
"bytes": "5B00A3",
"text": "MOV:I.W #H'00A3, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00A3, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6113,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6117,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_17EF",
"mnemonic": "BEQ",
"operands": "loc_17EF",
"kind": "branch",
"targets": [
6127
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6119,
"address_region": "program_or_external",
"bytes": "15F404F3",
"text": "BTST.B #3, @H'F404",
"mnemonic": "BTST.B",
"operands": "#3, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6123,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_17EF",
"mnemonic": "BEQ",
"operands": "loc_17EF",
"kind": "branch",
"targets": [
6127
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6125,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6127,
"address_region": "program_or_external",
"bytes": "1E01B0",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6130,
"address_region": "program_or_external",
"bytes": "1DF6AE84",
"text": "MOV:G.W @H'F6AE, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AE, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63150,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6134,
"address_region": "program_or_external",
"bytes": "1DF6CE94",
"text": "MOV:G.W R4, @H'F6CE",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6CE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63182,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6138,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6139,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6144,
"address_region": "program_or_external",
"bytes": "2222",
"text": "BHI loc_1824",
"mnemonic": "BHI",
"operands": "loc_1824",
"kind": "branch",
"targets": [
6180
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6146,
"address_region": "program_or_external",
"bytes": "1DE126FC",
"text": "BTST.W #12, @H'E126",
"mnemonic": "BTST.W",
"operands": "#12, @H'E126",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57638,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6150,
"address_region": "program_or_external",
"bytes": "271C",
"text": "BEQ loc_1824",
"mnemonic": "BEQ",
"operands": "loc_1824",
"kind": "branch",
"targets": [
6180
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6152,
"address_region": "program_or_external",
"bytes": "1DF6AC84",
"text": "MOV:G.W @H'F6AC, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63148,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6156,
"address_region": "program_or_external",
"bytes": "1DF6CC34",
"text": "SUB.W @H'F6CC, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6CC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63180,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6160,
"address_region": "program_or_external",
"bytes": "5B00A4",
"text": "MOV:I.W #H'00A4, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00A4, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6163,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6167,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_1821",
"mnemonic": "BEQ",
"operands": "loc_1821",
"kind": "branch",
"targets": [
6177
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6169,
"address_region": "program_or_external",
"bytes": "15F404F3",
"text": "BTST.B #3, @H'F404",
"mnemonic": "BTST.B",
"operands": "#3, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6173,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_1821",
"mnemonic": "BEQ",
"operands": "loc_1821",
"kind": "branch",
"targets": [
6177
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6175,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6177,
"address_region": "program_or_external",
"bytes": "1E017E",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6180,
"address_region": "program_or_external",
"bytes": "1DF6AC84",
"text": "MOV:G.W @H'F6AC, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63148,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6184,
"address_region": "program_or_external",
"bytes": "1DF6CC94",
"text": "MOV:G.W R4, @H'F6CC",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6CC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63180,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6188,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6189,
"address_region": "program_or_external",
"bytes": "15F717F2",
"text": "BTST.B #2, @H'F717",
"mnemonic": "BTST.B",
"operands": "#2, @H'F717",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63255,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6193,
"address_region": "program_or_external",
"bytes": "2632",
"text": "BNE loc_1865",
"mnemonic": "BNE",
"operands": "loc_1865",
"kind": "branch",
"targets": [
6245
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6195,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6200,
"address_region": "program_or_external",
"bytes": "2222",
"text": "BHI loc_185C",
"mnemonic": "BHI",
"operands": "loc_185C",
"kind": "branch",
"targets": [
6236
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6202,
"address_region": "program_or_external",
"bytes": "1DE126F5",
"text": "BTST.W #5, @H'E126",
"mnemonic": "BTST.W",
"operands": "#5, @H'E126",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57638,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6206,
"address_region": "program_or_external",
"bytes": "271C",
"text": "BEQ loc_185C",
"mnemonic": "BEQ",
"operands": "loc_185C",
"kind": "branch",
"targets": [
6236
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6208,
"address_region": "program_or_external",
"bytes": "1DF6AA84",
"text": "MOV:G.W @H'F6AA, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63146,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6212,
"address_region": "program_or_external",
"bytes": "1DF6CA34",
"text": "SUB.W @H'F6CA, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6CA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63178,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6216,
"address_region": "program_or_external",
"bytes": "5B00A5",
"text": "MOV:I.W #H'00A5, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00A5, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6219,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6223,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_1859",
"mnemonic": "BEQ",
"operands": "loc_1859",
"kind": "branch",
"targets": [
6233
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6225,
"address_region": "program_or_external",
"bytes": "15F404F2",
"text": "BTST.B #2, @H'F404",
"mnemonic": "BTST.B",
"operands": "#2, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6229,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_1859",
"mnemonic": "BEQ",
"operands": "loc_1859",
"kind": "branch",
"targets": [
6233
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6231,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6233,
"address_region": "program_or_external",
"bytes": "1E0146",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6236,
"address_region": "program_or_external",
"bytes": "1DF6AA84",
"text": "MOV:G.W @H'F6AA, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63146,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6240,
"address_region": "program_or_external",
"bytes": "1DF6CA94",
"text": "MOV:G.W R4, @H'F6CA",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6CA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63178,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6244,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6245,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6250,
"address_region": "program_or_external",
"bytes": "221C",
"text": "BHI loc_1888",
"mnemonic": "BHI",
"operands": "loc_1888",
"kind": "branch",
"targets": [
6280
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6252,
"address_region": "program_or_external",
"bytes": "1DF6AA84",
"text": "MOV:G.W @H'F6AA, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63146,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6256,
"address_region": "program_or_external",
"bytes": "1DF6CA34",
"text": "SUB.W @H'F6CA, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6CA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63178,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6260,
"address_region": "program_or_external",
"bytes": "5B00D8",
"text": "MOV:I.W #H'00D8, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00D8, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6263,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6267,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_1885",
"mnemonic": "BEQ",
"operands": "loc_1885",
"kind": "branch",
"targets": [
6277
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6269,
"address_region": "program_or_external",
"bytes": "15F404F1",
"text": "BTST.B #1, @H'F404",
"mnemonic": "BTST.B",
"operands": "#1, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6273,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_1885",
"mnemonic": "BEQ",
"operands": "loc_1885",
"kind": "branch",
"targets": [
6277
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6275,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6277,
"address_region": "program_or_external",
"bytes": "1E011A",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6280,
"address_region": "program_or_external",
"bytes": "1DF6AA84",
"text": "MOV:G.W @H'F6AA, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6AA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63146,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6284,
"address_region": "program_or_external",
"bytes": "1DF6CA94",
"text": "MOV:G.W R4, @H'F6CA",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6CA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63178,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6288,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6289,
"address_region": "program_or_external",
"bytes": "15F717F2",
"text": "BTST.B #2, @H'F717",
"mnemonic": "BTST.B",
"operands": "#2, @H'F717",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63255,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6293,
"address_region": "program_or_external",
"bytes": "2624",
"text": "BNE loc_18BB",
"mnemonic": "BNE",
"operands": "loc_18BB",
"kind": "branch",
"targets": [
6331
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6295,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6300,
"address_region": "program_or_external",
"bytes": "2214",
"text": "BHI loc_18B2",
"mnemonic": "BHI",
"operands": "loc_18B2",
"kind": "branch",
"targets": [
6322
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6302,
"address_region": "program_or_external",
"bytes": "1DE126F5",
"text": "BTST.W #5, @H'E126",
"mnemonic": "BTST.W",
"operands": "#5, @H'E126",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57638,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6306,
"address_region": "program_or_external",
"bytes": "270E",
"text": "BEQ loc_18B2",
"mnemonic": "BEQ",
"operands": "loc_18B2",
"kind": "branch",
"targets": [
6322
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6308,
"address_region": "program_or_external",
"bytes": "1DF6A884",
"text": "MOV:G.W @H'F6A8, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63144,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6312,
"address_region": "program_or_external",
"bytes": "1DF6C834",
"text": "SUB.W @H'F6C8, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6C8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63176,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6316,
"address_region": "program_or_external",
"bytes": "5B0080",
"text": "MOV:I.W #H'0080, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'0080, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6319,
"address_region": "program_or_external",
"bytes": "1E00F0",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6322,
"address_region": "program_or_external",
"bytes": "1DF6A884",
"text": "MOV:G.W @H'F6A8, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63144,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6326,
"address_region": "program_or_external",
"bytes": "1DF6C894",
"text": "MOV:G.W R4, @H'F6C8",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6C8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63176,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6330,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6331,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6336,
"address_region": "program_or_external",
"bytes": "221C",
"text": "BHI loc_18DE",
"mnemonic": "BHI",
"operands": "loc_18DE",
"kind": "branch",
"targets": [
6366
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6338,
"address_region": "program_or_external",
"bytes": "1DF6A884",
"text": "MOV:G.W @H'F6A8, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63144,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6342,
"address_region": "program_or_external",
"bytes": "1DF6C834",
"text": "SUB.W @H'F6C8, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6C8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63176,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6346,
"address_region": "program_or_external",
"bytes": "5B00D9",
"text": "MOV:I.W #H'00D9, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00D9, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6349,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6353,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_18DB",
"mnemonic": "BEQ",
"operands": "loc_18DB",
"kind": "branch",
"targets": [
6363
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6355,
"address_region": "program_or_external",
"bytes": "15F404F1",
"text": "BTST.B #1, @H'F404",
"mnemonic": "BTST.B",
"operands": "#1, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6359,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_18DB",
"mnemonic": "BEQ",
"operands": "loc_18DB",
"kind": "branch",
"targets": [
6363
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6361,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6363,
"address_region": "program_or_external",
"bytes": "1E00C4",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6366,
"address_region": "program_or_external",
"bytes": "1DF6A884",
"text": "MOV:G.W @H'F6A8, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63144,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6370,
"address_region": "program_or_external",
"bytes": "1DF6C894",
"text": "MOV:G.W R4, @H'F6C8",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6C8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63176,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6374,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6375,
"address_region": "program_or_external",
"bytes": "15F717F2",
"text": "BTST.B #2, @H'F717",
"mnemonic": "BTST.B",
"operands": "#2, @H'F717",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63255,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6379,
"address_region": "program_or_external",
"bytes": "2632",
"text": "BNE loc_191F",
"mnemonic": "BNE",
"operands": "loc_191F",
"kind": "branch",
"targets": [
6431
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6381,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6386,
"address_region": "program_or_external",
"bytes": "2222",
"text": "BHI loc_1916",
"mnemonic": "BHI",
"operands": "loc_1916",
"kind": "branch",
"targets": [
6422
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6388,
"address_region": "program_or_external",
"bytes": "1DE126F5",
"text": "BTST.W #5, @H'E126",
"mnemonic": "BTST.W",
"operands": "#5, @H'E126",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57638,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6392,
"address_region": "program_or_external",
"bytes": "271C",
"text": "BEQ loc_1916",
"mnemonic": "BEQ",
"operands": "loc_1916",
"kind": "branch",
"targets": [
6422
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6394,
"address_region": "program_or_external",
"bytes": "1DF6A684",
"text": "MOV:G.W @H'F6A6, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63142,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6398,
"address_region": "program_or_external",
"bytes": "1DF6C634",
"text": "SUB.W @H'F6C6, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6C6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63174,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6402,
"address_region": "program_or_external",
"bytes": "5B00A6",
"text": "MOV:I.W #H'00A6, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00A6, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6405,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6409,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_1913",
"mnemonic": "BEQ",
"operands": "loc_1913",
"kind": "branch",
"targets": [
6419
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6411,
"address_region": "program_or_external",
"bytes": "15F404F2",
"text": "BTST.B #2, @H'F404",
"mnemonic": "BTST.B",
"operands": "#2, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6415,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_1913",
"mnemonic": "BEQ",
"operands": "loc_1913",
"kind": "branch",
"targets": [
6419
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6417,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6419,
"address_region": "program_or_external",
"bytes": "1E008C",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6422,
"address_region": "program_or_external",
"bytes": "1DF6A684",
"text": "MOV:G.W @H'F6A6, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63142,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6426,
"address_region": "program_or_external",
"bytes": "1DF6C694",
"text": "MOV:G.W R4, @H'F6C6",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63174,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6430,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6431,
"address_region": "program_or_external",
"bytes": "15F7310402",
"text": "CMP:G.B #H'02, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6436,
"address_region": "program_or_external",
"bytes": "221B",
"text": "BHI loc_1941",
"mnemonic": "BHI",
"operands": "loc_1941",
"kind": "branch",
"targets": [
6465
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6438,
"address_region": "program_or_external",
"bytes": "1DF6A684",
"text": "MOV:G.W @H'F6A6, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63142,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6442,
"address_region": "program_or_external",
"bytes": "1DF6C634",
"text": "SUB.W @H'F6C6, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6C6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63174,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6446,
"address_region": "program_or_external",
"bytes": "5B00DA",
"text": "MOV:I.W #H'00DA, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00DA, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6449,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6453,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_193F",
"mnemonic": "BEQ",
"operands": "loc_193F",
"kind": "branch",
"targets": [
6463
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6455,
"address_region": "program_or_external",
"bytes": "15F404F1",
"text": "BTST.B #1, @H'F404",
"mnemonic": "BTST.B",
"operands": "#1, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 6459,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_193F",
"mnemonic": "BEQ",
"operands": "loc_193F",
"kind": "branch",
"targets": [
6463
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6461,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6463,
"address_region": "program_or_external",
"bytes": "0E61",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6465,
"address_region": "program_or_external",
"bytes": "1DF6A684",
"text": "MOV:G.W @H'F6A6, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63142,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6469,
"address_region": "program_or_external",
"bytes": "1DF6C694",
"text": "MOV:G.W R4, @H'F6C6",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63174,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6473,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6474,
"address_region": "program_or_external",
"bytes": "15F7310403",
"text": "CMP:G.B #H'03, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'03, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6479,
"address_region": "program_or_external",
"bytes": "221F",
"text": "BHI loc_1970",
"mnemonic": "BHI",
"operands": "loc_1970",
"kind": "branch",
"targets": [
6512
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6481,
"address_region": "program_or_external",
"bytes": "1DF6A484",
"text": "MOV:G.W @H'F6A4, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63140,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6485,
"address_region": "program_or_external",
"bytes": "1DF6C434",
"text": "SUB.W @H'F6C4, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6C4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63172,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6489,
"address_region": "program_or_external",
"bytes": "15FE8EF4",
"text": "BTST.B #4, @P7DR",
"mnemonic": "BTST.B",
"operands": "#4, @P7DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 6493,
"address_region": "program_or_external",
"bytes": "2600",
"text": "BNE loc_195F",
"mnemonic": "BNE",
"operands": "loc_195F",
"kind": "branch",
"targets": [
6495
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6495,
"address_region": "program_or_external",
"bytes": "5B0080",
"text": "MOV:I.W #H'0080, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'0080, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6498,
"address_region": "program_or_external",
"bytes": "15F791F5",
"text": "BTST.B #5, @H'F791",
"mnemonic": "BTST.B",
"operands": "#5, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6502,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_196A",
"mnemonic": "BEQ",
"operands": "loc_196A",
"kind": "branch",
"targets": [
6506
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6504,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6506,
"address_region": "program_or_external",
"bytes": "0E36",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6508,
"address_region": "program_or_external",
"bytes": "15F76DC7",
"text": "BSET.B #7, @H'F76D",
"mnemonic": "BSET.B",
"operands": "#7, @H'F76D",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63341,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6512,
"address_region": "program_or_external",
"bytes": "1DF6A484",
"text": "MOV:G.W @H'F6A4, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63140,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6516,
"address_region": "program_or_external",
"bytes": "1DF6C494",
"text": "MOV:G.W R4, @H'F6C4",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6C4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63172,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6520,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6521,
"address_region": "program_or_external",
"bytes": "15F7310403",
"text": "CMP:G.B #H'03, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'03, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6526,
"address_region": "program_or_external",
"bytes": "2219",
"text": "BHI loc_1999",
"mnemonic": "BHI",
"operands": "loc_1999",
"kind": "branch",
"targets": [
6553
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6528,
"address_region": "program_or_external",
"bytes": "1DF6A280",
"text": "MOV:G.W @H'F6A2, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63138,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6532,
"address_region": "program_or_external",
"bytes": "1DF6C230",
"text": "SUB.W @H'F6C2, R0",
"mnemonic": "SUB.W",
"operands": "@H'F6C2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63170,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6536,
"address_region": "program_or_external",
"bytes": "1DF68CA8",
"text": "MULXU.W @H'F68C, R0",
"mnemonic": "MULXU.W",
"operands": "@H'F68C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 26,
"base_cycles": 25,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63116,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6540,
"address_region": "program_or_external",
"bytes": "5B0081",
"text": "MOV:I.W #H'0081, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'0081, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6543,
"address_region": "program_or_external",
"bytes": "15F791F5",
"text": "BTST.B #5, @H'F791",
"mnemonic": "BTST.B",
"operands": "#5, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6547,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_1997",
"mnemonic": "BEQ",
"operands": "loc_1997",
"kind": "branch",
"targets": [
6551
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6549,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6551,
"address_region": "program_or_external",
"bytes": "0E42",
"text": "BSR loc_19DB",
"mnemonic": "BSR",
"operands": "loc_19DB",
"kind": "call",
"targets": [
6619
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6553,
"address_region": "program_or_external",
"bytes": "1DF6A284",
"text": "MOV:G.W @H'F6A2, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F6A2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63138,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6557,
"address_region": "program_or_external",
"bytes": "1DF6C294",
"text": "MOV:G.W R4, @H'F6C2",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6C2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63170,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6561,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6562,
"address_region": "program_or_external",
"bytes": "AB85",
"text": "MOV:G.W R3, R5",
"mnemonic": "MOV:G.W",
"operands": "R3, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6564,
"address_region": "program_or_external",
"bytes": "0C01FF53",
"text": "AND.W #H'01FF, R3",
"mnemonic": "AND.W",
"operands": "#H'01FF, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6568,
"address_region": "program_or_external",
"bytes": "AB1A",
"text": "SHLL.W R3",
"mnemonic": "SHLL.W",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6570,
"address_region": "program_or_external",
"bytes": "FBE40080",
"text": "MOV:G.W @(-H'1C00,R3), R0",
"mnemonic": "MOV:G.W",
"operands": "@(-H'1C00,R3), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6574,
"address_region": "program_or_external",
"bytes": "48FC00",
"text": "CMP:I #H'FC00, R0",
"mnemonic": "CMP:I",
"operands": "#H'FC00, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6577,
"address_region": "program_or_external",
"bytes": "2203",
"text": "BHI loc_19B6",
"mnemonic": "BHI",
"operands": "loc_19B6",
"kind": "branch",
"targets": [
6582
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6579,
"address_region": "program_or_external",
"bytes": "58FE00",
"text": "MOV:I.W #H'FE00, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'FE00, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6582,
"address_region": "program_or_external",
"bytes": "A815",
"text": "NOT.W R0",
"mnemonic": "NOT.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6584,
"address_region": "program_or_external",
"bytes": "A808",
"text": "ADD:Q.W #1, R0",
"mnemonic": "ADD:Q.W",
"operands": "#1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6586,
"address_region": "program_or_external",
"bytes": "4C000F",
"text": "CMP:I #H'000F, R4",
"mnemonic": "CMP:I",
"operands": "#H'000F, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6589,
"address_region": "program_or_external",
"bytes": "2314",
"text": "BLS loc_19D3",
"mnemonic": "BLS",
"operands": "loc_19D3",
"kind": "branch",
"targets": [
6611
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6591,
"address_region": "program_or_external",
"bytes": "4CFFF0",
"text": "CMP:I #H'FFF0, R4",
"mnemonic": "CMP:I",
"operands": "#H'FFF0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6594,
"address_region": "program_or_external",
"bytes": "240F",
"text": "BCC loc_19D3",
"mnemonic": "BCC",
"operands": "loc_19D3",
"kind": "branch",
"targets": [
6611
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6596,
"address_region": "program_or_external",
"bytes": "4C8000",
"text": "CMP:I #H'8000, R4",
"mnemonic": "CMP:I",
"operands": "#H'8000, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6599,
"address_region": "program_or_external",
"bytes": "2405",
"text": "BCC loc_19CE",
"mnemonic": "BCC",
"operands": "loc_19CE",
"kind": "branch",
"targets": [
6606
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6601,
"address_region": "program_or_external",
"bytes": "5C001A",
"text": "MOV:I.W #H'001A, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'001A, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6604,
"address_region": "program_or_external",
"bytes": "2009",
"text": "BRA loc_19D7",
"mnemonic": "BRA",
"operands": "loc_19D7",
"kind": "jump",
"targets": [
6615
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6606,
"address_region": "program_or_external",
"bytes": "5CFF1C",
"text": "MOV:I.W #H'FF1C, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'FF1C, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6609,
"address_region": "program_or_external",
"bytes": "2004",
"text": "BRA loc_19D7",
"mnemonic": "BRA",
"operands": "loc_19D7",
"kind": "jump",
"targets": [
6615
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6611,
"address_region": "program_or_external",
"bytes": "F41A2584",
"text": "MOV:G.B @(H'1A25,R4), R4",
"mnemonic": "MOV:G.B",
"operands": "@(H'1A25,R4), R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6615,
"address_region": "program_or_external",
"bytes": "ACA8",
"text": "MULXU.W R4, R0",
"mnemonic": "MULXU.W",
"operands": "R4, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 25,
"base_cycles": 25,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6617,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_19E3",
"mnemonic": "BRA",
"operands": "loc_19E3",
"kind": "jump",
"targets": [
6627
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6619,
"address_region": "program_or_external",
"bytes": "AB85",
"text": "MOV:G.W R3, R5",
"mnemonic": "MOV:G.W",
"operands": "R3, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6621,
"address_region": "program_or_external",
"bytes": "0C01FF53",
"text": "AND.W #H'01FF, R3",
"mnemonic": "AND.W",
"operands": "#H'01FF, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6625,
"address_region": "program_or_external",
"bytes": "AB1A",
"text": "SHLL.W R3",
"mnemonic": "SHLL.W",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6627,
"address_region": "program_or_external",
"bytes": "FBE00080",
"text": "MOV:G.W @(-H'2000,R3), R0",
"mnemonic": "MOV:G.W",
"operands": "@(-H'2000,R3), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6631,
"address_region": "program_or_external",
"bytes": "A821",
"text": "ADD:G.W R0, R1",
"mnemonic": "ADD:G.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6633,
"address_region": "program_or_external",
"bytes": "A982",
"text": "MOV:G.W R1, R2",
"mnemonic": "MOV:G.W",
"operands": "R1, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6635,
"address_region": "program_or_external",
"bytes": "250C",
"text": "BCS loc_19F9",
"mnemonic": "BCS",
"operands": "loc_19F9",
"kind": "branch",
"targets": [
6649
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6637,
"address_region": "program_or_external",
"bytes": "A832",
"text": "SUB.W R0, R2",
"mnemonic": "SUB.W",
"operands": "R0, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6639,
"address_region": "program_or_external",
"bytes": "4A8000",
"text": "CMP:I #H'8000, R2",
"mnemonic": "CMP:I",
"operands": "#H'8000, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6642,
"address_region": "program_or_external",
"bytes": "230F",
"text": "BLS loc_1A03",
"mnemonic": "BLS",
"operands": "loc_1A03",
"kind": "branch",
"targets": [
6659
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6644,
"address_region": "program_or_external",
"bytes": "590000",
"text": "MOV:I.W #H'0000, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6647,
"address_region": "program_or_external",
"bytes": "200A",
"text": "BRA loc_1A03",
"mnemonic": "BRA",
"operands": "loc_1A03",
"kind": "jump",
"targets": [
6659
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6649,
"address_region": "program_or_external",
"bytes": "AA30",
"text": "SUB.W R2, R0",
"mnemonic": "SUB.W",
"operands": "R2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6651,
"address_region": "program_or_external",
"bytes": "488000",
"text": "CMP:I #H'8000, R0",
"mnemonic": "CMP:I",
"operands": "#H'8000, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6654,
"address_region": "program_or_external",
"bytes": "2303",
"text": "BLS loc_1A03",
"mnemonic": "BLS",
"operands": "loc_1A03",
"kind": "branch",
"targets": [
6659
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6656,
"address_region": "program_or_external",
"bytes": "59FFFF",
"text": "MOV:I.W #H'FFFF, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'FFFF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6659,
"address_region": "program_or_external",
"bytes": "FBE00071",
"text": "CMP:G.W @(-H'2000,R3), R1",
"mnemonic": "CMP:G.W",
"operands": "@(-H'2000,R3), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6663,
"address_region": "program_or_external",
"bytes": "270B",
"text": "BEQ loc_1A14",
"mnemonic": "BEQ",
"operands": "loc_1A14",
"kind": "branch",
"targets": [
6676
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6665,
"address_region": "program_or_external",
"bytes": "FBE80091",
"text": "MOV:G.W R1, @(-H'1800,R3)",
"mnemonic": "MOV:G.W",
"operands": "R1, @(-H'1800,R3)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6669,
"address_region": "program_or_external",
"bytes": "5280",
"text": "MOV:E.B #H'80, R2",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6671,
"address_region": "program_or_external",
"bytes": "AD83",
"text": "MOV:G.W R5, R3",
"mnemonic": "MOV:G.W",
"operands": "R5, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6673,
"address_region": "program_or_external",
"bytes": "1E2440",
"text": "BSR loc_3E54",
"mnemonic": "BSR",
"operands": "loc_3E54",
"kind": "call",
"targets": [
15956
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6676,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6709,
"address_region": "program_or_external",
"bytes": "AB85",
"text": "MOV:G.W R3, R5",
"mnemonic": "MOV:G.W",
"operands": "R3, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6711,
"address_region": "program_or_external",
"bytes": "0C01FF53",
"text": "AND.W #H'01FF, R3",
"mnemonic": "AND.W",
"operands": "#H'01FF, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6715,
"address_region": "program_or_external",
"bytes": "AB1A",
"text": "SHLL.W R3",
"mnemonic": "SHLL.W",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6717,
"address_region": "program_or_external",
"bytes": "FBE00080",
"text": "MOV:G.W @(-H'2000,R3), R0",
"mnemonic": "MOV:G.W",
"operands": "@(-H'2000,R3), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6721,
"address_region": "program_or_external",
"bytes": "273A",
"text": "BEQ loc_1A7D",
"mnemonic": "BEQ",
"operands": "loc_1A7D",
"kind": "branch",
"targets": [
6781
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6723,
"address_region": "program_or_external",
"bytes": "0E48",
"text": "BSR loc_1A8D",
"mnemonic": "BSR",
"operands": "loc_1A8D",
"kind": "call",
"targets": [
6797
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6725,
"address_region": "program_or_external",
"bytes": "AC16",
"text": "TST.W R4",
"mnemonic": "TST.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6727,
"address_region": "program_or_external",
"bytes": "2610",
"text": "BNE loc_1A59",
"mnemonic": "BNE",
"operands": "loc_1A59",
"kind": "branch",
"targets": [
6745
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6729,
"address_region": "program_or_external",
"bytes": "A882",
"text": "MOV:G.W R0, R2",
"mnemonic": "MOV:G.W",
"operands": "R0, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6731,
"address_region": "program_or_external",
"bytes": "FBE40081",
"text": "MOV:G.W @(-H'1C00,R3), R1",
"mnemonic": "MOV:G.W",
"operands": "@(-H'1C00,R3), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6735,
"address_region": "program_or_external",
"bytes": "A81B",
"text": "SHLR.W R0",
"mnemonic": "SHLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6737,
"address_region": "program_or_external",
"bytes": "2716",
"text": "BEQ loc_1A69",
"mnemonic": "BEQ",
"operands": "loc_1A69",
"kind": "branch",
"targets": [
6761
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6739,
"address_region": "program_or_external",
"bytes": "A851",
"text": "AND.W R0, R1",
"mnemonic": "AND.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6741,
"address_region": "program_or_external",
"bytes": "27F4",
"text": "BEQ loc_1A4B",
"mnemonic": "BEQ",
"operands": "loc_1A4B",
"kind": "branch",
"targets": [
6731
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6743,
"address_region": "program_or_external",
"bytes": "2012",
"text": "BRA loc_1A6B",
"mnemonic": "BRA",
"operands": "loc_1A6B",
"kind": "jump",
"targets": [
6763
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6745,
"address_region": "program_or_external",
"bytes": "A882",
"text": "MOV:G.W R0, R2",
"mnemonic": "MOV:G.W",
"operands": "R0, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6747,
"address_region": "program_or_external",
"bytes": "FBE40081",
"text": "MOV:G.W @(-H'1C00,R3), R1",
"mnemonic": "MOV:G.W",
"operands": "@(-H'1C00,R3), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6751,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6753,
"address_region": "program_or_external",
"bytes": "2706",
"text": "BEQ loc_1A69",
"mnemonic": "BEQ",
"operands": "loc_1A69",
"kind": "branch",
"targets": [
6761
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6755,
"address_region": "program_or_external",
"bytes": "A851",
"text": "AND.W R0, R1",
"mnemonic": "AND.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6757,
"address_region": "program_or_external",
"bytes": "27F4",
"text": "BEQ loc_1A5B",
"mnemonic": "BEQ",
"operands": "loc_1A5B",
"kind": "branch",
"targets": [
6747
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6759,
"address_region": "program_or_external",
"bytes": "2002",
"text": "BRA loc_1A6B",
"mnemonic": "BRA",
"operands": "loc_1A6B",
"kind": "jump",
"targets": [
6763
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6761,
"address_region": "program_or_external",
"bytes": "AA80",
"text": "MOV:G.W R2, R0",
"mnemonic": "MOV:G.W",
"operands": "R2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6763,
"address_region": "program_or_external",
"bytes": "FBE00070",
"text": "CMP:G.W @(-H'2000,R3), R0",
"mnemonic": "CMP:G.W",
"operands": "@(-H'2000,R3), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6767,
"address_region": "program_or_external",
"bytes": "270B",
"text": "BEQ loc_1A7C",
"mnemonic": "BEQ",
"operands": "loc_1A7C",
"kind": "branch",
"targets": [
6780
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6769,
"address_region": "program_or_external",
"bytes": "FBE80090",
"text": "MOV:G.W R0, @(-H'1800,R3)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'1800,R3)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6773,
"address_region": "program_or_external",
"bytes": "5280",
"text": "MOV:E.B #H'80, R2",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6775,
"address_region": "program_or_external",
"bytes": "AD83",
"text": "MOV:G.W R5, R3",
"mnemonic": "MOV:G.W",
"operands": "R5, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6777,
"address_region": "program_or_external",
"bytes": "1E23D8",
"text": "BSR loc_3E54",
"mnemonic": "BSR",
"operands": "loc_3E54",
"kind": "call",
"targets": [
15956
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6780,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6781,
"address_region": "program_or_external",
"bytes": "A8CF",
"text": "BSET.W #15, R0",
"mnemonic": "BSET.W",
"operands": "#15, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6783,
"address_region": "program_or_external",
"bytes": "A881",
"text": "MOV:G.W R0, R1",
"mnemonic": "MOV:G.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6785,
"address_region": "program_or_external",
"bytes": "FBE40051",
"text": "AND.W @(-H'1C00,R3), R1",
"mnemonic": "AND.W",
"operands": "@(-H'1C00,R3), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6789,
"address_region": "program_or_external",
"bytes": "2604",
"text": "BNE loc_1A8B",
"mnemonic": "BNE",
"operands": "loc_1A8B",
"kind": "branch",
"targets": [
6795
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6791,
"address_region": "program_or_external",
"bytes": "A81B",
"text": "SHLR.W R0",
"mnemonic": "SHLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6793,
"address_region": "program_or_external",
"bytes": "20F4",
"text": "BRA loc_1A7F",
"mnemonic": "BRA",
"operands": "loc_1A7F",
"kind": "jump",
"targets": [
6783
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6795,
"address_region": "program_or_external",
"bytes": "20B8",
"text": "BRA loc_1A45",
"mnemonic": "BRA",
"operands": "loc_1A45",
"kind": "jump",
"targets": [
6725
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6797,
"address_region": "program_or_external",
"bytes": "59000F",
"text": "MOV:I.W #H'000F, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'000F, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6800,
"address_region": "program_or_external",
"bytes": "A879",
"text": "BTST.W R1, R0",
"mnemonic": "BTST.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6802,
"address_region": "program_or_external",
"bytes": "2603",
"text": "BNE loc_1A97",
"mnemonic": "BNE",
"operands": "loc_1A97",
"kind": "branch",
"targets": [
6807
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6804,
"address_region": "program_or_external",
"bytes": "01B9F9",
"text": "SCB/F R1, loc_1A90",
"mnemonic": "SCB/F",
"operands": "R1, loc_1A90",
"kind": "branch",
"targets": [
6800
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 8,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6807,
"address_region": "program_or_external",
"bytes": "A813",
"text": "CLR.W R0",
"mnemonic": "CLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6809,
"address_region": "program_or_external",
"bytes": "A849",
"text": "BSET.W R1, R0",
"mnemonic": "BSET.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6811,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6812,
"address_region": "program_or_external",
"bytes": "AB16",
"text": "TST.W R3",
"mnemonic": "TST.W",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6814,
"address_region": "program_or_external",
"bytes": "2732",
"text": "BEQ loc_1AD2",
"mnemonic": "BEQ",
"operands": "loc_1AD2",
"kind": "branch",
"targets": [
6866
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6816,
"address_region": "program_or_external",
"bytes": "AB1A",
"text": "SHLL.W R3",
"mnemonic": "SHLL.W",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6818,
"address_region": "program_or_external",
"bytes": "15F73380",
"text": "MOV:G.B @H'F733, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F733, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63283,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6822,
"address_region": "program_or_external",
"bytes": "A015",
"text": "NOT.B R0",
"mnemonic": "NOT.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6824,
"address_region": "program_or_external",
"bytes": "040F50",
"text": "AND.B #H'0F, R0",
"mnemonic": "AND.B",
"operands": "#H'0F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6827,
"address_region": "program_or_external",
"bytes": "AC16",
"text": "TST.W R4",
"mnemonic": "TST.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6829,
"address_region": "program_or_external",
"bytes": "260D",
"text": "BNE loc_1ABC",
"mnemonic": "BNE",
"operands": "loc_1ABC",
"kind": "branch",
"targets": [
6844
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6831,
"address_region": "program_or_external",
"bytes": "A00C",
"text": "ADD:Q.B #-1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#-1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6833,
"address_region": "program_or_external",
"bytes": "040F50",
"text": "AND.B #H'0F, R0",
"mnemonic": "AND.B",
"operands": "#H'0F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6836,
"address_region": "program_or_external",
"bytes": "FBE40078",
"text": "BTST.W R0, @(-H'1C00,R3)",
"mnemonic": "BTST.W",
"operands": "R0, @(-H'1C00,R3)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6840,
"address_region": "program_or_external",
"bytes": "27F5",
"text": "BEQ loc_1AAF",
"mnemonic": "BEQ",
"operands": "loc_1AAF",
"kind": "branch",
"targets": [
6831
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6842,
"address_region": "program_or_external",
"bytes": "200B",
"text": "BRA loc_1AC7",
"mnemonic": "BRA",
"operands": "loc_1AC7",
"kind": "jump",
"targets": [
6855
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6844,
"address_region": "program_or_external",
"bytes": "A008",
"text": "ADD:Q.B #1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6846,
"address_region": "program_or_external",
"bytes": "040F50",
"text": "AND.B #H'0F, R0",
"mnemonic": "AND.B",
"operands": "#H'0F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6849,
"address_region": "program_or_external",
"bytes": "FBE40078",
"text": "BTST.W R0, @(-H'1C00,R3)",
"mnemonic": "BTST.W",
"operands": "R0, @(-H'1C00,R3)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6853,
"address_region": "program_or_external",
"bytes": "27F5",
"text": "BEQ loc_1ABC",
"mnemonic": "BEQ",
"operands": "loc_1ABC",
"kind": "branch",
"targets": [
6844
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6855,
"address_region": "program_or_external",
"bytes": "A015",
"text": "NOT.B R0",
"mnemonic": "NOT.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6857,
"address_region": "program_or_external",
"bytes": "040F50",
"text": "AND.B #H'0F, R0",
"mnemonic": "AND.B",
"operands": "#H'0F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6860,
"address_region": "program_or_external",
"bytes": "15F73390",
"text": "MOV:G.B R0, @H'F733",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F733",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63283,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6864,
"address_region": "program_or_external",
"bytes": "200E",
"text": "BRA loc_1AE0",
"mnemonic": "BRA",
"operands": "loc_1AE0",
"kind": "jump",
"targets": [
6880
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6866,
"address_region": "program_or_external",
"bytes": "AC16",
"text": "TST.W R4",
"mnemonic": "TST.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6868,
"address_region": "program_or_external",
"bytes": "2606",
"text": "BNE loc_1ADC",
"mnemonic": "BNE",
"operands": "loc_1ADC",
"kind": "branch",
"targets": [
6876
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6870,
"address_region": "program_or_external",
"bytes": "15F73308",
"text": "ADD:Q.B #1, @H'F733",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F733",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63283,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6874,
"address_region": "program_or_external",
"bytes": "2004",
"text": "BRA loc_1AE0",
"mnemonic": "BRA",
"operands": "loc_1AE0",
"kind": "jump",
"targets": [
6880
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6876,
"address_region": "program_or_external",
"bytes": "15F7330C",
"text": "ADD:Q.B #-1, @H'F733",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F733",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63283,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6880,
"address_region": "program_or_external",
"bytes": "1E2E17",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6883,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6884,
"address_region": "program_or_external",
"bytes": "15F75B80",
"text": "MOV:G.B @H'F75B, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F75B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63323,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6888,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6890,
"address_region": "program_or_external",
"bytes": "F0F75D81",
"text": "MOV:G.B @(-H'08A3,R0), R1",
"mnemonic": "MOV:G.B",
"operands": "@(-H'08A3,R0), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6894,
"address_region": "program_or_external",
"bytes": "AC16",
"text": "TST.W R4",
"mnemonic": "TST.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6896,
"address_region": "program_or_external",
"bytes": "260A",
"text": "BNE loc_1AFC",
"mnemonic": "BNE",
"operands": "loc_1AFC",
"kind": "branch",
"targets": [
6908
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6898,
"address_region": "program_or_external",
"bytes": "A108",
"text": "ADD:Q.B #1, R1",
"mnemonic": "ADD:Q.B",
"operands": "#1, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6900,
"address_region": "program_or_external",
"bytes": "412E",
"text": "CMP:E #H'2E, R1",
"mnemonic": "CMP:E",
"operands": "#H'2E, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6902,
"address_region": "program_or_external",
"bytes": "230B",
"text": "BLS loc_1B03",
"mnemonic": "BLS",
"operands": "loc_1B03",
"kind": "branch",
"targets": [
6915
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6904,
"address_region": "program_or_external",
"bytes": "5100",
"text": "MOV:E.B #H'00, R1",
"mnemonic": "MOV:E.B",
"operands": "#H'00, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6906,
"address_region": "program_or_external",
"bytes": "2007",
"text": "BRA loc_1B03",
"mnemonic": "BRA",
"operands": "loc_1B03",
"kind": "jump",
"targets": [
6915
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6908,
"address_region": "program_or_external",
"bytes": "040131",
"text": "SUB.B #H'01, R1",
"mnemonic": "SUB.B",
"operands": "#H'01, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6911,
"address_region": "program_or_external",
"bytes": "2402",
"text": "BCC loc_1B03",
"mnemonic": "BCC",
"operands": "loc_1B03",
"kind": "branch",
"targets": [
6915
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6913,
"address_region": "program_or_external",
"bytes": "512E",
"text": "MOV:E.B #H'2E, R1",
"mnemonic": "MOV:E.B",
"operands": "#H'2E, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6915,
"address_region": "program_or_external",
"bytes": "F0F75D91",
"text": "MOV:G.B R1, @(-H'08A3,R0)",
"mnemonic": "MOV:G.B",
"operands": "R1, @(-H'08A3,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6919,
"address_region": "program_or_external",
"bytes": "1E2DF0",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6922,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6923,
"address_region": "program_or_external",
"bytes": "15F75B80",
"text": "MOV:G.B @H'F75B, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F75B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63323,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6927,
"address_region": "program_or_external",
"bytes": "AC16",
"text": "TST.W R4",
"mnemonic": "TST.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6929,
"address_region": "program_or_external",
"bytes": "260A",
"text": "BNE loc_1B1D",
"mnemonic": "BNE",
"operands": "loc_1B1D",
"kind": "branch",
"targets": [
6941
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6931,
"address_region": "program_or_external",
"bytes": "A008",
"text": "ADD:Q.B #1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6933,
"address_region": "program_or_external",
"bytes": "4008",
"text": "CMP:E #H'08, R0",
"mnemonic": "CMP:E",
"operands": "#H'08, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6935,
"address_region": "program_or_external",
"bytes": "230C",
"text": "BLS loc_1B25",
"mnemonic": "BLS",
"operands": "loc_1B25",
"kind": "branch",
"targets": [
6949
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6937,
"address_region": "program_or_external",
"bytes": "5008",
"text": "MOV:E.B #H'08, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'08, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6939,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_1B25",
"mnemonic": "BRA",
"operands": "loc_1B25",
"kind": "jump",
"targets": [
6949
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6941,
"address_region": "program_or_external",
"bytes": "A00C",
"text": "ADD:Q.B #-1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#-1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6943,
"address_region": "program_or_external",
"bytes": "4001",
"text": "CMP:E #H'01, R0",
"mnemonic": "CMP:E",
"operands": "#H'01, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6945,
"address_region": "program_or_external",
"bytes": "2402",
"text": "BCC loc_1B25",
"mnemonic": "BCC",
"operands": "loc_1B25",
"kind": "branch",
"targets": [
6949
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6947,
"address_region": "program_or_external",
"bytes": "5001",
"text": "MOV:E.B #H'01, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'01, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6949,
"address_region": "program_or_external",
"bytes": "15F75B90",
"text": "MOV:G.B R0, @H'F75B",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F75B",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63323,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6953,
"address_region": "program_or_external",
"bytes": "1E2DCE",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6956,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6957,
"address_region": "program_or_external",
"bytes": "15F6D784",
"text": "MOV:G.B @H'F6D7, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D7, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63191,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6961,
"address_region": "program_or_external",
"bytes": "15F6E764",
"text": "XOR.B @H'F6E7, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E7, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63207,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6965,
"address_region": "program_or_external",
"bytes": "5D007E",
"text": "MOV:I.W #H'007E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'007E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6968,
"address_region": "program_or_external",
"bytes": "1E00D3",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6971,
"address_region": "program_or_external",
"bytes": "15F6D784",
"text": "MOV:G.B @H'F6D7, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D7, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63191,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6975,
"address_region": "program_or_external",
"bytes": "15F6E794",
"text": "MOV:G.B R4, @H'F6E7",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63207,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6979,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6980,
"address_region": "program_or_external",
"bytes": "15F6D684",
"text": "MOV:G.B @H'F6D6, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63190,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6984,
"address_region": "program_or_external",
"bytes": "15F6E664",
"text": "XOR.B @H'F6E6, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63206,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6988,
"address_region": "program_or_external",
"bytes": "5D006E",
"text": "MOV:I.W #H'006E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'006E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6991,
"address_region": "program_or_external",
"bytes": "1E00BC",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 6994,
"address_region": "program_or_external",
"bytes": "15F6D684",
"text": "MOV:G.B @H'F6D6, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D6, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63190,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 6998,
"address_region": "program_or_external",
"bytes": "15F6E694",
"text": "MOV:G.B R4, @H'F6E6",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63206,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7002,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7003,
"address_region": "program_or_external",
"bytes": "15F6D584",
"text": "MOV:G.B @H'F6D5, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D5, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63189,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7007,
"address_region": "program_or_external",
"bytes": "15F6E564",
"text": "XOR.B @H'F6E5, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E5, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63205,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7011,
"address_region": "program_or_external",
"bytes": "5D005E",
"text": "MOV:I.W #H'005E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'005E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7014,
"address_region": "program_or_external",
"bytes": "1E00A5",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7017,
"address_region": "program_or_external",
"bytes": "15F6D584",
"text": "MOV:G.B @H'F6D5, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D5, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63189,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7021,
"address_region": "program_or_external",
"bytes": "15F6E594",
"text": "MOV:G.B R4, @H'F6E5",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63205,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7025,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7026,
"address_region": "program_or_external",
"bytes": "15F6D184",
"text": "MOV:G.B @H'F6D1, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D1, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63185,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7030,
"address_region": "program_or_external",
"bytes": "15F6E164",
"text": "XOR.B @H'F6E1, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E1, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63201,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7034,
"address_region": "program_or_external",
"bytes": "5D001E",
"text": "MOV:I.W #H'001E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'001E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7037,
"address_region": "program_or_external",
"bytes": "1E008E",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7040,
"address_region": "program_or_external",
"bytes": "15F6D184",
"text": "MOV:G.B @H'F6D1, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D1, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63185,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7044,
"address_region": "program_or_external",
"bytes": "15F6E194",
"text": "MOV:G.B R4, @H'F6E1",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63201,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7048,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7049,
"address_region": "program_or_external",
"bytes": "15F6D084",
"text": "MOV:G.B @H'F6D0, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63184,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7053,
"address_region": "program_or_external",
"bytes": "15F6E064",
"text": "XOR.B @H'F6E0, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63200,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7057,
"address_region": "program_or_external",
"bytes": "5D000E",
"text": "MOV:I.W #H'000E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'000E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7060,
"address_region": "program_or_external",
"bytes": "1E0077",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7063,
"address_region": "program_or_external",
"bytes": "15F6D084",
"text": "MOV:G.B @H'F6D0, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63184,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7067,
"address_region": "program_or_external",
"bytes": "15F6E094",
"text": "MOV:G.B R4, @H'F6E0",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63200,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7071,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7072,
"address_region": "program_or_external",
"bytes": "15F6D484",
"text": "MOV:G.B @H'F6D4, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63188,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7076,
"address_region": "program_or_external",
"bytes": "15F6E464",
"text": "XOR.B @H'F6E4, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63204,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7080,
"address_region": "program_or_external",
"bytes": "5D004E",
"text": "MOV:I.W #H'004E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'004E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7083,
"address_region": "program_or_external",
"bytes": "0E61",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7085,
"address_region": "program_or_external",
"bytes": "15F6D484",
"text": "MOV:G.B @H'F6D4, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D4, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63188,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7089,
"address_region": "program_or_external",
"bytes": "15F6E494",
"text": "MOV:G.B R4, @H'F6E4",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63204,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7093,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7094,
"address_region": "program_or_external",
"bytes": "15F6D384",
"text": "MOV:G.B @H'F6D3, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D3, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63187,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7098,
"address_region": "program_or_external",
"bytes": "15F6E364",
"text": "XOR.B @H'F6E3, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E3, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63203,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7102,
"address_region": "program_or_external",
"bytes": "5D003E",
"text": "MOV:I.W #H'003E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'003E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7105,
"address_region": "program_or_external",
"bytes": "0E4B",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7107,
"address_region": "program_or_external",
"bytes": "15F6D384",
"text": "MOV:G.B @H'F6D3, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D3, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63187,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7111,
"address_region": "program_or_external",
"bytes": "15F6E394",
"text": "MOV:G.B R4, @H'F6E3",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63203,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7115,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7116,
"address_region": "program_or_external",
"bytes": "15F6D284",
"text": "MOV:G.B @H'F6D2, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63186,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7120,
"address_region": "program_or_external",
"bytes": "15F6E264",
"text": "XOR.B @H'F6E2, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6E2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63202,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7124,
"address_region": "program_or_external",
"bytes": "5D002E",
"text": "MOV:I.W #H'002E, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'002E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7127,
"address_region": "program_or_external",
"bytes": "0E35",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7129,
"address_region": "program_or_external",
"bytes": "15F6D284",
"text": "MOV:G.B @H'F6D2, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6D2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63186,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7133,
"address_region": "program_or_external",
"bytes": "15F6E294",
"text": "MOV:G.B R4, @H'F6E2",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6E2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63202,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7137,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7138,
"address_region": "program_or_external",
"bytes": "15F6DC84",
"text": "MOV:G.B @H'F6DC, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6DC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63196,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7142,
"address_region": "program_or_external",
"bytes": "15F6EC64",
"text": "XOR.B @H'F6EC, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6EC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63212,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7146,
"address_region": "program_or_external",
"bytes": "5D00CE",
"text": "MOV:I.W #H'00CE, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'00CE, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7149,
"address_region": "program_or_external",
"bytes": "0E1F",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7151,
"address_region": "program_or_external",
"bytes": "15F6DC84",
"text": "MOV:G.B @H'F6DC, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6DC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63196,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7155,
"address_region": "program_or_external",
"bytes": "15F6EC94",
"text": "MOV:G.B R4, @H'F6EC",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6EC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63212,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7159,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7160,
"address_region": "program_or_external",
"bytes": "15F6DB84",
"text": "MOV:G.B @H'F6DB, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6DB, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63195,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7164,
"address_region": "program_or_external",
"bytes": "15F6EB64",
"text": "XOR.B @H'F6EB, R4",
"mnemonic": "XOR.B",
"operands": "@H'F6EB, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63211,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7168,
"address_region": "program_or_external",
"bytes": "5D00BE",
"text": "MOV:I.W #H'00BE, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'00BE, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7171,
"address_region": "program_or_external",
"bytes": "0E09",
"text": "BSR loc_1C0E",
"mnemonic": "BSR",
"operands": "loc_1C0E",
"kind": "call",
"targets": [
7182
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7173,
"address_region": "program_or_external",
"bytes": "15F6DB84",
"text": "MOV:G.B @H'F6DB, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F6DB, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63195,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7177,
"address_region": "program_or_external",
"bytes": "15F6EB94",
"text": "MOV:G.B R4, @H'F6EB",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6EB",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63211,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 7181,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7182,
"address_region": "program_or_external",
"bytes": "A41A",
"text": "SHLL.B R4",
"mnemonic": "SHLL.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7184,
"address_region": "program_or_external",
"bytes": "240A",
"text": "BCC loc_1C1C",
"mnemonic": "BCC",
"operands": "loc_1C1C",
"kind": "branch",
"targets": [
7196
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7186,
"address_region": "program_or_external",
"bytes": "FD270680",
"text": "MOV:G.W @(H'2706,R5), R0",
"mnemonic": "MOV:G.W",
"operands": "@(H'2706,R5), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7190,
"address_region": "program_or_external",
"bytes": "1230",
"text": "STM.W {R4,R5}, @-SP",
"mnemonic": "STM.W",
"operands": "{R4,R5}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7192,
"address_region": "program_or_external",
"bytes": "11D8",
"text": "JSR @R0",
"mnemonic": "JSR",
"operands": "@R0",
"kind": "call",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7194,
"address_region": "program_or_external",
"bytes": "0230",
"text": "LDM.W @SP+, {R4,R5}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R4,R5}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7196,
"address_region": "program_or_external",
"bytes": "A416",
"text": "TST.B R4",
"mnemonic": "TST.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7198,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_1C24",
"mnemonic": "BEQ",
"operands": "loc_1C24",
"kind": "branch",
"targets": [
7204
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7200,
"address_region": "program_or_external",
"bytes": "AD0D",
"text": "ADD:Q.W #-2, R5",
"mnemonic": "ADD:Q.W",
"operands": "#-2, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7202,
"address_region": "program_or_external",
"bytes": "20EA",
"text": "BRA loc_1C0E",
"mnemonic": "BRA",
"operands": "loc_1C0E",
"kind": "jump",
"targets": [
7182
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 7204,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 8487,
"address_region": "program_or_external",
"bytes": "15FB03C7",
"text": "BSET.B #7, @H'FB03",
"mnemonic": "BSET.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 8491,
"address_region": "program_or_external",
"bytes": "2608",
"text": "BNE loc_2135",
"mnemonic": "BNE",
"operands": "loc_2135",
"kind": "branch",
"targets": [
8501
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 8493,
"address_region": "program_or_external",
"bytes": "1DF73281",
"text": "MOV:G.W @H'F732, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F732, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 8497,
"address_region": "program_or_external",
"bytes": "1DF73491",
"text": "MOV:G.W R1, @H'F734",
"mnemonic": "MOV:G.W",
"operands": "R1, @H'F734",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63284,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 8501,
"address_region": "program_or_external",
"bytes": "1DF732071C03",
"text": "MOV:G.W #H'1C03, @H'F732",
"mnemonic": "MOV:G.W",
"operands": "#H'1C03, @H'F732",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 8507,
"address_region": "program_or_external",
"bytes": "15FB020614",
"text": "MOV:G.B #H'14, @H'FB02",
"mnemonic": "MOV:G.B",
"operands": "#H'14, @H'FB02",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 8512,
"address_region": "program_or_external",
"bytes": "1E27B7",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 8515,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9808,
"address_region": "program_or_external",
"bytes": "15F6F6D5",
"text": "BCLR.B #5, @H'F6F6",
"mnemonic": "BCLR.B",
"operands": "#5, @H'F6F6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63222,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 9812,
"address_region": "program_or_external",
"bytes": "370068",
"text": "BEQ loc_26BF",
"mnemonic": "BEQ",
"operands": "loc_26BF",
"kind": "branch",
"targets": [
9919
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9815,
"address_region": "program_or_external",
"bytes": "1DE12480",
"text": "MOV:G.W @H'E124, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'E124, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57636,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 9819,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9821,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9823,
"address_region": "program_or_external",
"bytes": "15F6F6F6",
"text": "BTST.B #6, @H'F6F6",
"mnemonic": "BTST.B",
"operands": "#6, @H'F6F6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63222,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 9827,
"address_region": "program_or_external",
"bytes": "2608",
"text": "BNE loc_266D",
"mnemonic": "BNE",
"operands": "loc_266D",
"kind": "branch",
"targets": [
9837
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9829,
"address_region": "program_or_external",
"bytes": "A008",
"text": "ADD:Q.B #1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9831,
"address_region": "program_or_external",
"bytes": "241A",
"text": "BCC loc_2683",
"mnemonic": "BCC",
"operands": "loc_2683",
"kind": "branch",
"targets": [
9859
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9833,
"address_region": "program_or_external",
"bytes": "50FF",
"text": "MOV:E.B #H'FF, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'FF, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9835,
"address_region": "program_or_external",
"bytes": "2016",
"text": "BRA loc_2683",
"mnemonic": "BRA",
"operands": "loc_2683",
"kind": "jump",
"targets": [
9859
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9837,
"address_region": "program_or_external",
"bytes": "A00C",
"text": "ADD:Q.B #-1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#-1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9839,
"address_region": "program_or_external",
"bytes": "1DE004FD",
"text": "BTST.W #13, @H'E004",
"mnemonic": "BTST.W",
"operands": "#13, @H'E004",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57348,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 9843,
"address_region": "program_or_external",
"bytes": "2608",
"text": "BNE loc_267D",
"mnemonic": "BNE",
"operands": "loc_267D",
"kind": "branch",
"targets": [
9853
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9845,
"address_region": "program_or_external",
"bytes": "4049",
"text": "CMP:E #H'49, R0",
"mnemonic": "CMP:E",
"operands": "#H'49, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9847,
"address_region": "program_or_external",
"bytes": "240A",
"text": "BCC loc_2683",
"mnemonic": "BCC",
"operands": "loc_2683",
"kind": "branch",
"targets": [
9859
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9849,
"address_region": "program_or_external",
"bytes": "5049",
"text": "MOV:E.B #H'49, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'49, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9851,
"address_region": "program_or_external",
"bytes": "2006",
"text": "BRA loc_2683",
"mnemonic": "BRA",
"operands": "loc_2683",
"kind": "jump",
"targets": [
9859
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9853,
"address_region": "program_or_external",
"bytes": "4016",
"text": "CMP:E #H'16, R0",
"mnemonic": "CMP:E",
"operands": "#H'16, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9855,
"address_region": "program_or_external",
"bytes": "2402",
"text": "BCC loc_2683",
"mnemonic": "BCC",
"operands": "loc_2683",
"kind": "branch",
"targets": [
9859
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9857,
"address_region": "program_or_external",
"bytes": "5016",
"text": "MOV:E.B #H'16, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'16, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9859,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9861,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9863,
"address_region": "program_or_external",
"bytes": "A81B",
"text": "SHLR.W R0",
"mnemonic": "SHLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9865,
"address_region": "program_or_external",
"bytes": "A8CF",
"text": "BSET.W #15, R0",
"mnemonic": "BSET.W",
"operands": "#15, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9867,
"address_region": "program_or_external",
"bytes": "1DE12470",
"text": "CMP:G.W @H'E124, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'E124, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57636,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 9871,
"address_region": "program_or_external",
"bytes": "272E",
"text": "BEQ loc_26BF",
"mnemonic": "BEQ",
"operands": "loc_26BF",
"kind": "branch",
"targets": [
9919
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9873,
"address_region": "program_or_external",
"bytes": "1DE92490",
"text": "MOV:G.W R0, @H'E924",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'E924",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 59684,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 9877,
"address_region": "program_or_external",
"bytes": "5280",
"text": "MOV:E.B #H'80, R2",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9879,
"address_region": "program_or_external",
"bytes": "5B0092",
"text": "MOV:I.W #H'0092, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'0092, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9882,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 9886,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_26A8",
"mnemonic": "BEQ",
"operands": "loc_26A8",
"kind": "branch",
"targets": [
9896
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9888,
"address_region": "program_or_external",
"bytes": "15F404F4",
"text": "BTST.B #4, @H'F404",
"mnemonic": "BTST.B",
"operands": "#4, @H'F404",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62468,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 9892,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_26A8",
"mnemonic": "BEQ",
"operands": "loc_26A8",
"kind": "branch",
"targets": [
9896
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9894,
"address_region": "program_or_external",
"bytes": "ABCE",
"text": "BSET.W #14, R3",
"mnemonic": "BSET.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9896,
"address_region": "program_or_external",
"bytes": "1E17A9",
"text": "BSR loc_3E54",
"mnemonic": "BSR",
"operands": "loc_3E54",
"kind": "call",
"targets": [
15956
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9899,
"address_region": "program_or_external",
"bytes": "15F6F6C0",
"text": "BSET.B #0, @H'F6F6",
"mnemonic": "BSET.B",
"operands": "#0, @H'F6F6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63222,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 9903,
"address_region": "program_or_external",
"bytes": "2608",
"text": "BNE loc_26B9",
"mnemonic": "BNE",
"operands": "loc_26B9",
"kind": "branch",
"targets": [
9913
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9905,
"address_region": "program_or_external",
"bytes": "1DF6F40707D0",
"text": "MOV:G.W #H'07D0, @H'F6F4",
"mnemonic": "MOV:G.W",
"operands": "#H'07D0, @H'F6F4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63220,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 9911,
"address_region": "program_or_external",
"bytes": "2006",
"text": "BRA loc_26BF",
"mnemonic": "BRA",
"operands": "loc_26BF",
"kind": "jump",
"targets": [
9919
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 9913,
"address_region": "program_or_external",
"bytes": "1DF6F40700C8",
"text": "MOV:G.W #H'00C8, @H'F6F4",
"mnemonic": "MOV:G.W",
"operands": "#H'00C8, @H'F6F4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63220,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 9919,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10246,
"address_region": "program_or_external",
"bytes": "15F9B981",
"text": "MOV:G.B @H'F9B9, R1",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B9, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63929,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10250,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10252,
"address_region": "program_or_external",
"bytes": "15F9B471",
"text": "CMP:G.B @H'F9B4, R1",
"mnemonic": "CMP:G.B",
"operands": "@H'F9B4, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10256,
"address_region": "program_or_external",
"bytes": "2603",
"text": "BNE loc_2815",
"mnemonic": "BNE",
"operands": "loc_2815",
"kind": "branch",
"targets": [
10261
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10258,
"address_region": "program_or_external",
"bytes": "300491",
"text": "BRA loc_2CA6",
"mnemonic": "BRA",
"operands": "loc_2CA6",
"kind": "jump",
"targets": [
11430
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10261,
"address_region": "program_or_external",
"bytes": "A980",
"text": "MOV:G.W R1, R0",
"mnemonic": "MOV:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10263,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10265,
"address_region": "program_or_external",
"bytes": "F8F97080",
"text": "MOV:G.W @(-H'0690,R0), R0",
"mnemonic": "MOV:G.W",
"operands": "@(-H'0690,R0), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10269,
"address_region": "program_or_external",
"bytes": "A108",
"text": "ADD:Q.B #1, R1",
"mnemonic": "ADD:Q.B",
"operands": "#1, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10271,
"address_region": "program_or_external",
"bytes": "041F51",
"text": "AND.B #H'1F, R1",
"mnemonic": "AND.B",
"operands": "#H'1F, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10274,
"address_region": "program_or_external",
"bytes": "15F9B991",
"text": "MOV:G.B R1, @H'F9B9",
"mnemonic": "MOV:G.B",
"operands": "R1, @H'F9B9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63929,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10278,
"address_region": "program_or_external",
"bytes": "0C01FF50",
"text": "AND.W #H'01FF, R0",
"mnemonic": "AND.W",
"operands": "#H'01FF, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10282,
"address_region": "program_or_external",
"bytes": "A885",
"text": "MOV:G.W R0, R5",
"mnemonic": "MOV:G.W",
"operands": "R0, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10284,
"address_region": "program_or_external",
"bytes": "1E39D7",
"text": "BSR loc_6206",
"mnemonic": "BSR",
"operands": "loc_6206",
"kind": "call",
"targets": [
25094
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10287,
"address_region": "program_or_external",
"bytes": "A884",
"text": "MOV:G.W R0, R4",
"mnemonic": "MOV:G.W",
"operands": "R0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10289,
"address_region": "program_or_external",
"bytes": "AC1A",
"text": "SHLL.W R4",
"mnemonic": "SHLL.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10291,
"address_region": "program_or_external",
"bytes": "A816",
"text": "TST.W R0",
"mnemonic": "TST.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10293,
"address_region": "program_or_external",
"bytes": "2768",
"text": "BEQ loc_289F",
"mnemonic": "BEQ",
"operands": "loc_289F",
"kind": "branch",
"targets": [
10399
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10295,
"address_region": "program_or_external",
"bytes": "1DF73681",
"text": "MOV:G.W @H'F736, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F736, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63286,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10299,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10303,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10305,
"address_region": "program_or_external",
"bytes": "370467",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10308,
"address_region": "program_or_external",
"bytes": "1DF73881",
"text": "MOV:G.W @H'F738, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F738, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63288,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10312,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10316,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10318,
"address_region": "program_or_external",
"bytes": "37045A",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10321,
"address_region": "program_or_external",
"bytes": "1DF73A81",
"text": "MOV:G.W @H'F73A, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F73A, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63290,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10325,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10329,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10331,
"address_region": "program_or_external",
"bytes": "37044D",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10334,
"address_region": "program_or_external",
"bytes": "1DF73C81",
"text": "MOV:G.W @H'F73C, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F73C, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63292,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10338,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10342,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10344,
"address_region": "program_or_external",
"bytes": "370440",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10347,
"address_region": "program_or_external",
"bytes": "1DF73E81",
"text": "MOV:G.W @H'F73E, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F73E, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63294,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10351,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10355,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10357,
"address_region": "program_or_external",
"bytes": "370433",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10360,
"address_region": "program_or_external",
"bytes": "1DF74081",
"text": "MOV:G.W @H'F740, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F740, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63296,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10364,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10368,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10370,
"address_region": "program_or_external",
"bytes": "370426",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10373,
"address_region": "program_or_external",
"bytes": "1DF74281",
"text": "MOV:G.W @H'F742, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F742, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63298,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10377,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10381,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10383,
"address_region": "program_or_external",
"bytes": "370419",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10386,
"address_region": "program_or_external",
"bytes": "1DF75481",
"text": "MOV:G.W @H'F754, R1",
"mnemonic": "MOV:G.W",
"operands": "@H'F754, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63316,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 10390,
"address_region": "program_or_external",
"bytes": "0C01FF51",
"text": "AND.W #H'01FF, R1",
"mnemonic": "AND.W",
"operands": "#H'01FF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10394,
"address_region": "program_or_external",
"bytes": "A970",
"text": "CMP:G.W R1, R0",
"mnemonic": "CMP:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10396,
"address_region": "program_or_external",
"bytes": "37040C",
"text": "BEQ loc_2CAB",
"mnemonic": "BEQ",
"operands": "loc_2CAB",
"kind": "branch",
"targets": [
11435
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10399,
"address_region": "program_or_external",
"bytes": "FC28A681",
"text": "MOV:G.W @(H'28A6,R4), R1",
"mnemonic": "MOV:G.W",
"operands": "@(H'28A6,R4), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 10403,
"address_region": "program_or_external",
"bytes": "11D1",
"text": "JMP @R1",
"mnemonic": "JMP",
"operands": "@R1",
"kind": "jump",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 11430,
"address_region": "program_or_external",
"bytes": "15F769D7",
"text": "BCLR.B #7, @H'F769",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F769",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63337,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 11434,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 11435,
"address_region": "program_or_external",
"bytes": "1231",
"text": "STM.W {R0,R4,R5}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R4,R5}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 15,
"note": "6+3n, n=3",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 11437,
"address_region": "program_or_external",
"bytes": "1E1C4A",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 11440,
"address_region": "program_or_external",
"bytes": "0231",
"text": "LDM.W @SP+, {R0,R4,R5}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R4,R5}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 18,
"note": "6+4n, n=3",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 11442,
"address_region": "program_or_external",
"bytes": "15F769C7",
"text": "BSET.B #7, @H'F769",
"mnemonic": "BSET.B",
"operands": "#7, @H'F769",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63337,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 11446,
"address_region": "program_or_external",
"bytes": "30FBE6",
"text": "BRA loc_289F",
"mnemonic": "BRA",
"operands": "loc_289F",
"kind": "jump",
"targets": [
10399
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14640,
"address_region": "program_or_external",
"bytes": "580007",
"text": "MOV:I.W #H'0007, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'0007, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14643,
"address_region": "program_or_external",
"bytes": "15FE8E78",
"text": "BTST.B R0, @P7DR",
"mnemonic": "BTST.B",
"operands": "R0, @P7DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 14647,
"address_region": "program_or_external",
"bytes": "270A",
"text": "BEQ loc_3943",
"mnemonic": "BEQ",
"operands": "loc_3943",
"kind": "branch",
"targets": [
14659
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14649,
"address_region": "program_or_external",
"bytes": "F0F6801A",
"text": "SHLL.B @(-H'0980,R0)",
"mnemonic": "SHLL.B",
"operands": "@(-H'0980,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14653,
"address_region": "program_or_external",
"bytes": "F0F680C0",
"text": "BSET.B #0, @(-H'0980,R0)",
"mnemonic": "BSET.B",
"operands": "#0, @(-H'0980,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14657,
"address_region": "program_or_external",
"bytes": "2004",
"text": "BRA loc_3947",
"mnemonic": "BRA",
"operands": "loc_3947",
"kind": "jump",
"targets": [
14663
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14659,
"address_region": "program_or_external",
"bytes": "F0F6801A",
"text": "SHLL.B @(-H'0980,R0)",
"mnemonic": "SHLL.B",
"operands": "@(-H'0980,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14663,
"address_region": "program_or_external",
"bytes": "F0F68004FF",
"text": "CMP:G.B #H'FF, @(-H'0980,R0)",
"mnemonic": "CMP:G.B",
"operands": "#H'FF, @(-H'0980,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14668,
"address_region": "program_or_external",
"bytes": "2606",
"text": "BNE loc_3954",
"mnemonic": "BNE",
"operands": "loc_3954",
"kind": "branch",
"targets": [
14676
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14670,
"address_region": "program_or_external",
"bytes": "15F68848",
"text": "BSET.B R0, @H'F688",
"mnemonic": "BSET.B",
"operands": "R0, @H'F688",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63112,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14674,
"address_region": "program_or_external",
"bytes": "200B",
"text": "BRA loc_395F",
"mnemonic": "BRA",
"operands": "loc_395F",
"kind": "jump",
"targets": [
14687
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14676,
"address_region": "program_or_external",
"bytes": "F0F6800400",
"text": "CMP:G.B #H'00, @(-H'0980,R0)",
"mnemonic": "CMP:G.B",
"operands": "#H'00, @(-H'0980,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14681,
"address_region": "program_or_external",
"bytes": "2604",
"text": "BNE loc_395F",
"mnemonic": "BNE",
"operands": "loc_395F",
"kind": "branch",
"targets": [
14687
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14683,
"address_region": "program_or_external",
"bytes": "15F68858",
"text": "BCLR.B R0, @H'F688",
"mnemonic": "BCLR.B",
"operands": "R0, @H'F688",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63112,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14687,
"address_region": "program_or_external",
"bytes": "01B8D1",
"text": "SCB/F R0, loc_3933",
"mnemonic": "SCB/F",
"operands": "R0, loc_3933",
"kind": "branch",
"targets": [
14643
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 9,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14690,
"address_region": "program_or_external",
"bytes": "15F72208",
"text": "ADD:Q.B #1, @H'F722",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F722",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63266,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14694,
"address_region": "program_or_external",
"bytes": "15F722043C",
"text": "CMP:G.B #H'3C, @H'F722",
"mnemonic": "CMP:G.B",
"operands": "#H'3C, @H'F722",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63266,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14699,
"address_region": "program_or_external",
"bytes": "270F",
"text": "BEQ loc_397C",
"mnemonic": "BEQ",
"operands": "loc_397C",
"kind": "branch",
"targets": [
14716
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14701,
"address_region": "program_or_external",
"bytes": "15F7220478",
"text": "CMP:G.B #H'78, @H'F722",
"mnemonic": "CMP:G.B",
"operands": "#H'78, @H'F722",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63266,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14706,
"address_region": "program_or_external",
"bytes": "270B",
"text": "BEQ loc_397F",
"mnemonic": "BEQ",
"operands": "loc_397F",
"kind": "branch",
"targets": [
14719
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14708,
"address_region": "program_or_external",
"bytes": "15F72204B4",
"text": "CMP:G.B #H'B4, @H'F722",
"mnemonic": "CMP:G.B",
"operands": "#H'B4, @H'F722",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63266,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14713,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3983",
"mnemonic": "BEQ",
"operands": "loc_3983",
"kind": "branch",
"targets": [
14723
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14715,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14716,
"address_region": "program_or_external",
"bytes": "0E17",
"text": "BSR loc_3995",
"mnemonic": "BSR",
"operands": "loc_3995",
"kind": "call",
"targets": [
14741
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14718,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14719,
"address_region": "program_or_external",
"bytes": "1E00AC",
"text": "BSR loc_3A2E",
"mnemonic": "BSR",
"operands": "loc_3A2E",
"kind": "call",
"targets": [
14894
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14722,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14723,
"address_region": "program_or_external",
"bytes": "0E05",
"text": "BSR loc_398A",
"mnemonic": "BSR",
"operands": "loc_398A",
"kind": "call",
"targets": [
14730
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14725,
"address_region": "program_or_external",
"bytes": "15F72213",
"text": "CLR.B @H'F722",
"mnemonic": "CLR.B",
"operands": "@H'F722",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63266,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14729,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14730,
"address_region": "program_or_external",
"bytes": "15FEE8F7",
"text": "BTST.B #7, @ADCSR",
"mnemonic": "BTST.B",
"operands": "#7, @ADCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65256,
"name": "ADCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 14734,
"address_region": "program_or_external",
"bytes": "2604",
"text": "BNE loc_3994",
"mnemonic": "BNE",
"operands": "loc_3994",
"kind": "branch",
"targets": [
14740
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14736,
"address_region": "program_or_external",
"bytes": "15FEE8C5",
"text": "BSET.B #5, @ADCSR",
"mnemonic": "BSET.B",
"operands": "#5, @ADCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65256,
"name": "ADCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set ADST (bit 5) of ADCSR",
"valid": true
},
{
"address": 14740,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14741,
"address_region": "program_or_external",
"bytes": "15F72016",
"text": "TST.B @H'F720",
"mnemonic": "TST.B",
"operands": "@H'F720",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63264,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14745,
"address_region": "program_or_external",
"bytes": "360091",
"text": "BNE loc_3A2D",
"mnemonic": "BNE",
"operands": "loc_3A2D",
"kind": "branch",
"targets": [
14893
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14748,
"address_region": "program_or_external",
"bytes": "15F10106A0",
"text": "MOV:G.B #H'A0, @H'F101",
"mnemonic": "MOV:G.B",
"operands": "#H'A0, @H'F101",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61697,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14753,
"address_region": "program_or_external",
"bytes": "15F100F1",
"text": "BTST.B #1, @H'F100",
"mnemonic": "BTST.B",
"operands": "#1, @H'F100",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61696,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14757,
"address_region": "program_or_external",
"bytes": "370085",
"text": "BEQ loc_3A2D",
"mnemonic": "BEQ",
"operands": "loc_3A2D",
"kind": "branch",
"targets": [
14893
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14760,
"address_region": "program_or_external",
"bytes": "15F71B80",
"text": "MOV:G.B @H'F71B, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F71B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14764,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14768,
"address_region": "program_or_external",
"bytes": "15F71350",
"text": "AND.B @H'F713, R0",
"mnemonic": "AND.B",
"operands": "@H'F713, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63251,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14772,
"address_region": "program_or_external",
"bytes": "15F10290",
"text": "MOV:G.B R0, @H'F102",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F102",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61698,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14776,
"address_region": "program_or_external",
"bytes": "15F71A80",
"text": "MOV:G.B @H'F71A, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F71A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14780,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14784,
"address_region": "program_or_external",
"bytes": "15F71250",
"text": "AND.B @H'F712, R0",
"mnemonic": "AND.B",
"operands": "@H'F712, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63250,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14788,
"address_region": "program_or_external",
"bytes": "15F10390",
"text": "MOV:G.B R0, @H'F103",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F103",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61699,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14792,
"address_region": "program_or_external",
"bytes": "15F71980",
"text": "MOV:G.B @H'F719, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F719, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63257,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14796,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14800,
"address_region": "program_or_external",
"bytes": "15F71150",
"text": "AND.B @H'F711, R0",
"mnemonic": "AND.B",
"operands": "@H'F711, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63249,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14804,
"address_region": "program_or_external",
"bytes": "15F10490",
"text": "MOV:G.B R0, @H'F104",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F104",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61700,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14808,
"address_region": "program_or_external",
"bytes": "15F71880",
"text": "MOV:G.B @H'F718, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F718, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63256,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14812,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14816,
"address_region": "program_or_external",
"bytes": "15F71050",
"text": "AND.B @H'F710, R0",
"mnemonic": "AND.B",
"operands": "@H'F710, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63248,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14820,
"address_region": "program_or_external",
"bytes": "15F10590",
"text": "MOV:G.B R0, @H'F105",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F105",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61701,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14824,
"address_region": "program_or_external",
"bytes": "15F70280",
"text": "MOV:G.B @H'F702, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F702, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63234,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14828,
"address_region": "program_or_external",
"bytes": "15F10990",
"text": "MOV:G.B R0, @H'F109",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F109",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61705,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14832,
"address_region": "program_or_external",
"bytes": "15F70380",
"text": "MOV:G.B @H'F703, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F703, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63235,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14836,
"address_region": "program_or_external",
"bytes": "15F10A90",
"text": "MOV:G.B R0, @H'F10A",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F10A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61706,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14840,
"address_region": "program_or_external",
"bytes": "15F70480",
"text": "MOV:G.B @H'F704, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F704, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63236,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14844,
"address_region": "program_or_external",
"bytes": "15F10B90",
"text": "MOV:G.B R0, @H'F10B",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F10B",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61707,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14848,
"address_region": "program_or_external",
"bytes": "15F70580",
"text": "MOV:G.B @H'F705, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F705, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63237,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14852,
"address_region": "program_or_external",
"bytes": "15F10C90",
"text": "MOV:G.B R0, @H'F10C",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F10C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61708,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14856,
"address_region": "program_or_external",
"bytes": "15F70080",
"text": "MOV:G.B @H'F700, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F700, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63232,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14860,
"address_region": "program_or_external",
"bytes": "15F10D90",
"text": "MOV:G.B R0, @H'F10D",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F10D",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61709,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14864,
"address_region": "program_or_external",
"bytes": "15F70180",
"text": "MOV:G.B @H'F701, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F701, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63233,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14868,
"address_region": "program_or_external",
"bytes": "15F10E90",
"text": "MOV:G.B R0, @H'F10E",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F10E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61710,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14872,
"address_region": "program_or_external",
"bytes": "15FE8E80",
"text": "MOV:G.B @P7DR, R0",
"mnemonic": "MOV:G.B",
"operands": "@P7DR, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 14876,
"address_region": "program_or_external",
"bytes": "A015",
"text": "NOT.B R0",
"mnemonic": "NOT.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14878,
"address_region": "program_or_external",
"bytes": "040350",
"text": "AND.B #H'03, R0",
"mnemonic": "AND.B",
"operands": "#H'03, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14881,
"address_region": "program_or_external",
"bytes": "04A040",
"text": "OR.B #H'A0, R0",
"mnemonic": "OR.B",
"operands": "#H'A0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14884,
"address_region": "program_or_external",
"bytes": "15F10F90",
"text": "MOV:G.B R0, @H'F10F",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F10F",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61711,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14888,
"address_region": "program_or_external",
"bytes": "15F7200603",
"text": "MOV:G.B #H'03, @H'F720",
"mnemonic": "MOV:G.B",
"operands": "#H'03, @H'F720",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63264,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14893,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14894,
"address_region": "program_or_external",
"bytes": "15F72116",
"text": "TST.B @H'F721",
"mnemonic": "TST.B",
"operands": "@H'F721",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63265,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14898,
"address_region": "program_or_external",
"bytes": "360091",
"text": "BNE loc_3AC6",
"mnemonic": "BNE",
"operands": "loc_3AC6",
"kind": "branch",
"targets": [
15046
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14901,
"address_region": "program_or_external",
"bytes": "15F00106A0",
"text": "MOV:G.B #H'A0, @H'F001",
"mnemonic": "MOV:G.B",
"operands": "#H'A0, @H'F001",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61441,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14906,
"address_region": "program_or_external",
"bytes": "15F000F1",
"text": "BTST.B #1, @H'F000",
"mnemonic": "BTST.B",
"operands": "#1, @H'F000",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61440,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14910,
"address_region": "program_or_external",
"bytes": "370085",
"text": "BEQ loc_3AC6",
"mnemonic": "BEQ",
"operands": "loc_3AC6",
"kind": "branch",
"targets": [
15046
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 14913,
"address_region": "program_or_external",
"bytes": "15F71F80",
"text": "MOV:G.B @H'F71F, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F71F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63263,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14917,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14921,
"address_region": "program_or_external",
"bytes": "15F71750",
"text": "AND.B @H'F717, R0",
"mnemonic": "AND.B",
"operands": "@H'F717, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63255,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14925,
"address_region": "program_or_external",
"bytes": "15F00290",
"text": "MOV:G.B R0, @H'F002",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F002",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61442,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14929,
"address_region": "program_or_external",
"bytes": "15F71E80",
"text": "MOV:G.B @H'F71E, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F71E, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63262,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14933,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14937,
"address_region": "program_or_external",
"bytes": "15F71650",
"text": "AND.B @H'F716, R0",
"mnemonic": "AND.B",
"operands": "@H'F716, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63254,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14941,
"address_region": "program_or_external",
"bytes": "15F00390",
"text": "MOV:G.B R0, @H'F003",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F003",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61443,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14945,
"address_region": "program_or_external",
"bytes": "15F71D80",
"text": "MOV:G.B @H'F71D, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F71D, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63261,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14949,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14953,
"address_region": "program_or_external",
"bytes": "15F71550",
"text": "AND.B @H'F715, R0",
"mnemonic": "AND.B",
"operands": "@H'F715, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63253,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14957,
"address_region": "program_or_external",
"bytes": "15F00490",
"text": "MOV:G.B R0, @H'F004",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F004",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61444,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14961,
"address_region": "program_or_external",
"bytes": "15F71C80",
"text": "MOV:G.B @H'F71C, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F71C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63260,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14965,
"address_region": "program_or_external",
"bytes": "15F72340",
"text": "OR.B @H'F723, R0",
"mnemonic": "OR.B",
"operands": "@H'F723, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63267,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14969,
"address_region": "program_or_external",
"bytes": "15F71450",
"text": "AND.B @H'F714, R0",
"mnemonic": "AND.B",
"operands": "@H'F714, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63252,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14973,
"address_region": "program_or_external",
"bytes": "15F00590",
"text": "MOV:G.B R0, @H'F005",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F005",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61445,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14977,
"address_region": "program_or_external",
"bytes": "15F70880",
"text": "MOV:G.B @H'F708, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F708, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63240,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14981,
"address_region": "program_or_external",
"bytes": "15F00990",
"text": "MOV:G.B R0, @H'F009",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F009",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61449,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14985,
"address_region": "program_or_external",
"bytes": "15F70980",
"text": "MOV:G.B @H'F709, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F709, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63241,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14989,
"address_region": "program_or_external",
"bytes": "15F00A90",
"text": "MOV:G.B R0, @H'F00A",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F00A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61450,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 14993,
"address_region": "program_or_external",
"bytes": "15F70A80",
"text": "MOV:G.B @H'F70A, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F70A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63242,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 14997,
"address_region": "program_or_external",
"bytes": "15F00B90",
"text": "MOV:G.B R0, @H'F00B",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F00B",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61451,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15001,
"address_region": "program_or_external",
"bytes": "15F70B80",
"text": "MOV:G.B @H'F70B, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F70B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63243,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15005,
"address_region": "program_or_external",
"bytes": "15F00C90",
"text": "MOV:G.B R0, @H'F00C",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F00C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61452,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15009,
"address_region": "program_or_external",
"bytes": "15F70680",
"text": "MOV:G.B @H'F706, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F706, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63238,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15013,
"address_region": "program_or_external",
"bytes": "15F00D90",
"text": "MOV:G.B R0, @H'F00D",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F00D",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61453,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15017,
"address_region": "program_or_external",
"bytes": "15F70780",
"text": "MOV:G.B @H'F707, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F707, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63239,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15021,
"address_region": "program_or_external",
"bytes": "15F00E90",
"text": "MOV:G.B R0, @H'F00E",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F00E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61454,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15025,
"address_region": "program_or_external",
"bytes": "15FE8E80",
"text": "MOV:G.B @P7DR, R0",
"mnemonic": "MOV:G.B",
"operands": "@P7DR, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 15029,
"address_region": "program_or_external",
"bytes": "A015",
"text": "NOT.B R0",
"mnemonic": "NOT.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15031,
"address_region": "program_or_external",
"bytes": "040350",
"text": "AND.B #H'03, R0",
"mnemonic": "AND.B",
"operands": "#H'03, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15034,
"address_region": "program_or_external",
"bytes": "04A040",
"text": "OR.B #H'A0, R0",
"mnemonic": "OR.B",
"operands": "#H'A0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15037,
"address_region": "program_or_external",
"bytes": "15F00F90",
"text": "MOV:G.B R0, @H'F00F",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F00F",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61455,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15041,
"address_region": "program_or_external",
"bytes": "15F7210603",
"text": "MOV:G.B #H'03, @H'F721",
"mnemonic": "MOV:G.B",
"operands": "#H'03, @H'F721",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63265,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15046,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15047,
"address_region": "program_or_external",
"bytes": "BF90",
"text": "MOV:G.W R0, @-R7",
"mnemonic": "MOV:G.W",
"operands": "R0, @-R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 5,
"base_cycles": 5,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15049,
"address_region": "program_or_external",
"bytes": "15F100F1",
"text": "BTST.B #1, @H'F100",
"mnemonic": "BTST.B",
"operands": "#1, @H'F100",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61696,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15053,
"address_region": "program_or_external",
"bytes": "36015D",
"text": "BNE loc_3C2D",
"mnemonic": "BNE",
"operands": "loc_3C2D",
"kind": "branch",
"targets": [
15405
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15056,
"address_region": "program_or_external",
"bytes": "15F10F80",
"text": "MOV:G.B @H'F10F, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F10F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61711,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15060,
"address_region": "program_or_external",
"bytes": "40A9",
"text": "CMP:E #H'A9, R0",
"mnemonic": "CMP:E",
"operands": "#H'A9, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15062,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3AE0",
"mnemonic": "BEQ",
"operands": "loc_3AE0",
"kind": "branch",
"targets": [
15072
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15064,
"address_region": "program_or_external",
"bytes": "40A8",
"text": "CMP:E #H'A8, R0",
"mnemonic": "CMP:E",
"operands": "#H'A8, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15066,
"address_region": "program_or_external",
"bytes": "370085",
"text": "BEQ loc_3B62",
"mnemonic": "BEQ",
"operands": "loc_3B62",
"kind": "branch",
"targets": [
15202
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15069,
"address_region": "program_or_external",
"bytes": "30014D",
"text": "BRA loc_3C2D",
"mnemonic": "BRA",
"operands": "loc_3C2D",
"kind": "jump",
"targets": [
15405
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15072,
"address_region": "program_or_external",
"bytes": "15F6F080",
"text": "MOV:G.B @H'F6F0, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F6F0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15076,
"address_region": "program_or_external",
"bytes": "04C050",
"text": "AND.B #H'C0, R0",
"mnemonic": "AND.B",
"operands": "#H'C0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15079,
"address_region": "program_or_external",
"bytes": "15F6F090",
"text": "MOV:G.B R0, @H'F6F0",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15083,
"address_region": "program_or_external",
"bytes": "1DF10C80",
"text": "MOV:G.W @H'F10C, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F10C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61708,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15087,
"address_region": "program_or_external",
"bytes": "1DF69A70",
"text": "CMP:G.W @H'F69A, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F69A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63130,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15091,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3AFD",
"mnemonic": "BEQ",
"operands": "loc_3AFD",
"kind": "branch",
"targets": [
15101
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15093,
"address_region": "program_or_external",
"bytes": "15F6F0C5",
"text": "BSET.B #5, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#5, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15097,
"address_region": "program_or_external",
"bytes": "1DF69A90",
"text": "MOV:G.W R0, @H'F69A",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F69A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63130,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15101,
"address_region": "program_or_external",
"bytes": "1DF10A80",
"text": "MOV:G.W @H'F10A, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F10A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61706,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15105,
"address_region": "program_or_external",
"bytes": "1DF69870",
"text": "CMP:G.W @H'F698, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F698, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63128,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15109,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B0F",
"mnemonic": "BEQ",
"operands": "loc_3B0F",
"kind": "branch",
"targets": [
15119
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15111,
"address_region": "program_or_external",
"bytes": "15F6F0C4",
"text": "BSET.B #4, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#4, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15115,
"address_region": "program_or_external",
"bytes": "1DF69890",
"text": "MOV:G.W R0, @H'F698",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F698",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63128,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15119,
"address_region": "program_or_external",
"bytes": "1DF10880",
"text": "MOV:G.W @H'F108, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F108, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61704,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15123,
"address_region": "program_or_external",
"bytes": "1DF69670",
"text": "CMP:G.W @H'F696, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F696, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63126,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15127,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B21",
"mnemonic": "BEQ",
"operands": "loc_3B21",
"kind": "branch",
"targets": [
15137
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15129,
"address_region": "program_or_external",
"bytes": "15F6F0C3",
"text": "BSET.B #3, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#3, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15133,
"address_region": "program_or_external",
"bytes": "1DF69690",
"text": "MOV:G.W R0, @H'F696",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F696",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63126,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15137,
"address_region": "program_or_external",
"bytes": "1DF10680",
"text": "MOV:G.W @H'F106, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F106, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61702,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15141,
"address_region": "program_or_external",
"bytes": "1DF69470",
"text": "CMP:G.W @H'F694, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F694, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63124,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15145,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B33",
"mnemonic": "BEQ",
"operands": "loc_3B33",
"kind": "branch",
"targets": [
15155
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15147,
"address_region": "program_or_external",
"bytes": "15F6F0C2",
"text": "BSET.B #2, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#2, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15151,
"address_region": "program_or_external",
"bytes": "1DF69490",
"text": "MOV:G.W R0, @H'F694",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F694",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63124,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15155,
"address_region": "program_or_external",
"bytes": "1DF10480",
"text": "MOV:G.W @H'F104, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F104, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61700,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15159,
"address_region": "program_or_external",
"bytes": "1DF69270",
"text": "CMP:G.W @H'F692, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F692, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63122,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15163,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B45",
"mnemonic": "BEQ",
"operands": "loc_3B45",
"kind": "branch",
"targets": [
15173
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15165,
"address_region": "program_or_external",
"bytes": "15F6F0C1",
"text": "BSET.B #1, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#1, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15169,
"address_region": "program_or_external",
"bytes": "1DF69290",
"text": "MOV:G.W R0, @H'F692",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F692",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63122,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15173,
"address_region": "program_or_external",
"bytes": "1DF10280",
"text": "MOV:G.W @H'F102, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F102, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61698,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15177,
"address_region": "program_or_external",
"bytes": "1DF69070",
"text": "CMP:G.W @H'F690, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F690, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63120,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15181,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B57",
"mnemonic": "BEQ",
"operands": "loc_3B57",
"kind": "branch",
"targets": [
15191
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15183,
"address_region": "program_or_external",
"bytes": "15F6F0C0",
"text": "BSET.B #0, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#0, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15187,
"address_region": "program_or_external",
"bytes": "1DF69090",
"text": "MOV:G.W R0, @H'F690",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F690",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63120,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15191,
"address_region": "program_or_external",
"bytes": "15F10180",
"text": "MOV:G.B @H'F101, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F101, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61697,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15195,
"address_region": "program_or_external",
"bytes": "15F720D0",
"text": "BCLR.B #0, @H'F720",
"mnemonic": "BCLR.B",
"operands": "#0, @H'F720",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63264,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15199,
"address_region": "program_or_external",
"bytes": "3000CB",
"text": "BRA loc_3C2D",
"mnemonic": "BRA",
"operands": "loc_3C2D",
"kind": "jump",
"targets": [
15405
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15202,
"address_region": "program_or_external",
"bytes": "15F6F080",
"text": "MOV:G.B @H'F6F0, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F6F0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15206,
"address_region": "program_or_external",
"bytes": "043F50",
"text": "AND.B #H'3F, R0",
"mnemonic": "AND.B",
"operands": "#H'3F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15209,
"address_region": "program_or_external",
"bytes": "15F6F090",
"text": "MOV:G.B R0, @H'F6F0",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15213,
"address_region": "program_or_external",
"bytes": "15F6F213",
"text": "CLR.B @H'F6F2",
"mnemonic": "CLR.B",
"operands": "@H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15217,
"address_region": "program_or_external",
"bytes": "1DF10C80",
"text": "MOV:G.W @H'F10C, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F10C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61708,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15221,
"address_region": "program_or_external",
"bytes": "1DF69E70",
"text": "CMP:G.W @H'F69E, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F69E, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63134,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15225,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B83",
"mnemonic": "BEQ",
"operands": "loc_3B83",
"kind": "branch",
"targets": [
15235
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15227,
"address_region": "program_or_external",
"bytes": "15F6F0C7",
"text": "BSET.B #7, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#7, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15231,
"address_region": "program_or_external",
"bytes": "1DF69E90",
"text": "MOV:G.W R0, @H'F69E",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F69E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63134,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15235,
"address_region": "program_or_external",
"bytes": "1DF10A80",
"text": "MOV:G.W @H'F10A, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F10A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61706,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15239,
"address_region": "program_or_external",
"bytes": "1DF69C70",
"text": "CMP:G.W @H'F69C, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F69C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63132,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15243,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3B95",
"mnemonic": "BEQ",
"operands": "loc_3B95",
"kind": "branch",
"targets": [
15253
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15245,
"address_region": "program_or_external",
"bytes": "15F6F0C6",
"text": "BSET.B #6, @H'F6F0",
"mnemonic": "BSET.B",
"operands": "#6, @H'F6F0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63216,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15249,
"address_region": "program_or_external",
"bytes": "1DF69C90",
"text": "MOV:G.W R0, @H'F69C",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F69C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63132,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15253,
"address_region": "program_or_external",
"bytes": "15F10980",
"text": "MOV:G.B @H'F109, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F109, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61705,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15257,
"address_region": "program_or_external",
"bytes": "15F6D070",
"text": "CMP:G.B @H'F6D0, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63184,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15261,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3BA7",
"mnemonic": "BEQ",
"operands": "loc_3BA7",
"kind": "branch",
"targets": [
15271
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15263,
"address_region": "program_or_external",
"bytes": "15F6F2C0",
"text": "BSET.B #0, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#0, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15267,
"address_region": "program_or_external",
"bytes": "15F6D090",
"text": "MOV:G.B R0, @H'F6D0",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63184,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15271,
"address_region": "program_or_external",
"bytes": "15F10880",
"text": "MOV:G.B @H'F108, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F108, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61704,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15275,
"address_region": "program_or_external",
"bytes": "15F6D170",
"text": "CMP:G.B @H'F6D1, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63185,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15279,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3BB9",
"mnemonic": "BEQ",
"operands": "loc_3BB9",
"kind": "branch",
"targets": [
15289
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15281,
"address_region": "program_or_external",
"bytes": "15F6F2C1",
"text": "BSET.B #1, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#1, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15285,
"address_region": "program_or_external",
"bytes": "15F6D190",
"text": "MOV:G.B R0, @H'F6D1",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63185,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15289,
"address_region": "program_or_external",
"bytes": "15F10780",
"text": "MOV:G.B @H'F107, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F107, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61703,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15293,
"address_region": "program_or_external",
"bytes": "15F6D270",
"text": "CMP:G.B @H'F6D2, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63186,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15297,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3BCB",
"mnemonic": "BEQ",
"operands": "loc_3BCB",
"kind": "branch",
"targets": [
15307
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15299,
"address_region": "program_or_external",
"bytes": "15F6F2C2",
"text": "BSET.B #2, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#2, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15303,
"address_region": "program_or_external",
"bytes": "15F6D290",
"text": "MOV:G.B R0, @H'F6D2",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63186,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15307,
"address_region": "program_or_external",
"bytes": "15F10680",
"text": "MOV:G.B @H'F106, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F106, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61702,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15311,
"address_region": "program_or_external",
"bytes": "15F6D370",
"text": "CMP:G.B @H'F6D3, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D3, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63187,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15315,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3BDD",
"mnemonic": "BEQ",
"operands": "loc_3BDD",
"kind": "branch",
"targets": [
15325
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15317,
"address_region": "program_or_external",
"bytes": "15F6F2C3",
"text": "BSET.B #3, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#3, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15321,
"address_region": "program_or_external",
"bytes": "15F6D390",
"text": "MOV:G.B R0, @H'F6D3",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63187,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15325,
"address_region": "program_or_external",
"bytes": "15F10580",
"text": "MOV:G.B @H'F105, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F105, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61701,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15329,
"address_region": "program_or_external",
"bytes": "15F6D470",
"text": "CMP:G.B @H'F6D4, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D4, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63188,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15333,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3BEF",
"mnemonic": "BEQ",
"operands": "loc_3BEF",
"kind": "branch",
"targets": [
15343
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15335,
"address_region": "program_or_external",
"bytes": "15F6F2C4",
"text": "BSET.B #4, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#4, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15339,
"address_region": "program_or_external",
"bytes": "15F6D490",
"text": "MOV:G.B R0, @H'F6D4",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63188,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15343,
"address_region": "program_or_external",
"bytes": "15F10480",
"text": "MOV:G.B @H'F104, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F104, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61700,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15347,
"address_region": "program_or_external",
"bytes": "15F6D570",
"text": "CMP:G.B @H'F6D5, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D5, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63189,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15351,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C01",
"mnemonic": "BEQ",
"operands": "loc_3C01",
"kind": "branch",
"targets": [
15361
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15353,
"address_region": "program_or_external",
"bytes": "15F6F2C5",
"text": "BSET.B #5, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#5, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15357,
"address_region": "program_or_external",
"bytes": "15F6D590",
"text": "MOV:G.B R0, @H'F6D5",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63189,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15361,
"address_region": "program_or_external",
"bytes": "15F10380",
"text": "MOV:G.B @H'F103, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F103, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61699,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15365,
"address_region": "program_or_external",
"bytes": "15F6D670",
"text": "CMP:G.B @H'F6D6, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D6, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63190,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15369,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C13",
"mnemonic": "BEQ",
"operands": "loc_3C13",
"kind": "branch",
"targets": [
15379
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15371,
"address_region": "program_or_external",
"bytes": "15F6F2C6",
"text": "BSET.B #6, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#6, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15375,
"address_region": "program_or_external",
"bytes": "15F6D690",
"text": "MOV:G.B R0, @H'F6D6",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63190,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15379,
"address_region": "program_or_external",
"bytes": "15F10280",
"text": "MOV:G.B @H'F102, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F102, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61698,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15383,
"address_region": "program_or_external",
"bytes": "15F6D770",
"text": "CMP:G.B @H'F6D7, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D7, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63191,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15387,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C25",
"mnemonic": "BEQ",
"operands": "loc_3C25",
"kind": "branch",
"targets": [
15397
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15389,
"address_region": "program_or_external",
"bytes": "15F6F2C7",
"text": "BSET.B #7, @H'F6F2",
"mnemonic": "BSET.B",
"operands": "#7, @H'F6F2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63218,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15393,
"address_region": "program_or_external",
"bytes": "15F6D790",
"text": "MOV:G.B R0, @H'F6D7",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63191,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15397,
"address_region": "program_or_external",
"bytes": "15F10180",
"text": "MOV:G.B @H'F101, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F101, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61697,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15401,
"address_region": "program_or_external",
"bytes": "15F720D1",
"text": "BCLR.B #1, @H'F720",
"mnemonic": "BCLR.B",
"operands": "#1, @H'F720",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63264,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15405,
"address_region": "program_or_external",
"bytes": "CF80",
"text": "MOV:G.W @R7+, R0",
"mnemonic": "MOV:G.W",
"operands": "@R7+, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15407,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 13,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15408,
"address_region": "program_or_external",
"bytes": "BF90",
"text": "MOV:G.W R0, @-R7",
"mnemonic": "MOV:G.W",
"operands": "R0, @-R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15410,
"address_region": "program_or_external",
"bytes": "15F000F1",
"text": "BTST.B #1, @H'F000",
"mnemonic": "BTST.B",
"operands": "#1, @H'F000",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61440,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15414,
"address_region": "program_or_external",
"bytes": "36015D",
"text": "BNE loc_3D96",
"mnemonic": "BNE",
"operands": "loc_3D96",
"kind": "branch",
"targets": [
15766
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15417,
"address_region": "program_or_external",
"bytes": "15F00F80",
"text": "MOV:G.B @H'F00F, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F00F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61455,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15421,
"address_region": "program_or_external",
"bytes": "40A9",
"text": "CMP:E #H'A9, R0",
"mnemonic": "CMP:E",
"operands": "#H'A9, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15423,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C49",
"mnemonic": "BEQ",
"operands": "loc_3C49",
"kind": "branch",
"targets": [
15433
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15425,
"address_region": "program_or_external",
"bytes": "40A8",
"text": "CMP:E #H'A8, R0",
"mnemonic": "CMP:E",
"operands": "#H'A8, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15427,
"address_region": "program_or_external",
"bytes": "370085",
"text": "BEQ loc_3CCB",
"mnemonic": "BEQ",
"operands": "loc_3CCB",
"kind": "branch",
"targets": [
15563
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15430,
"address_region": "program_or_external",
"bytes": "30014D",
"text": "BRA loc_3D96",
"mnemonic": "BRA",
"operands": "loc_3D96",
"kind": "jump",
"targets": [
15766
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15433,
"address_region": "program_or_external",
"bytes": "15F6F180",
"text": "MOV:G.B @H'F6F1, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F6F1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15437,
"address_region": "program_or_external",
"bytes": "04C050",
"text": "AND.B #H'C0, R0",
"mnemonic": "AND.B",
"operands": "#H'C0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15440,
"address_region": "program_or_external",
"bytes": "15F6F190",
"text": "MOV:G.B R0, @H'F6F1",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15444,
"address_region": "program_or_external",
"bytes": "1DF00C80",
"text": "MOV:G.W @H'F00C, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F00C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61452,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15448,
"address_region": "program_or_external",
"bytes": "1DF6AA70",
"text": "CMP:G.W @H'F6AA, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6AA, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63146,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15452,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C66",
"mnemonic": "BEQ",
"operands": "loc_3C66",
"kind": "branch",
"targets": [
15462
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15454,
"address_region": "program_or_external",
"bytes": "15F6F1C5",
"text": "BSET.B #5, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#5, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15458,
"address_region": "program_or_external",
"bytes": "1DF6AA90",
"text": "MOV:G.W R0, @H'F6AA",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6AA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63146,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15462,
"address_region": "program_or_external",
"bytes": "1DF00A80",
"text": "MOV:G.W @H'F00A, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F00A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61450,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15466,
"address_region": "program_or_external",
"bytes": "1DF6A870",
"text": "CMP:G.W @H'F6A8, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6A8, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63144,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15470,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C78",
"mnemonic": "BEQ",
"operands": "loc_3C78",
"kind": "branch",
"targets": [
15480
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15472,
"address_region": "program_or_external",
"bytes": "15F6F1C4",
"text": "BSET.B #4, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#4, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15476,
"address_region": "program_or_external",
"bytes": "1DF6A890",
"text": "MOV:G.W R0, @H'F6A8",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6A8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63144,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15480,
"address_region": "program_or_external",
"bytes": "1DF00880",
"text": "MOV:G.W @H'F008, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F008, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61448,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15484,
"address_region": "program_or_external",
"bytes": "1DF6A670",
"text": "CMP:G.W @H'F6A6, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6A6, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63142,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15488,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C8A",
"mnemonic": "BEQ",
"operands": "loc_3C8A",
"kind": "branch",
"targets": [
15498
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15490,
"address_region": "program_or_external",
"bytes": "15F6F1C3",
"text": "BSET.B #3, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#3, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15494,
"address_region": "program_or_external",
"bytes": "1DF6A690",
"text": "MOV:G.W R0, @H'F6A6",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6A6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63142,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15498,
"address_region": "program_or_external",
"bytes": "1DF00680",
"text": "MOV:G.W @H'F006, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F006, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61446,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15502,
"address_region": "program_or_external",
"bytes": "1DF6A470",
"text": "CMP:G.W @H'F6A4, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6A4, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63140,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15506,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3C9C",
"mnemonic": "BEQ",
"operands": "loc_3C9C",
"kind": "branch",
"targets": [
15516
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15508,
"address_region": "program_or_external",
"bytes": "15F6F1C2",
"text": "BSET.B #2, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#2, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15512,
"address_region": "program_or_external",
"bytes": "1DF6A490",
"text": "MOV:G.W R0, @H'F6A4",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6A4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63140,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15516,
"address_region": "program_or_external",
"bytes": "1DF00480",
"text": "MOV:G.W @H'F004, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F004, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61444,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15520,
"address_region": "program_or_external",
"bytes": "1DF6A270",
"text": "CMP:G.W @H'F6A2, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6A2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63138,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15524,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3CAE",
"mnemonic": "BEQ",
"operands": "loc_3CAE",
"kind": "branch",
"targets": [
15534
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15526,
"address_region": "program_or_external",
"bytes": "15F6F1C1",
"text": "BSET.B #1, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#1, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15530,
"address_region": "program_or_external",
"bytes": "1DF6A290",
"text": "MOV:G.W R0, @H'F6A2",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6A2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63138,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15534,
"address_region": "program_or_external",
"bytes": "1DF00280",
"text": "MOV:G.W @H'F002, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F002, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61442,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15538,
"address_region": "program_or_external",
"bytes": "1DF6A070",
"text": "CMP:G.W @H'F6A0, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6A0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63136,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15542,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3CC0",
"mnemonic": "BEQ",
"operands": "loc_3CC0",
"kind": "branch",
"targets": [
15552
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15544,
"address_region": "program_or_external",
"bytes": "15F6F1C0",
"text": "BSET.B #0, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#0, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15548,
"address_region": "program_or_external",
"bytes": "1DF6A090",
"text": "MOV:G.W R0, @H'F6A0",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6A0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63136,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15552,
"address_region": "program_or_external",
"bytes": "15F00180",
"text": "MOV:G.B @H'F001, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F001, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61441,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15556,
"address_region": "program_or_external",
"bytes": "15F721D0",
"text": "BCLR.B #0, @H'F721",
"mnemonic": "BCLR.B",
"operands": "#0, @H'F721",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63265,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15560,
"address_region": "program_or_external",
"bytes": "3000CB",
"text": "BRA loc_3D96",
"mnemonic": "BRA",
"operands": "loc_3D96",
"kind": "jump",
"targets": [
15766
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15563,
"address_region": "program_or_external",
"bytes": "15F6F180",
"text": "MOV:G.B @H'F6F1, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F6F1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15567,
"address_region": "program_or_external",
"bytes": "043F50",
"text": "AND.B #H'3F, R0",
"mnemonic": "AND.B",
"operands": "#H'3F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15570,
"address_region": "program_or_external",
"bytes": "15F6F190",
"text": "MOV:G.B R0, @H'F6F1",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15574,
"address_region": "program_or_external",
"bytes": "15F6F313",
"text": "CLR.B @H'F6F3",
"mnemonic": "CLR.B",
"operands": "@H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15578,
"address_region": "program_or_external",
"bytes": "1DF00C80",
"text": "MOV:G.W @H'F00C, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F00C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61452,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15582,
"address_region": "program_or_external",
"bytes": "1DF6AE70",
"text": "CMP:G.W @H'F6AE, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6AE, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63150,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15586,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3CEC",
"mnemonic": "BEQ",
"operands": "loc_3CEC",
"kind": "branch",
"targets": [
15596
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15588,
"address_region": "program_or_external",
"bytes": "15F6F1C7",
"text": "BSET.B #7, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#7, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15592,
"address_region": "program_or_external",
"bytes": "1DF6AE90",
"text": "MOV:G.W R0, @H'F6AE",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6AE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63150,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15596,
"address_region": "program_or_external",
"bytes": "1DF00A80",
"text": "MOV:G.W @H'F00A, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F00A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61450,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15600,
"address_region": "program_or_external",
"bytes": "1DF6AC70",
"text": "CMP:G.W @H'F6AC, R0",
"mnemonic": "CMP:G.W",
"operands": "@H'F6AC, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63148,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15604,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3CFE",
"mnemonic": "BEQ",
"operands": "loc_3CFE",
"kind": "branch",
"targets": [
15614
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15606,
"address_region": "program_or_external",
"bytes": "15F6F1C6",
"text": "BSET.B #6, @H'F6F1",
"mnemonic": "BSET.B",
"operands": "#6, @H'F6F1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63217,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15610,
"address_region": "program_or_external",
"bytes": "1DF6AC90",
"text": "MOV:G.W R0, @H'F6AC",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F6AC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63148,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15614,
"address_region": "program_or_external",
"bytes": "15F00980",
"text": "MOV:G.B @H'F009, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F009, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61449,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15618,
"address_region": "program_or_external",
"bytes": "15F6D870",
"text": "CMP:G.B @H'F6D8, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D8, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63192,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15622,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D10",
"mnemonic": "BEQ",
"operands": "loc_3D10",
"kind": "branch",
"targets": [
15632
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15624,
"address_region": "program_or_external",
"bytes": "15F6F3C0",
"text": "BSET.B #0, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#0, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15628,
"address_region": "program_or_external",
"bytes": "15F6D890",
"text": "MOV:G.B R0, @H'F6D8",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63192,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15632,
"address_region": "program_or_external",
"bytes": "15F00880",
"text": "MOV:G.B @H'F008, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F008, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61448,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15636,
"address_region": "program_or_external",
"bytes": "15F6D970",
"text": "CMP:G.B @H'F6D9, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6D9, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63193,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15640,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D22",
"mnemonic": "BEQ",
"operands": "loc_3D22",
"kind": "branch",
"targets": [
15650
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15642,
"address_region": "program_or_external",
"bytes": "15F6F3C1",
"text": "BSET.B #1, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#1, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15646,
"address_region": "program_or_external",
"bytes": "15F6D990",
"text": "MOV:G.B R0, @H'F6D9",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6D9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63193,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15650,
"address_region": "program_or_external",
"bytes": "15F00780",
"text": "MOV:G.B @H'F007, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F007, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61447,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15654,
"address_region": "program_or_external",
"bytes": "15F6DA70",
"text": "CMP:G.B @H'F6DA, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6DA, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63194,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15658,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D34",
"mnemonic": "BEQ",
"operands": "loc_3D34",
"kind": "branch",
"targets": [
15668
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15660,
"address_region": "program_or_external",
"bytes": "15F6F3C2",
"text": "BSET.B #2, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#2, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15664,
"address_region": "program_or_external",
"bytes": "15F6DA90",
"text": "MOV:G.B R0, @H'F6DA",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6DA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63194,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15668,
"address_region": "program_or_external",
"bytes": "15F00680",
"text": "MOV:G.B @H'F006, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F006, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61446,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15672,
"address_region": "program_or_external",
"bytes": "15F6DB70",
"text": "CMP:G.B @H'F6DB, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6DB, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63195,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15676,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D46",
"mnemonic": "BEQ",
"operands": "loc_3D46",
"kind": "branch",
"targets": [
15686
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15678,
"address_region": "program_or_external",
"bytes": "15F6F3C3",
"text": "BSET.B #3, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#3, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15682,
"address_region": "program_or_external",
"bytes": "15F6DB90",
"text": "MOV:G.B R0, @H'F6DB",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6DB",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63195,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15686,
"address_region": "program_or_external",
"bytes": "15F00580",
"text": "MOV:G.B @H'F005, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F005, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61445,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15690,
"address_region": "program_or_external",
"bytes": "15F6DC70",
"text": "CMP:G.B @H'F6DC, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6DC, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63196,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15694,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D58",
"mnemonic": "BEQ",
"operands": "loc_3D58",
"kind": "branch",
"targets": [
15704
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15696,
"address_region": "program_or_external",
"bytes": "15F6F3C4",
"text": "BSET.B #4, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#4, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15700,
"address_region": "program_or_external",
"bytes": "15F6DC90",
"text": "MOV:G.B R0, @H'F6DC",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6DC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63196,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15704,
"address_region": "program_or_external",
"bytes": "15F00480",
"text": "MOV:G.B @H'F004, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F004, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61444,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15708,
"address_region": "program_or_external",
"bytes": "15F6DD70",
"text": "CMP:G.B @H'F6DD, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6DD, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63197,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15712,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D6A",
"mnemonic": "BEQ",
"operands": "loc_3D6A",
"kind": "branch",
"targets": [
15722
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15714,
"address_region": "program_or_external",
"bytes": "15F6F3C5",
"text": "BSET.B #5, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#5, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15718,
"address_region": "program_or_external",
"bytes": "15F6DD90",
"text": "MOV:G.B R0, @H'F6DD",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6DD",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63197,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15722,
"address_region": "program_or_external",
"bytes": "15F00380",
"text": "MOV:G.B @H'F003, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F003, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61443,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15726,
"address_region": "program_or_external",
"bytes": "15F6DE70",
"text": "CMP:G.B @H'F6DE, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6DE, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63198,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15730,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D7C",
"mnemonic": "BEQ",
"operands": "loc_3D7C",
"kind": "branch",
"targets": [
15740
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15732,
"address_region": "program_or_external",
"bytes": "15F6F3C6",
"text": "BSET.B #6, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#6, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15736,
"address_region": "program_or_external",
"bytes": "15F6DE90",
"text": "MOV:G.B R0, @H'F6DE",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6DE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63198,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15740,
"address_region": "program_or_external",
"bytes": "15F00280",
"text": "MOV:G.B @H'F002, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F002, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61442,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15744,
"address_region": "program_or_external",
"bytes": "15F6DF70",
"text": "CMP:G.B @H'F6DF, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F6DF, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63199,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15748,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3D8E",
"mnemonic": "BEQ",
"operands": "loc_3D8E",
"kind": "branch",
"targets": [
15758
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15750,
"address_region": "program_or_external",
"bytes": "15F6F3C7",
"text": "BSET.B #7, @H'F6F3",
"mnemonic": "BSET.B",
"operands": "#7, @H'F6F3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63219,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15754,
"address_region": "program_or_external",
"bytes": "15F6DF90",
"text": "MOV:G.B R0, @H'F6DF",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F6DF",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63199,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15758,
"address_region": "program_or_external",
"bytes": "15F00180",
"text": "MOV:G.B @H'F001, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F001, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61441,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15762,
"address_region": "program_or_external",
"bytes": "15F721D1",
"text": "BCLR.B #1, @H'F721",
"mnemonic": "BCLR.B",
"operands": "#1, @H'F721",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63265,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15766,
"address_region": "program_or_external",
"bytes": "CF80",
"text": "MOV:G.W @R7+, R0",
"mnemonic": "MOV:G.W",
"operands": "@R7+, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 5,
"base_cycles": 5,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15768,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 13,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15769,
"address_region": "program_or_external",
"bytes": "15FEE8D5",
"text": "BCLR.B #5, @ADCSR",
"mnemonic": "BCLR.B",
"operands": "#5, @ADCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65256,
"name": "ADCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear ADST (bit 5) of ADCSR",
"valid": true
},
{
"address": 15773,
"address_region": "program_or_external",
"bytes": "123F",
"text": "STM.W {R0,R1,R2,R3,R4,R5}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1,R2,R3,R4,R5}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 24,
"note": "6+3n, n=6",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15775,
"address_region": "program_or_external",
"bytes": "15F68A80",
"text": "MOV:G.B @H'F68A, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F68A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63114,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15779,
"address_region": "program_or_external",
"bytes": "0414A8",
"text": "MULXU.B #H'14, R0",
"mnemonic": "MULXU.B",
"operands": "#H'14, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 19,
"base_cycles": 19,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15782,
"address_region": "program_or_external",
"bytes": "1DFEE081",
"text": "MOV:G.W @ADDRA_H, R1",
"mnemonic": "MOV:G.W",
"operands": "@ADDRA_H, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65248,
"name": "ADDRA_H",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true,
"peripheral_access": [
{
"address": 15782,
"instruction": "MOV:G.W @ADDRA_H, R1",
"register": "ADDRA",
"high_address": 65248,
"low_address": 65249,
"referenced_address": 65248,
"referenced_address_hex": "H'FEE0",
"byte": "high",
"size": "W",
"direction": "read"
}
]
},
{
"address": 15786,
"address_region": "program_or_external",
"bytes": "A110",
"text": "SWAP.B R1",
"mnemonic": "SWAP.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15788,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15790,
"address_region": "program_or_external",
"bytes": "F1CFB681",
"text": "MOV:G.B @(-H'304A,R1), R1",
"mnemonic": "MOV:G.B",
"operands": "@(-H'304A,R1), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15794,
"address_region": "program_or_external",
"bytes": "A920",
"text": "ADD:G.W R1, R0",
"mnemonic": "ADD:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15796,
"address_region": "program_or_external",
"bytes": "0415B8",
"text": "DIVXU.B #H'15, R0",
"mnemonic": "DIVXU.B",
"operands": "#H'15, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 23,
"base_cycles": 23,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15799,
"address_region": "program_or_external",
"bytes": "15F68A70",
"text": "CMP:G.B @H'F68A, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F68A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63114,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15803,
"address_region": "program_or_external",
"bytes": "274B",
"text": "BEQ loc_3E08",
"mnemonic": "BEQ",
"operands": "loc_3E08",
"kind": "branch",
"targets": [
15880
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15805,
"address_region": "program_or_external",
"bytes": "15F68A82",
"text": "MOV:G.B @H'F68A, R2",
"mnemonic": "MOV:G.B",
"operands": "@H'F68A, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63114,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15809,
"address_region": "program_or_external",
"bytes": "15F68A90",
"text": "MOV:G.B R0, @H'F68A",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F68A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63114,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15813,
"address_region": "program_or_external",
"bytes": "15F7310403",
"text": "CMP:G.B #H'03, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'03, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15818,
"address_region": "program_or_external",
"bytes": "223C",
"text": "BHI loc_3E08",
"mnemonic": "BHI",
"operands": "loc_3E08",
"kind": "branch",
"targets": [
15880
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15820,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15822,
"address_region": "program_or_external",
"bytes": "A212",
"text": "EXTU.B R2",
"mnemonic": "EXTU.B",
"operands": "R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15824,
"address_region": "program_or_external",
"bytes": "0C0101A8",
"text": "MULXU.W #H'0101, R0",
"mnemonic": "MULXU.W",
"operands": "#H'0101, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 25,
"base_cycles": 25,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15828,
"address_region": "program_or_external",
"bytes": "0C0101AA",
"text": "MULXU.W #H'0101, R2",
"mnemonic": "MULXU.W",
"operands": "#H'0101, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 25,
"base_cycles": 25,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15832,
"address_region": "program_or_external",
"bytes": "AB31",
"text": "SUB.W R3, R1",
"mnemonic": "SUB.W",
"operands": "R3, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15834,
"address_region": "program_or_external",
"bytes": "1DE10280",
"text": "MOV:G.W @H'E102, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'E102, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57602,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15838,
"address_region": "program_or_external",
"bytes": "A821",
"text": "ADD:G.W R0, R1",
"mnemonic": "ADD:G.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15840,
"address_region": "program_or_external",
"bytes": "A982",
"text": "MOV:G.W R1, R2",
"mnemonic": "MOV:G.W",
"operands": "R1, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15842,
"address_region": "program_or_external",
"bytes": "250C",
"text": "BCS loc_3DF0",
"mnemonic": "BCS",
"operands": "loc_3DF0",
"kind": "branch",
"targets": [
15856
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15844,
"address_region": "program_or_external",
"bytes": "A832",
"text": "SUB.W R0, R2",
"mnemonic": "SUB.W",
"operands": "R0, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15846,
"address_region": "program_or_external",
"bytes": "4A8000",
"text": "CMP:I #H'8000, R2",
"mnemonic": "CMP:I",
"operands": "#H'8000, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15849,
"address_region": "program_or_external",
"bytes": "230F",
"text": "BLS loc_3DFA",
"mnemonic": "BLS",
"operands": "loc_3DFA",
"kind": "branch",
"targets": [
15866
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15851,
"address_region": "program_or_external",
"bytes": "590000",
"text": "MOV:I.W #H'0000, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15854,
"address_region": "program_or_external",
"bytes": "200A",
"text": "BRA loc_3DFA",
"mnemonic": "BRA",
"operands": "loc_3DFA",
"kind": "jump",
"targets": [
15866
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15856,
"address_region": "program_or_external",
"bytes": "AA30",
"text": "SUB.W R2, R0",
"mnemonic": "SUB.W",
"operands": "R2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15858,
"address_region": "program_or_external",
"bytes": "488000",
"text": "CMP:I #H'8000, R0",
"mnemonic": "CMP:I",
"operands": "#H'8000, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15861,
"address_region": "program_or_external",
"bytes": "2303",
"text": "BLS loc_3DFA",
"mnemonic": "BLS",
"operands": "loc_3DFA",
"kind": "branch",
"targets": [
15866
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15863,
"address_region": "program_or_external",
"bytes": "59FFFF",
"text": "MOV:I.W #H'FFFF, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'FFFF, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15866,
"address_region": "program_or_external",
"bytes": "1DE10271",
"text": "CMP:G.W @H'E102, R1",
"mnemonic": "CMP:G.W",
"operands": "@H'E102, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57602,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 15870,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_3E08",
"mnemonic": "BEQ",
"operands": "loc_3E08",
"kind": "branch",
"targets": [
15880
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15872,
"address_region": "program_or_external",
"bytes": "1DF68E91",
"text": "MOV:G.W R1, @H'F68E",
"mnemonic": "MOV:G.W",
"operands": "R1, @H'F68E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63118,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15876,
"address_region": "program_or_external",
"bytes": "15F689C7",
"text": "BSET.B #7, @H'F689",
"mnemonic": "BSET.B",
"operands": "#7, @H'F689",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63113,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15880,
"address_region": "program_or_external",
"bytes": "15F68B80",
"text": "MOV:G.B @H'F68B, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F68B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63115,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15884,
"address_region": "program_or_external",
"bytes": "0414A8",
"text": "MULXU.B #H'14, R0",
"mnemonic": "MULXU.B",
"operands": "#H'14, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 19,
"base_cycles": 19,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15887,
"address_region": "program_or_external",
"bytes": "1DFEE281",
"text": "MOV:G.W @ADDRB_H, R1",
"mnemonic": "MOV:G.W",
"operands": "@ADDRB_H, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65250,
"name": "ADDRB_H",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true,
"peripheral_access": [
{
"address": 15887,
"instruction": "MOV:G.W @ADDRB_H, R1",
"register": "ADDRB",
"high_address": 65250,
"low_address": 65251,
"referenced_address": 65250,
"referenced_address_hex": "H'FEE2",
"byte": "high",
"size": "W",
"direction": "read"
}
]
},
{
"address": 15891,
"address_region": "program_or_external",
"bytes": "A110",
"text": "SWAP.B R1",
"mnemonic": "SWAP.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15893,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15895,
"address_region": "program_or_external",
"bytes": "A920",
"text": "ADD:G.W R1, R0",
"mnemonic": "ADD:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15897,
"address_region": "program_or_external",
"bytes": "0415B8",
"text": "DIVXU.B #H'15, R0",
"mnemonic": "DIVXU.B",
"operands": "#H'15, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 23,
"base_cycles": 23,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15900,
"address_region": "program_or_external",
"bytes": "1DF68C16",
"text": "TST.W @H'F68C",
"mnemonic": "TST.W",
"operands": "@H'F68C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63116,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15904,
"address_region": "program_or_external",
"bytes": "2706",
"text": "BEQ loc_3E28",
"mnemonic": "BEQ",
"operands": "loc_3E28",
"kind": "branch",
"targets": [
15912
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15906,
"address_region": "program_or_external",
"bytes": "15F68B70",
"text": "CMP:G.B @H'F68B, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F68B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63115,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15910,
"address_region": "program_or_external",
"bytes": "2725",
"text": "BEQ loc_3E4D",
"mnemonic": "BEQ",
"operands": "loc_3E4D",
"kind": "branch",
"targets": [
15949
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15912,
"address_region": "program_or_external",
"bytes": "15F68B90",
"text": "MOV:G.B R0, @H'F68B",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F68B",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63115,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15916,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15918,
"address_region": "program_or_external",
"bytes": "A883",
"text": "MOV:G.W R0, R3",
"mnemonic": "MOV:G.W",
"operands": "R0, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15920,
"address_region": "program_or_external",
"bytes": "A3AB",
"text": "MULXU.B R3, R3",
"mnemonic": "MULXU.B",
"operands": "R3, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 18,
"base_cycles": 18,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15922,
"address_region": "program_or_external",
"bytes": "AA13",
"text": "CLR.W R2",
"mnemonic": "CLR.W",
"operands": "R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15924,
"address_region": "program_or_external",
"bytes": "0C00C8BA",
"text": "DIVXU.W #H'00C8, R2",
"mnemonic": "DIVXU.W",
"operands": "#H'00C8, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 29,
"base_cycles": 29,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15928,
"address_region": "program_or_external",
"bytes": "0404A8",
"text": "MULXU.B #H'04, R0",
"mnemonic": "MULXU.B",
"operands": "#H'04, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 19,
"base_cycles": 19,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15931,
"address_region": "program_or_external",
"bytes": "0C00AB20",
"text": "ADD:G.W #H'00AB, R0",
"mnemonic": "ADD:G.W",
"operands": "#H'00AB, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15935,
"address_region": "program_or_external",
"bytes": "AB20",
"text": "ADD:G.W R3, R0",
"mnemonic": "ADD:G.W",
"operands": "R3, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15937,
"address_region": "program_or_external",
"bytes": "15FE8EF4",
"text": "BTST.B #4, @P7DR",
"mnemonic": "BTST.B",
"operands": "#4, @P7DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 15941,
"address_region": "program_or_external",
"bytes": "2602",
"text": "BNE loc_3E49",
"mnemonic": "BNE",
"operands": "loc_3E49",
"kind": "branch",
"targets": [
15945
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15943,
"address_region": "program_or_external",
"bytes": "A81B",
"text": "SHLR.W R0",
"mnemonic": "SHLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15945,
"address_region": "program_or_external",
"bytes": "1DF68C90",
"text": "MOV:G.W R0, @H'F68C",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F68C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63116,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15949,
"address_region": "program_or_external",
"bytes": "023F",
"text": "LDM.W @SP+, {R0,R1,R2,R3,R4,R5}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1,R2,R3,R4,R5}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 30,
"note": "6+4n, n=6",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15951,
"address_region": "program_or_external",
"bytes": "15FEE8D7",
"text": "BCLR.B #7, @ADCSR",
"mnemonic": "BCLR.B",
"operands": "#7, @ADCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65256,
"name": "ADCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear ADF (bit 7) of ADCSR",
"valid": true
},
{
"address": 15955,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 13,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15956,
"address_region": "program_or_external",
"bytes": "A2F7",
"text": "BTST.B #7, R2",
"mnemonic": "BTST.B",
"operands": "#7, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15958,
"address_region": "program_or_external",
"bytes": "2742",
"text": "BEQ loc_3E9A",
"mnemonic": "BEQ",
"operands": "loc_3E9A",
"kind": "branch",
"targets": [
16026
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15960,
"address_region": "program_or_external",
"bytes": "15F9B580",
"text": "MOV:G.B @H'F9B5, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B5, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15964,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15966,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15968,
"address_region": "program_or_external",
"bytes": "15F9B081",
"text": "MOV:G.B @H'F9B0, R1",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15972,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15974,
"address_region": "program_or_external",
"bytes": "A91A",
"text": "SHLL.W R1",
"mnemonic": "SHLL.W",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15976,
"address_region": "program_or_external",
"bytes": "A071",
"text": "CMP:G.B R0, R1",
"mnemonic": "CMP:G.B",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15978,
"address_region": "program_or_external",
"bytes": "270A",
"text": "BEQ loc_3E76",
"mnemonic": "BEQ",
"operands": "loc_3E76",
"kind": "branch",
"targets": [
15990
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15980,
"address_region": "program_or_external",
"bytes": "F8F87073",
"text": "CMP:G.W @(-H'0790,R0), R3",
"mnemonic": "CMP:G.W",
"operands": "@(-H'0790,R0), R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15984,
"address_region": "program_or_external",
"bytes": "2728",
"text": "BEQ loc_3E9A",
"mnemonic": "BEQ",
"operands": "loc_3E9A",
"kind": "branch",
"targets": [
16026
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15986,
"address_region": "program_or_external",
"bytes": "A009",
"text": "ADD:Q.B #2, R0",
"mnemonic": "ADD:Q.B",
"operands": "#2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15988,
"address_region": "program_or_external",
"bytes": "20F2",
"text": "BRA loc_3E68",
"mnemonic": "BRA",
"operands": "loc_3E68",
"kind": "jump",
"targets": [
15976
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15990,
"address_region": "program_or_external",
"bytes": "F9F87093",
"text": "MOV:G.W R3, @(-H'0790,R1)",
"mnemonic": "MOV:G.W",
"operands": "R3, @(-H'0790,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 15994,
"address_region": "program_or_external",
"bytes": "15F9B008",
"text": "ADD:Q.B #1, @H'F9B0",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 15998,
"address_region": "program_or_external",
"bytes": "15F9B0D7",
"text": "BCLR.B #7, @H'F9B0",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F9B0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16002,
"address_region": "program_or_external",
"bytes": "15F9B080",
"text": "MOV:G.B @H'F9B0, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16006,
"address_region": "program_or_external",
"bytes": "A008",
"text": "ADD:Q.B #1, R0",
"mnemonic": "ADD:Q.B",
"operands": "#1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16008,
"address_region": "program_or_external",
"bytes": "047F50",
"text": "AND.B #H'7F, R0",
"mnemonic": "AND.B",
"operands": "#H'7F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16011,
"address_region": "program_or_external",
"bytes": "15F9B570",
"text": "CMP:G.B @H'F9B5, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F9B5, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16015,
"address_region": "program_or_external",
"bytes": "2609",
"text": "BNE loc_3E9A",
"mnemonic": "BNE",
"operands": "loc_3E9A",
"kind": "branch",
"targets": [
16026
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16017,
"address_region": "program_or_external",
"bytes": "120C",
"text": "STM.W {R2,R3}, @-SP",
"mnemonic": "STM.W",
"operands": "{R2,R3}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16019,
"address_region": "program_or_external",
"bytes": "1E013D",
"text": "BSR loc_3FD3",
"mnemonic": "BSR",
"operands": "loc_3FD3",
"kind": "call",
"targets": [
16339
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16022,
"address_region": "program_or_external",
"bytes": "020C",
"text": "LDM.W @SP+, {R2,R3}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R2,R3}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16024,
"address_region": "program_or_external",
"bytes": "20E8",
"text": "BRA loc_3E82",
"mnemonic": "BRA",
"operands": "loc_3E82",
"kind": "jump",
"targets": [
16002
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16026,
"address_region": "program_or_external",
"bytes": "A2F6",
"text": "BTST.B #6, R2",
"mnemonic": "BTST.B",
"operands": "#6, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16028,
"address_region": "program_or_external",
"bytes": "272D",
"text": "BEQ loc_3ECB",
"mnemonic": "BEQ",
"operands": "loc_3ECB",
"kind": "branch",
"targets": [
16075
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16030,
"address_region": "program_or_external",
"bytes": "15F9B980",
"text": "MOV:G.B @H'F9B9, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B9, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63929,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16034,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16036,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16038,
"address_region": "program_or_external",
"bytes": "15F9B481",
"text": "MOV:G.B @H'F9B4, R1",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B4, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16042,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16044,
"address_region": "program_or_external",
"bytes": "A91A",
"text": "SHLL.W R1",
"mnemonic": "SHLL.W",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16046,
"address_region": "program_or_external",
"bytes": "A071",
"text": "CMP:G.B R0, R1",
"mnemonic": "CMP:G.B",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16048,
"address_region": "program_or_external",
"bytes": "270D",
"text": "BEQ loc_3EBF",
"mnemonic": "BEQ",
"operands": "loc_3EBF",
"kind": "branch",
"targets": [
16063
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16050,
"address_region": "program_or_external",
"bytes": "F8F97073",
"text": "CMP:G.W @(-H'0690,R0), R3",
"mnemonic": "CMP:G.W",
"operands": "@(-H'0690,R0), R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16054,
"address_region": "program_or_external",
"bytes": "2713",
"text": "BEQ loc_3ECB",
"mnemonic": "BEQ",
"operands": "loc_3ECB",
"kind": "branch",
"targets": [
16075
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16056,
"address_region": "program_or_external",
"bytes": "A009",
"text": "ADD:Q.B #2, R0",
"mnemonic": "ADD:Q.B",
"operands": "#2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16058,
"address_region": "program_or_external",
"bytes": "043F50",
"text": "AND.B #H'3F, R0",
"mnemonic": "AND.B",
"operands": "#H'3F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16061,
"address_region": "program_or_external",
"bytes": "20EF",
"text": "BRA loc_3EAE",
"mnemonic": "BRA",
"operands": "loc_3EAE",
"kind": "jump",
"targets": [
16046
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16063,
"address_region": "program_or_external",
"bytes": "F9F97093",
"text": "MOV:G.W R3, @(-H'0690,R1)",
"mnemonic": "MOV:G.W",
"operands": "R3, @(-H'0690,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16067,
"address_region": "program_or_external",
"bytes": "15F9B408",
"text": "ADD:Q.B #1, @H'F9B4",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16071,
"address_region": "program_or_external",
"bytes": "15F9B4D5",
"text": "BCLR.B #5, @H'F9B4",
"mnemonic": "BCLR.B",
"operands": "#5, @H'F9B4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16075,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16076,
"address_region": "program_or_external",
"bytes": "121F",
"text": "STM.W {R0,R1,R2,R3,R4}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1,R2,R3,R4}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 21,
"note": "6+3n, n=5",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16078,
"address_region": "program_or_external",
"bytes": "A512",
"text": "EXTU.B R5",
"mnemonic": "EXTU.B",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16080,
"address_region": "program_or_external",
"bytes": "4503",
"text": "CMP:E #H'03, R5",
"mnemonic": "CMP:E",
"operands": "#H'03, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16082,
"address_region": "program_or_external",
"bytes": "2305",
"text": "BLS loc_3ED9",
"mnemonic": "BLS",
"operands": "loc_3ED9",
"kind": "branch",
"targets": [
16089
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16084,
"address_region": "program_or_external",
"bytes": "1E0069",
"text": "BSR loc_3F40",
"mnemonic": "BSR",
"operands": "loc_3F40",
"kind": "call",
"targets": [
16192
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16087,
"address_region": "program_or_external",
"bytes": "204C",
"text": "BRA loc_3F25",
"mnemonic": "BRA",
"operands": "loc_3F25",
"kind": "jump",
"targets": [
16165
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16089,
"address_region": "program_or_external",
"bytes": "A583",
"text": "MOV:G.B R5, R3",
"mnemonic": "MOV:G.B",
"operands": "R5, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16091,
"address_region": "program_or_external",
"bytes": "4500",
"text": "CMP:E #H'00, R5",
"mnemonic": "CMP:E",
"operands": "#H'00, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16093,
"address_region": "program_or_external",
"bytes": "270A",
"text": "BEQ loc_3EE9",
"mnemonic": "BEQ",
"operands": "loc_3EE9",
"kind": "branch",
"targets": [
16105
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16095,
"address_region": "program_or_external",
"bytes": "4501",
"text": "CMP:E #H'01, R5",
"mnemonic": "CMP:E",
"operands": "#H'01, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16097,
"address_region": "program_or_external",
"bytes": "270B",
"text": "BEQ loc_3EEE",
"mnemonic": "BEQ",
"operands": "loc_3EEE",
"kind": "branch",
"targets": [
16110
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16099,
"address_region": "program_or_external",
"bytes": "4502",
"text": "CMP:E #H'02, R5",
"mnemonic": "CMP:E",
"operands": "#H'02, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16101,
"address_region": "program_or_external",
"bytes": "270C",
"text": "BEQ loc_3EF3",
"mnemonic": "BEQ",
"operands": "loc_3EF3",
"kind": "branch",
"targets": [
16115
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16103,
"address_region": "program_or_external",
"bytes": "200F",
"text": "BRA loc_3EF8",
"mnemonic": "BRA",
"operands": "loc_3EF8",
"kind": "jump",
"targets": [
16120
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16105,
"address_region": "program_or_external",
"bytes": "5D0080",
"text": "MOV:I.W #H'0080, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0080, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16108,
"address_region": "program_or_external",
"bytes": "200D",
"text": "BRA loc_3EFB",
"mnemonic": "BRA",
"operands": "loc_3EFB",
"kind": "jump",
"targets": [
16123
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16110,
"address_region": "program_or_external",
"bytes": "5D00C0",
"text": "MOV:I.W #H'00C0, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'00C0, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16113,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_3EFB",
"mnemonic": "BRA",
"operands": "loc_3EFB",
"kind": "jump",
"targets": [
16123
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16115,
"address_region": "program_or_external",
"bytes": "5D0090",
"text": "MOV:I.W #H'0090, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0090, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16118,
"address_region": "program_or_external",
"bytes": "2003",
"text": "BRA loc_3EFB",
"mnemonic": "BRA",
"operands": "loc_3EFB",
"kind": "jump",
"targets": [
16123
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16120,
"address_region": "program_or_external",
"bytes": "5D00D0",
"text": "MOV:I.W #H'00D0, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'00D0, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16123,
"address_region": "program_or_external",
"bytes": "0410AB",
"text": "MULXU.B #H'10, R3",
"mnemonic": "MULXU.B",
"operands": "#H'10, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 19,
"base_cycles": 19,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16126,
"address_region": "program_or_external",
"bytes": "0CFAB023",
"text": "ADD:G.W #H'FAB0, R3",
"mnemonic": "ADD:G.W",
"operands": "#H'FAB0, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16130,
"address_region": "program_or_external",
"bytes": "A913",
"text": "CLR.W R1",
"mnemonic": "CLR.W",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16132,
"address_region": "program_or_external",
"bytes": "F1FAF082",
"text": "MOV:G.B @(-H'0510,R1), R2",
"mnemonic": "MOV:G.B",
"operands": "@(-H'0510,R1), R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16136,
"address_region": "program_or_external",
"bytes": "D372",
"text": "CMP:G.B @R3, R2",
"mnemonic": "CMP:G.B",
"operands": "@R3, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16138,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_3F10",
"mnemonic": "BEQ",
"operands": "loc_3F10",
"kind": "branch",
"targets": [
16144
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16140,
"address_region": "program_or_external",
"bytes": "D392",
"text": "MOV:G.B R2, @R3",
"mnemonic": "MOV:G.B",
"operands": "R2, @R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16142,
"address_region": "program_or_external",
"bytes": "0E18",
"text": "BSR loc_3F28",
"mnemonic": "BSR",
"operands": "loc_3F28",
"kind": "call",
"targets": [
16168
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16144,
"address_region": "program_or_external",
"bytes": "A108",
"text": "ADD:Q.B #1, R1",
"mnemonic": "ADD:Q.B",
"operands": "#1, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16146,
"address_region": "program_or_external",
"bytes": "A308",
"text": "ADD:Q.B #1, R3",
"mnemonic": "ADD:Q.B",
"operands": "#1, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16148,
"address_region": "program_or_external",
"bytes": "4110",
"text": "CMP:E #H'10, R1",
"mnemonic": "CMP:E",
"operands": "#H'10, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16150,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_3F1A",
"mnemonic": "BEQ",
"operands": "loc_3F1A",
"kind": "branch",
"targets": [
16154
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16152,
"address_region": "program_or_external",
"bytes": "20EA",
"text": "BRA loc_3F04",
"mnemonic": "BRA",
"operands": "loc_3F04",
"kind": "jump",
"targets": [
16132
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16154,
"address_region": "program_or_external",
"bytes": "1DFB000700E0",
"text": "MOV:G.W #H'00E0, @H'FB00",
"mnemonic": "MOV:G.W",
"operands": "#H'00E0, @H'FB00",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64256,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16160,
"address_region": "program_or_external",
"bytes": "5C00E0",
"text": "MOV:I.W #H'00E0, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'00E0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16163,
"address_region": "program_or_external",
"bytes": "0E1B",
"text": "BSR loc_3F40",
"mnemonic": "BSR",
"operands": "loc_3F40",
"kind": "call",
"targets": [
16192
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16165,
"address_region": "program_or_external",
"bytes": "021F",
"text": "LDM.W @SP+, {R0,R1,R2,R3,R4}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1,R2,R3,R4}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 26,
"note": "6+4n, n=5",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16167,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16168,
"address_region": "program_or_external",
"bytes": "AD84",
"text": "MOV:G.W R5, R4",
"mnemonic": "MOV:G.W",
"operands": "R5, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16170,
"address_region": "program_or_external",
"bytes": "A124",
"text": "ADD:G.B R1, R4",
"mnemonic": "ADD:G.B",
"operands": "R1, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16172,
"address_region": "program_or_external",
"bytes": "1DFB0074",
"text": "CMP:G.W @H'FB00, R4",
"mnemonic": "CMP:G.W",
"operands": "@H'FB00, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64256,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16176,
"address_region": "program_or_external",
"bytes": "2706",
"text": "BEQ loc_3F38",
"mnemonic": "BEQ",
"operands": "loc_3F38",
"kind": "branch",
"targets": [
16184
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16178,
"address_region": "program_or_external",
"bytes": "1DFB0094",
"text": "MOV:G.W R4, @H'FB00",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'FB00",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64256,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16182,
"address_region": "program_or_external",
"bytes": "0E08",
"text": "BSR loc_3F40",
"mnemonic": "BSR",
"operands": "loc_3F40",
"kind": "call",
"targets": [
16192
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16184,
"address_region": "program_or_external",
"bytes": "5C0200",
"text": "MOV:I.W #H'0200, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0200, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16187,
"address_region": "program_or_external",
"bytes": "A224",
"text": "ADD:G.B R2, R4",
"mnemonic": "ADD:G.B",
"operands": "R2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16189,
"address_region": "program_or_external",
"bytes": "0E01",
"text": "BSR loc_3F40",
"mnemonic": "BSR",
"operands": "loc_3F40",
"kind": "call",
"targets": [
16192
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16191,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16192,
"address_region": "program_or_external",
"bytes": "BF98",
"text": "STC.W SR, @-R7",
"mnemonic": "STC.W",
"operands": "SR, @-R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 7,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16194,
"address_region": "program_or_external",
"bytes": "0C00FF58",
"text": "ANDC.W #H'00FF, SR",
"mnemonic": "ANDC.W",
"operands": "#H'00FF, SR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16198,
"address_region": "program_or_external",
"bytes": "0C060048",
"text": "ORC.W #H'0600, SR",
"mnemonic": "ORC.W",
"operands": "#H'0600, SR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16202,
"address_region": "program_or_external",
"bytes": "15F2000080",
"text": "MOVFPE.B @H'F200, R0",
"mnemonic": "MOVFPE.B",
"operands": "@H'F200, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 13,
"note": "E-clock peripheral transfer",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61952,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16207,
"address_region": "program_or_external",
"bytes": "A0F7",
"text": "BTST.B #7, R0",
"mnemonic": "BTST.B",
"operands": "#7, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16209,
"address_region": "program_or_external",
"bytes": "26F7",
"text": "BNE loc_3F4A",
"mnemonic": "BNE",
"operands": "loc_3F4A",
"kind": "branch",
"targets": [
16202
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16211,
"address_region": "program_or_external",
"bytes": "ACF8",
"text": "BTST.W #8, R4",
"mnemonic": "BTST.W",
"operands": "#8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16213,
"address_region": "program_or_external",
"bytes": "2616",
"text": "BNE loc_3F6D",
"mnemonic": "BNE",
"operands": "loc_3F6D",
"kind": "branch",
"targets": [
16237
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16215,
"address_region": "program_or_external",
"bytes": "ACF9",
"text": "BTST.W #9, R4",
"mnemonic": "BTST.W",
"operands": "#9, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16217,
"address_region": "program_or_external",
"bytes": "2607",
"text": "BNE loc_3F62",
"mnemonic": "BNE",
"operands": "loc_3F62",
"kind": "branch",
"targets": [
16226
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16219,
"address_region": "program_or_external",
"bytes": "15F2000094",
"text": "MOVTPE.B R4, @H'F200",
"mnemonic": "MOVTPE.B",
"operands": "R4, @H'F200",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 13,
"note": "E-clock peripheral transfer",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61952,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16224,
"address_region": "program_or_external",
"bytes": "2010",
"text": "BRA loc_3F72",
"mnemonic": "BRA",
"operands": "loc_3F72",
"kind": "jump",
"targets": [
16242
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16226,
"address_region": "program_or_external",
"bytes": "15F2010094",
"text": "MOVTPE.B R4, @H'F201",
"mnemonic": "MOVTPE.B",
"operands": "R4, @H'F201",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 13,
"note": "E-clock peripheral transfer",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61953,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16231,
"address_region": "program_or_external",
"bytes": "1DFB0008",
"text": "ADD:Q.W #1, @H'FB00",
"mnemonic": "ADD:Q.W",
"operands": "#1, @H'FB00",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64256,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16235,
"address_region": "program_or_external",
"bytes": "2005",
"text": "BRA loc_3F72",
"mnemonic": "BRA",
"operands": "loc_3F72",
"kind": "jump",
"targets": [
16242
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16237,
"address_region": "program_or_external",
"bytes": "15F2010084",
"text": "MOVFPE.B @H'F201, R4",
"mnemonic": "MOVFPE.B",
"operands": "@H'F201, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 13,
"note": "E-clock peripheral transfer",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 61953,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16242,
"address_region": "program_or_external",
"bytes": "CF88",
"text": "LDC.W @R7+, SR",
"mnemonic": "LDC.W",
"operands": "@R7+, SR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16244,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16246,
"address_region": "program_or_external",
"bytes": "582710",
"text": "MOV:I.W #H'2710, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'2710, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16249,
"address_region": "program_or_external",
"bytes": "59C350",
"text": "MOV:I.W #H'C350, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'C350, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16252,
"address_region": "program_or_external",
"bytes": "15FE82D7",
"text": "BCLR.B #7, @P1DR",
"mnemonic": "BCLR.B",
"operands": "#7, @P1DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65154,
"name": "P1DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 7 of P1DR",
"valid": true
},
{
"address": 16256,
"address_region": "program_or_external",
"bytes": "01B8F9",
"text": "SCB/F R0, loc_3F7C",
"mnemonic": "SCB/F",
"operands": "R0, loc_3F7C",
"kind": "branch",
"targets": [
16252
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 8,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16259,
"address_region": "program_or_external",
"bytes": "15FE82C7",
"text": "BSET.B #7, @P1DR",
"mnemonic": "BSET.B",
"operands": "#7, @P1DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65154,
"name": "P1DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 7 of P1DR",
"valid": true
},
{
"address": 16263,
"address_region": "program_or_external",
"bytes": "01B9F9",
"text": "SCB/F R1, loc_3F83",
"mnemonic": "SCB/F",
"operands": "R1, loc_3F83",
"kind": "branch",
"targets": [
16259
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 9,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16266,
"address_region": "program_or_external",
"bytes": "A813",
"text": "CLR.W R0",
"mnemonic": "CLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16268,
"address_region": "program_or_external",
"bytes": "F8E00013",
"text": "CLR.W @(-H'2000,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'2000,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16272,
"address_region": "program_or_external",
"bytes": "F8E80013",
"text": "CLR.W @(-H'1800,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'1800,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16276,
"address_region": "program_or_external",
"bytes": "F8F68013",
"text": "CLR.W @(-H'0980,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'0980,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16280,
"address_region": "program_or_external",
"bytes": "A809",
"text": "ADD:Q.W #2, R0",
"mnemonic": "ADD:Q.W",
"operands": "#2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16282,
"address_region": "program_or_external",
"bytes": "480800",
"text": "CMP:I #H'0800, R0",
"mnemonic": "CMP:I",
"operands": "#H'0800, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16285,
"address_region": "program_or_external",
"bytes": "26ED",
"text": "BNE loc_3F8C",
"mnemonic": "BNE",
"operands": "loc_3F8C",
"kind": "branch",
"targets": [
16268
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16287,
"address_region": "program_or_external",
"bytes": "1E036A",
"text": "BSR loc_430C",
"mnemonic": "BSR",
"operands": "loc_430C",
"kind": "call",
"targets": [
17164
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16290,
"address_region": "program_or_external",
"bytes": "1E037F",
"text": "BSR loc_4324",
"mnemonic": "BSR",
"operands": "loc_4324",
"kind": "call",
"targets": [
17188
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16293,
"address_region": "program_or_external",
"bytes": "1E00EE",
"text": "BSR loc_4096",
"mnemonic": "BSR",
"operands": "loc_4096",
"kind": "call",
"targets": [
16534
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16296,
"address_region": "program_or_external",
"bytes": "1E0110",
"text": "BSR loc_40BB",
"mnemonic": "BSR",
"operands": "loc_40BB",
"kind": "call",
"targets": [
16571
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16299,
"address_region": "program_or_external",
"bytes": "1E0269",
"text": "BSR loc_4217",
"mnemonic": "BSR",
"operands": "loc_4217",
"kind": "call",
"targets": [
16919
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16302,
"address_region": "program_or_external",
"bytes": "1E039B",
"text": "BSR loc_434C",
"mnemonic": "BSR",
"operands": "loc_434C",
"kind": "call",
"targets": [
17228
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16305,
"address_region": "program_or_external",
"bytes": "1DFEEC075A00",
"text": "MOV:G.W #H'5A00, @WDT_TCSR_R",
"mnemonic": "MOV:G.W",
"operands": "#H'5A00, @WDT_TCSR_R",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65260,
"name": "WDT_TCSR_R",
"region": "register_field",
"kind": "registers"
}
],
"comment": "WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00)",
"valid": true
},
{
"address": 16311,
"address_region": "program_or_external",
"bytes": "15F79413",
"text": "CLR.B @H'F794",
"mnemonic": "CLR.B",
"operands": "@H'F794",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63380,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16315,
"address_region": "program_or_external",
"bytes": "0E16",
"text": "BSR loc_3FD3",
"mnemonic": "BSR",
"operands": "loc_3FD3",
"kind": "call",
"targets": [
16339
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16317,
"address_region": "program_or_external",
"bytes": "1E7BEB",
"text": "BSR loc_BBAB",
"mnemonic": "BSR",
"operands": "loc_BBAB",
"kind": "call",
"targets": [
48043
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16320,
"address_region": "program_or_external",
"bytes": "0E2D",
"text": "BSR loc_3FEF",
"mnemonic": "BSR",
"operands": "loc_3FEF",
"kind": "call",
"targets": [
16367
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16322,
"address_region": "program_or_external",
"bytes": "1E0081",
"text": "BSR loc_4046",
"mnemonic": "BSR",
"operands": "loc_4046",
"kind": "call",
"targets": [
16454
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16325,
"address_region": "program_or_external",
"bytes": "1E7ED6",
"text": "BSR loc_BE9E",
"mnemonic": "BSR",
"operands": "loc_BE9E",
"kind": "call",
"targets": [
48798
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16328,
"address_region": "program_or_external",
"bytes": "1EE83B",
"text": "BSR loc_2806",
"mnemonic": "BSR",
"operands": "loc_2806",
"kind": "call",
"targets": [
10246
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16331,
"address_region": "program_or_external",
"bytes": "1EF962",
"text": "BSR loc_3930",
"mnemonic": "BSR",
"operands": "loc_3930",
"kind": "call",
"targets": [
14640
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16334,
"address_region": "program_or_external",
"bytes": "1ED60F",
"text": "BSR loc_15E0",
"mnemonic": "BSR",
"operands": "loc_15E0",
"kind": "call",
"targets": [
5600
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16337,
"address_region": "program_or_external",
"bytes": "20DE",
"text": "BRA loc_3FB1",
"mnemonic": "BRA",
"operands": "loc_3FB1",
"kind": "jump",
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"address": 16454,
"address_region": "program_or_external",
"bytes": "15F9C416",
"text": "TST.B @H'F9C4",
"mnemonic": "TST.B",
"operands": "@H'F9C4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63940,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16458,
"address_region": "program_or_external",
"bytes": "260C",
"text": "BNE loc_4058",
"mnemonic": "BNE",
"operands": "loc_4058",
"kind": "branch",
"targets": [
16472
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16460,
"address_region": "program_or_external",
"bytes": "15FAA5F7",
"text": "BTST.B #7, @H'FAA5",
"mnemonic": "BTST.B",
"operands": "#7, @H'FAA5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64165,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16464,
"address_region": "program_or_external",
"bytes": "2707",
"text": "BEQ loc_4059",
"mnemonic": "BEQ",
"operands": "loc_4059",
"kind": "branch",
"targets": [
16473
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16466,
"address_region": "program_or_external",
"bytes": "15F9C316",
"text": "TST.B @H'F9C3",
"mnemonic": "TST.B",
"operands": "@H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16470,
"address_region": "program_or_external",
"bytes": "2701",
"text": "BEQ loc_4059",
"mnemonic": "BEQ",
"operands": "loc_4059",
"kind": "branch",
"targets": [
16473
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16472,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16473,
"address_region": "program_or_external",
"bytes": "15F9B082",
"text": "MOV:G.B @H'F9B0, R2",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B0, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16477,
"address_region": "program_or_external",
"bytes": "A212",
"text": "EXTU.B R2",
"mnemonic": "EXTU.B",
"operands": "R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16479,
"address_region": "program_or_external",
"bytes": "15F9B572",
"text": "CMP:G.B @H'F9B5, R2",
"mnemonic": "CMP:G.B",
"operands": "@H'F9B5, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16483,
"address_region": "program_or_external",
"bytes": "260F",
"text": "BNE loc_4074",
"mnemonic": "BNE",
"operands": "loc_4074",
"kind": "branch",
"targets": [
16500
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16485,
"address_region": "program_or_external",
"bytes": "A21A",
"text": "SHLL.B R2",
"mnemonic": "SHLL.B",
"operands": "R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16487,
"address_region": "program_or_external",
"bytes": "FAF8700600",
"text": "MOV:G.W #H'00, @(-H'0790,R2)",
"mnemonic": "MOV:G.W",
"operands": "#H'00, @(-H'0790,R2)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16492,
"address_region": "program_or_external",
"bytes": "15F9B008",
"text": "ADD:Q.B #1, @H'F9B0",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16496,
"address_region": "program_or_external",
"bytes": "15F9B0D7",
"text": "BCLR.B #7, @H'F9B0",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F9B0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16500,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16501,
"address_region": "program_or_external",
"bytes": "A813",
"text": "CLR.W R0",
"mnemonic": "CLR.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16503,
"address_region": "program_or_external",
"bytes": "F8E00013",
"text": "CLR.W @(-H'2000,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'2000,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16507,
"address_region": "program_or_external",
"bytes": "F8E40013",
"text": "CLR.W @(-H'1C00,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'1C00,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16511,
"address_region": "program_or_external",
"bytes": "F8E80013",
"text": "CLR.W @(-H'1800,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'1800,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16515,
"address_region": "program_or_external",
"bytes": "480200",
"text": "CMP:I #H'0200, R0",
"mnemonic": "CMP:I",
"operands": "#H'0200, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16518,
"address_region": "program_or_external",
"bytes": "2404",
"text": "BCC loc_408C",
"mnemonic": "BCC",
"operands": "loc_408C",
"kind": "branch",
"targets": [
16524
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16520,
"address_region": "program_or_external",
"bytes": "F8EC0013",
"text": "CLR.W @(-H'1400,R0)",
"mnemonic": "CLR.W",
"operands": "@(-H'1400,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16524,
"address_region": "program_or_external",
"bytes": "A809",
"text": "ADD:Q.W #2, R0",
"mnemonic": "ADD:Q.W",
"operands": "#2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16526,
"address_region": "program_or_external",
"bytes": "480400",
"text": "CMP:I #H'0400, R0",
"mnemonic": "CMP:I",
"operands": "#H'0400, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16529,
"address_region": "program_or_external",
"bytes": "26E4",
"text": "BNE loc_4077",
"mnemonic": "BNE",
"operands": "loc_4077",
"kind": "branch",
"targets": [
16503
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16531,
"address_region": "program_or_external",
"bytes": "0E01",
"text": "BSR loc_4096",
"mnemonic": "BSR",
"operands": "loc_4096",
"kind": "call",
"targets": [
16534
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16533,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16534,
"address_region": "program_or_external",
"bytes": "1DE000070080",
"text": "MOV:G.W #H'0080, @H'E000",
"mnemonic": "MOV:G.W",
"operands": "#H'0080, @H'E000",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57344,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16540,
"address_region": "program_or_external",
"bytes": "1DE006078000",
"text": "MOV:G.W #H'8000, @H'E006",
"mnemonic": "MOV:G.W",
"operands": "#H'8000, @H'E006",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57350,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16546,
"address_region": "program_or_external",
"bytes": "1DE08007FFFF",
"text": "MOV:G.W #H'FFFF, @H'E080",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @H'E080",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57472,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16552,
"address_region": "program_or_external",
"bytes": "1DE800070080",
"text": "MOV:G.W #H'0080, @H'E800",
"mnemonic": "MOV:G.W",
"operands": "#H'0080, @H'E800",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 59392,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16558,
"address_region": "program_or_external",
"bytes": "1DE806078000",
"text": "MOV:G.W #H'8000, @H'E806",
"mnemonic": "MOV:G.W",
"operands": "#H'8000, @H'E806",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 59398,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16564,
"address_region": "program_or_external",
"bytes": "1DE88007FFFF",
"text": "MOV:G.W #H'FFFF, @H'E880",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @H'E880",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 59520,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16570,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16571,
"address_region": "program_or_external",
"bytes": "580040",
"text": "MOV:I.W #H'0040, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'0040, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16574,
"address_region": "program_or_external",
"bytes": "F8F86E07FFFF",
"text": "MOV:G.W #H'FFFF, @(-H'0792,R0)",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @(-H'0792,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16580,
"address_region": "program_or_external",
"bytes": "F8F8AE07FFFF",
"text": "MOV:G.W #H'FFFF, @(-H'0752,R0)",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @(-H'0752,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16586,
"address_region": "program_or_external",
"bytes": "F8F8EE07FFFF",
"text": "MOV:G.W #H'FFFF, @(-H'0712,R0)",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @(-H'0712,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16592,
"address_region": "program_or_external",
"bytes": "F8F92E07FFFF",
"text": "MOV:G.W #H'FFFF, @(-H'06D2,R0)",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @(-H'06D2,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16598,
"address_region": "program_or_external",
"bytes": "F8F96E07FFFF",
"text": "MOV:G.W #H'FFFF, @(-H'0692,R0)",
"mnemonic": "MOV:G.W",
"operands": "#H'FFFF, @(-H'0692,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16604,
"address_region": "program_or_external",
"bytes": "A80D",
"text": "ADD:Q.W #-2, R0",
"mnemonic": "ADD:Q.W",
"operands": "#-2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16606,
"address_region": "program_or_external",
"bytes": "26DE",
"text": "BNE loc_40BE",
"mnemonic": "BNE",
"operands": "loc_40BE",
"kind": "branch",
"targets": [
16574
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16608,
"address_region": "program_or_external",
"bytes": "15F9C40614",
"text": "MOV:G.B #H'14, @H'F9C4",
"mnemonic": "MOV:G.B",
"operands": "#H'14, @H'F9C4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63940,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16613,
"address_region": "program_or_external",
"bytes": "15F6F70680",
"text": "MOV:G.B #H'80, @H'F6F7",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63223,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16618,
"address_region": "program_or_external",
"bytes": "15F6F80680",
"text": "MOV:G.B #H'80, @H'F6F8",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63224,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16623,
"address_region": "program_or_external",
"bytes": "15F6F90680",
"text": "MOV:G.B #H'80, @H'F6F9",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63225,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16628,
"address_region": "program_or_external",
"bytes": "15FE8EF7",
"text": "BTST.B #7, @P7DR",
"mnemonic": "BTST.B",
"operands": "#7, @P7DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 16632,
"address_region": "program_or_external",
"bytes": "2709",
"text": "BEQ loc_4103",
"mnemonic": "BEQ",
"operands": "loc_4103",
"kind": "branch",
"targets": [
16643
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16634,
"address_region": "program_or_external",
"bytes": "1DF402056B6F",
"text": "CMP:G.W #H'6B6F, @H'F402",
"mnemonic": "CMP:G.W",
"operands": "#H'6B6F, @H'F402",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62466,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 16640,
"address_region": "program_or_external",
"bytes": "3700AD",
"text": "BEQ loc_41B0",
"mnemonic": "BEQ",
"operands": "loc_41B0",
"kind": "branch",
"targets": [
16816
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16643,
"address_region": "program_or_external",
"bytes": "580100",
"text": "MOV:I.W #H'0100, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'0100, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16646,
"address_region": "program_or_external",
"bytes": "A80D",
"text": "ADD:Q.W #-2, R0",
"mnemonic": "ADD:Q.W",
"operands": "#-2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16648,
"address_region": "program_or_external",
"bytes": "F8C96485",
"text": "MOV:G.W @(-H'369C,R0), R5",
"mnemonic": "MOV:G.W",
"operands": "@(-H'369C,R0), R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16652,
"address_region": "program_or_external",
"bytes": "F8F40095",
"text": "MOV:G.W R5, @(-H'0C00,R0)",
"mnemonic": "MOV:G.W",
"operands": "R5, @(-H'0C00,R0)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16656,
"address_region": "program_or_external",
"bytes": "BF90",
"text": "MOV:G.W R0, @-R7",
"mnemonic": "MOV:G.W",
"operands": "R0, @-R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16658,
"address_region": "program_or_external",
"bytes": "A884",
"text": "MOV:G.W R0, R4",
"mnemonic": "MOV:G.W",
"operands": "R0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16660,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16663,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16667,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16670,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16674,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16677,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16681,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16684,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16688,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16691,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16695,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16698,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16702,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16705,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16709,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16712,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16716,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16719,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16723,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16726,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16730,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16733,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16737,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16740,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16744,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16747,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16751,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16754,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16758,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16761,
"address_region": "program_or_external",
"bytes": "0C010024",
"text": "ADD:G.W #H'0100, R4",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16765,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16768,
"address_region": "program_or_external",
"bytes": "CF80",
"text": "MOV:G.W @R7+, R0",
"mnemonic": "MOV:G.W",
"operands": "@R7+, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 5,
"base_cycles": 5,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16770,
"address_region": "program_or_external",
"bytes": "2682",
"text": "BNE loc_4106",
"mnemonic": "BNE",
"operands": "loc_4106",
"kind": "branch",
"targets": [
16646
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16772,
"address_region": "program_or_external",
"bytes": "58000F",
"text": "MOV:I.W #H'000F, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'000F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16775,
"address_region": "program_or_external",
"bytes": "BF90",
"text": "MOV:G.W R0, @-R7",
"mnemonic": "MOV:G.W",
"operands": "R0, @-R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 5,
"base_cycles": 5,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16777,
"address_region": "program_or_external",
"bytes": "A884",
"text": "MOV:G.W R0, R4",
"mnemonic": "MOV:G.W",
"operands": "R0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16779,
"address_region": "program_or_external",
"bytes": "A410",
"text": "SWAP.B R4",
"mnemonic": "SWAP.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16781,
"address_region": "program_or_external",
"bytes": "5D2020",
"text": "MOV:I.W #H'2020, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'2020, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16784,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16787,
"address_region": "program_or_external",
"bytes": "AC09",
"text": "ADD:Q.W #2, R4",
"mnemonic": "ADD:Q.W",
"operands": "#2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16789,
"address_region": "program_or_external",
"bytes": "5D2020",
"text": "MOV:I.W #H'2020, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'2020, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16792,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16795,
"address_region": "program_or_external",
"bytes": "AC09",
"text": "ADD:Q.W #2, R4",
"mnemonic": "ADD:Q.W",
"operands": "#2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16797,
"address_region": "program_or_external",
"bytes": "5D2020",
"text": "MOV:I.W #H'2020, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'2020, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16800,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16803,
"address_region": "program_or_external",
"bytes": "AC09",
"text": "ADD:Q.W #2, R4",
"mnemonic": "ADD:Q.W",
"operands": "#2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16805,
"address_region": "program_or_external",
"bytes": "5D2020",
"text": "MOV:I.W #H'2020, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'2020, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16808,
"address_region": "program_or_external",
"bytes": "18BFE0",
"text": "JSR @loc_BFE0",
"mnemonic": "JSR",
"operands": "@loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16811,
"address_region": "program_or_external",
"bytes": "CF80",
"text": "MOV:G.W @R7+, R0",
"mnemonic": "MOV:G.W",
"operands": "@R7+, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16813,
"address_region": "program_or_external",
"bytes": "01B8D7",
"text": "SCB/F R0, loc_4187",
"mnemonic": "SCB/F",
"operands": "R0, loc_4187",
"kind": "branch",
"targets": [
16775
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 9,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16816,
"address_region": "program_or_external",
"bytes": "2020",
"text": "BRA loc_41D2",
"mnemonic": "BRA",
"operands": "loc_41D2",
"kind": "jump",
"targets": [
16850
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16850,
"address_region": "program_or_external",
"bytes": "58000F",
"text": "MOV:I.W #H'000F, R0",
"mnemonic": "MOV:I.W",
"operands": "#H'000F, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16853,
"address_region": "program_or_external",
"bytes": "A881",
"text": "MOV:G.W R0, R1",
"mnemonic": "MOV:G.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16855,
"address_region": "program_or_external",
"bytes": "A11A",
"text": "SHLL.B R1",
"mnemonic": "SHLL.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16857,
"address_region": "program_or_external",
"bytes": "A11A",
"text": "SHLL.B R1",
"mnemonic": "SHLL.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16859,
"address_region": "program_or_external",
"bytes": "A11A",
"text": "SHLL.B R1",
"mnemonic": "SHLL.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16861,
"address_region": "program_or_external",
"bytes": "A884",
"text": "MOV:G.W R0, R4",
"mnemonic": "MOV:G.W",
"operands": "R0, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16863,
"address_region": "program_or_external",
"bytes": "A410",
"text": "SWAP.B R4",
"mnemonic": "SWAP.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16865,
"address_region": "program_or_external",
"bytes": "1203",
"text": "STM.W {R0,R1}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16867,
"address_region": "program_or_external",
"bytes": "18BFFE",
"text": "JSR @loc_BFFE",
"mnemonic": "JSR",
"operands": "@loc_BFFE",
"kind": "call",
"targets": [
49150
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16870,
"address_region": "program_or_external",
"bytes": "0203",
"text": "LDM.W @SP+, {R0,R1}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16872,
"address_region": "program_or_external",
"bytes": "F9F7B095",
"text": "MOV:G.W R5, @(-H'0850,R1)",
"mnemonic": "MOV:G.W",
"operands": "R5, @(-H'0850,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16876,
"address_region": "program_or_external",
"bytes": "AC09",
"text": "ADD:Q.W #2, R4",
"mnemonic": "ADD:Q.W",
"operands": "#2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16878,
"address_region": "program_or_external",
"bytes": "1203",
"text": "STM.W {R0,R1}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16880,
"address_region": "program_or_external",
"bytes": "18BFFE",
"text": "JSR @loc_BFFE",
"mnemonic": "JSR",
"operands": "@loc_BFFE",
"kind": "call",
"targets": [
49150
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16883,
"address_region": "program_or_external",
"bytes": "0203",
"text": "LDM.W @SP+, {R0,R1}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16885,
"address_region": "program_or_external",
"bytes": "F9F7B295",
"text": "MOV:G.W R5, @(-H'084E,R1)",
"mnemonic": "MOV:G.W",
"operands": "R5, @(-H'084E,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16889,
"address_region": "program_or_external",
"bytes": "AC09",
"text": "ADD:Q.W #2, R4",
"mnemonic": "ADD:Q.W",
"operands": "#2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16891,
"address_region": "program_or_external",
"bytes": "1203",
"text": "STM.W {R0,R1}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16893,
"address_region": "program_or_external",
"bytes": "18BFFE",
"text": "JSR @loc_BFFE",
"mnemonic": "JSR",
"operands": "@loc_BFFE",
"kind": "call",
"targets": [
49150
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16896,
"address_region": "program_or_external",
"bytes": "0203",
"text": "LDM.W @SP+, {R0,R1}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16898,
"address_region": "program_or_external",
"bytes": "F9F7B495",
"text": "MOV:G.W R5, @(-H'084C,R1)",
"mnemonic": "MOV:G.W",
"operands": "R5, @(-H'084C,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16902,
"address_region": "program_or_external",
"bytes": "AC09",
"text": "ADD:Q.W #2, R4",
"mnemonic": "ADD:Q.W",
"operands": "#2, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16904,
"address_region": "program_or_external",
"bytes": "1203",
"text": "STM.W {R0,R1}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16906,
"address_region": "program_or_external",
"bytes": "18BFFE",
"text": "JSR @loc_BFFE",
"mnemonic": "JSR",
"operands": "@loc_BFFE",
"kind": "call",
"targets": [
49150
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16909,
"address_region": "program_or_external",
"bytes": "0203",
"text": "LDM.W @SP+, {R0,R1}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16911,
"address_region": "program_or_external",
"bytes": "F9F7B695",
"text": "MOV:G.W R5, @(-H'084A,R1)",
"mnemonic": "MOV:G.W",
"operands": "R5, @(-H'084A,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16915,
"address_region": "program_or_external",
"bytes": "01B8BF",
"text": "SCB/F R0, loc_41D5",
"mnemonic": "SCB/F",
"operands": "R0, loc_41D5",
"kind": "branch",
"targets": [
16853
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 9,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16918,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 16919,
"address_region": "program_or_external",
"bytes": "15F79813",
"text": "CLR.B @H'F798",
"mnemonic": "CLR.B",
"operands": "@H'F798",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63384,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16923,
"address_region": "program_or_external",
"bytes": "15F731C7",
"text": "BSET.B #7, @H'F731",
"mnemonic": "BSET.B",
"operands": "#7, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16927,
"address_region": "program_or_external",
"bytes": "15FE82D2",
"text": "BCLR.B #2, @P1DR",
"mnemonic": "BCLR.B",
"operands": "#2, @P1DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65154,
"name": "P1DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 2 of P1DR",
"valid": true
},
{
"address": 16931,
"address_region": "program_or_external",
"bytes": "1DF700072424",
"text": "MOV:G.W #H'2424, @H'F700",
"mnemonic": "MOV:G.W",
"operands": "#H'2424, @H'F700",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63232,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16937,
"address_region": "program_or_external",
"bytes": "1DF702072424",
"text": "MOV:G.W #H'2424, @H'F702",
"mnemonic": "MOV:G.W",
"operands": "#H'2424, @H'F702",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63234,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16943,
"address_region": "program_or_external",
"bytes": "1DF704072424",
"text": "MOV:G.W #H'2424, @H'F704",
"mnemonic": "MOV:G.W",
"operands": "#H'2424, @H'F704",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63236,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16949,
"address_region": "program_or_external",
"bytes": "1DF706072424",
"text": "MOV:G.W #H'2424, @H'F706",
"mnemonic": "MOV:G.W",
"operands": "#H'2424, @H'F706",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63238,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16955,
"address_region": "program_or_external",
"bytes": "15F708067F",
"text": "MOV:G.B #H'7F, @H'F708",
"mnemonic": "MOV:G.B",
"operands": "#H'7F, @H'F708",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63240,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16960,
"address_region": "program_or_external",
"bytes": "15F7090624",
"text": "MOV:G.B #H'24, @H'F709",
"mnemonic": "MOV:G.B",
"operands": "#H'24, @H'F709",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63241,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16965,
"address_region": "program_or_external",
"bytes": "1DF70A072424",
"text": "MOV:G.W #H'2424, @H'F70A",
"mnemonic": "MOV:G.W",
"operands": "#H'2424, @H'F70A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63242,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16971,
"address_region": "program_or_external",
"bytes": "15F71013",
"text": "CLR.B @H'F710",
"mnemonic": "CLR.B",
"operands": "@H'F710",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63248,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16975,
"address_region": "program_or_external",
"bytes": "15F71113",
"text": "CLR.B @H'F711",
"mnemonic": "CLR.B",
"operands": "@H'F711",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63249,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16979,
"address_region": "program_or_external",
"bytes": "15F71213",
"text": "CLR.B @H'F712",
"mnemonic": "CLR.B",
"operands": "@H'F712",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63250,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16983,
"address_region": "program_or_external",
"bytes": "15F71313",
"text": "CLR.B @H'F713",
"mnemonic": "CLR.B",
"operands": "@H'F713",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63251,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16987,
"address_region": "program_or_external",
"bytes": "15F71413",
"text": "CLR.B @H'F714",
"mnemonic": "CLR.B",
"operands": "@H'F714",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63252,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16991,
"address_region": "program_or_external",
"bytes": "15F71513",
"text": "CLR.B @H'F715",
"mnemonic": "CLR.B",
"operands": "@H'F715",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63253,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16995,
"address_region": "program_or_external",
"bytes": "15F71613",
"text": "CLR.B @H'F716",
"mnemonic": "CLR.B",
"operands": "@H'F716",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63254,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 16999,
"address_region": "program_or_external",
"bytes": "15F71713",
"text": "CLR.B @H'F717",
"mnemonic": "CLR.B",
"operands": "@H'F717",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63255,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17003,
"address_region": "program_or_external",
"bytes": "15F71806FF",
"text": "MOV:G.B #H'FF, @H'F718",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F718",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63256,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17008,
"address_region": "program_or_external",
"bytes": "15F71906FF",
"text": "MOV:G.B #H'FF, @H'F719",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F719",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63257,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17013,
"address_region": "program_or_external",
"bytes": "15F71A06FF",
"text": "MOV:G.B #H'FF, @H'F71A",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F71A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17018,
"address_region": "program_or_external",
"bytes": "15F71B06FF",
"text": "MOV:G.B #H'FF, @H'F71B",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F71B",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17023,
"address_region": "program_or_external",
"bytes": "15F71C06FF",
"text": "MOV:G.B #H'FF, @H'F71C",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F71C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63260,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17028,
"address_region": "program_or_external",
"bytes": "15F71D06FF",
"text": "MOV:G.B #H'FF, @H'F71D",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F71D",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63261,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17033,
"address_region": "program_or_external",
"bytes": "15F71E06FF",
"text": "MOV:G.B #H'FF, @H'F71E",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F71E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63262,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17038,
"address_region": "program_or_external",
"bytes": "15F71F06FF",
"text": "MOV:G.B #H'FF, @H'F71F",
"mnemonic": "MOV:G.B",
"operands": "#H'FF, @H'F71F",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63263,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17043,
"address_region": "program_or_external",
"bytes": "1DFAF0072043",
"text": "MOV:G.W #H'2043, @H'FAF0",
"mnemonic": "MOV:G.W",
"operands": "#H'2043, @H'FAF0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64240,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17049,
"address_region": "program_or_external",
"bytes": "1DFAF2074F4E",
"text": "MOV:G.W #H'4F4E, @H'FAF2",
"mnemonic": "MOV:G.W",
"operands": "#H'4F4E, @H'FAF2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64242,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17055,
"address_region": "program_or_external",
"bytes": "1DFAF4074E45",
"text": "MOV:G.W #H'4E45, @H'FAF4",
"mnemonic": "MOV:G.W",
"operands": "#H'4E45, @H'FAF4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64244,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17061,
"address_region": "program_or_external",
"bytes": "1DFAF6074354",
"text": "MOV:G.W #H'4354, @H'FAF6",
"mnemonic": "MOV:G.W",
"operands": "#H'4354, @H'FAF6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64246,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17067,
"address_region": "program_or_external",
"bytes": "1DFAF8073A4E",
"text": "MOV:G.W #H'3A4E, @H'FAF8",
"mnemonic": "MOV:G.W",
"operands": "#H'3A4E, @H'FAF8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64248,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17073,
"address_region": "program_or_external",
"bytes": "1DFAFA074F54",
"text": "MOV:G.W #H'4F54, @H'FAFA",
"mnemonic": "MOV:G.W",
"operands": "#H'4F54, @H'FAFA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64250,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17079,
"address_region": "program_or_external",
"bytes": "1DFAFC072041",
"text": "MOV:G.W #H'2041, @H'FAFC",
"mnemonic": "MOV:G.W",
"operands": "#H'2041, @H'FAFC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64252,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17085,
"address_region": "program_or_external",
"bytes": "1DFAFE074354",
"text": "MOV:G.W #H'4354, @H'FAFE",
"mnemonic": "MOV:G.W",
"operands": "#H'4354, @H'FAFE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64254,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17091,
"address_region": "program_or_external",
"bytes": "5D0000",
"text": "MOV:I.W #H'0000, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17094,
"address_region": "program_or_external",
"bytes": "1EFC03",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17097,
"address_region": "program_or_external",
"bytes": "1DFAF0072020",
"text": "MOV:G.W #H'2020, @H'FAF0",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAF0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64240,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17103,
"address_region": "program_or_external",
"bytes": "1DFAF2072020",
"text": "MOV:G.W #H'2020, @H'FAF2",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAF2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64242,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17109,
"address_region": "program_or_external",
"bytes": "1DFAF4072020",
"text": "MOV:G.W #H'2020, @H'FAF4",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAF4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64244,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17115,
"address_region": "program_or_external",
"bytes": "1DFAF6072020",
"text": "MOV:G.W #H'2020, @H'FAF6",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAF6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64246,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17121,
"address_region": "program_or_external",
"bytes": "1DFAF8072020",
"text": "MOV:G.W #H'2020, @H'FAF8",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAF8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64248,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17127,
"address_region": "program_or_external",
"bytes": "1DFAFA072020",
"text": "MOV:G.W #H'2020, @H'FAFA",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAFA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64250,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17133,
"address_region": "program_or_external",
"bytes": "1DFAFC072020",
"text": "MOV:G.W #H'2020, @H'FAFC",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAFC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64252,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17139,
"address_region": "program_or_external",
"bytes": "1DFAFE072020",
"text": "MOV:G.W #H'2020, @H'FAFE",
"mnemonic": "MOV:G.W",
"operands": "#H'2020, @H'FAFE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64254,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17145,
"address_region": "program_or_external",
"bytes": "5D0001",
"text": "MOV:I.W #H'0001, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0001, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17148,
"address_region": "program_or_external",
"bytes": "1EFBCD",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17151,
"address_region": "program_or_external",
"bytes": "5D0002",
"text": "MOV:I.W #H'0002, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0002, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17154,
"address_region": "program_or_external",
"bytes": "1EFBC7",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17157,
"address_region": "program_or_external",
"bytes": "5D0003",
"text": "MOV:I.W #H'0003, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0003, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17160,
"address_region": "program_or_external",
"bytes": "1EFBC1",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17163,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17164,
"address_region": "program_or_external",
"bytes": "15FE8BD0",
"text": "BCLR.B #0, @P6DR",
"mnemonic": "BCLR.B",
"operands": "#0, @P6DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65163,
"name": "P6DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 0 of P6DR",
"valid": true
},
{
"address": 17168,
"address_region": "program_or_external",
"bytes": "15F55506AA",
"text": "MOV:G.B #H'AA, @H'F555",
"mnemonic": "MOV:G.B",
"operands": "#H'AA, @H'F555",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62805,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 17173,
"address_region": "program_or_external",
"bytes": "15F4AA0655",
"text": "MOV:G.B #H'55, @H'F4AA",
"mnemonic": "MOV:G.B",
"operands": "#H'55, @H'F4AA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62634,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 17178,
"address_region": "program_or_external",
"bytes": "15F55506CC",
"text": "MOV:G.B #H'CC, @H'F555",
"mnemonic": "MOV:G.B",
"operands": "#H'CC, @H'F555",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 62805,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 17183,
"address_region": "program_or_external",
"bytes": "15FE8BC0",
"text": "BSET.B #0, @P6DR",
"mnemonic": "BSET.B",
"operands": "#0, @P6DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65163,
"name": "P6DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 0 of P6DR",
"valid": true
},
{
"address": 17187,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17188,
"address_region": "program_or_external",
"bytes": "5C0038",
"text": "MOV:I.W #H'0038, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0038, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17191,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17194,
"address_region": "program_or_external",
"bytes": "1EFB9F",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17197,
"address_region": "program_or_external",
"bytes": "5C0001",
"text": "MOV:I.W #H'0001, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0001, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17200,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17203,
"address_region": "program_or_external",
"bytes": "1EFB96",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17206,
"address_region": "program_or_external",
"bytes": "5C000E",
"text": "MOV:I.W #H'000E, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'000E, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17209,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17212,
"address_region": "program_or_external",
"bytes": "1EFB8D",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17215,
"address_region": "program_or_external",
"bytes": "5C0006",
"text": "MOV:I.W #H'0006, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0006, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17218,
"address_region": "program_or_external",
"bytes": "5D0004",
"text": "MOV:I.W #H'0004, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'0004, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17221,
"address_region": "program_or_external",
"bytes": "1EFB84",
"text": "BSR loc_3ECC",
"mnemonic": "BSR",
"operands": "loc_3ECC",
"kind": "call",
"targets": [
16076
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17224,
"address_region": "program_or_external",
"bytes": "1ECD83",
"text": "BSR loc_10CE",
"mnemonic": "BSR",
"operands": "loc_10CE",
"kind": "call",
"targets": [
4302
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17227,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17228,
"address_region": "program_or_external",
"bytes": "15FF000670",
"text": "MOV:G.B #H'70, @IPRA",
"mnemonic": "MOV:G.B",
"operands": "#H'70, @IPRA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65280,
"name": "IPRA",
"region": "register_field",
"kind": "registers"
}
],
"comment": "IPRA = H'70 (irq0 priority=7; irq1 priority=0)",
"valid": true
},
{
"address": 17233,
"address_region": "program_or_external",
"bytes": "15FF010644",
"text": "MOV:G.B #H'44, @IPRB",
"mnemonic": "MOV:G.B",
"operands": "#H'44, @IPRB",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65281,
"name": "IPRB",
"region": "register_field",
"kind": "registers"
}
],
"comment": "IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4)",
"valid": true
},
{
"address": 17238,
"address_region": "program_or_external",
"bytes": "15FF020666",
"text": "MOV:G.B #H'66, @IPRC",
"mnemonic": "MOV:G.B",
"operands": "#H'66, @IPRC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65282,
"name": "IPRC",
"region": "register_field",
"kind": "registers"
}
],
"comment": "IPRC = H'66 (FRT1 priority=6; FRT2 priority=6)",
"valid": true
},
{
"address": 17243,
"address_region": "program_or_external",
"bytes": "15FF030600",
"text": "MOV:G.B #H'00, @IPRD",
"mnemonic": "MOV:G.B",
"operands": "#H'00, @IPRD",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65283,
"name": "IPRD",
"region": "register_field",
"kind": "registers"
}
],
"comment": "IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0)",
"valid": true
},
{
"address": 17248,
"address_region": "program_or_external",
"bytes": "15FF040650",
"text": "MOV:G.B #H'50, @IPRE",
"mnemonic": "MOV:G.B",
"operands": "#H'50, @IPRE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65284,
"name": "IPRE",
"region": "register_field",
"kind": "registers"
}
],
"comment": "IPRE = H'50 (SCI1 priority=5; SCI2 priority=0)",
"valid": true
},
{
"address": 17253,
"address_region": "program_or_external",
"bytes": "15FF050640",
"text": "MOV:G.B #H'40, @IPRF",
"mnemonic": "MOV:G.B",
"operands": "#H'40, @IPRF",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65285,
"name": "IPRF",
"region": "register_field",
"kind": "registers"
}
],
"comment": "IPRF = H'40 (A/D priority=4)",
"valid": true
},
{
"address": 17258,
"address_region": "program_or_external",
"bytes": "15FEDAC6",
"text": "BSET.B #6, @SCI1_SCR",
"mnemonic": "BSET.B",
"operands": "#6, @SCI1_SCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65242,
"name": "SCI1_SCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set RIE (bit 6) of SCI1_SCR",
"valid": true,
"sci": {
"writes": [
{
"address": 17258,
"instruction": "BSET.B #6, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BSET",
"value": 124,
"value_hex": "H'7C"
}
]
}
},
{
"address": 17262,
"address_region": "program_or_external",
"bytes": "15FE90C5",
"text": "BSET.B #5, @FRT1_TCR",
"mnemonic": "BSET.B",
"operands": "#5, @FRT1_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65168,
"name": "FRT1_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set OCIEA (bit 5) of FRT1_TCR",
"valid": true
},
{
"address": 17266,
"address_region": "program_or_external",
"bytes": "15FEA0C5",
"text": "BSET.B #5, @FRT2_TCR",
"mnemonic": "BSET.B",
"operands": "#5, @FRT2_TCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65184,
"name": "FRT2_TCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set OCIEA (bit 5) of FRT2_TCR",
"valid": true
},
{
"address": 17270,
"address_region": "program_or_external",
"bytes": "15FEE8C6",
"text": "BSET.B #6, @ADCSR",
"mnemonic": "BSET.B",
"operands": "#6, @ADCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65256,
"name": "ADCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set ADIE (bit 6) of ADCSR",
"valid": true
},
{
"address": 17274,
"address_region": "program_or_external",
"bytes": "15FEFDC4",
"text": "BSET.B #4, @SYSCR2",
"mnemonic": "BSET.B",
"operands": "#4, @SYSCR2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65277,
"name": "SYSCR2",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set IRQ3E (bit 4) of SYSCR2",
"valid": true
},
{
"address": 17278,
"address_region": "program_or_external",
"bytes": "15FEFDC5",
"text": "BSET.B #5, @SYSCR2",
"mnemonic": "BSET.B",
"operands": "#5, @SYSCR2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65277,
"name": "SYSCR2",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set IRQ4E (bit 5) of SYSCR2",
"valid": true
},
{
"address": 17282,
"address_region": "program_or_external",
"bytes": "15FE8EF6",
"text": "BTST.B #6, @P7DR",
"mnemonic": "BTST.B",
"operands": "#6, @P7DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65166,
"name": "P7DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 17286,
"address_region": "program_or_external",
"bytes": "2706",
"text": "BEQ loc_438E",
"mnemonic": "BEQ",
"operands": "loc_438E",
"kind": "branch",
"targets": [
17294
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17288,
"address_region": "program_or_external",
"bytes": "1DFEEC07A53F",
"text": "MOV:G.W #H'A53F, @WDT_TCSR_R",
"mnemonic": "MOV:G.W",
"operands": "#H'A53F, @WDT_TCSR_R",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65260,
"name": "WDT_TCSR_R",
"region": "register_field",
"kind": "registers"
}
],
"comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)",
"valid": true
},
{
"address": 17294,
"address_region": "program_or_external",
"bytes": "0C030088",
"text": "LDC.W #H'0300, SR",
"mnemonic": "LDC.W",
"operands": "#H'0300, SR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17298,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17299,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 13,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17300,
"address_region": "program_or_external",
"bytes": "15F7310401",
"text": "CMP:G.B #H'01, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'01, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17305,
"address_region": "program_or_external",
"bytes": "320086",
"text": "BHI loc_4422",
"mnemonic": "BHI",
"operands": "loc_4422",
"kind": "branch",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17308,
"address_region": "program_or_external",
"bytes": "15FB03F7",
"text": "BTST.B #7, @H'FB03",
"mnemonic": "BTST.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17312,
"address_region": "program_or_external",
"bytes": "36007F",
"text": "BNE loc_4422",
"mnemonic": "BNE",
"operands": "loc_4422",
"kind": "branch",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17315,
"address_region": "program_or_external",
"bytes": "1DF73683",
"text": "MOV:G.W @H'F736, R3",
"mnemonic": "MOV:G.W",
"operands": "@H'F736, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63286,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17319,
"address_region": "program_or_external",
"bytes": "370078",
"text": "BEQ loc_4422",
"mnemonic": "BEQ",
"operands": "loc_4422",
"kind": "branch",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17322,
"address_region": "program_or_external",
"bytes": "1DF69E84",
"text": "MOV:G.W @H'F69E, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F69E, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63134,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17326,
"address_region": "program_or_external",
"bytes": "1DF6BE34",
"text": "SUB.W @H'F6BE, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6BE, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63166,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17330,
"address_region": "program_or_external",
"bytes": "ABDF",
"text": "BCLR.W #15, R3",
"mnemonic": "BCLR.W",
"operands": "#15, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17332,
"address_region": "program_or_external",
"bytes": "2619",
"text": "BNE loc_43CF",
"mnemonic": "BNE",
"operands": "loc_43CF",
"kind": "branch",
"targets": [
17359
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17334,
"address_region": "program_or_external",
"bytes": "ABDE",
"text": "BCLR.W #14, R3",
"mnemonic": "BCLR.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17336,
"address_region": "program_or_external",
"bytes": "2621",
"text": "BNE loc_43DB",
"mnemonic": "BNE",
"operands": "loc_43DB",
"kind": "branch",
"targets": [
17371
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17338,
"address_region": "program_or_external",
"bytes": "ABDD",
"text": "BCLR.W #13, R3",
"mnemonic": "BCLR.W",
"operands": "#13, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17340,
"address_region": "program_or_external",
"bytes": "2629",
"text": "BNE loc_43E7",
"mnemonic": "BNE",
"operands": "loc_43E7",
"kind": "branch",
"targets": [
17383
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17342,
"address_region": "program_or_external",
"bytes": "ABDC",
"text": "BCLR.W #12, R3",
"mnemonic": "BCLR.W",
"operands": "#12, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17344,
"address_region": "program_or_external",
"bytes": "2631",
"text": "BNE loc_43F3",
"mnemonic": "BNE",
"operands": "loc_43F3",
"kind": "branch",
"targets": [
17395
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17346,
"address_region": "program_or_external",
"bytes": "ABDB",
"text": "BCLR.W #11, R3",
"mnemonic": "BCLR.W",
"operands": "#11, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17348,
"address_region": "program_or_external",
"bytes": "2639",
"text": "BNE loc_43FF",
"mnemonic": "BNE",
"operands": "loc_43FF",
"kind": "branch",
"targets": [
17407
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17350,
"address_region": "program_or_external",
"bytes": "ABDA",
"text": "BCLR.W #10, R3",
"mnemonic": "BCLR.W",
"operands": "#10, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17352,
"address_region": "program_or_external",
"bytes": "2643",
"text": "BNE loc_440D",
"mnemonic": "BNE",
"operands": "loc_440D",
"kind": "branch",
"targets": [
17421
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17354,
"address_region": "program_or_external",
"bytes": "1ED5D5",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17357,
"address_region": "program_or_external",
"bytes": "2053",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17359,
"address_region": "program_or_external",
"bytes": "0E5E",
"text": "BSR loc_442F",
"mnemonic": "BSR",
"operands": "loc_442F",
"kind": "call",
"targets": [
17455
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17361,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17364,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_43D9",
"mnemonic": "BEQ",
"operands": "loc_43D9",
"kind": "branch",
"targets": [
17369
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17366,
"address_region": "program_or_external",
"bytes": "1ED65C",
"text": "BSR loc_1A35",
"mnemonic": "BSR",
"operands": "loc_1A35",
"kind": "call",
"targets": [
6709
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17369,
"address_region": "program_or_external",
"bytes": "2047",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17371,
"address_region": "program_or_external",
"bytes": "0E52",
"text": "BSR loc_442F",
"mnemonic": "BSR",
"operands": "loc_442F",
"kind": "call",
"targets": [
17455
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17373,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17376,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_43E5",
"mnemonic": "BEQ",
"operands": "loc_43E5",
"kind": "branch",
"targets": [
17381
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17378,
"address_region": "program_or_external",
"bytes": "1ED6B7",
"text": "BSR loc_1A9C",
"mnemonic": "BSR",
"operands": "loc_1A9C",
"kind": "call",
"targets": [
6812
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17381,
"address_region": "program_or_external",
"bytes": "203B",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17383,
"address_region": "program_or_external",
"bytes": "0E46",
"text": "BSR loc_442F",
"mnemonic": "BSR",
"operands": "loc_442F",
"kind": "call",
"targets": [
17455
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17385,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17388,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_43F1",
"mnemonic": "BEQ",
"operands": "loc_43F1",
"kind": "branch",
"targets": [
17393
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17390,
"address_region": "program_or_external",
"bytes": "1ED6F3",
"text": "BSR loc_1AE4",
"mnemonic": "BSR",
"operands": "loc_1AE4",
"kind": "call",
"targets": [
6884
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17393,
"address_region": "program_or_external",
"bytes": "202F",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17395,
"address_region": "program_or_external",
"bytes": "0E3A",
"text": "BSR loc_442F",
"mnemonic": "BSR",
"operands": "loc_442F",
"kind": "call",
"targets": [
17455
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17397,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17400,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_43FD",
"mnemonic": "BEQ",
"operands": "loc_43FD",
"kind": "branch",
"targets": [
17405
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17402,
"address_region": "program_or_external",
"bytes": "1ED70E",
"text": "BSR loc_1B0B",
"mnemonic": "BSR",
"operands": "loc_1B0B",
"kind": "call",
"targets": [
6923
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17405,
"address_region": "program_or_external",
"bytes": "2023",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17407,
"address_region": "program_or_external",
"bytes": "15F7700680",
"text": "MOV:G.B #H'80, @H'F770",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F770",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63344,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17412,
"address_region": "program_or_external",
"bytes": "1DF77294",
"text": "MOV:G.W R4, @H'F772",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F772",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63346,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17416,
"address_region": "program_or_external",
"bytes": "1E04EF",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17419,
"address_region": "program_or_external",
"bytes": "2015",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17421,
"address_region": "program_or_external",
"bytes": "0E20",
"text": "BSR loc_442F",
"mnemonic": "BSR",
"operands": "loc_442F",
"kind": "call",
"targets": [
17455
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17423,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17426,
"address_region": "program_or_external",
"bytes": "270C",
"text": "BEQ loc_4420",
"mnemonic": "BEQ",
"operands": "loc_4420",
"kind": "branch",
"targets": [
17440
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17428,
"address_region": "program_or_external",
"bytes": "15F7700680",
"text": "MOV:G.B #H'80, @H'F770",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F770",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63344,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17433,
"address_region": "program_or_external",
"bytes": "1DF77294",
"text": "MOV:G.W R4, @H'F772",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F772",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63346,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17437,
"address_region": "program_or_external",
"bytes": "1E04DA",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17440,
"address_region": "program_or_external",
"bytes": "2000",
"text": "BRA loc_4422",
"mnemonic": "BRA",
"operands": "loc_4422",
"kind": "jump",
"targets": [
17442
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17442,
"address_region": "program_or_external",
"bytes": "1DF69E84",
"text": "MOV:G.W @H'F69E, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F69E, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63134,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17446,
"address_region": "program_or_external",
"bytes": "1DF6BE94",
"text": "MOV:G.W R4, @H'F6BE",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6BE",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63166,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17450,
"address_region": "program_or_external",
"bytes": "15FB0213",
"text": "CLR.B @H'FB02",
"mnemonic": "CLR.B",
"operands": "@H'FB02",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17454,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17455,
"address_region": "program_or_external",
"bytes": "15F6F724",
"text": "ADD:G.B @H'F6F7, R4",
"mnemonic": "ADD:G.B",
"operands": "@H'F6F7, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63223,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17459,
"address_region": "program_or_external",
"bytes": "4488",
"text": "CMP:E #H'88, R4",
"mnemonic": "CMP:E",
"operands": "#H'88, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17461,
"address_region": "program_or_external",
"bytes": "240D",
"text": "BCC loc_4444",
"mnemonic": "BCC",
"operands": "loc_4444",
"kind": "branch",
"targets": [
17476
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17463,
"address_region": "program_or_external",
"bytes": "4478",
"text": "CMP:E #H'78, R4",
"mnemonic": "CMP:E",
"operands": "#H'78, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17465,
"address_region": "program_or_external",
"bytes": "2313",
"text": "BLS loc_444E",
"mnemonic": "BLS",
"operands": "loc_444E",
"kind": "branch",
"targets": [
17486
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17467,
"address_region": "program_or_external",
"bytes": "15F6F794",
"text": "MOV:G.B R4, @H'F6F7",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6F7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63223,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17471,
"address_region": "program_or_external",
"bytes": "5C0002",
"text": "MOV:I.W #H'0002, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17474,
"address_region": "program_or_external",
"bytes": "2012",
"text": "BRA loc_4456",
"mnemonic": "BRA",
"operands": "loc_4456",
"kind": "jump",
"targets": [
17494
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17476,
"address_region": "program_or_external",
"bytes": "15F6F70680",
"text": "MOV:G.B #H'80, @H'F6F7",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63223,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17481,
"address_region": "program_or_external",
"bytes": "5C0000",
"text": "MOV:I.W #H'0000, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17484,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_4456",
"mnemonic": "BRA",
"operands": "loc_4456",
"kind": "jump",
"targets": [
17494
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17486,
"address_region": "program_or_external",
"bytes": "15F6F70680",
"text": "MOV:G.B #H'80, @H'F6F7",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63223,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17491,
"address_region": "program_or_external",
"bytes": "5C0001",
"text": "MOV:I.W #H'0001, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0001, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17494,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17495,
"address_region": "program_or_external",
"bytes": "15F7310401",
"text": "CMP:G.B #H'01, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'01, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17500,
"address_region": "program_or_external",
"bytes": "320086",
"text": "BHI loc_44E5",
"mnemonic": "BHI",
"operands": "loc_44E5",
"kind": "branch",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17503,
"address_region": "program_or_external",
"bytes": "15FB03F7",
"text": "BTST.B #7, @H'FB03",
"mnemonic": "BTST.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17507,
"address_region": "program_or_external",
"bytes": "36007F",
"text": "BNE loc_44E5",
"mnemonic": "BNE",
"operands": "loc_44E5",
"kind": "branch",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17510,
"address_region": "program_or_external",
"bytes": "1DF73883",
"text": "MOV:G.W @H'F738, R3",
"mnemonic": "MOV:G.W",
"operands": "@H'F738, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63288,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17514,
"address_region": "program_or_external",
"bytes": "370078",
"text": "BEQ loc_44E5",
"mnemonic": "BEQ",
"operands": "loc_44E5",
"kind": "branch",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17517,
"address_region": "program_or_external",
"bytes": "1DF69C84",
"text": "MOV:G.W @H'F69C, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F69C, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63132,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17521,
"address_region": "program_or_external",
"bytes": "1DF6BC34",
"text": "SUB.W @H'F6BC, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6BC, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63164,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17525,
"address_region": "program_or_external",
"bytes": "ABDF",
"text": "BCLR.W #15, R3",
"mnemonic": "BCLR.W",
"operands": "#15, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17527,
"address_region": "program_or_external",
"bytes": "2619",
"text": "BNE loc_4492",
"mnemonic": "BNE",
"operands": "loc_4492",
"kind": "branch",
"targets": [
17554
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17529,
"address_region": "program_or_external",
"bytes": "ABDE",
"text": "BCLR.W #14, R3",
"mnemonic": "BCLR.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17531,
"address_region": "program_or_external",
"bytes": "2621",
"text": "BNE loc_449E",
"mnemonic": "BNE",
"operands": "loc_449E",
"kind": "branch",
"targets": [
17566
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17533,
"address_region": "program_or_external",
"bytes": "ABDD",
"text": "BCLR.W #13, R3",
"mnemonic": "BCLR.W",
"operands": "#13, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17535,
"address_region": "program_or_external",
"bytes": "2629",
"text": "BNE loc_44AA",
"mnemonic": "BNE",
"operands": "loc_44AA",
"kind": "branch",
"targets": [
17578
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17537,
"address_region": "program_or_external",
"bytes": "ABDC",
"text": "BCLR.W #12, R3",
"mnemonic": "BCLR.W",
"operands": "#12, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17539,
"address_region": "program_or_external",
"bytes": "2631",
"text": "BNE loc_44B6",
"mnemonic": "BNE",
"operands": "loc_44B6",
"kind": "branch",
"targets": [
17590
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17541,
"address_region": "program_or_external",
"bytes": "ABDB",
"text": "BCLR.W #11, R3",
"mnemonic": "BCLR.W",
"operands": "#11, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17543,
"address_region": "program_or_external",
"bytes": "2639",
"text": "BNE loc_44C2",
"mnemonic": "BNE",
"operands": "loc_44C2",
"kind": "branch",
"targets": [
17602
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17545,
"address_region": "program_or_external",
"bytes": "ABDA",
"text": "BCLR.W #10, R3",
"mnemonic": "BCLR.W",
"operands": "#10, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17547,
"address_region": "program_or_external",
"bytes": "2643",
"text": "BNE loc_44D0",
"mnemonic": "BNE",
"operands": "loc_44D0",
"kind": "branch",
"targets": [
17616
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17549,
"address_region": "program_or_external",
"bytes": "1ED512",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17552,
"address_region": "program_or_external",
"bytes": "2053",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17554,
"address_region": "program_or_external",
"bytes": "0E5E",
"text": "BSR loc_44F2",
"mnemonic": "BSR",
"operands": "loc_44F2",
"kind": "call",
"targets": [
17650
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17556,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17559,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_449C",
"mnemonic": "BEQ",
"operands": "loc_449C",
"kind": "branch",
"targets": [
17564
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17561,
"address_region": "program_or_external",
"bytes": "1ED599",
"text": "BSR loc_1A35",
"mnemonic": "BSR",
"operands": "loc_1A35",
"kind": "call",
"targets": [
6709
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17564,
"address_region": "program_or_external",
"bytes": "2047",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17566,
"address_region": "program_or_external",
"bytes": "0E52",
"text": "BSR loc_44F2",
"mnemonic": "BSR",
"operands": "loc_44F2",
"kind": "call",
"targets": [
17650
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17568,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17571,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_44A8",
"mnemonic": "BEQ",
"operands": "loc_44A8",
"kind": "branch",
"targets": [
17576
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17573,
"address_region": "program_or_external",
"bytes": "1ED5F4",
"text": "BSR loc_1A9C",
"mnemonic": "BSR",
"operands": "loc_1A9C",
"kind": "call",
"targets": [
6812
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17576,
"address_region": "program_or_external",
"bytes": "203B",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17578,
"address_region": "program_or_external",
"bytes": "0E46",
"text": "BSR loc_44F2",
"mnemonic": "BSR",
"operands": "loc_44F2",
"kind": "call",
"targets": [
17650
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17580,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17583,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_44B4",
"mnemonic": "BEQ",
"operands": "loc_44B4",
"kind": "branch",
"targets": [
17588
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17585,
"address_region": "program_or_external",
"bytes": "1ED630",
"text": "BSR loc_1AE4",
"mnemonic": "BSR",
"operands": "loc_1AE4",
"kind": "call",
"targets": [
6884
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17588,
"address_region": "program_or_external",
"bytes": "202F",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17590,
"address_region": "program_or_external",
"bytes": "0E3A",
"text": "BSR loc_44F2",
"mnemonic": "BSR",
"operands": "loc_44F2",
"kind": "call",
"targets": [
17650
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17592,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17595,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_44C0",
"mnemonic": "BEQ",
"operands": "loc_44C0",
"kind": "branch",
"targets": [
17600
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17597,
"address_region": "program_or_external",
"bytes": "1ED64B",
"text": "BSR loc_1B0B",
"mnemonic": "BSR",
"operands": "loc_1B0B",
"kind": "call",
"targets": [
6923
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17600,
"address_region": "program_or_external",
"bytes": "2023",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17602,
"address_region": "program_or_external",
"bytes": "15F7700640",
"text": "MOV:G.B #H'40, @H'F770",
"mnemonic": "MOV:G.B",
"operands": "#H'40, @H'F770",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63344,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17607,
"address_region": "program_or_external",
"bytes": "1DF77294",
"text": "MOV:G.W R4, @H'F772",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F772",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63346,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17611,
"address_region": "program_or_external",
"bytes": "1E042C",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17614,
"address_region": "program_or_external",
"bytes": "2015",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17616,
"address_region": "program_or_external",
"bytes": "0E20",
"text": "BSR loc_44F2",
"mnemonic": "BSR",
"operands": "loc_44F2",
"kind": "call",
"targets": [
17650
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17618,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17621,
"address_region": "program_or_external",
"bytes": "270C",
"text": "BEQ loc_44E3",
"mnemonic": "BEQ",
"operands": "loc_44E3",
"kind": "branch",
"targets": [
17635
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17623,
"address_region": "program_or_external",
"bytes": "15F7700640",
"text": "MOV:G.B #H'40, @H'F770",
"mnemonic": "MOV:G.B",
"operands": "#H'40, @H'F770",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63344,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17628,
"address_region": "program_or_external",
"bytes": "1DF77294",
"text": "MOV:G.W R4, @H'F772",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F772",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63346,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17632,
"address_region": "program_or_external",
"bytes": "1E0417",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17635,
"address_region": "program_or_external",
"bytes": "2000",
"text": "BRA loc_44E5",
"mnemonic": "BRA",
"operands": "loc_44E5",
"kind": "jump",
"targets": [
17637
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17637,
"address_region": "program_or_external",
"bytes": "1DF69C84",
"text": "MOV:G.W @H'F69C, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F69C, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63132,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17641,
"address_region": "program_or_external",
"bytes": "1DF6BC94",
"text": "MOV:G.W R4, @H'F6BC",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6BC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63164,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17645,
"address_region": "program_or_external",
"bytes": "15FB0213",
"text": "CLR.B @H'FB02",
"mnemonic": "CLR.B",
"operands": "@H'FB02",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17649,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17650,
"address_region": "program_or_external",
"bytes": "15F6F824",
"text": "ADD:G.B @H'F6F8, R4",
"mnemonic": "ADD:G.B",
"operands": "@H'F6F8, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63224,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17654,
"address_region": "program_or_external",
"bytes": "4488",
"text": "CMP:E #H'88, R4",
"mnemonic": "CMP:E",
"operands": "#H'88, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17656,
"address_region": "program_or_external",
"bytes": "240D",
"text": "BCC loc_4507",
"mnemonic": "BCC",
"operands": "loc_4507",
"kind": "branch",
"targets": [
17671
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17658,
"address_region": "program_or_external",
"bytes": "4478",
"text": "CMP:E #H'78, R4",
"mnemonic": "CMP:E",
"operands": "#H'78, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17660,
"address_region": "program_or_external",
"bytes": "2313",
"text": "BLS loc_4511",
"mnemonic": "BLS",
"operands": "loc_4511",
"kind": "branch",
"targets": [
17681
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17662,
"address_region": "program_or_external",
"bytes": "15F6F894",
"text": "MOV:G.B R4, @H'F6F8",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6F8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63224,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17666,
"address_region": "program_or_external",
"bytes": "5C0002",
"text": "MOV:I.W #H'0002, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17669,
"address_region": "program_or_external",
"bytes": "2012",
"text": "BRA loc_4519",
"mnemonic": "BRA",
"operands": "loc_4519",
"kind": "jump",
"targets": [
17689
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17671,
"address_region": "program_or_external",
"bytes": "15F6F80680",
"text": "MOV:G.B #H'80, @H'F6F8",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63224,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17676,
"address_region": "program_or_external",
"bytes": "5C0000",
"text": "MOV:I.W #H'0000, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17679,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_4519",
"mnemonic": "BRA",
"operands": "loc_4519",
"kind": "jump",
"targets": [
17689
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17681,
"address_region": "program_or_external",
"bytes": "15F6F80680",
"text": "MOV:G.B #H'80, @H'F6F8",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63224,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17686,
"address_region": "program_or_external",
"bytes": "5C0001",
"text": "MOV:I.W #H'0001, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0001, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17689,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17690,
"address_region": "program_or_external",
"bytes": "15F7310401",
"text": "CMP:G.B #H'01, @H'F731",
"mnemonic": "CMP:G.B",
"operands": "#H'01, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17695,
"address_region": "program_or_external",
"bytes": "320086",
"text": "BHI loc_45A8",
"mnemonic": "BHI",
"operands": "loc_45A8",
"kind": "branch",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17698,
"address_region": "program_or_external",
"bytes": "15FB03F7",
"text": "BTST.B #7, @H'FB03",
"mnemonic": "BTST.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17702,
"address_region": "program_or_external",
"bytes": "36007F",
"text": "BNE loc_45A8",
"mnemonic": "BNE",
"operands": "loc_45A8",
"kind": "branch",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17705,
"address_region": "program_or_external",
"bytes": "1DF73A83",
"text": "MOV:G.W @H'F73A, R3",
"mnemonic": "MOV:G.W",
"operands": "@H'F73A, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63290,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17709,
"address_region": "program_or_external",
"bytes": "370078",
"text": "BEQ loc_45A8",
"mnemonic": "BEQ",
"operands": "loc_45A8",
"kind": "branch",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17712,
"address_region": "program_or_external",
"bytes": "1DF69A84",
"text": "MOV:G.W @H'F69A, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F69A, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63130,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17716,
"address_region": "program_or_external",
"bytes": "1DF6BA34",
"text": "SUB.W @H'F6BA, R4",
"mnemonic": "SUB.W",
"operands": "@H'F6BA, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17720,
"address_region": "program_or_external",
"bytes": "ABDF",
"text": "BCLR.W #15, R3",
"mnemonic": "BCLR.W",
"operands": "#15, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17722,
"address_region": "program_or_external",
"bytes": "2619",
"text": "BNE loc_4555",
"mnemonic": "BNE",
"operands": "loc_4555",
"kind": "branch",
"targets": [
17749
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17724,
"address_region": "program_or_external",
"bytes": "ABDE",
"text": "BCLR.W #14, R3",
"mnemonic": "BCLR.W",
"operands": "#14, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17726,
"address_region": "program_or_external",
"bytes": "2621",
"text": "BNE loc_4561",
"mnemonic": "BNE",
"operands": "loc_4561",
"kind": "branch",
"targets": [
17761
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17728,
"address_region": "program_or_external",
"bytes": "ABDD",
"text": "BCLR.W #13, R3",
"mnemonic": "BCLR.W",
"operands": "#13, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17730,
"address_region": "program_or_external",
"bytes": "2629",
"text": "BNE loc_456D",
"mnemonic": "BNE",
"operands": "loc_456D",
"kind": "branch",
"targets": [
17773
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17732,
"address_region": "program_or_external",
"bytes": "ABDC",
"text": "BCLR.W #12, R3",
"mnemonic": "BCLR.W",
"operands": "#12, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17734,
"address_region": "program_or_external",
"bytes": "2631",
"text": "BNE loc_4579",
"mnemonic": "BNE",
"operands": "loc_4579",
"kind": "branch",
"targets": [
17785
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17736,
"address_region": "program_or_external",
"bytes": "ABDB",
"text": "BCLR.W #11, R3",
"mnemonic": "BCLR.W",
"operands": "#11, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17738,
"address_region": "program_or_external",
"bytes": "2639",
"text": "BNE loc_4585",
"mnemonic": "BNE",
"operands": "loc_4585",
"kind": "branch",
"targets": [
17797
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17740,
"address_region": "program_or_external",
"bytes": "ABDA",
"text": "BCLR.W #10, R3",
"mnemonic": "BCLR.W",
"operands": "#10, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17742,
"address_region": "program_or_external",
"bytes": "2643",
"text": "BNE loc_4593",
"mnemonic": "BNE",
"operands": "loc_4593",
"kind": "branch",
"targets": [
17811
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17744,
"address_region": "program_or_external",
"bytes": "1ED44F",
"text": "BSR loc_19A2",
"mnemonic": "BSR",
"operands": "loc_19A2",
"kind": "call",
"targets": [
6562
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17747,
"address_region": "program_or_external",
"bytes": "2053",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17749,
"address_region": "program_or_external",
"bytes": "0E5E",
"text": "BSR loc_45B5",
"mnemonic": "BSR",
"operands": "loc_45B5",
"kind": "call",
"targets": [
17845
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17751,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17754,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_455F",
"mnemonic": "BEQ",
"operands": "loc_455F",
"kind": "branch",
"targets": [
17759
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17756,
"address_region": "program_or_external",
"bytes": "1ED4D6",
"text": "BSR loc_1A35",
"mnemonic": "BSR",
"operands": "loc_1A35",
"kind": "call",
"targets": [
6709
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17759,
"address_region": "program_or_external",
"bytes": "2047",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17761,
"address_region": "program_or_external",
"bytes": "0E52",
"text": "BSR loc_45B5",
"mnemonic": "BSR",
"operands": "loc_45B5",
"kind": "call",
"targets": [
17845
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17763,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17766,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_456B",
"mnemonic": "BEQ",
"operands": "loc_456B",
"kind": "branch",
"targets": [
17771
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17768,
"address_region": "program_or_external",
"bytes": "1ED531",
"text": "BSR loc_1A9C",
"mnemonic": "BSR",
"operands": "loc_1A9C",
"kind": "call",
"targets": [
6812
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17771,
"address_region": "program_or_external",
"bytes": "203B",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17773,
"address_region": "program_or_external",
"bytes": "0E46",
"text": "BSR loc_45B5",
"mnemonic": "BSR",
"operands": "loc_45B5",
"kind": "call",
"targets": [
17845
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17775,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17778,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_4577",
"mnemonic": "BEQ",
"operands": "loc_4577",
"kind": "branch",
"targets": [
17783
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17780,
"address_region": "program_or_external",
"bytes": "1ED56D",
"text": "BSR loc_1AE4",
"mnemonic": "BSR",
"operands": "loc_1AE4",
"kind": "call",
"targets": [
6884
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17783,
"address_region": "program_or_external",
"bytes": "202F",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17785,
"address_region": "program_or_external",
"bytes": "0E3A",
"text": "BSR loc_45B5",
"mnemonic": "BSR",
"operands": "loc_45B5",
"kind": "call",
"targets": [
17845
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17787,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17790,
"address_region": "program_or_external",
"bytes": "2703",
"text": "BEQ loc_4583",
"mnemonic": "BEQ",
"operands": "loc_4583",
"kind": "branch",
"targets": [
17795
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17792,
"address_region": "program_or_external",
"bytes": "1ED588",
"text": "BSR loc_1B0B",
"mnemonic": "BSR",
"operands": "loc_1B0B",
"kind": "call",
"targets": [
6923
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17795,
"address_region": "program_or_external",
"bytes": "2023",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17797,
"address_region": "program_or_external",
"bytes": "15F7700620",
"text": "MOV:G.B #H'20, @H'F770",
"mnemonic": "MOV:G.B",
"operands": "#H'20, @H'F770",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63344,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17802,
"address_region": "program_or_external",
"bytes": "1DF77294",
"text": "MOV:G.W R4, @H'F772",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F772",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63346,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17806,
"address_region": "program_or_external",
"bytes": "1E0369",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17809,
"address_region": "program_or_external",
"bytes": "2015",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17811,
"address_region": "program_or_external",
"bytes": "0E20",
"text": "BSR loc_45B5",
"mnemonic": "BSR",
"operands": "loc_45B5",
"kind": "call",
"targets": [
17845
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17813,
"address_region": "program_or_external",
"bytes": "4C0002",
"text": "CMP:I #H'0002, R4",
"mnemonic": "CMP:I",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17816,
"address_region": "program_or_external",
"bytes": "270C",
"text": "BEQ loc_45A6",
"mnemonic": "BEQ",
"operands": "loc_45A6",
"kind": "branch",
"targets": [
17830
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17818,
"address_region": "program_or_external",
"bytes": "15F7700620",
"text": "MOV:G.B #H'20, @H'F770",
"mnemonic": "MOV:G.B",
"operands": "#H'20, @H'F770",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63344,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17823,
"address_region": "program_or_external",
"bytes": "1DF77294",
"text": "MOV:G.W R4, @H'F772",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F772",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63346,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17827,
"address_region": "program_or_external",
"bytes": "1E0354",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17830,
"address_region": "program_or_external",
"bytes": "2000",
"text": "BRA loc_45A8",
"mnemonic": "BRA",
"operands": "loc_45A8",
"kind": "jump",
"targets": [
17832
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17832,
"address_region": "program_or_external",
"bytes": "1DF69A84",
"text": "MOV:G.W @H'F69A, R4",
"mnemonic": "MOV:G.W",
"operands": "@H'F69A, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63130,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17836,
"address_region": "program_or_external",
"bytes": "1DF6BA94",
"text": "MOV:G.W R4, @H'F6BA",
"mnemonic": "MOV:G.W",
"operands": "R4, @H'F6BA",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17840,
"address_region": "program_or_external",
"bytes": "15FB0213",
"text": "CLR.B @H'FB02",
"mnemonic": "CLR.B",
"operands": "@H'FB02",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64258,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17844,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17845,
"address_region": "program_or_external",
"bytes": "15F6F924",
"text": "ADD:G.B @H'F6F9, R4",
"mnemonic": "ADD:G.B",
"operands": "@H'F6F9, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63225,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17849,
"address_region": "program_or_external",
"bytes": "4488",
"text": "CMP:E #H'88, R4",
"mnemonic": "CMP:E",
"operands": "#H'88, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17851,
"address_region": "program_or_external",
"bytes": "240D",
"text": "BCC loc_45CA",
"mnemonic": "BCC",
"operands": "loc_45CA",
"kind": "branch",
"targets": [
17866
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17853,
"address_region": "program_or_external",
"bytes": "4478",
"text": "CMP:E #H'78, R4",
"mnemonic": "CMP:E",
"operands": "#H'78, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17855,
"address_region": "program_or_external",
"bytes": "2313",
"text": "BLS loc_45D4",
"mnemonic": "BLS",
"operands": "loc_45D4",
"kind": "branch",
"targets": [
17876
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17857,
"address_region": "program_or_external",
"bytes": "15F6F994",
"text": "MOV:G.B R4, @H'F6F9",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F6F9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63225,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17861,
"address_region": "program_or_external",
"bytes": "5C0002",
"text": "MOV:I.W #H'0002, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0002, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17864,
"address_region": "program_or_external",
"bytes": "2012",
"text": "BRA loc_45DC",
"mnemonic": "BRA",
"operands": "loc_45DC",
"kind": "jump",
"targets": [
17884
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17866,
"address_region": "program_or_external",
"bytes": "15F6F90680",
"text": "MOV:G.B #H'80, @H'F6F9",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63225,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17871,
"address_region": "program_or_external",
"bytes": "5C0000",
"text": "MOV:I.W #H'0000, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17874,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_45DC",
"mnemonic": "BRA",
"operands": "loc_45DC",
"kind": "jump",
"targets": [
17884
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17876,
"address_region": "program_or_external",
"bytes": "15F6F90680",
"text": "MOV:G.B #H'80, @H'F6F9",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F6F9",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63225,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 17881,
"address_region": "program_or_external",
"bytes": "5C0001",
"text": "MOV:I.W #H'0001, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0001, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 17884,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18671,
"address_region": "program_or_external",
"bytes": "1DF73480",
"text": "MOV:G.W @H'F734, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F734, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63284,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18675,
"address_region": "program_or_external",
"bytes": "1DF73290",
"text": "MOV:G.W R0, @H'F732",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F732",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18679,
"address_region": "program_or_external",
"bytes": "0E01",
"text": "BSR loc_48FA",
"mnemonic": "BSR",
"operands": "loc_48FA",
"kind": "call",
"targets": [
18682
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18681,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18682,
"address_region": "program_or_external",
"bytes": "15FB03F7",
"text": "BTST.B #7, @H'FB03",
"mnemonic": "BTST.B",
"operands": "#7, @H'FB03",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64259,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18686,
"address_region": "program_or_external",
"bytes": "2629",
"text": "BNE loc_4929",
"mnemonic": "BNE",
"operands": "loc_4929",
"kind": "branch",
"targets": [
18729
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18688,
"address_region": "program_or_external",
"bytes": "15F732041A",
"text": "CMP:G.B #H'1A, @H'F732",
"mnemonic": "CMP:G.B",
"operands": "#H'1A, @H'F732",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18693,
"address_region": "program_or_external",
"bytes": "2722",
"text": "BEQ loc_4929",
"mnemonic": "BEQ",
"operands": "loc_4929",
"kind": "branch",
"targets": [
18729
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18695,
"address_region": "program_or_external",
"bytes": "1DF732051900",
"text": "CMP:G.W #H'1900, @H'F732",
"mnemonic": "CMP:G.W",
"operands": "#H'1900, @H'F732",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18701,
"address_region": "program_or_external",
"bytes": "271A",
"text": "BEQ loc_4929",
"mnemonic": "BEQ",
"operands": "loc_4929",
"kind": "branch",
"targets": [
18729
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18703,
"address_region": "program_or_external",
"bytes": "1DE1ECFD",
"text": "BTST.W #13, @H'E1EC",
"mnemonic": "BTST.W",
"operands": "#13, @H'E1EC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57836,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 18707,
"address_region": "program_or_external",
"bytes": "2714",
"text": "BEQ loc_4929",
"mnemonic": "BEQ",
"operands": "loc_4929",
"kind": "branch",
"targets": [
18729
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18709,
"address_region": "program_or_external",
"bytes": "1DE1EC80",
"text": "MOV:G.W @H'E1EC, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'E1EC, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 57836,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 18713,
"address_region": "program_or_external",
"bytes": "0C9FFF50",
"text": "AND.W #H'9FFF, R0",
"mnemonic": "AND.W",
"operands": "#H'9FFF, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18717,
"address_region": "program_or_external",
"bytes": "1DE9EC90",
"text": "MOV:G.W R0, @H'E9EC",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'E9EC",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 59884,
"name": null,
"region": "program_or_external",
"kind": "program"
}
],
"comment": "",
"valid": true
},
{
"address": 18721,
"address_region": "program_or_external",
"bytes": "5280",
"text": "MOV:E.B #H'80, R2",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18723,
"address_region": "program_or_external",
"bytes": "5B00F6",
"text": "MOV:I.W #H'00F6, R3",
"mnemonic": "MOV:I.W",
"operands": "#H'00F6, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18726,
"address_region": "program_or_external",
"bytes": "1EF52B",
"text": "BSR loc_3E54",
"mnemonic": "BSR",
"operands": "loc_3E54",
"kind": "call",
"targets": [
15956
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18729,
"address_region": "program_or_external",
"bytes": "15F76EF6",
"text": "BTST.B #6, @H'F76E",
"mnemonic": "BTST.B",
"operands": "#6, @H'F76E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63342,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18733,
"address_region": "program_or_external",
"bytes": "260E",
"text": "BNE loc_493D",
"mnemonic": "BNE",
"operands": "loc_493D",
"kind": "branch",
"targets": [
18749
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18735,
"address_region": "program_or_external",
"bytes": "15F73280",
"text": "MOV:G.B @H'F732, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F732, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63282,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 18739,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18741,
"address_region": "program_or_external",
"bytes": "A01A",
"text": "SHLL.B R0",
"mnemonic": "SHLL.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18743,
"address_region": "program_or_external",
"bytes": "F8493E80",
"text": "MOV:G.W @(H'493E,R0), R0",
"mnemonic": "MOV:G.W",
"operands": "@(H'493E,R0), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18747,
"address_region": "program_or_external",
"bytes": "11D8",
"text": "JSR @R0",
"mnemonic": "JSR",
"operands": "@R0",
"kind": "call",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 18749,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25094,
"address_region": "program_or_external",
"bytes": "0C01FF55",
"text": "AND.W #H'01FF, R5",
"mnemonic": "AND.W",
"operands": "#H'01FF, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25098,
"address_region": "program_or_external",
"bytes": "4D007F",
"text": "CMP:I #H'007F, R5",
"mnemonic": "CMP:I",
"operands": "#H'007F, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25101,
"address_region": "program_or_external",
"bytes": "2307",
"text": "BLS loc_6216",
"mnemonic": "BLS",
"operands": "loc_6216",
"kind": "branch",
"targets": [
25110
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25103,
"address_region": "program_or_external",
"bytes": "4D017F",
"text": "CMP:I #H'017F, R5",
"mnemonic": "CMP:I",
"operands": "#H'017F, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25106,
"address_region": "program_or_external",
"bytes": "2304",
"text": "BLS loc_6218",
"mnemonic": "BLS",
"operands": "loc_6218",
"kind": "branch",
"targets": [
25112
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25108,
"address_region": "program_or_external",
"bytes": "200C",
"text": "BRA loc_6222",
"mnemonic": "BRA",
"operands": "loc_6222",
"kind": "jump",
"targets": [
25122
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25110,
"address_region": "program_or_external",
"bytes": "2012",
"text": "BRA loc_622A",
"mnemonic": "BRA",
"operands": "loc_622A",
"kind": "jump",
"targets": [
25130
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25112,
"address_region": "program_or_external",
"bytes": "0C008035",
"text": "SUB.W #H'0080, R5",
"mnemonic": "SUB.W",
"operands": "#H'0080, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25116,
"address_region": "program_or_external",
"bytes": "0C010025",
"text": "ADD:G.W #H'0100, R5",
"mnemonic": "ADD:G.W",
"operands": "#H'0100, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25120,
"address_region": "program_or_external",
"bytes": "2008",
"text": "BRA loc_622A",
"mnemonic": "BRA",
"operands": "loc_622A",
"kind": "jump",
"targets": [
25130
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25122,
"address_region": "program_or_external",
"bytes": "0C018035",
"text": "SUB.W #H'0180, R5",
"mnemonic": "SUB.W",
"operands": "#H'0180, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25126,
"address_region": "program_or_external",
"bytes": "0C020025",
"text": "ADD:G.W #H'0200, R5",
"mnemonic": "ADD:G.W",
"operands": "#H'0200, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25130,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25131,
"address_region": "program_or_external",
"bytes": "AD84",
"text": "MOV:G.W R5, R4",
"mnemonic": "MOV:G.W",
"operands": "R5, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25133,
"address_region": "program_or_external",
"bytes": "A512",
"text": "EXTU.B R5",
"mnemonic": "EXTU.B",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25135,
"address_region": "program_or_external",
"bytes": "A410",
"text": "SWAP.B R4",
"mnemonic": "SWAP.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25137,
"address_region": "program_or_external",
"bytes": "040754",
"text": "AND.B #H'07, R4",
"mnemonic": "AND.B",
"operands": "#H'07, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25140,
"address_region": "program_or_external",
"bytes": "4400",
"text": "CMP:E #H'00, R4",
"mnemonic": "CMP:E",
"operands": "#H'00, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25142,
"address_region": "program_or_external",
"bytes": "270C",
"text": "BEQ loc_6244",
"mnemonic": "BEQ",
"operands": "loc_6244",
"kind": "branch",
"targets": [
25156
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25144,
"address_region": "program_or_external",
"bytes": "4401",
"text": "CMP:E #H'01, R4",
"mnemonic": "CMP:E",
"operands": "#H'01, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25146,
"address_region": "program_or_external",
"bytes": "2711",
"text": "BEQ loc_624D",
"mnemonic": "BEQ",
"operands": "loc_624D",
"kind": "branch",
"targets": [
25165
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25148,
"address_region": "program_or_external",
"bytes": "4402",
"text": "CMP:E #H'02, R4",
"mnemonic": "CMP:E",
"operands": "#H'02, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25150,
"address_region": "program_or_external",
"bytes": "2716",
"text": "BEQ loc_6256",
"mnemonic": "BEQ",
"operands": "loc_6256",
"kind": "branch",
"targets": [
25174
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25152,
"address_region": "program_or_external",
"bytes": "4403",
"text": "CMP:E #H'03, R4",
"mnemonic": "CMP:E",
"operands": "#H'03, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25154,
"address_region": "program_or_external",
"bytes": "271B",
"text": "BEQ loc_625F",
"mnemonic": "BEQ",
"operands": "loc_625F",
"kind": "branch",
"targets": [
25183
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25156,
"address_region": "program_or_external",
"bytes": "457F",
"text": "CMP:E #H'7F, R5",
"mnemonic": "CMP:E",
"operands": "#H'7F, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25158,
"address_region": "program_or_external",
"bytes": "2217",
"text": "BHI loc_625F",
"mnemonic": "BHI",
"operands": "loc_625F",
"kind": "branch",
"targets": [
25183
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25160,
"address_region": "program_or_external",
"bytes": "5C0000",
"text": "MOV:I.W #H'0000, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0000, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25163,
"address_region": "program_or_external",
"bytes": "2017",
"text": "BRA loc_6264",
"mnemonic": "BRA",
"operands": "loc_6264",
"kind": "jump",
"targets": [
25188
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25165,
"address_region": "program_or_external",
"bytes": "45FF",
"text": "CMP:E #H'FF, R5",
"mnemonic": "CMP:E",
"operands": "#H'FF, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25167,
"address_region": "program_or_external",
"bytes": "220E",
"text": "BHI loc_625F",
"mnemonic": "BHI",
"operands": "loc_625F",
"kind": "branch",
"targets": [
25183
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25169,
"address_region": "program_or_external",
"bytes": "5C0080",
"text": "MOV:I.W #H'0080, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0080, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25172,
"address_region": "program_or_external",
"bytes": "200E",
"text": "BRA loc_6264",
"mnemonic": "BRA",
"operands": "loc_6264",
"kind": "jump",
"targets": [
25188
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25174,
"address_region": "program_or_external",
"bytes": "457F",
"text": "CMP:E #H'7F, R5",
"mnemonic": "CMP:E",
"operands": "#H'7F, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25176,
"address_region": "program_or_external",
"bytes": "2205",
"text": "BHI loc_625F",
"mnemonic": "BHI",
"operands": "loc_625F",
"kind": "branch",
"targets": [
25183
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25178,
"address_region": "program_or_external",
"bytes": "5C0180",
"text": "MOV:I.W #H'0180, R4",
"mnemonic": "MOV:I.W",
"operands": "#H'0180, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25181,
"address_region": "program_or_external",
"bytes": "2005",
"text": "BRA loc_6264",
"mnemonic": "BRA",
"operands": "loc_6264",
"kind": "jump",
"targets": [
25188
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25183,
"address_region": "program_or_external",
"bytes": "AC13",
"text": "CLR.W R4",
"mnemonic": "CLR.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25185,
"address_region": "program_or_external",
"bytes": "5D01FF",
"text": "MOV:I.W #H'01FF, R5",
"mnemonic": "MOV:I.W",
"operands": "#H'01FF, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25188,
"address_region": "program_or_external",
"bytes": "AC25",
"text": "ADD:G.W R4, R5",
"mnemonic": "ADD:G.W",
"operands": "R4, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 25190,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47654,
"address_region": "program_or_external",
"bytes": "15F9C016",
"text": "TST.B @H'F9C0",
"mnemonic": "TST.B",
"operands": "@H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47658,
"address_region": "program_or_external",
"bytes": "26FA",
"text": "BNE loc_BA26",
"mnemonic": "BNE",
"operands": "loc_BA26",
"kind": "branch",
"targets": [
47654
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47660,
"address_region": "program_or_external",
"bytes": "15F9C00664",
"text": "MOV:G.B #H'64, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'64, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47665,
"address_region": "program_or_external",
"bytes": "15F9C40607",
"text": "MOV:G.B #H'07, @H'F9C4",
"mnemonic": "MOV:G.B",
"operands": "#H'07, @H'F9C4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63940,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47670,
"address_region": "program_or_external",
"bytes": "1DF85080",
"text": "MOV:G.W @H'F850, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F850, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63568,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47674,
"address_region": "program_or_external",
"bytes": "1DF85890",
"text": "MOV:G.W R0, @H'F858",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F858",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63576,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47678,
"address_region": "program_or_external",
"bytes": "1DF85280",
"text": "MOV:G.W @H'F852, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F852, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63570,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47682,
"address_region": "program_or_external",
"bytes": "1DF85A90",
"text": "MOV:G.W R0, @H'F85A",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F85A",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63578,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47686,
"address_region": "program_or_external",
"bytes": "15F85480",
"text": "MOV:G.B @H'F854, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F854, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63572,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47690,
"address_region": "program_or_external",
"bytes": "15F85C90",
"text": "MOV:G.B R0, @H'F85C",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F85C",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63580,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47694,
"address_region": "program_or_external",
"bytes": "505A",
"text": "MOV:E.B #H'5A, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'5A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47696,
"address_region": "program_or_external",
"bytes": "15F85860",
"text": "XOR.B @H'F858, R0",
"mnemonic": "XOR.B",
"operands": "@H'F858, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63576,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47700,
"address_region": "program_or_external",
"bytes": "15F85960",
"text": "XOR.B @H'F859, R0",
"mnemonic": "XOR.B",
"operands": "@H'F859, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63577,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47704,
"address_region": "program_or_external",
"bytes": "15F85A60",
"text": "XOR.B @H'F85A, R0",
"mnemonic": "XOR.B",
"operands": "@H'F85A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63578,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47708,
"address_region": "program_or_external",
"bytes": "15F85B60",
"text": "XOR.B @H'F85B, R0",
"mnemonic": "XOR.B",
"operands": "@H'F85B, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63579,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47712,
"address_region": "program_or_external",
"bytes": "15F85C60",
"text": "XOR.B @H'F85C, R0",
"mnemonic": "XOR.B",
"operands": "@H'F85C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63580,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47716,
"address_region": "program_or_external",
"bytes": "15F85D90",
"text": "MOV:G.B R0, @H'F85D",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F85D",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63581,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47720,
"address_region": "program_or_external",
"bytes": "15FEDCF7",
"text": "BTST.B #7, @SCI1_SSR",
"mnemonic": "BTST.B",
"operands": "#7, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 47724,
"address_region": "program_or_external",
"bytes": "27FA",
"text": "BEQ loc_BA68",
"mnemonic": "BEQ",
"operands": "loc_BA68",
"kind": "branch",
"targets": [
47720
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47726,
"address_region": "program_or_external",
"bytes": "15F85880",
"text": "MOV:G.B @H'F858, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F858, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63576,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47730,
"address_region": "program_or_external",
"bytes": "15FEDB90",
"text": "MOV:G.B R0, @SCI1_TDR",
"mnemonic": "MOV:G.B",
"operands": "R0, @SCI1_TDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65243,
"name": "SCI1_TDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI1_TDR",
"valid": true
},
{
"address": 47734,
"address_region": "program_or_external",
"bytes": "15F9C20601",
"text": "MOV:G.B #H'01, @H'F9C2",
"mnemonic": "MOV:G.B",
"operands": "#H'01, @H'F9C2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63938,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47739,
"address_region": "program_or_external",
"bytes": "15FEDCD7",
"text": "BCLR.B #7, @SCI1_SSR",
"mnemonic": "BCLR.B",
"operands": "#7, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear TDRE (bit 7) of SCI1_SSR",
"valid": true
},
{
"address": 47743,
"address_region": "program_or_external",
"bytes": "15FEDAC7",
"text": "BSET.B #7, @SCI1_SCR",
"mnemonic": "BSET.B",
"operands": "#7, @SCI1_SCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65242,
"name": "SCI1_SCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set TIE (bit 7) of SCI1_SCR",
"valid": true,
"sci": {
"writes": [
{
"address": 47743,
"instruction": "BSET.B #7, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BSET",
"value": 252,
"value_hex": "H'FC"
}
]
}
},
{
"address": 47747,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47748,
"address_region": "program_or_external",
"bytes": "15FAA2F3",
"text": "BTST.B #3, @H'FAA2",
"mnemonic": "BTST.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47752,
"address_region": "program_or_external",
"bytes": "271F",
"text": "BEQ loc_BAA9",
"mnemonic": "BEQ",
"operands": "loc_BAA9",
"kind": "branch",
"targets": [
47785
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47754,
"address_region": "program_or_external",
"bytes": "15FAA5F7",
"text": "BTST.B #7, @H'FAA5",
"mnemonic": "BTST.B",
"operands": "#7, @H'FAA5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64165,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47758,
"address_region": "program_or_external",
"bytes": "2719",
"text": "BEQ loc_BAA9",
"mnemonic": "BEQ",
"operands": "loc_BAA9",
"kind": "branch",
"targets": [
47785
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47760,
"address_region": "program_or_external",
"bytes": "15F9C316",
"text": "TST.B @H'F9C3",
"mnemonic": "TST.B",
"operands": "@H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47764,
"address_region": "program_or_external",
"bytes": "2713",
"text": "BEQ loc_BAA9",
"mnemonic": "BEQ",
"operands": "loc_BAA9",
"kind": "branch",
"targets": [
47785
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47766,
"address_region": "program_or_external",
"bytes": "15FAA2D3",
"text": "BCLR.B #3, @H'FAA2",
"mnemonic": "BCLR.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47770,
"address_region": "program_or_external",
"bytes": "15FAA313",
"text": "CLR.B @H'FAA3",
"mnemonic": "CLR.B",
"operands": "@H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47774,
"address_region": "program_or_external",
"bytes": "15FEDAD7",
"text": "BCLR.B #7, @SCI1_SCR",
"mnemonic": "BCLR.B",
"operands": "#7, @SCI1_SCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65242,
"name": "SCI1_SCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear TIE (bit 7) of SCI1_SCR",
"valid": true,
"sci": {
"writes": [
{
"address": 47774,
"instruction": "BCLR.B #7, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BCLR",
"value": 124,
"value_hex": "H'7C"
}
]
}
},
{
"address": 47778,
"address_region": "program_or_external",
"bytes": "15F9C0061F",
"text": "MOV:G.B #H'1F, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'1F, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47783,
"address_region": "program_or_external",
"bytes": "2048",
"text": "BRA loc_BAF1",
"mnemonic": "BRA",
"operands": "loc_BAF1",
"kind": "jump",
"targets": [
47857
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47785,
"address_region": "program_or_external",
"bytes": "BF90",
"text": "MOV:G.W R0, @-R7",
"mnemonic": "MOV:G.W",
"operands": "R0, @-R7",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 5,
"base_cycles": 5,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47787,
"address_region": "program_or_external",
"bytes": "15F9C280",
"text": "MOV:G.B @H'F9C2, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F9C2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63938,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47791,
"address_region": "program_or_external",
"bytes": "A012",
"text": "EXTU.B R0",
"mnemonic": "EXTU.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47793,
"address_region": "program_or_external",
"bytes": "F0F85880",
"text": "MOV:G.B @(-H'07A8,R0), R0",
"mnemonic": "MOV:G.B",
"operands": "@(-H'07A8,R0), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47797,
"address_region": "program_or_external",
"bytes": "15FEDB90",
"text": "MOV:G.B R0, @SCI1_TDR",
"mnemonic": "MOV:G.B",
"operands": "R0, @SCI1_TDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65243,
"name": "SCI1_TDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "SCI1_TDR",
"valid": true
},
{
"address": 47801,
"address_region": "program_or_external",
"bytes": "CF80",
"text": "MOV:G.W @R7+, R0",
"mnemonic": "MOV:G.W",
"operands": "@R7+, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 5,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47803,
"address_region": "program_or_external",
"bytes": "15FEDCD7",
"text": "BCLR.B #7, @SCI1_SSR",
"mnemonic": "BCLR.B",
"operands": "#7, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear TDRE (bit 7) of SCI1_SSR",
"valid": true
},
{
"address": 47807,
"address_region": "program_or_external",
"bytes": "15F9C208",
"text": "ADD:Q.B #1, @H'F9C2",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9C2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63938,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47811,
"address_region": "program_or_external",
"bytes": "15F9C20406",
"text": "CMP:G.B #H'06, @H'F9C2",
"mnemonic": "CMP:G.B",
"operands": "#H'06, @H'F9C2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63938,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47816,
"address_region": "program_or_external",
"bytes": "2627",
"text": "BNE loc_BAF1",
"mnemonic": "BNE",
"operands": "loc_BAF1",
"kind": "branch",
"targets": [
47857
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47818,
"address_region": "program_or_external",
"bytes": "15FEDAD7",
"text": "BCLR.B #7, @SCI1_SCR",
"mnemonic": "BCLR.B",
"operands": "#7, @SCI1_SCR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65242,
"name": "SCI1_SCR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear TIE (bit 7) of SCI1_SCR",
"valid": true,
"sci": {
"writes": [
{
"address": 47818,
"instruction": "BCLR.B #7, @SCI1_SCR",
"channel": "SCI1",
"register": "SCR",
"register_address": 65242,
"operation": "BCLR",
"value": 124,
"value_hex": "H'7C"
}
]
}
},
{
"address": 47822,
"address_region": "program_or_external",
"bytes": "15F795F6",
"text": "BTST.B #6, @H'F795",
"mnemonic": "BTST.B",
"operands": "#6, @H'F795",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63381,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47826,
"address_region": "program_or_external",
"bytes": "2614",
"text": "BNE loc_BAE8",
"mnemonic": "BNE",
"operands": "loc_BAE8",
"kind": "branch",
"targets": [
47848
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47828,
"address_region": "program_or_external",
"bytes": "15F791F7",
"text": "BTST.B #7, @H'F791",
"mnemonic": "BTST.B",
"operands": "#7, @H'F791",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63377,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47832,
"address_region": "program_or_external",
"bytes": "2607",
"text": "BNE loc_BAE1",
"mnemonic": "BNE",
"operands": "loc_BAE1",
"kind": "branch",
"targets": [
47841
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47834,
"address_region": "program_or_external",
"bytes": "15F9C00609",
"text": "MOV:G.B #H'09, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'09, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47839,
"address_region": "program_or_external",
"bytes": "200C",
"text": "BRA loc_BAED",
"mnemonic": "BRA",
"operands": "loc_BAED",
"kind": "jump",
"targets": [
47853
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47841,
"address_region": "program_or_external",
"bytes": "15F9C00609",
"text": "MOV:G.B #H'09, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'09, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47846,
"address_region": "program_or_external",
"bytes": "2005",
"text": "BRA loc_BAED",
"mnemonic": "BRA",
"operands": "loc_BAED",
"kind": "jump",
"targets": [
47853
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47848,
"address_region": "program_or_external",
"bytes": "15F9C006F0",
"text": "MOV:G.B #H'F0, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'F0, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47853,
"address_region": "program_or_external",
"bytes": "15F9C113",
"text": "CLR.B @H'F9C1",
"mnemonic": "CLR.B",
"operands": "@H'F9C1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63937,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47857,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 13,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47858,
"address_region": "program_or_external",
"bytes": "15F9B581",
"text": "MOV:G.B @H'F9B5, R1",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B5, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47862,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47864,
"address_region": "program_or_external",
"bytes": "15F9B071",
"text": "CMP:G.B @H'F9B0, R1",
"mnemonic": "CMP:G.B",
"operands": "@H'F9B0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63920,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47868,
"address_region": "program_or_external",
"bytes": "2602",
"text": "BNE loc_BB00",
"mnemonic": "BNE",
"operands": "loc_BB00",
"kind": "branch",
"targets": [
47872
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47870,
"address_region": "program_or_external",
"bytes": "2056",
"text": "BRA loc_BB56",
"mnemonic": "BRA",
"operands": "loc_BB56",
"kind": "jump",
"targets": [
47958
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47872,
"address_region": "program_or_external",
"bytes": "15FAA2C3",
"text": "BSET.B #3, @H'FAA2",
"mnemonic": "BSET.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47876,
"address_region": "program_or_external",
"bytes": "A980",
"text": "MOV:G.W R1, R0",
"mnemonic": "MOV:G.W",
"operands": "R1, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47878,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47880,
"address_region": "program_or_external",
"bytes": "F8F87080",
"text": "MOV:G.W @(-H'0790,R0), R0",
"mnemonic": "MOV:G.W",
"operands": "@(-H'0790,R0), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47884,
"address_region": "program_or_external",
"bytes": "A885",
"text": "MOV:G.W R0, R5",
"mnemonic": "MOV:G.W",
"operands": "R0, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47886,
"address_region": "program_or_external",
"bytes": "1EA6F5",
"text": "BSR loc_6206",
"mnemonic": "BSR",
"operands": "loc_6206",
"kind": "call",
"targets": [
25094
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47889,
"address_region": "program_or_external",
"bytes": "A881",
"text": "MOV:G.W R0, R1",
"mnemonic": "MOV:G.W",
"operands": "R0, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47891,
"address_region": "program_or_external",
"bytes": "A110",
"text": "SWAP.B R1",
"mnemonic": "SWAP.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47893,
"address_region": "program_or_external",
"bytes": "A11B",
"text": "SHLR.B R1",
"mnemonic": "SHLR.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47895,
"address_region": "program_or_external",
"bytes": "A182",
"text": "MOV:G.B R1, R2",
"mnemonic": "MOV:G.B",
"operands": "R1, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47897,
"address_region": "program_or_external",
"bytes": "040751",
"text": "AND.B #H'07, R1",
"mnemonic": "AND.B",
"operands": "#H'07, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47900,
"address_region": "program_or_external",
"bytes": "15F85091",
"text": "MOV:G.B R1, @H'F850",
"mnemonic": "MOV:G.B",
"operands": "R1, @H'F850",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63568,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47904,
"address_region": "program_or_external",
"bytes": "15F85295",
"text": "MOV:G.B R5, @H'F852",
"mnemonic": "MOV:G.B",
"operands": "R5, @H'F852",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63570,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47908,
"address_region": "program_or_external",
"bytes": "A510",
"text": "SWAP.B R5",
"mnemonic": "SWAP.B",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47910,
"address_region": "program_or_external",
"bytes": "047852",
"text": "AND.B #H'78, R2",
"mnemonic": "AND.B",
"operands": "#H'78, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47913,
"address_region": "program_or_external",
"bytes": "A245",
"text": "OR.B R2, R5",
"mnemonic": "OR.B",
"operands": "R2, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47915,
"address_region": "program_or_external",
"bytes": "15F85195",
"text": "MOV:G.B R5, @H'F851",
"mnemonic": "MOV:G.B",
"operands": "R5, @H'F851",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63569,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47919,
"address_region": "program_or_external",
"bytes": "0C01FF50",
"text": "AND.W #H'01FF, R0",
"mnemonic": "AND.W",
"operands": "#H'01FF, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47923,
"address_region": "program_or_external",
"bytes": "A81A",
"text": "SHLL.W R0",
"mnemonic": "SHLL.W",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47925,
"address_region": "program_or_external",
"bytes": "F8E80084",
"text": "MOV:G.W @(-H'1800,R0), R4",
"mnemonic": "MOV:G.W",
"operands": "@(-H'1800,R0), R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47929,
"address_region": "program_or_external",
"bytes": "15F85494",
"text": "MOV:G.B R4, @H'F854",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F854",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63572,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47933,
"address_region": "program_or_external",
"bytes": "A410",
"text": "SWAP.B R4",
"mnemonic": "SWAP.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47935,
"address_region": "program_or_external",
"bytes": "15F85394",
"text": "MOV:G.B R4, @H'F853",
"mnemonic": "MOV:G.B",
"operands": "R4, @H'F853",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63571,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47939,
"address_region": "program_or_external",
"bytes": "1EFEE0",
"text": "BSR loc_BA26",
"mnemonic": "BSR",
"operands": "loc_BA26",
"kind": "call",
"targets": [
47654
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47942,
"address_region": "program_or_external",
"bytes": "1DF9C60701F4",
"text": "MOV:G.W #H'01F4, @H'F9C6",
"mnemonic": "MOV:G.W",
"operands": "#H'01F4, @H'F9C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63942,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47948,
"address_region": "program_or_external",
"bytes": "15F9C80614",
"text": "MOV:G.B #H'14, @H'F9C8",
"mnemonic": "MOV:G.B",
"operands": "#H'14, @H'F9C8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63944,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47953,
"address_region": "program_or_external",
"bytes": "15FAA30680",
"text": "MOV:G.B #H'80, @H'FAA3",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47958,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47959,
"address_region": "program_or_external",
"bytes": "15FAA4C7",
"text": "BSET.B #7, @H'FAA4",
"mnemonic": "BSET.B",
"operands": "#7, @H'FAA4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64164,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47963,
"address_region": "program_or_external",
"bytes": "15FEDCD5",
"text": "BCLR.B #5, @SCI1_SSR",
"mnemonic": "BCLR.B",
"operands": "#5, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear ORER (bit 5) of SCI1_SSR",
"valid": true
},
{
"address": 47967,
"address_region": "program_or_external",
"bytes": "15FEDCD4",
"text": "BCLR.B #4, @SCI1_SSR",
"mnemonic": "BCLR.B",
"operands": "#4, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear FER (bit 4) of SCI1_SSR",
"valid": true
},
{
"address": 47971,
"address_region": "program_or_external",
"bytes": "15FEDCD3",
"text": "BCLR.B #3, @SCI1_SSR",
"mnemonic": "BCLR.B",
"operands": "#3, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear PER (bit 3) of SCI1_SSR",
"valid": true
},
{
"address": 47975,
"address_region": "program_or_external",
"bytes": "1203",
"text": "STM.W {R0,R1}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R1}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 12,
"note": "6+3n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47977,
"address_region": "program_or_external",
"bytes": "15FEDCD6",
"text": "BCLR.B #6, @SCI1_SSR",
"mnemonic": "BCLR.B",
"operands": "#6, @SCI1_SSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65244,
"name": "SCI1_SSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear RDRF (bit 6) of SCI1_SSR",
"valid": true
},
{
"address": 47981,
"address_region": "program_or_external",
"bytes": "15FEDD80",
"text": "MOV:G.B @SCI1_RDR, R0",
"mnemonic": "MOV:G.B",
"operands": "@SCI1_RDR, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65245,
"name": "SCI1_RDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 47985,
"address_region": "program_or_external",
"bytes": "15F9C116",
"text": "TST.B @H'F9C1",
"mnemonic": "TST.B",
"operands": "@H'F9C1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63937,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47989,
"address_region": "program_or_external",
"bytes": "2606",
"text": "BNE loc_BB7D",
"mnemonic": "BNE",
"operands": "loc_BB7D",
"kind": "branch",
"targets": [
47997
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47991,
"address_region": "program_or_external",
"bytes": "15F9C313",
"text": "CLR.B @H'F9C3",
"mnemonic": "CLR.B",
"operands": "@H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 47995,
"address_region": "program_or_external",
"bytes": "200D",
"text": "BRA loc_BB8A",
"mnemonic": "BRA",
"operands": "loc_BB8A",
"kind": "jump",
"targets": [
48010
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 47997,
"address_region": "program_or_external",
"bytes": "15F9C30405",
"text": "CMP:G.B #H'05, @H'F9C3",
"mnemonic": "CMP:G.B",
"operands": "#H'05, @H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48002,
"address_region": "program_or_external",
"bytes": "2306",
"text": "BLS loc_BB8A",
"mnemonic": "BLS",
"operands": "loc_BB8A",
"kind": "branch",
"targets": [
48010
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48004,
"address_region": "program_or_external",
"bytes": "15FAA413",
"text": "CLR.B @H'FAA4",
"mnemonic": "CLR.B",
"operands": "@H'FAA4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64164,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48008,
"address_region": "program_or_external",
"bytes": "2019",
"text": "BRA loc_BBA3",
"mnemonic": "BRA",
"operands": "loc_BBA3",
"kind": "jump",
"targets": [
48035
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48010,
"address_region": "program_or_external",
"bytes": "15F9C381",
"text": "MOV:G.B @H'F9C3, R1",
"mnemonic": "MOV:G.B",
"operands": "@H'F9C3, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48014,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48016,
"address_region": "program_or_external",
"bytes": "F1F86890",
"text": "MOV:G.B R0, @(-H'0798,R1)",
"mnemonic": "MOV:G.B",
"operands": "R0, @(-H'0798,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48020,
"address_region": "program_or_external",
"bytes": "A108",
"text": "ADD:Q.B #1, R1",
"mnemonic": "ADD:Q.B",
"operands": "#1, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48022,
"address_region": "program_or_external",
"bytes": "15F9C391",
"text": "MOV:G.B R1, @H'F9C3",
"mnemonic": "MOV:G.B",
"operands": "R1, @H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48026,
"address_region": "program_or_external",
"bytes": "4106",
"text": "CMP:E #H'06, R1",
"mnemonic": "CMP:E",
"operands": "#H'06, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48028,
"address_region": "program_or_external",
"bytes": "2605",
"text": "BNE loc_BBA3",
"mnemonic": "BNE",
"operands": "loc_BBA3",
"kind": "branch",
"targets": [
48035
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48030,
"address_region": "program_or_external",
"bytes": "15F9C50614",
"text": "MOV:G.B #H'14, @H'F9C5",
"mnemonic": "MOV:G.B",
"operands": "#H'14, @H'F9C5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63941,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48035,
"address_region": "program_or_external",
"bytes": "15F9C10605",
"text": "MOV:G.B #H'05, @H'F9C1",
"mnemonic": "MOV:G.B",
"operands": "#H'05, @H'F9C1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63937,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48040,
"address_region": "program_or_external",
"bytes": "0203",
"text": "LDM.W @SP+, {R0,R1}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R1}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 14,
"note": "6+4n, n=2",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48042,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 13,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48043,
"address_region": "program_or_external",
"bytes": "15F9C30406",
"text": "CMP:G.B #H'06, @H'F9C3",
"mnemonic": "CMP:G.B",
"operands": "#H'06, @H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48048,
"address_region": "program_or_external",
"bytes": "3602BC",
"text": "BNE loc_BE6F",
"mnemonic": "BNE",
"operands": "loc_BE6F",
"kind": "branch",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48051,
"address_region": "program_or_external",
"bytes": "1DF86880",
"text": "MOV:G.W @H'F868, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F868, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63592,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48055,
"address_region": "program_or_external",
"bytes": "1DF86090",
"text": "MOV:G.W R0, @H'F860",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F860",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63584,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48059,
"address_region": "program_or_external",
"bytes": "1DF86A80",
"text": "MOV:G.W @H'F86A, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F86A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63594,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48063,
"address_region": "program_or_external",
"bytes": "1DF86290",
"text": "MOV:G.W R0, @H'F862",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F862",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63586,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48067,
"address_region": "program_or_external",
"bytes": "1DF86C80",
"text": "MOV:G.W @H'F86C, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F86C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63596,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48071,
"address_region": "program_or_external",
"bytes": "1DF86490",
"text": "MOV:G.W R0, @H'F864",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F864",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48075,
"address_region": "program_or_external",
"bytes": "15F9C313",
"text": "CLR.B @H'F9C3",
"mnemonic": "CLR.B",
"operands": "@H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48079,
"address_region": "program_or_external",
"bytes": "15FAA4F7",
"text": "BTST.B #7, @H'FAA4",
"mnemonic": "BTST.B",
"operands": "#7, @H'FAA4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64164,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48083,
"address_region": "program_or_external",
"bytes": "360253",
"text": "BNE loc_BE29",
"mnemonic": "BNE",
"operands": "loc_BE29",
"kind": "branch",
"targets": [
48681
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48086,
"address_region": "program_or_external",
"bytes": "505A",
"text": "MOV:E.B #H'5A, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'5A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48088,
"address_region": "program_or_external",
"bytes": "15F86060",
"text": "XOR.B @H'F860, R0",
"mnemonic": "XOR.B",
"operands": "@H'F860, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63584,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48092,
"address_region": "program_or_external",
"bytes": "15F86160",
"text": "XOR.B @H'F861, R0",
"mnemonic": "XOR.B",
"operands": "@H'F861, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48096,
"address_region": "program_or_external",
"bytes": "15F86260",
"text": "XOR.B @H'F862, R0",
"mnemonic": "XOR.B",
"operands": "@H'F862, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63586,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48100,
"address_region": "program_or_external",
"bytes": "15F86360",
"text": "XOR.B @H'F863, R0",
"mnemonic": "XOR.B",
"operands": "@H'F863, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63587,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48104,
"address_region": "program_or_external",
"bytes": "15F86460",
"text": "XOR.B @H'F864, R0",
"mnemonic": "XOR.B",
"operands": "@H'F864, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48108,
"address_region": "program_or_external",
"bytes": "15F86570",
"text": "CMP:G.B @H'F865, R0",
"mnemonic": "CMP:G.B",
"operands": "@H'F865, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63589,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48112,
"address_region": "program_or_external",
"bytes": "360236",
"text": "BNE loc_BE29",
"mnemonic": "BNE",
"operands": "loc_BE29",
"kind": "branch",
"targets": [
48681
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48115,
"address_region": "program_or_external",
"bytes": "15FAA613",
"text": "CLR.B @H'FAA6",
"mnemonic": "CLR.B",
"operands": "@H'FAA6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64166,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48119,
"address_region": "program_or_external",
"bytes": "15F86185",
"text": "MOV:G.B @H'F861, R5",
"mnemonic": "MOV:G.B",
"operands": "@H'F861, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48123,
"address_region": "program_or_external",
"bytes": "A510",
"text": "SWAP.B R5",
"mnemonic": "SWAP.B",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48125,
"address_region": "program_or_external",
"bytes": "15F86285",
"text": "MOV:G.B @H'F862, R5",
"mnemonic": "MOV:G.B",
"operands": "@H'F862, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63586,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48129,
"address_region": "program_or_external",
"bytes": "1EA627",
"text": "BSR loc_622B",
"mnemonic": "BSR",
"operands": "loc_622B",
"kind": "call",
"targets": [
25131
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48132,
"address_region": "program_or_external",
"bytes": "AD84",
"text": "MOV:G.W R5, R4",
"mnemonic": "MOV:G.W",
"operands": "R5, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48134,
"address_region": "program_or_external",
"bytes": "AC1A",
"text": "SHLL.W R4",
"mnemonic": "SHLL.W",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48136,
"address_region": "program_or_external",
"bytes": "15F86080",
"text": "MOV:G.B @H'F860, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F860, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63584,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48140,
"address_region": "program_or_external",
"bytes": "040750",
"text": "AND.B #H'07, R0",
"mnemonic": "AND.B",
"operands": "#H'07, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48143,
"address_region": "program_or_external",
"bytes": "15FAA216",
"text": "TST.B @H'FAA2",
"mnemonic": "TST.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48147,
"address_region": "program_or_external",
"bytes": "2625",
"text": "BNE loc_BC3A",
"mnemonic": "BNE",
"operands": "loc_BC3A",
"kind": "branch",
"targets": [
48186
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48149,
"address_region": "program_or_external",
"bytes": "15FAA2C7",
"text": "BSET.B #7, @H'FAA2",
"mnemonic": "BSET.B",
"operands": "#7, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48153,
"address_region": "program_or_external",
"bytes": "15F861F7",
"text": "BTST.B #7, @H'F861",
"mnemonic": "BTST.B",
"operands": "#7, @H'F861",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48157,
"address_region": "program_or_external",
"bytes": "3600EB",
"text": "BNE loc_BD0B",
"mnemonic": "BNE",
"operands": "loc_BD0B",
"kind": "branch",
"targets": [
48395
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48160,
"address_region": "program_or_external",
"bytes": "4000",
"text": "CMP:E #H'00, R0",
"mnemonic": "CMP:E",
"operands": "#H'00, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48162,
"address_region": "program_or_external",
"bytes": "2745",
"text": "BEQ loc_BC69",
"mnemonic": "BEQ",
"operands": "loc_BC69",
"kind": "branch",
"targets": [
48233
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48164,
"address_region": "program_or_external",
"bytes": "4001",
"text": "CMP:E #H'01, R0",
"mnemonic": "CMP:E",
"operands": "#H'01, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48166,
"address_region": "program_or_external",
"bytes": "3700AE",
"text": "BEQ loc_BCD7",
"mnemonic": "BEQ",
"operands": "loc_BCD7",
"kind": "branch",
"targets": [
48343
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48169,
"address_region": "program_or_external",
"bytes": "4002",
"text": "CMP:E #H'02, R0",
"mnemonic": "CMP:E",
"operands": "#H'02, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48171,
"address_region": "program_or_external",
"bytes": "3700D6",
"text": "BEQ loc_BD04",
"mnemonic": "BEQ",
"operands": "loc_BD04",
"kind": "branch",
"targets": [
48388
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48174,
"address_region": "program_or_external",
"bytes": "4007",
"text": "CMP:E #H'07, R0",
"mnemonic": "CMP:E",
"operands": "#H'07, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48176,
"address_region": "program_or_external",
"bytes": "3701D2",
"text": "BEQ loc_BE05",
"mnemonic": "BEQ",
"operands": "loc_BE05",
"kind": "branch",
"targets": [
48645
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48179,
"address_region": "program_or_external",
"bytes": "15FAA213",
"text": "CLR.B @H'FAA2",
"mnemonic": "CLR.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48183,
"address_region": "program_or_external",
"bytes": "300235",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48186,
"address_region": "program_or_external",
"bytes": "A0F2",
"text": "BTST.B #2, R0",
"mnemonic": "BTST.B",
"operands": "#2, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48188,
"address_region": "program_or_external",
"bytes": "271E",
"text": "BEQ loc_BC5C",
"mnemonic": "BEQ",
"operands": "loc_BC5C",
"kind": "branch",
"targets": [
48220
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48190,
"address_region": "program_or_external",
"bytes": "15F861F7",
"text": "BTST.B #7, @H'F861",
"mnemonic": "BTST.B",
"operands": "#7, @H'F861",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48194,
"address_region": "program_or_external",
"bytes": "3601E2",
"text": "BNE loc_BE27",
"mnemonic": "BNE",
"operands": "loc_BE27",
"kind": "branch",
"targets": [
48679
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48197,
"address_region": "program_or_external",
"bytes": "4004",
"text": "CMP:E #H'04, R0",
"mnemonic": "CMP:E",
"operands": "#H'04, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48199,
"address_region": "program_or_external",
"bytes": "3700C4",
"text": "BEQ loc_BD0E",
"mnemonic": "BEQ",
"operands": "loc_BD0E",
"kind": "branch",
"targets": [
48398
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48202,
"address_region": "program_or_external",
"bytes": "4005",
"text": "CMP:E #H'05, R0",
"mnemonic": "CMP:E",
"operands": "#H'05, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48204,
"address_region": "program_or_external",
"bytes": "370131",
"text": "BEQ loc_BD80",
"mnemonic": "BEQ",
"operands": "loc_BD80",
"kind": "branch",
"targets": [
48512
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48207,
"address_region": "program_or_external",
"bytes": "4006",
"text": "CMP:E #H'06, R0",
"mnemonic": "CMP:E",
"operands": "#H'06, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48209,
"address_region": "program_or_external",
"bytes": "370187",
"text": "BEQ loc_BDDB",
"mnemonic": "BEQ",
"operands": "loc_BDDB",
"kind": "branch",
"targets": [
48603
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48212,
"address_region": "program_or_external",
"bytes": "4007",
"text": "CMP:E #H'07, R0",
"mnemonic": "CMP:E",
"operands": "#H'07, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48214,
"address_region": "program_or_external",
"bytes": "3701AC",
"text": "BEQ loc_BE05",
"mnemonic": "BEQ",
"operands": "loc_BE05",
"kind": "branch",
"targets": [
48645
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48217,
"address_region": "program_or_external",
"bytes": "300213",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48220,
"address_region": "program_or_external",
"bytes": "15FAA2D3",
"text": "BCLR.B #3, @H'FAA2",
"mnemonic": "BCLR.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48224,
"address_region": "program_or_external",
"bytes": "37020C",
"text": "BEQ loc_BE6F",
"mnemonic": "BEQ",
"operands": "loc_BE6F",
"kind": "branch",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48227,
"address_region": "program_or_external",
"bytes": "15FAA313",
"text": "CLR.B @H'FAA3",
"mnemonic": "CLR.B",
"operands": "@H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48231,
"address_region": "program_or_external",
"bytes": "20AC",
"text": "BRA loc_BC15",
"mnemonic": "BRA",
"operands": "loc_BC15",
"kind": "jump",
"targets": [
48149
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48233,
"address_region": "program_or_external",
"bytes": "AD16",
"text": "TST.W R5",
"mnemonic": "TST.W",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48235,
"address_region": "program_or_external",
"bytes": "261E",
"text": "BNE loc_BC8B",
"mnemonic": "BNE",
"operands": "loc_BC8B",
"kind": "branch",
"targets": [
48267
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48237,
"address_region": "program_or_external",
"bytes": "15F86380",
"text": "MOV:G.B @H'F863, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F863, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63587,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48241,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48243,
"address_region": "program_or_external",
"bytes": "5080",
"text": "MOV:E.B #H'80, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48245,
"address_region": "program_or_external",
"bytes": "FCE00090",
"text": "MOV:G.W R0, @(-H'2000,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'2000,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48249,
"address_region": "program_or_external",
"bytes": "FCE80090",
"text": "MOV:G.W R0, @(-H'1800,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'1800,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48253,
"address_region": "program_or_external",
"bytes": "15F8640680",
"text": "MOV:G.B #H'80, @H'F864",
"mnemonic": "MOV:G.B",
"operands": "#H'80, @H'F864",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48258,
"address_region": "program_or_external",
"bytes": "F5EC00C7",
"text": "BSET.B #7, @(-H'1400,R5)",
"mnemonic": "BSET.B",
"operands": "#7, @(-H'1400,R5)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48262,
"address_region": "program_or_external",
"bytes": "1E01E7",
"text": "BSR loc_BE70",
"mnemonic": "BSR",
"operands": "loc_BE70",
"kind": "call",
"targets": [
48752
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48265,
"address_region": "program_or_external",
"bytes": "2025",
"text": "BRA loc_BCB0",
"mnemonic": "BRA",
"operands": "loc_BCB0",
"kind": "jump",
"targets": [
48304
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48267,
"address_region": "program_or_external",
"bytes": "15F86380",
"text": "MOV:G.B @H'F863, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F863, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63587,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48271,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48273,
"address_region": "program_or_external",
"bytes": "15F86480",
"text": "MOV:G.B @H'F864, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F864, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48277,
"address_region": "program_or_external",
"bytes": "FCE00090",
"text": "MOV:G.W R0, @(-H'2000,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'2000,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48281,
"address_region": "program_or_external",
"bytes": "FCE80090",
"text": "MOV:G.W R0, @(-H'1800,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'1800,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48285,
"address_region": "program_or_external",
"bytes": "F5EC00C7",
"text": "BSET.B #7, @(-H'1400,R5)",
"mnemonic": "BSET.B",
"operands": "#7, @(-H'1400,R5)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48289,
"address_region": "program_or_external",
"bytes": "FCC56481",
"text": "MOV:G.W @(-H'3A9C,R4), R1",
"mnemonic": "MOV:G.W",
"operands": "@(-H'3A9C,R4), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48293,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48295,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_BCAD",
"mnemonic": "BEQ",
"operands": "loc_BCAD",
"kind": "branch",
"targets": [
48301
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48297,
"address_region": "program_or_external",
"bytes": "F9F40090",
"text": "MOV:G.W R0, @(-H'0C00,R1)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'0C00,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48301,
"address_region": "program_or_external",
"bytes": "1E01C0",
"text": "BSR loc_BE70",
"mnemonic": "BSR",
"operands": "loc_BE70",
"kind": "call",
"targets": [
48752
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48304,
"address_region": "program_or_external",
"bytes": "15F8500604",
"text": "MOV:G.B #H'04, @H'F850",
"mnemonic": "MOV:G.B",
"operands": "#H'04, @H'F850",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63568,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48309,
"address_region": "program_or_external",
"bytes": "15F86180",
"text": "MOV:G.B @H'F861, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F861, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48313,
"address_region": "program_or_external",
"bytes": "15F85190",
"text": "MOV:G.B R0, @H'F851",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F851",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63569,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48317,
"address_region": "program_or_external",
"bytes": "1DF86280",
"text": "MOV:G.W @H'F862, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F862, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63586,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48321,
"address_region": "program_or_external",
"bytes": "1DF85290",
"text": "MOV:G.W R0, @H'F852",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F852",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63570,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48325,
"address_region": "program_or_external",
"bytes": "15F86480",
"text": "MOV:G.B @H'F864, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F864, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48329,
"address_region": "program_or_external",
"bytes": "15F85490",
"text": "MOV:G.B R0, @H'F854",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F854",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63572,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48333,
"address_region": "program_or_external",
"bytes": "1EFD56",
"text": "BSR loc_BA26",
"mnemonic": "BSR",
"operands": "loc_BA26",
"kind": "call",
"targets": [
47654
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48336,
"address_region": "program_or_external",
"bytes": "15FAA2D7",
"text": "BCLR.B #7, @H'FAA2",
"mnemonic": "BCLR.B",
"operands": "#7, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48340,
"address_region": "program_or_external",
"bytes": "300198",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48343,
"address_region": "program_or_external",
"bytes": "15F8500604",
"text": "MOV:G.B #H'04, @H'F850",
"mnemonic": "MOV:G.B",
"operands": "#H'04, @H'F850",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63568,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48348,
"address_region": "program_or_external",
"bytes": "15F86180",
"text": "MOV:G.B @H'F861, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F861, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48352,
"address_region": "program_or_external",
"bytes": "15F85190",
"text": "MOV:G.B R0, @H'F851",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F851",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63569,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48356,
"address_region": "program_or_external",
"bytes": "15F86280",
"text": "MOV:G.B @H'F862, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F862, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63586,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48360,
"address_region": "program_or_external",
"bytes": "15F85190",
"text": "MOV:G.B R0, @H'F851",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F851",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63569,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48364,
"address_region": "program_or_external",
"bytes": "FCE00080",
"text": "MOV:G.W @(-H'2000,R4), R0",
"mnemonic": "MOV:G.W",
"operands": "@(-H'2000,R4), R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48368,
"address_region": "program_or_external",
"bytes": "15F85490",
"text": "MOV:G.B R0, @H'F854",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F854",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63572,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48372,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48374,
"address_region": "program_or_external",
"bytes": "15F85390",
"text": "MOV:G.B R0, @H'F853",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F853",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63571,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48378,
"address_region": "program_or_external",
"bytes": "1EFD29",
"text": "BSR loc_BA26",
"mnemonic": "BSR",
"operands": "loc_BA26",
"kind": "call",
"targets": [
47654
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48381,
"address_region": "program_or_external",
"bytes": "15FAA2D7",
"text": "BCLR.B #7, @H'FAA2",
"mnemonic": "BCLR.B",
"operands": "#7, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48385,
"address_region": "program_or_external",
"bytes": "30016B",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48388,
"address_region": "program_or_external",
"bytes": "15FAA2D7",
"text": "BCLR.B #7, @H'FAA2",
"mnemonic": "BCLR.B",
"operands": "#7, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48392,
"address_region": "program_or_external",
"bytes": "300164",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48395,
"address_region": "program_or_external",
"bytes": "300161",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48398,
"address_region": "program_or_external",
"bytes": "AD16",
"text": "TST.W R5",
"mnemonic": "TST.W",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48400,
"address_region": "program_or_external",
"bytes": "2619",
"text": "BNE loc_BD2B",
"mnemonic": "BNE",
"operands": "loc_BD2B",
"kind": "branch",
"targets": [
48427
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48402,
"address_region": "program_or_external",
"bytes": "15F86380",
"text": "MOV:G.B @H'F863, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F863, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63587,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48406,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48408,
"address_region": "program_or_external",
"bytes": "5080",
"text": "MOV:E.B #H'80, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'80, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48410,
"address_region": "program_or_external",
"bytes": "FCE00090",
"text": "MOV:G.W R0, @(-H'2000,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'2000,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48414,
"address_region": "program_or_external",
"bytes": "FCE80090",
"text": "MOV:G.W R0, @(-H'1800,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'1800,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48418,
"address_region": "program_or_external",
"bytes": "F5EC00C7",
"text": "BSET.B #7, @(-H'1400,R5)",
"mnemonic": "BSET.B",
"operands": "#7, @(-H'1400,R5)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48422,
"address_region": "program_or_external",
"bytes": "1E0147",
"text": "BSR loc_BE70",
"mnemonic": "BSR",
"operands": "loc_BE70",
"kind": "call",
"targets": [
48752
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48425,
"address_region": "program_or_external",
"bytes": "203C",
"text": "BRA loc_BD67",
"mnemonic": "BRA",
"operands": "loc_BD67",
"kind": "jump",
"targets": [
48487
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48427,
"address_region": "program_or_external",
"bytes": "15F86380",
"text": "MOV:G.B @H'F863, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F863, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63587,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48431,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48433,
"address_region": "program_or_external",
"bytes": "15F86480",
"text": "MOV:G.B @H'F864, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F864, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48437,
"address_region": "program_or_external",
"bytes": "FCE00090",
"text": "MOV:G.W R0, @(-H'2000,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'2000,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48441,
"address_region": "program_or_external",
"bytes": "F5EC00C7",
"text": "BSET.B #7, @(-H'1400,R5)",
"mnemonic": "BSET.B",
"operands": "#7, @(-H'1400,R5)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48445,
"address_region": "program_or_external",
"bytes": "F4C56581",
"text": "MOV:G.B @(-H'3A9B,R4), R1",
"mnemonic": "MOV:G.B",
"operands": "@(-H'3A9B,R4), R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48449,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48451,
"address_region": "program_or_external",
"bytes": "271F",
"text": "BEQ loc_BD64",
"mnemonic": "BEQ",
"operands": "loc_BD64",
"kind": "branch",
"targets": [
48484
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48453,
"address_region": "program_or_external",
"bytes": "F9F40090",
"text": "MOV:G.W R0, @(-H'0C00,R1)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'0C00,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48457,
"address_region": "program_or_external",
"bytes": "15F76EF7",
"text": "BTST.B #7, @H'F76E",
"mnemonic": "BTST.B",
"operands": "#7, @H'F76E",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63342,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48461,
"address_region": "program_or_external",
"bytes": "2715",
"text": "BEQ loc_BD64",
"mnemonic": "BEQ",
"operands": "loc_BD64",
"kind": "branch",
"targets": [
48484
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48463,
"address_region": "program_or_external",
"bytes": "1231",
"text": "STM.W {R0,R4,R5}, @-SP",
"mnemonic": "STM.W",
"operands": "{R0,R4,R5}, @-SP",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 15,
"note": "6+3n, n=3",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48465,
"address_region": "program_or_external",
"bytes": "15F76E84",
"text": "MOV:G.B @H'F76E, R4",
"mnemonic": "MOV:G.B",
"operands": "@H'F76E, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63342,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48469,
"address_region": "program_or_external",
"bytes": "A410",
"text": "SWAP.B R4",
"mnemonic": "SWAP.B",
"operands": "R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48471,
"address_region": "program_or_external",
"bytes": "A184",
"text": "MOV:G.B R1, R4",
"mnemonic": "MOV:G.B",
"operands": "R1, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48473,
"address_region": "program_or_external",
"bytes": "0C0FFE54",
"text": "AND.W #H'0FFE, R4",
"mnemonic": "AND.W",
"operands": "#H'0FFE, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48477,
"address_region": "program_or_external",
"bytes": "A885",
"text": "MOV:G.W R0, R5",
"mnemonic": "MOV:G.W",
"operands": "R0, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48479,
"address_region": "program_or_external",
"bytes": "1E027E",
"text": "BSR loc_BFE0",
"mnemonic": "BSR",
"operands": "loc_BFE0",
"kind": "call",
"targets": [
49120
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48482,
"address_region": "program_or_external",
"bytes": "0231",
"text": "LDM.W @SP+, {R0,R4,R5}",
"mnemonic": "LDM.W",
"operands": "@SP+, {R0,R4,R5}",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 18,
"note": "6+4n, n=3",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48484,
"address_region": "program_or_external",
"bytes": "1E0109",
"text": "BSR loc_BE70",
"mnemonic": "BSR",
"operands": "loc_BE70",
"kind": "call",
"targets": [
48752
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48487,
"address_region": "program_or_external",
"bytes": "15FAA2F3",
"text": "BTST.B #3, @H'FAA2",
"mnemonic": "BTST.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48491,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_BD75",
"mnemonic": "BEQ",
"operands": "loc_BD75",
"kind": "branch",
"targets": [
48501
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48493,
"address_region": "program_or_external",
"bytes": "15F9B508",
"text": "ADD:Q.B #1, @H'F9B5",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48497,
"address_region": "program_or_external",
"bytes": "15F9B5D7",
"text": "BCLR.B #7, @H'F9B5",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F9B5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48501,
"address_region": "program_or_external",
"bytes": "15FAA313",
"text": "CLR.B @H'FAA3",
"mnemonic": "CLR.B",
"operands": "@H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48505,
"address_region": "program_or_external",
"bytes": "15FAA213",
"text": "CLR.B @H'FAA2",
"mnemonic": "CLR.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48509,
"address_region": "program_or_external",
"bytes": "3000EF",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48512,
"address_region": "program_or_external",
"bytes": "4D006C",
"text": "CMP:I #H'006C, R5",
"mnemonic": "CMP:I",
"operands": "#H'006C, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48515,
"address_region": "program_or_external",
"bytes": "273A",
"text": "BEQ loc_BDBF",
"mnemonic": "BEQ",
"operands": "loc_BDBF",
"kind": "branch",
"targets": [
48575
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48517,
"address_region": "program_or_external",
"bytes": "4D006D",
"text": "CMP:I #H'006D, R5",
"mnemonic": "CMP:I",
"operands": "#H'006D, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48520,
"address_region": "program_or_external",
"bytes": "2735",
"text": "BEQ loc_BDBF",
"mnemonic": "BEQ",
"operands": "loc_BDBF",
"kind": "branch",
"targets": [
48575
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48522,
"address_region": "program_or_external",
"bytes": "4D006E",
"text": "CMP:I #H'006E, R5",
"mnemonic": "CMP:I",
"operands": "#H'006E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48525,
"address_region": "program_or_external",
"bytes": "2730",
"text": "BEQ loc_BDBF",
"mnemonic": "BEQ",
"operands": "loc_BDBF",
"kind": "branch",
"targets": [
48575
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48527,
"address_region": "program_or_external",
"bytes": "4D006E",
"text": "CMP:I #H'006E, R5",
"mnemonic": "CMP:I",
"operands": "#H'006E, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48530,
"address_region": "program_or_external",
"bytes": "272B",
"text": "BEQ loc_BDBF",
"mnemonic": "BEQ",
"operands": "loc_BDBF",
"kind": "branch",
"targets": [
48575
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48532,
"address_region": "program_or_external",
"bytes": "15F731F7",
"text": "BTST.B #7, @H'F731",
"mnemonic": "BTST.B",
"operands": "#7, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48536,
"address_region": "program_or_external",
"bytes": "2728",
"text": "BEQ loc_BDC2",
"mnemonic": "BEQ",
"operands": "loc_BDC2",
"kind": "branch",
"targets": [
48578
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48538,
"address_region": "program_or_external",
"bytes": "4D006B",
"text": "CMP:I #H'006B, R5",
"mnemonic": "CMP:I",
"operands": "#H'006B, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48541,
"address_region": "program_or_external",
"bytes": "2716",
"text": "BEQ loc_BDB5",
"mnemonic": "BEQ",
"operands": "loc_BDB5",
"kind": "branch",
"targets": [
48565
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48543,
"address_region": "program_or_external",
"bytes": "4D0096",
"text": "CMP:I #H'0096, R5",
"mnemonic": "CMP:I",
"operands": "#H'0096, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48546,
"address_region": "program_or_external",
"bytes": "2711",
"text": "BEQ loc_BDB5",
"mnemonic": "BEQ",
"operands": "loc_BDB5",
"kind": "branch",
"targets": [
48565
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48548,
"address_region": "program_or_external",
"bytes": "4D0097",
"text": "CMP:I #H'0097, R5",
"mnemonic": "CMP:I",
"operands": "#H'0097, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48551,
"address_region": "program_or_external",
"bytes": "270C",
"text": "BEQ loc_BDB5",
"mnemonic": "BEQ",
"operands": "loc_BDB5",
"kind": "branch",
"targets": [
48565
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48553,
"address_region": "program_or_external",
"bytes": "4D00C6",
"text": "CMP:I #H'00C6, R5",
"mnemonic": "CMP:I",
"operands": "#H'00C6, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48556,
"address_region": "program_or_external",
"bytes": "2707",
"text": "BEQ loc_BDB5",
"mnemonic": "BEQ",
"operands": "loc_BDB5",
"kind": "branch",
"targets": [
48565
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48558,
"address_region": "program_or_external",
"bytes": "4D00F8",
"text": "CMP:I #H'00F8, R5",
"mnemonic": "CMP:I",
"operands": "#H'00F8, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48561,
"address_region": "program_or_external",
"bytes": "2702",
"text": "BEQ loc_BDB5",
"mnemonic": "BEQ",
"operands": "loc_BDB5",
"kind": "branch",
"targets": [
48565
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48563,
"address_region": "program_or_external",
"bytes": "200D",
"text": "BRA loc_BDC2",
"mnemonic": "BRA",
"operands": "loc_BDC2",
"kind": "jump",
"targets": [
48578
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48565,
"address_region": "program_or_external",
"bytes": "15F731D7",
"text": "BCLR.B #7, @H'F731",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48569,
"address_region": "program_or_external",
"bytes": "15F790D7",
"text": "BCLR.B #7, @H'F790",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F790",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63376,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48573,
"address_region": "program_or_external",
"bytes": "2003",
"text": "BRA loc_BDC2",
"mnemonic": "BRA",
"operands": "loc_BDC2",
"kind": "jump",
"targets": [
48578
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48575,
"address_region": "program_or_external",
"bytes": "1E00AE",
"text": "BSR loc_BE70",
"mnemonic": "BSR",
"operands": "loc_BE70",
"kind": "call",
"targets": [
48752
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48578,
"address_region": "program_or_external",
"bytes": "15FAA2F3",
"text": "BTST.B #3, @H'FAA2",
"mnemonic": "BTST.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48582,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_BDD0",
"mnemonic": "BEQ",
"operands": "loc_BDD0",
"kind": "branch",
"targets": [
48592
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48584,
"address_region": "program_or_external",
"bytes": "15F9B508",
"text": "ADD:Q.B #1, @H'F9B5",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48588,
"address_region": "program_or_external",
"bytes": "15F9B5D7",
"text": "BCLR.B #7, @H'F9B5",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F9B5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48592,
"address_region": "program_or_external",
"bytes": "15FAA313",
"text": "CLR.B @H'FAA3",
"mnemonic": "CLR.B",
"operands": "@H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48596,
"address_region": "program_or_external",
"bytes": "15FAA213",
"text": "CLR.B @H'FAA2",
"mnemonic": "CLR.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48600,
"address_region": "program_or_external",
"bytes": "300094",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48603,
"address_region": "program_or_external",
"bytes": "15F86380",
"text": "MOV:G.B @H'F863, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F863, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63587,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48607,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48609,
"address_region": "program_or_external",
"bytes": "15F86480",
"text": "MOV:G.B @H'F864, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F864, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48613,
"address_region": "program_or_external",
"bytes": "FCE40090",
"text": "MOV:G.W R0, @(-H'1C00,R4)",
"mnemonic": "MOV:G.W",
"operands": "R0, @(-H'1C00,R4)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48617,
"address_region": "program_or_external",
"bytes": "F5EC00C6",
"text": "BSET.B #6, @(-H'1400,R5)",
"mnemonic": "BSET.B",
"operands": "#6, @(-H'1400,R5)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48621,
"address_region": "program_or_external",
"bytes": "15FAA2F3",
"text": "BTST.B #3, @H'FAA2",
"mnemonic": "BTST.B",
"operands": "#3, @H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48625,
"address_region": "program_or_external",
"bytes": "2708",
"text": "BEQ loc_BDFB",
"mnemonic": "BEQ",
"operands": "loc_BDFB",
"kind": "branch",
"targets": [
48635
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48627,
"address_region": "program_or_external",
"bytes": "15F9B508",
"text": "ADD:Q.B #1, @H'F9B5",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48631,
"address_region": "program_or_external",
"bytes": "15F9B5D7",
"text": "BCLR.B #7, @H'F9B5",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F9B5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63925,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48635,
"address_region": "program_or_external",
"bytes": "15FAA313",
"text": "CLR.B @H'FAA3",
"mnemonic": "CLR.B",
"operands": "@H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48639,
"address_region": "program_or_external",
"bytes": "15FAA213",
"text": "CLR.B @H'FAA2",
"mnemonic": "CLR.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48643,
"address_region": "program_or_external",
"bytes": "206A",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48645,
"address_region": "program_or_external",
"bytes": "1DF85880",
"text": "MOV:G.W @H'F858, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F858, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63576,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48649,
"address_region": "program_or_external",
"bytes": "1DF85090",
"text": "MOV:G.W R0, @H'F850",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F850",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63568,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48653,
"address_region": "program_or_external",
"bytes": "1DF85A80",
"text": "MOV:G.W @H'F85A, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F85A, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63578,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48657,
"address_region": "program_or_external",
"bytes": "1DF85290",
"text": "MOV:G.W R0, @H'F852",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F852",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63570,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48661,
"address_region": "program_or_external",
"bytes": "1DF85C80",
"text": "MOV:G.W @H'F85C, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F85C, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63580,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48665,
"address_region": "program_or_external",
"bytes": "1DF85490",
"text": "MOV:G.W R0, @H'F854",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F854",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63572,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48669,
"address_region": "program_or_external",
"bytes": "15F9C0061F",
"text": "MOV:G.B #H'1F, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'1F, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48674,
"address_region": "program_or_external",
"bytes": "1EFC01",
"text": "BSR loc_BA26",
"mnemonic": "BSR",
"operands": "loc_BA26",
"kind": "call",
"targets": [
47654
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48677,
"address_region": "program_or_external",
"bytes": "2048",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48679,
"address_region": "program_or_external",
"bytes": "2046",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48681,
"address_region": "program_or_external",
"bytes": "15FAA4D7",
"text": "BCLR.B #7, @H'FAA4",
"mnemonic": "BCLR.B",
"operands": "#7, @H'FAA4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64164,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48685,
"address_region": "program_or_external",
"bytes": "15FAA5F7",
"text": "BTST.B #7, @H'FAA5",
"mnemonic": "BTST.B",
"operands": "#7, @H'FAA5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64165,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48689,
"address_region": "program_or_external",
"bytes": "273A",
"text": "BEQ loc_BE6D",
"mnemonic": "BEQ",
"operands": "loc_BE6D",
"kind": "branch",
"targets": [
48749
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48691,
"address_region": "program_or_external",
"bytes": "15FAA608",
"text": "ADD:Q.B #1, @H'FAA6",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'FAA6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64166,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48695,
"address_region": "program_or_external",
"bytes": "15FAA60402",
"text": "CMP:G.B #H'02, @H'FAA6",
"mnemonic": "CMP:G.B",
"operands": "#H'02, @H'FAA6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64166,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48700,
"address_region": "program_or_external",
"bytes": "250F",
"text": "BCS loc_BE4D",
"mnemonic": "BCS",
"operands": "loc_BE4D",
"kind": "branch",
"targets": [
48717
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48702,
"address_region": "program_or_external",
"bytes": "15F9C0061F",
"text": "MOV:G.B #H'1F, @H'F9C0",
"mnemonic": "MOV:G.B",
"operands": "#H'1F, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48707,
"address_region": "program_or_external",
"bytes": "15FAA313",
"text": "CLR.B @H'FAA3",
"mnemonic": "CLR.B",
"operands": "@H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48711,
"address_region": "program_or_external",
"bytes": "15FAA213",
"text": "CLR.B @H'FAA2",
"mnemonic": "CLR.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48715,
"address_region": "program_or_external",
"bytes": "2020",
"text": "BRA loc_BE6D",
"mnemonic": "BRA",
"operands": "loc_BE6D",
"kind": "jump",
"targets": [
48749
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48717,
"address_region": "program_or_external",
"bytes": "15F8500607",
"text": "MOV:G.B #H'07, @H'F850",
"mnemonic": "MOV:G.B",
"operands": "#H'07, @H'F850",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63568,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48722,
"address_region": "program_or_external",
"bytes": "15F86180",
"text": "MOV:G.B @H'F861, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F861, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63585,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48726,
"address_region": "program_or_external",
"bytes": "15F85190",
"text": "MOV:G.B R0, @H'F851",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F851",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63569,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48730,
"address_region": "program_or_external",
"bytes": "1DF86280",
"text": "MOV:G.W @H'F862, R0",
"mnemonic": "MOV:G.W",
"operands": "@H'F862, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63586,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48734,
"address_region": "program_or_external",
"bytes": "1DF85290",
"text": "MOV:G.W R0, @H'F852",
"mnemonic": "MOV:G.W",
"operands": "R0, @H'F852",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63570,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48738,
"address_region": "program_or_external",
"bytes": "15F86480",
"text": "MOV:G.B @H'F864, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'F864, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63588,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48742,
"address_region": "program_or_external",
"bytes": "15F85490",
"text": "MOV:G.B R0, @H'F854",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'F854",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63572,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48746,
"address_region": "program_or_external",
"bytes": "1EFBB9",
"text": "BSR loc_BA26",
"mnemonic": "BSR",
"operands": "loc_BA26",
"kind": "call",
"targets": [
47654
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48749,
"address_region": "program_or_external",
"bytes": "2000",
"text": "BRA loc_BE6F",
"mnemonic": "BRA",
"operands": "loc_BE6F",
"kind": "jump",
"targets": [
48751
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48751,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48752,
"address_region": "program_or_external",
"bytes": "15F9B983",
"text": "MOV:G.B @H'F9B9, R3",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B9, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63929,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48756,
"address_region": "program_or_external",
"bytes": "A312",
"text": "EXTU.B R3",
"mnemonic": "EXTU.B",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48758,
"address_region": "program_or_external",
"bytes": "AB1A",
"text": "SHLL.W R3",
"mnemonic": "SHLL.W",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48760,
"address_region": "program_or_external",
"bytes": "15F9B481",
"text": "MOV:G.B @H'F9B4, R1",
"mnemonic": "MOV:G.B",
"operands": "@H'F9B4, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48764,
"address_region": "program_or_external",
"bytes": "A112",
"text": "EXTU.B R1",
"mnemonic": "EXTU.B",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48766,
"address_region": "program_or_external",
"bytes": "A91A",
"text": "SHLL.W R1",
"mnemonic": "SHLL.W",
"operands": "R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48768,
"address_region": "program_or_external",
"bytes": "A371",
"text": "CMP:G.B R3, R1",
"mnemonic": "CMP:G.B",
"operands": "R3, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48770,
"address_region": "program_or_external",
"bytes": "270D",
"text": "BEQ loc_BE91",
"mnemonic": "BEQ",
"operands": "loc_BE91",
"kind": "branch",
"targets": [
48785
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48772,
"address_region": "program_or_external",
"bytes": "FBF97075",
"text": "CMP:G.W @(-H'0690,R3), R5",
"mnemonic": "CMP:G.W",
"operands": "@(-H'0690,R3), R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48776,
"address_region": "program_or_external",
"bytes": "2713",
"text": "BEQ loc_BE9D",
"mnemonic": "BEQ",
"operands": "loc_BE9D",
"kind": "branch",
"targets": [
48797
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48778,
"address_region": "program_or_external",
"bytes": "A309",
"text": "ADD:Q.B #2, R3",
"mnemonic": "ADD:Q.B",
"operands": "#2, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48780,
"address_region": "program_or_external",
"bytes": "043F53",
"text": "AND.B #H'3F, R3",
"mnemonic": "AND.B",
"operands": "#H'3F, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48783,
"address_region": "program_or_external",
"bytes": "20EF",
"text": "BRA loc_BE80",
"mnemonic": "BRA",
"operands": "loc_BE80",
"kind": "jump",
"targets": [
48768
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48785,
"address_region": "program_or_external",
"bytes": "F9F97095",
"text": "MOV:G.W R5, @(-H'0690,R1)",
"mnemonic": "MOV:G.W",
"operands": "R5, @(-H'0690,R1)",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48789,
"address_region": "program_or_external",
"bytes": "15F9B408",
"text": "ADD:Q.B #1, @H'F9B4",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F9B4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48793,
"address_region": "program_or_external",
"bytes": "15F9B4D5",
"text": "BCLR.B #5, @H'F9B4",
"mnemonic": "BCLR.B",
"operands": "#5, @H'F9B4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63924,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48797,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48798,
"address_region": "program_or_external",
"bytes": "15FAA580",
"text": "MOV:G.B @H'FAA5, R0",
"mnemonic": "MOV:G.B",
"operands": "@H'FAA5, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64165,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48802,
"address_region": "program_or_external",
"bytes": "048050",
"text": "AND.B #H'80, R0",
"mnemonic": "AND.B",
"operands": "#H'80, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48805,
"address_region": "program_or_external",
"bytes": "15FAA350",
"text": "AND.B @H'FAA3, R0",
"mnemonic": "AND.B",
"operands": "@H'FAA3, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48809,
"address_region": "program_or_external",
"bytes": "15FAA390",
"text": "MOV:G.B R0, @H'FAA3",
"mnemonic": "MOV:G.B",
"operands": "R0, @H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48813,
"address_region": "program_or_external",
"bytes": "2606",
"text": "BNE loc_BEB5",
"mnemonic": "BNE",
"operands": "loc_BEB5",
"kind": "branch",
"targets": [
48821
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48815,
"address_region": "program_or_external",
"bytes": "15FAA213",
"text": "CLR.B @H'FAA2",
"mnemonic": "CLR.B",
"operands": "@H'FAA2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64162,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48819,
"address_region": "program_or_external",
"bytes": "2033",
"text": "BRA loc_BEE8",
"mnemonic": "BRA",
"operands": "loc_BEE8",
"kind": "jump",
"targets": [
48872
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48821,
"address_region": "program_or_external",
"bytes": "1DF9C616",
"text": "TST.W @H'F9C6",
"mnemonic": "TST.W",
"operands": "@H'F9C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63942,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48825,
"address_region": "program_or_external",
"bytes": "262D",
"text": "BNE loc_BEE8",
"mnemonic": "BNE",
"operands": "loc_BEE8",
"kind": "branch",
"targets": [
48872
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48827,
"address_region": "program_or_external",
"bytes": "15F9C816",
"text": "TST.B @H'F9C8",
"mnemonic": "TST.B",
"operands": "@H'F9C8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63944,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48831,
"address_region": "program_or_external",
"bytes": "2723",
"text": "BEQ loc_BEE4",
"mnemonic": "BEQ",
"operands": "loc_BEE4",
"kind": "branch",
"targets": [
48868
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48833,
"address_region": "program_or_external",
"bytes": "15F9C80C",
"text": "ADD:Q.B #-1, @H'F9C8",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F9C8",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63944,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48837,
"address_region": "program_or_external",
"bytes": "1DF9C60701F4",
"text": "MOV:G.W #H'01F4, @H'F9C6",
"mnemonic": "MOV:G.W",
"operands": "#H'01F4, @H'F9C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63942,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48843,
"address_region": "program_or_external",
"bytes": "15FAA3F7",
"text": "BTST.B #7, @H'FAA3",
"mnemonic": "BTST.B",
"operands": "#7, @H'FAA3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 64163,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48847,
"address_region": "program_or_external",
"bytes": "2717",
"text": "BEQ loc_BEE8",
"mnemonic": "BEQ",
"operands": "loc_BEE8",
"kind": "branch",
"targets": [
48872
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48849,
"address_region": "program_or_external",
"bytes": "15F9C313",
"text": "CLR.B @H'F9C3",
"mnemonic": "CLR.B",
"operands": "@H'F9C3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63939,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48853,
"address_region": "program_or_external",
"bytes": "1EFB4E",
"text": "BSR loc_BA26",
"mnemonic": "BSR",
"operands": "loc_BA26",
"kind": "call",
"targets": [
47654
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48856,
"address_region": "program_or_external",
"bytes": "200E",
"text": "BRA loc_BEE8",
"mnemonic": "BRA",
"operands": "loc_BEE8",
"kind": "jump",
"targets": [
48872
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48868,
"address_region": "program_or_external",
"bytes": "15F9C513",
"text": "CLR.B @H'F9C5",
"mnemonic": "CLR.B",
"operands": "@H'F9C5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63941,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48872,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48874,
"address_region": "program_or_external",
"bytes": "15FE91D5",
"text": "BCLR.B #5, @FRT1_TCSR",
"mnemonic": "BCLR.B",
"operands": "#5, @FRT1_TCSR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65169,
"name": "FRT1_TCSR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear OCFA (bit 5) of FRT1_TCSR",
"valid": true
},
{
"address": 48878,
"address_region": "program_or_external",
"bytes": "15F9C016",
"text": "TST.B @H'F9C0",
"mnemonic": "TST.B",
"operands": "@H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48882,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_BEF8",
"mnemonic": "BEQ",
"operands": "loc_BEF8",
"kind": "branch",
"targets": [
48888
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48884,
"address_region": "program_or_external",
"bytes": "15F9C00C",
"text": "ADD:Q.B #-1, @H'F9C0",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F9C0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63936,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48888,
"address_region": "program_or_external",
"bytes": "15F9C116",
"text": "TST.B @H'F9C1",
"mnemonic": "TST.B",
"operands": "@H'F9C1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63937,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48892,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_BF02",
"mnemonic": "BEQ",
"operands": "loc_BF02",
"kind": "branch",
"targets": [
48898
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48894,
"address_region": "program_or_external",
"bytes": "15F9C10C",
"text": "ADD:Q.B #-1, @H'F9C1",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F9C1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63937,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48898,
"address_region": "program_or_external",
"bytes": "1DF9C616",
"text": "TST.W @H'F9C6",
"mnemonic": "TST.W",
"operands": "@H'F9C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63942,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 48902,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_BF0C",
"mnemonic": "BEQ",
"operands": "loc_BF0C",
"kind": "branch",
"targets": [
48908
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 48904,
"address_region": "program_or_external",
"bytes": "1DF9C60C",
"text": "ADD:Q.W #-1, @H'F9C6",
"mnemonic": "ADD:Q.W",
"operands": "#-1, @H'F9C6",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
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"address": 63942,
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{
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{
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"bytes": "15F8400C",
"text": "ADD:Q.B #-1, @H'F840",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49025,
"address_region": "program_or_external",
"bytes": "15F72616",
"text": "TST.B @H'F726",
"mnemonic": "TST.B",
"operands": "@H'F726",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63270,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49029,
"address_region": "program_or_external",
"bytes": "271C",
"text": "BEQ loc_BFA3",
"mnemonic": "BEQ",
"operands": "loc_BFA3",
"kind": "branch",
"targets": [
49059
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49031,
"address_region": "program_or_external",
"bytes": "15F7260C",
"text": "ADD:Q.B #-1, @H'F726",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F726",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63270,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49035,
"address_region": "program_or_external",
"bytes": "2616",
"text": "BNE loc_BFA3",
"mnemonic": "BNE",
"operands": "loc_BFA3",
"kind": "branch",
"targets": [
49059
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49037,
"address_region": "program_or_external",
"bytes": "15F713D6",
"text": "BCLR.B #6, @H'F713",
"mnemonic": "BCLR.B",
"operands": "#6, @H'F713",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63251,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49041,
"address_region": "program_or_external",
"bytes": "2610",
"text": "BNE loc_BFA3",
"mnemonic": "BNE",
"operands": "loc_BFA3",
"kind": "branch",
"targets": [
49059
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49043,
"address_region": "program_or_external",
"bytes": "15F711D7",
"text": "BCLR.B #7, @H'F711",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F711",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63249,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49047,
"address_region": "program_or_external",
"bytes": "15F711D6",
"text": "BCLR.B #6, @H'F711",
"mnemonic": "BCLR.B",
"operands": "#6, @H'F711",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63249,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49051,
"address_region": "program_or_external",
"bytes": "15F711D5",
"text": "BCLR.B #5, @H'F711",
"mnemonic": "BCLR.B",
"operands": "#5, @H'F711",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63249,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49055,
"address_region": "program_or_external",
"bytes": "15F711D4",
"text": "BCLR.B #4, @H'F711",
"mnemonic": "BCLR.B",
"operands": "#4, @H'F711",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63249,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49059,
"address_region": "program_or_external",
"bytes": "15F79716",
"text": "TST.B @H'F797",
"mnemonic": "TST.B",
"operands": "@H'F797",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63383,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49063,
"address_region": "program_or_external",
"bytes": "270A",
"text": "BEQ loc_BFB3",
"mnemonic": "BEQ",
"operands": "loc_BFB3",
"kind": "branch",
"targets": [
49075
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49065,
"address_region": "program_or_external",
"bytes": "15F7970C",
"text": "ADD:Q.B #-1, @H'F797",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F797",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63383,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49069,
"address_region": "program_or_external",
"bytes": "2604",
"text": "BNE loc_BFB3",
"mnemonic": "BNE",
"operands": "loc_BFB3",
"kind": "branch",
"targets": [
49075
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49071,
"address_region": "program_or_external",
"bytes": "15F731D7",
"text": "BCLR.B #7, @H'F731",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49075,
"address_region": "program_or_external",
"bytes": "15F79816",
"text": "TST.B @H'F798",
"mnemonic": "TST.B",
"operands": "@H'F798",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63384,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49079,
"address_region": "program_or_external",
"bytes": "270A",
"text": "BEQ loc_BFC3",
"mnemonic": "BEQ",
"operands": "loc_BFC3",
"kind": "branch",
"targets": [
49091
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49081,
"address_region": "program_or_external",
"bytes": "15F7980C",
"text": "ADD:Q.B #-1, @H'F798",
"mnemonic": "ADD:Q.B",
"operands": "#-1, @H'F798",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63384,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49085,
"address_region": "program_or_external",
"bytes": "2604",
"text": "BNE loc_BFC3",
"mnemonic": "BNE",
"operands": "loc_BFC3",
"kind": "branch",
"targets": [
49091
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49087,
"address_region": "program_or_external",
"bytes": "15F731D7",
"text": "BCLR.B #7, @H'F731",
"mnemonic": "BCLR.B",
"operands": "#7, @H'F731",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63281,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49091,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 13,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49092,
"address_region": "program_or_external",
"bytes": "15FEECF7",
"text": "BTST.B #7, @WDT_TCSR_R",
"mnemonic": "BTST.B",
"operands": "#7, @WDT_TCSR_R",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65260,
"name": "WDT_TCSR_R",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 49096,
"address_region": "program_or_external",
"bytes": "1DFEEC07A53F",
"text": "MOV:G.W #H'A53F, @WDT_TCSR_R",
"mnemonic": "MOV:G.W",
"operands": "#H'A53F, @WDT_TCSR_R",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 11,
"base_cycles": 9,
"alignment_adjustment": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65260,
"name": "WDT_TCSR_R",
"region": "register_field",
"kind": "registers"
}
],
"comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)",
"valid": true
},
{
"address": 49102,
"address_region": "program_or_external",
"bytes": "15F79408",
"text": "ADD:Q.B #1, @H'F794",
"mnemonic": "ADD:Q.B",
"operands": "#1, @H'F794",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63380,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49106,
"address_region": "program_or_external",
"bytes": "15F794040A",
"text": "CMP:G.B #H'0A, @H'F794",
"mnemonic": "CMP:G.B",
"operands": "#H'0A, @H'F794",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63380,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49111,
"address_region": "program_or_external",
"bytes": "2606",
"text": "BNE loc_BFDF",
"mnemonic": "BNE",
"operands": "loc_BFDF",
"kind": "branch",
"targets": [
49119
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49113,
"address_region": "program_or_external",
"bytes": "1DFEEC07A57F",
"text": "MOV:G.W #H'A57F, @WDT_TCSR_R",
"mnemonic": "MOV:G.W",
"operands": "#H'A57F, @WDT_TCSR_R",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 9,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65260,
"name": "WDT_TCSR_R",
"region": "register_field",
"kind": "registers"
}
],
"comment": "WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096)",
"valid": true
},
{
"address": 49119,
"address_region": "program_or_external",
"bytes": "0A",
"text": "RTE",
"mnemonic": "RTE",
"operands": "",
"kind": "rte",
"targets": [],
"cycles": {
"cycles": 14,
"base_cycles": 13,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49120,
"address_region": "program_or_external",
"bytes": "15F840060A",
"text": "MOV:G.B #H'0A, @H'F840",
"mnemonic": "MOV:G.B",
"operands": "#H'0A, @H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49125,
"address_region": "program_or_external",
"bytes": "AD82",
"text": "MOV:G.W R5, R2",
"mnemonic": "MOV:G.W",
"operands": "R5, R2",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49127,
"address_region": "program_or_external",
"bytes": "0E27",
"text": "BSR loc_C010",
"mnemonic": "BSR",
"operands": "loc_C010",
"kind": "call",
"targets": [
49168
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49129,
"address_region": "program_or_external",
"bytes": "0E4E",
"text": "BSR loc_C039",
"mnemonic": "BSR",
"operands": "loc_C039",
"kind": "call",
"targets": [
49209
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49131,
"address_region": "program_or_external",
"bytes": "AA75",
"text": "CMP:G.W R2, R5",
"mnemonic": "CMP:G.W",
"operands": "R2, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49133,
"address_region": "program_or_external",
"bytes": "270E",
"text": "BEQ loc_BFFD",
"mnemonic": "BEQ",
"operands": "loc_BFFD",
"kind": "branch",
"targets": [
49149
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49135,
"address_region": "program_or_external",
"bytes": "15F84016",
"text": "TST.B @H'F840",
"mnemonic": "TST.B",
"operands": "@H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49139,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_BFF9",
"mnemonic": "BEQ",
"operands": "loc_BFF9",
"kind": "branch",
"targets": [
49145
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49141,
"address_region": "program_or_external",
"bytes": "AA85",
"text": "MOV:G.W R2, R5",
"mnemonic": "MOV:G.W",
"operands": "R2, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49143,
"address_region": "program_or_external",
"bytes": "20EC",
"text": "BRA loc_BFE5",
"mnemonic": "BRA",
"operands": "loc_BFE5",
"kind": "jump",
"targets": [
49125
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49145,
"address_region": "program_or_external",
"bytes": "15F841C7",
"text": "BSET.B #7, @H'F841",
"mnemonic": "BSET.B",
"operands": "#7, @H'F841",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63553,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49149,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49150,
"address_region": "program_or_external",
"bytes": "15F840060A",
"text": "MOV:G.B #H'0A, @H'F840",
"mnemonic": "MOV:G.B",
"operands": "#H'0A, @H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49155,
"address_region": "program_or_external",
"bytes": "0E34",
"text": "BSR loc_C039",
"mnemonic": "BSR",
"operands": "loc_C039",
"kind": "call",
"targets": [
49209
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49157,
"address_region": "program_or_external",
"bytes": "15F84016",
"text": "TST.B @H'F840",
"mnemonic": "TST.B",
"operands": "@H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49161,
"address_region": "program_or_external",
"bytes": "2604",
"text": "BNE loc_C00F",
"mnemonic": "BNE",
"operands": "loc_C00F",
"kind": "branch",
"targets": [
49167
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49163,
"address_region": "program_or_external",
"bytes": "15F841C6",
"text": "BSET.B #6, @H'F841",
"mnemonic": "BSET.B",
"operands": "#6, @H'F841",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63553,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49167,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49168,
"address_region": "program_or_external",
"bytes": "0E58",
"text": "BSR loc_C06A",
"mnemonic": "BSR",
"operands": "loc_C06A",
"kind": "call",
"targets": [
49258
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49170,
"address_region": "program_or_external",
"bytes": "15F84016",
"text": "TST.B @H'F840",
"mnemonic": "TST.B",
"operands": "@H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49174,
"address_region": "program_or_external",
"bytes": "2720",
"text": "BEQ loc_C038",
"mnemonic": "BEQ",
"operands": "loc_C038",
"kind": "branch",
"targets": [
49208
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49176,
"address_region": "program_or_external",
"bytes": "1E0106",
"text": "BSR loc_C121",
"mnemonic": "BSR",
"operands": "loc_C121",
"kind": "call",
"targets": [
49441
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49179,
"address_region": "program_or_external",
"bytes": "A380",
"text": "MOV:G.B R3, R0",
"mnemonic": "MOV:G.B",
"operands": "R3, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49181,
"address_region": "program_or_external",
"bytes": "0E6C",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49183,
"address_region": "program_or_external",
"bytes": "27F1",
"text": "BEQ loc_C012",
"mnemonic": "BEQ",
"operands": "loc_C012",
"kind": "branch",
"targets": [
49170
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49185,
"address_region": "program_or_external",
"bytes": "A480",
"text": "MOV:G.B R4, R0",
"mnemonic": "MOV:G.B",
"operands": "R4, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49187,
"address_region": "program_or_external",
"bytes": "0E66",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49189,
"address_region": "program_or_external",
"bytes": "27EB",
"text": "BEQ loc_C012",
"mnemonic": "BEQ",
"operands": "loc_C012",
"kind": "branch",
"targets": [
49170
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49191,
"address_region": "program_or_external",
"bytes": "AD80",
"text": "MOV:G.W R5, R0",
"mnemonic": "MOV:G.W",
"operands": "R5, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49193,
"address_region": "program_or_external",
"bytes": "A010",
"text": "SWAP.B R0",
"mnemonic": "SWAP.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49195,
"address_region": "program_or_external",
"bytes": "0E5E",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49197,
"address_region": "program_or_external",
"bytes": "27E3",
"text": "BEQ loc_C012",
"mnemonic": "BEQ",
"operands": "loc_C012",
"kind": "branch",
"targets": [
49170
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49199,
"address_region": "program_or_external",
"bytes": "A580",
"text": "MOV:G.B R5, R0",
"mnemonic": "MOV:G.B",
"operands": "R5, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49201,
"address_region": "program_or_external",
"bytes": "0E58",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49203,
"address_region": "program_or_external",
"bytes": "27DD",
"text": "BEQ loc_C012",
"mnemonic": "BEQ",
"operands": "loc_C012",
"kind": "branch",
"targets": [
49170
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49205,
"address_region": "program_or_external",
"bytes": "1E010A",
"text": "BSR loc_C142",
"mnemonic": "BSR",
"operands": "loc_C142",
"kind": "call",
"targets": [
49474
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49208,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49209,
"address_region": "program_or_external",
"bytes": "0E2F",
"text": "BSR loc_C06A",
"mnemonic": "BSR",
"operands": "loc_C06A",
"kind": "call",
"targets": [
49258
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49211,
"address_region": "program_or_external",
"bytes": "15F84016",
"text": "TST.B @H'F840",
"mnemonic": "TST.B",
"operands": "@H'F840",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 63552,
"name": null,
"region": "on_chip_ram",
"kind": "ram"
}
],
"comment": "",
"valid": true
},
{
"address": 49215,
"address_region": "program_or_external",
"bytes": "2728",
"text": "BEQ loc_C069",
"mnemonic": "BEQ",
"operands": "loc_C069",
"kind": "branch",
"targets": [
49257
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49217,
"address_region": "program_or_external",
"bytes": "1E00DD",
"text": "BSR loc_C121",
"mnemonic": "BSR",
"operands": "loc_C121",
"kind": "call",
"targets": [
49441
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49220,
"address_region": "program_or_external",
"bytes": "A380",
"text": "MOV:G.B R3, R0",
"mnemonic": "MOV:G.B",
"operands": "R3, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49222,
"address_region": "program_or_external",
"bytes": "0E43",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49224,
"address_region": "program_or_external",
"bytes": "27F1",
"text": "BEQ loc_C03B",
"mnemonic": "BEQ",
"operands": "loc_C03B",
"kind": "branch",
"targets": [
49211
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49226,
"address_region": "program_or_external",
"bytes": "A480",
"text": "MOV:G.B R4, R0",
"mnemonic": "MOV:G.B",
"operands": "R4, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49228,
"address_region": "program_or_external",
"bytes": "0E3D",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49230,
"address_region": "program_or_external",
"bytes": "27EB",
"text": "BEQ loc_C03B",
"mnemonic": "BEQ",
"operands": "loc_C03B",
"kind": "branch",
"targets": [
49211
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49232,
"address_region": "program_or_external",
"bytes": "1E00CE",
"text": "BSR loc_C121",
"mnemonic": "BSR",
"operands": "loc_C121",
"kind": "call",
"targets": [
49441
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49235,
"address_region": "program_or_external",
"bytes": "A380",
"text": "MOV:G.B R3, R0",
"mnemonic": "MOV:G.B",
"operands": "R3, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49237,
"address_region": "program_or_external",
"bytes": "A0C0",
"text": "BSET.B #0, R0",
"mnemonic": "BSET.B",
"operands": "#0, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49239,
"address_region": "program_or_external",
"bytes": "0E32",
"text": "BSR loc_C08B",
"mnemonic": "BSR",
"operands": "loc_C08B",
"kind": "call",
"targets": [
49291
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49241,
"address_region": "program_or_external",
"bytes": "27E0",
"text": "BEQ loc_C03B",
"mnemonic": "BEQ",
"operands": "loc_C03B",
"kind": "branch",
"targets": [
49211
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49243,
"address_region": "program_or_external",
"bytes": "1E007D",
"text": "BSR loc_C0DB",
"mnemonic": "BSR",
"operands": "loc_C0DB",
"kind": "call",
"targets": [
49371
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49246,
"address_region": "program_or_external",
"bytes": "A510",
"text": "SWAP.B R5",
"mnemonic": "SWAP.B",
"operands": "R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49248,
"address_region": "program_or_external",
"bytes": "1E00A9",
"text": "BSR loc_C10C",
"mnemonic": "BSR",
"operands": "loc_C10C",
"kind": "call",
"targets": [
49420
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49251,
"address_region": "program_or_external",
"bytes": "1E0075",
"text": "BSR loc_C0DB",
"mnemonic": "BSR",
"operands": "loc_C0DB",
"kind": "call",
"targets": [
49371
],
"cycles": {
"cycles": 14,
"base_cycles": 9,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49254,
"address_region": "program_or_external",
"bytes": "1E00D9",
"text": "BSR loc_C142",
"mnemonic": "BSR",
"operands": "loc_C142",
"kind": "call",
"targets": [
49474
],
"cycles": {
"cycles": 13,
"base_cycles": 9,
"stack_adjustment": 4,
"note": "PC word push to stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49257,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49258,
"address_region": "program_or_external",
"bytes": "0C0FFF54",
"text": "AND.W #H'0FFF, R4",
"mnemonic": "AND.W",
"operands": "#H'0FFF, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 4,
"base_cycles": 4,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49262,
"address_region": "program_or_external",
"bytes": "4C0800",
"text": "CMP:I #H'0800, R4",
"mnemonic": "CMP:I",
"operands": "#H'0800, R4",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49265,
"address_region": "program_or_external",
"bytes": "240B",
"text": "BCC loc_C07E",
"mnemonic": "BCC",
"operands": "loc_C07E",
"kind": "branch",
"targets": [
49278
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49267,
"address_region": "program_or_external",
"bytes": "AC83",
"text": "MOV:G.W R4, R3",
"mnemonic": "MOV:G.W",
"operands": "R4, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49269,
"address_region": "program_or_external",
"bytes": "A310",
"text": "SWAP.B R3",
"mnemonic": "SWAP.B",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49271,
"address_region": "program_or_external",
"bytes": "A31A",
"text": "SHLL.B R3",
"mnemonic": "SHLL.B",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49273,
"address_region": "program_or_external",
"bytes": "04A043",
"text": "OR.B #H'A0, R3",
"mnemonic": "OR.B",
"operands": "#H'A0, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49276,
"address_region": "program_or_external",
"bytes": "200C",
"text": "BRA loc_C08A",
"mnemonic": "BRA",
"operands": "loc_C08A",
"kind": "jump",
"targets": [
49290
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49278,
"address_region": "program_or_external",
"bytes": "AC83",
"text": "MOV:G.W R4, R3",
"mnemonic": "MOV:G.W",
"operands": "R4, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49280,
"address_region": "program_or_external",
"bytes": "A310",
"text": "SWAP.B R3",
"mnemonic": "SWAP.B",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49282,
"address_region": "program_or_external",
"bytes": "A31A",
"text": "SHLL.B R3",
"mnemonic": "SHLL.B",
"operands": "R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49284,
"address_region": "program_or_external",
"bytes": "040E53",
"text": "AND.B #H'0E, R3",
"mnemonic": "AND.B",
"operands": "#H'0E, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49287,
"address_region": "program_or_external",
"bytes": "04E043",
"text": "OR.B #H'E0, R3",
"mnemonic": "OR.B",
"operands": "#H'E0, R3",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"base_cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49290,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49291,
"address_region": "program_or_external",
"bytes": "590007",
"text": "MOV:I.W #H'0007, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'0007, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49294,
"address_region": "program_or_external",
"bytes": "A01A",
"text": "SHLL.B R0",
"mnemonic": "SHLL.B",
"operands": "R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49296,
"address_region": "program_or_external",
"bytes": "2406",
"text": "BCC loc_C098",
"mnemonic": "BCC",
"operands": "loc_C098",
"kind": "branch",
"targets": [
49304
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49298,
"address_region": "program_or_external",
"bytes": "15FEFFC7",
"text": "BSET.B #7, @P9DR",
"mnemonic": "BSET.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 7 of P9DR",
"valid": true
},
{
"address": 49302,
"address_region": "program_or_external",
"bytes": "2004",
"text": "BRA loc_C09C",
"mnemonic": "BRA",
"operands": "loc_C09C",
"kind": "jump",
"targets": [
49308
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"cycles": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49304,
"address_region": "program_or_external",
"bytes": "15FEFFD7",
"text": "BCLR.B #7, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 7 of P9DR",
"valid": true
},
{
"address": 49308,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49312,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49316,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49320,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49324,
"address_region": "program_or_external",
"bytes": "01B9DF",
"text": "SCB/F R1, loc_C08E",
"mnemonic": "SCB/F",
"operands": "R1, loc_C08E",
"kind": "branch",
"targets": [
49294
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 8,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49327,
"address_region": "program_or_external",
"bytes": "15FEFE0613",
"text": "MOV:G.B #H'13, @P9DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'13, @P9DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65278,
"name": "P9DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DDR = H'13",
"valid": true
},
{
"address": 49332,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49336,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49340,
"address_region": "program_or_external",
"bytes": "15FEFFF7",
"text": "BTST.B #7, @P9DR",
"mnemonic": "BTST.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 7,
"base_cycles": 6,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 49344,
"address_region": "program_or_external",
"bytes": "270D",
"text": "BEQ loc_C0CF",
"mnemonic": "BEQ",
"operands": "loc_C0CF",
"kind": "branch",
"targets": [
49359
],
"cycles": {
"not_taken": 3,
"taken": 7,
"base_taken": 7,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49346,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49350,
"address_region": "program_or_external",
"bytes": "15FEFE0693",
"text": "MOV:G.B #H'93, @P9DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'93, @P9DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65278,
"name": "P9DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DDR = H'93",
"valid": true
},
{
"address": 49355,
"address_region": "program_or_external",
"bytes": "5000",
"text": "MOV:E.B #H'00, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'00, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49357,
"address_region": "program_or_external",
"bytes": "200B",
"text": "BRA loc_C0DA",
"mnemonic": "BRA",
"operands": "loc_C0DA",
"kind": "jump",
"targets": [
49370
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49359,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49363,
"address_region": "program_or_external",
"bytes": "15FEFE0693",
"text": "MOV:G.B #H'93, @P9DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'93, @P9DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65278,
"name": "P9DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DDR = H'93",
"valid": true
},
{
"address": 49368,
"address_region": "program_or_external",
"bytes": "5001",
"text": "MOV:E.B #H'01, R0",
"mnemonic": "MOV:E.B",
"operands": "#H'01, R0",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49370,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49371,
"address_region": "program_or_external",
"bytes": "15FEFE0613",
"text": "MOV:G.B #H'13, @P9DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'13, @P9DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65278,
"name": "P9DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DDR = H'13",
"valid": true
},
{
"address": 49376,
"address_region": "program_or_external",
"bytes": "590007",
"text": "MOV:I.W #H'0007, R1",
"mnemonic": "MOV:I.W",
"operands": "#H'0007, R1",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 3,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49379,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49383,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49387,
"address_region": "program_or_external",
"bytes": "15FEFFF7",
"text": "BTST.B #7, @P9DR",
"mnemonic": "BTST.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 6,
"base_cycles": 6,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "",
"valid": true
},
{
"address": 49391,
"address_region": "program_or_external",
"bytes": "2704",
"text": "BEQ loc_C0F5",
"mnemonic": "BEQ",
"operands": "loc_C0F5",
"kind": "branch",
"targets": [
49397
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49393,
"address_region": "program_or_external",
"bytes": "A549",
"text": "BSET.B R1, R5",
"mnemonic": "BSET.B",
"operands": "R1, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49395,
"address_region": "program_or_external",
"bytes": "2002",
"text": "BRA loc_C0F7",
"mnemonic": "BRA",
"operands": "loc_C0F7",
"kind": "jump",
"targets": [
49399
],
"cycles": {
"not_taken": 3,
"taken": 8,
"base_taken": 7,
"alignment_adjustment_taken": 1,
"cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49397,
"address_region": "program_or_external",
"bytes": "A559",
"text": "BCLR.B R1, R5",
"mnemonic": "BCLR.B",
"operands": "R1, R5",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 2,
"base_cycles": 2,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49399,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49403,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49407,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49411,
"address_region": "program_or_external",
"bytes": "01B9DD",
"text": "SCB/F R1, loc_C0E3",
"mnemonic": "SCB/F",
"operands": "R1, loc_C0E3",
"kind": "branch",
"targets": [
49379
],
"cycles": {
"false": 3,
"count_minus_1": 4,
"taken": 9,
"base_taken": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49414,
"address_region": "program_or_external",
"bytes": "15FEFE0693",
"text": "MOV:G.B #H'93, @P9DDR",
"mnemonic": "MOV:G.B",
"operands": "#H'93, @P9DDR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65278,
"name": "P9DDR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "P9DDR = H'93",
"valid": true
},
{
"address": 49419,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49420,
"address_region": "program_or_external",
"bytes": "15FEFFD7",
"text": "BCLR.B #7, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 7 of P9DR",
"valid": true
},
{
"address": 49424,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49428,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49432,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49436,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49440,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49441,
"address_region": "program_or_external",
"bytes": "15FEFFC7",
"text": "BSET.B #7, @P9DR",
"mnemonic": "BSET.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 7 of P9DR",
"valid": true
},
{
"address": 49445,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49449,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49453,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49457,
"address_region": "program_or_external",
"bytes": "15FEFFD7",
"text": "BCLR.B #7, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 7 of P9DR",
"valid": true
},
{
"address": 49461,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49465,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49469,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 8,
"base_cycles": 8,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49473,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 13,
"base_cycles": 8,
"alignment_adjustment": 1,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
},
{
"address": 49474,
"address_region": "program_or_external",
"bytes": "15FEFFD7",
"text": "BCLR.B #7, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 7 of P9DR",
"valid": true
},
{
"address": 49478,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49482,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49486,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49490,
"address_region": "program_or_external",
"bytes": "15FEFFC7",
"text": "BSET.B #7, @P9DR",
"mnemonic": "BSET.B",
"operands": "#7, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 7 of P9DR",
"valid": true
},
{
"address": 49494,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49498,
"address_region": "program_or_external",
"bytes": "15FEFFC1",
"text": "BSET.B #1, @P9DR",
"mnemonic": "BSET.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "set bit 1 of P9DR",
"valid": true
},
{
"address": 49502,
"address_region": "program_or_external",
"bytes": "15FEFFD1",
"text": "BCLR.B #1, @P9DR",
"mnemonic": "BCLR.B",
"operands": "#1, @P9DR",
"kind": "normal",
"targets": [],
"cycles": {
"cycles": 9,
"base_cycles": 8,
"alignment_adjustment": 1,
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [
{
"address": 65279,
"name": "P9DR",
"region": "register_field",
"kind": "registers"
}
],
"comment": "clear bit 1 of P9DR",
"valid": true
},
{
"address": 49506,
"address_region": "program_or_external",
"bytes": "19",
"text": "RTS",
"mnemonic": "RTS",
"operands": "",
"kind": "return",
"targets": [],
"cycles": {
"cycles": 12,
"base_cycles": 8,
"stack_adjustment": 4,
"note": "PC word pop from stack",
"source": "manual Appendix A.4, tables A-7/A-8",
"assumption": "on-chip instruction fetch/operand access, no external wait states"
},
"references": [],
"comment": "",
"valid": true
}
]
}
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