143 lines
5.2 KiB
Python
143 lines
5.2 KiB
Python
import unittest
|
|
from pathlib import Path
|
|
|
|
from h8536.emulator import (
|
|
HEARTBEAT_FRAME,
|
|
IPRA,
|
|
IPRE,
|
|
ON_CHIP_RAM_START,
|
|
REGISTER_FIELD_START,
|
|
SCI1_SCR,
|
|
SCI1_SSR,
|
|
SCI1_TDR,
|
|
SCI_SCR_TE,
|
|
SCI_SSR_TDRE,
|
|
H8536Emulator,
|
|
MemoryMap,
|
|
SCI1,
|
|
discover_rom_path,
|
|
load_rom,
|
|
)
|
|
|
|
|
|
def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1100) -> bytearray:
|
|
rom = bytearray([0xFF] * size)
|
|
rom[0:2] = reset.to_bytes(2, "big")
|
|
return rom
|
|
|
|
|
|
class EmulatorHarnessTest(unittest.TestCase):
|
|
def test_memory_map_routes_rom_ram_register_and_external(self):
|
|
memory = MemoryMap(bytes([0x12, 0x34, 0x56, 0x78]))
|
|
|
|
self.assertEqual(memory.read8(0x0001), 0x34)
|
|
memory.write8(ON_CHIP_RAM_START, 0xA5)
|
|
self.assertEqual(memory.read8(ON_CHIP_RAM_START), 0xA5)
|
|
memory.write8(REGISTER_FIELD_START, 0x5A)
|
|
self.assertEqual(memory.read8(REGISTER_FIELD_START), 0x5A)
|
|
memory.write8(0xF000, 0x11)
|
|
self.assertEqual(memory.read8(0xF000), 0x11)
|
|
|
|
def test_sci_transmit_capture_requires_enabled_transmitter(self):
|
|
sci = SCI1()
|
|
sci.write(SCI1_TDR, 0x33)
|
|
self.assertEqual(sci.tx_bytes, [])
|
|
self.assertFalse(sci.tx_events[-1].emitted)
|
|
|
|
sci.write(SCI1_SCR, sci.scr | SCI_SCR_TE)
|
|
for byte in HEARTBEAT_FRAME:
|
|
sci.write(SCI1_TDR, byte)
|
|
|
|
self.assertEqual(bytes(sci.tx_bytes), HEARTBEAT_FRAME)
|
|
self.assertEqual(sci.tx_frames, [HEARTBEAT_FRAME])
|
|
self.assertTrue(sci.saw_heartbeat())
|
|
self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
|
|
|
|
def test_vector_decoding_uses_minimum_mode_reset_word(self):
|
|
rom = bytearray(0x1004)
|
|
rom[0:2] = b"\x10\x00"
|
|
rom[0x1000] = 0x00
|
|
|
|
emulator = H8536Emulator(bytes(rom))
|
|
|
|
self.assertEqual(emulator.reset_vector(), 0x1000)
|
|
self.assertEqual(emulator.cpu.pc, 0x1000)
|
|
self.assertEqual(emulator.vectors[0x0000][1], 0x1000)
|
|
|
|
def test_harness_instantiates_on_repo_artifacts(self):
|
|
root = Path(__file__).resolve().parents[1]
|
|
rom_path = discover_rom_path(root)
|
|
self.assertIsNotNone(rom_path)
|
|
rom_bytes, loaded_path = load_rom(root=root)
|
|
|
|
emulator = H8536Emulator(rom_bytes)
|
|
report = emulator.run(max_steps=4)
|
|
|
|
self.assertEqual(loaded_path, rom_path)
|
|
self.assertEqual(emulator.reset_vector(), 0x1000)
|
|
self.assertGreaterEqual(len(rom_bytes), 0x1002)
|
|
self.assertEqual(report.steps, 4)
|
|
self.assertFalse(report.heartbeat_seen)
|
|
|
|
def test_scb_false_decrements_and_branches_until_zero(self):
|
|
rom = rom_with_reset()
|
|
rom[0x1000:0x1003] = b"\x58\x00\x03" # MOV:I.W #H'0003, R0
|
|
rom[0x1003:0x1006] = b"\x01\xB8\xFD" # SCB/F R0, H'1003
|
|
|
|
emulator = H8536Emulator(bytes(rom))
|
|
report = emulator.run(max_steps=4)
|
|
|
|
self.assertEqual(report.stopped_reason, "max_steps")
|
|
self.assertEqual(emulator.cpu.regs[0], 0)
|
|
self.assertEqual(emulator.cpu.pc, 0x1006)
|
|
|
|
def test_bsr_rts_and_stack_restore_return_to_caller(self):
|
|
rom = rom_with_reset()
|
|
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
|
|
rom[0x1003:0x1005] = b"\x0E\x03" # BSR H'1008
|
|
rom[0x1005:0x1008] = b"\x59\x12\x34" # MOV:I.W #H'1234, R1
|
|
rom[0x1008:0x100B] = b"\x58\xAB\xCD" # MOV:I.W #H'ABCD, R0
|
|
rom[0x100B] = 0x19 # RTS
|
|
|
|
emulator = H8536Emulator(bytes(rom))
|
|
emulator.run(max_steps=5)
|
|
|
|
self.assertEqual(emulator.cpu.regs[0], 0xABCD)
|
|
self.assertEqual(emulator.cpu.regs[1], 0x1234)
|
|
self.assertEqual(emulator.cpu.regs[7], 0xFE80)
|
|
|
|
def test_sci1_txi_interrupt_can_emit_through_tdr(self):
|
|
rom = rom_with_reset(size=0x1040)
|
|
rom[0x0084:0x0086] = (0x1010).to_bytes(2, "big")
|
|
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
|
|
rom[0x1003:0x1008] = bytes([0x15, (IPRE >> 8) & 0xFF, IPRE & 0xFF, 0x06, 0x50])
|
|
rom[0x1008:0x100D] = bytes([0x15, (SCI1_SCR >> 8) & 0xFF, SCI1_SCR & 0xFF, 0x06, 0xA0])
|
|
rom[0x100D] = 0x00 # NOP after interrupt return
|
|
rom[0x1010:0x1015] = bytes([0x15, (SCI1_SCR >> 8) & 0xFF, SCI1_SCR & 0xFF, 0x06, SCI_SCR_TE])
|
|
rom[0x1015:0x101A] = bytes([0x15, (SCI1_TDR >> 8) & 0xFF, SCI1_TDR & 0xFF, 0x06, 0x42])
|
|
rom[0x101A] = 0x0A # RTE
|
|
|
|
emulator = H8536Emulator(bytes(rom))
|
|
report = emulator.run(max_steps=8)
|
|
|
|
self.assertEqual(bytes(emulator.sci1.tx_bytes), b"\x42")
|
|
self.assertFalse(report.heartbeat_seen)
|
|
|
|
def test_interval_interrupt_vector_can_fire(self):
|
|
rom = rom_with_reset(size=0x1040)
|
|
rom[0x0042:0x0044] = (0x1020).to_bytes(2, "big")
|
|
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
|
|
rom[0x1003:0x1008] = bytes([0x15, (IPRA >> 8) & 0xFF, IPRA & 0xFF, 0x06, 0x70])
|
|
rom[0x1008:0x100A] = b"\x20\xFC" # BRA H'1006-ish idle loop
|
|
rom[0x1020:0x1025] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x06, 0x99])
|
|
rom[0x1025] = 0x0A # RTE
|
|
|
|
emulator = H8536Emulator(bytes(rom), interval_steps=2)
|
|
emulator.run(max_steps=8)
|
|
|
|
self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 0x99)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
unittest.main()
|