2076 lines
50 KiB
JSON
2076 lines
50 KiB
JSON
{
|
|
"vectors": [
|
|
{
|
|
"address": 0,
|
|
"name": "reset",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 4,
|
|
"name": "invalid_instruction",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 6,
|
|
"name": "zero_divide",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 8,
|
|
"name": "trap_vs",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 16,
|
|
"name": "address_error",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 18,
|
|
"name": "trace",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 22,
|
|
"name": "nmi",
|
|
"target": 17299,
|
|
"target_label": "vec_nmi_4393"
|
|
},
|
|
{
|
|
"address": 32,
|
|
"name": "trapa_0",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 34,
|
|
"name": "trapa_1",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 36,
|
|
"name": "trapa_2",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 38,
|
|
"name": "trapa_3",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 40,
|
|
"name": "trapa_4",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
|
|
{
|
|
"address": 42,
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|
"name": "trapa_5",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 44,
|
|
"name": "trapa_6",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 46,
|
|
"name": "trapa_7",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 48,
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|
"name": "trapa_8",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 50,
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|
"name": "trapa_9",
|
|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 52,
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|
"name": "trapa_a",
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|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 54,
|
|
"name": "trapa_b",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 56,
|
|
"name": "trapa_c",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 58,
|
|
"name": "trapa_d",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 60,
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|
"name": "trapa_e",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 62,
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|
"name": "trapa_f",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
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|
"address": 64,
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|
"name": "irq0",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
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|
"address": 66,
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|
"name": "interval_timer",
|
|
"target": 49092,
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|
"target_label": "vec_interval_timer_BFC4"
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|
},
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|
{
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|
"address": 72,
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|
"name": "irq1",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
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|
"address": 80,
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|
"name": "irq2",
|
|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 82,
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|
"name": "irq3",
|
|
"target": 15408,
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|
"target_label": "vec_irq3_3C30"
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|
},
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|
{
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|
"address": 88,
|
|
"name": "irq4",
|
|
"target": 15047,
|
|
"target_label": "vec_irq4_3AC7"
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|
},
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|
{
|
|
"address": 90,
|
|
"name": "irq5",
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|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
|
|
},
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|
{
|
|
"address": 98,
|
|
"name": "frt1_ocia",
|
|
"target": 48874,
|
|
"target_label": "vec_frt1_ocia_BEEA"
|
|
},
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|
{
|
|
"address": 106,
|
|
"name": "frt2_ocia",
|
|
"target": 48931,
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|
"target_label": "vec_frt2_ocia_BF23"
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|
},
|
|
{
|
|
"address": 128,
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|
"name": "sci1_eri",
|
|
"target": 47959,
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|
"target_label": "vec_sci1_eri_BB57"
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|
},
|
|
{
|
|
"address": 130,
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|
"name": "sci1_rxi",
|
|
"target": 47975,
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|
"target_label": "vec_sci1_rxi_BB67"
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|
},
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|
{
|
|
"address": 132,
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|
"name": "sci1_txi",
|
|
"target": 47748,
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|
"target_label": "vec_sci1_txi_BA84"
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},
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|
{
|
|
"address": 144,
|
|
"name": "ad_adi",
|
|
"target": 15769,
|
|
"target_label": "vec_ad_adi_3D99"
|
|
}
|
|
],
|
|
"dtc_vectors": [],
|
|
"memory_regions": [
|
|
{
|
|
"name": "exception_vectors",
|
|
"start": 0,
|
|
"end": 159,
|
|
"kind": "vectors",
|
|
"manual": "section 2 address space"
|
|
},
|
|
{
|
|
"name": "dtc_vectors",
|
|
"start": 160,
|
|
"end": 255,
|
|
"kind": "dtc_vectors",
|
|
"manual": "section 2 address space"
|
|
},
|
|
{
|
|
"name": "program_or_external",
|
|
"start": 256,
|
|
"end": 63103,
|
|
"kind": "program",
|
|
"manual": "section 2/17 mode-dependent ROM or external space"
|
|
},
|
|
{
|
|
"name": "on_chip_ram",
|
|
"start": 63104,
|
|
"end": 65151,
|
|
"kind": "ram",
|
|
"manual": "section 16 RAM"
|
|
},
|
|
{
|
|
"name": "register_field",
|
|
"start": 65152,
|
|
"end": 65535,
|
|
"kind": "registers",
|
|
"manual": "appendix B register map"
|
|
}
|
|
],
|
|
"data_candidates": {
|
|
"strings": [],
|
|
"pointer_tables": []
|
|
},
|
|
"call_graph": {
|
|
"nodes": [],
|
|
"edges": []
|
|
},
|
|
"timing_summary": {
|
|
"blocks": [],
|
|
"loops": []
|
|
},
|
|
"sci": {
|
|
"clock_hz": null,
|
|
"formulas": {
|
|
"async": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
|
|
"sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))"
|
|
},
|
|
"manual_references": [
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|
"Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source",
|
|
"Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source",
|
|
"Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator",
|
|
"Manual/0900766b802125d0.md:16303 asynchronous BRR formula",
|
|
"Manual/0900766b802125d0.md:16379 synchronous BRR formula",
|
|
"Manual/0900766b802125d0.md:16410 SCI clock source selection tables"
|
|
],
|
|
"channels": {
|
|
"SCI1": {
|
|
"writes": [],
|
|
"configurations": []
|
|
},
|
|
"SCI2": {
|
|
"writes": [],
|
|
"configurations": []
|
|
}
|
|
}
|
|
},
|
|
"sci_protocol": {
|
|
"manual_references": [
|
|
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
|
|
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
|
|
"Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
|
|
"Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
|
|
"Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
|
|
"Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
|
|
"Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
|
|
"Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
|
|
"Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
|
|
"Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
|
|
"Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
|
|
"Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
|
|
"Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
|
|
],
|
|
"channels": {
|
|
"SCI1": {
|
|
"events": []
|
|
},
|
|
"SCI2": {
|
|
"events": []
|
|
}
|
|
},
|
|
"events": []
|
|
},
|
|
"serial_reconstruction": {
|
|
"kind": "serial_reconstruction",
|
|
"candidates": [],
|
|
"ram_roles": [],
|
|
"evidence": [],
|
|
"required_evidence": {
|
|
"tx": [
|
|
"tx_buffer_region",
|
|
"tx_checksum_seed",
|
|
"checksum_byte",
|
|
"xor_checksum_chain",
|
|
"initial_send_from_buffer_start",
|
|
"tx_index_initialized_to_one",
|
|
"tx_isr_indexed_send",
|
|
"tx_index_increment",
|
|
"tx_index_compare_frame_length"
|
|
],
|
|
"rx": [
|
|
"rx_rdr_read",
|
|
"rx_indexed_store",
|
|
"rx_index_increment_store",
|
|
"rx_isr_compare_frame_length",
|
|
"rx_complete_timer",
|
|
"rx_processor_requires_six_bytes",
|
|
"rx_copy_capture_to_frame_buffer",
|
|
"rx_checksum_seed",
|
|
"rx_xor_checksum_validation"
|
|
]
|
|
}
|
|
},
|
|
"board_profile": {
|
|
"board": "sony_rcp_tx7",
|
|
"name": "Sony RCP-TX7",
|
|
"summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.",
|
|
"manual_references": [
|
|
"Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD",
|
|
"Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD",
|
|
"Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals",
|
|
"Manual/0900766b802125d0.md:11201 P96 is RXD1 input",
|
|
"Manual/0900766b802125d0.md:11202 P95 is TXD1 output",
|
|
"Manual/0900766b802125d0.md:15725 SCI1 RXD input pin",
|
|
"Manual/0900766b802125d0.md:15726 SCI1 TXD output pin",
|
|
"Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR",
|
|
"Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR",
|
|
"Manual/0900766b802125d0.md:15794 RDR receive data register",
|
|
"Manual/0900766b802125d0.md:15823 TDR transmit data register",
|
|
"Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions",
|
|
"Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output",
|
|
"Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input",
|
|
"Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags",
|
|
"Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions",
|
|
"Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94"
|
|
],
|
|
"traces": [
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "TXD",
|
|
"h8_pin": 66,
|
|
"h8_pin_name": "P95/TXD",
|
|
"h8_function": "TXD1",
|
|
"max202_pin": 11,
|
|
"evidence": "MAX202 pin 11 traces to H8 pin 66"
|
|
},
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "RXD",
|
|
"h8_pin": 67,
|
|
"h8_pin_name": "P96/RXD",
|
|
"h8_function": "RXD1",
|
|
"max202_pin": 12,
|
|
"evidence": "MAX202 pin 12 traces to H8 pin 67"
|
|
}
|
|
],
|
|
"channels": {
|
|
"SCI1": {
|
|
"traced_to_max202": true,
|
|
"path": "RS232/MAX202",
|
|
"pins": [
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "TXD",
|
|
"h8_pin": 66,
|
|
"h8_pin_name": "P95/TXD",
|
|
"h8_function": "TXD1",
|
|
"max202_pin": 11,
|
|
"evidence": "MAX202 pin 11 traces to H8 pin 66"
|
|
},
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "RXD",
|
|
"h8_pin": 67,
|
|
"h8_pin_name": "P96/RXD",
|
|
"h8_function": "RXD1",
|
|
"max202_pin": 12,
|
|
"evidence": "MAX202 pin 12 traces to H8 pin 67"
|
|
}
|
|
],
|
|
"scr": {
|
|
"value": 12,
|
|
"value_hex": "H'0C",
|
|
"tie": false,
|
|
"rie": false,
|
|
"tx_enabled": false,
|
|
"rx_enabled": false
|
|
},
|
|
"accesses": []
|
|
},
|
|
"SCI2": {
|
|
"traced_to_max202": false,
|
|
"path": null,
|
|
"note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.",
|
|
"p9sci2e": false,
|
|
"scr": {
|
|
"value": 12,
|
|
"value_hex": "H'0C",
|
|
"tie": false,
|
|
"rie": false,
|
|
"tx_enabled": false,
|
|
"rx_enabled": false
|
|
},
|
|
"accesses": []
|
|
}
|
|
},
|
|
"instructions": {},
|
|
"state": {
|
|
"SYSCR2": {
|
|
"value": 128,
|
|
"value_hex": "H'80"
|
|
},
|
|
"P9SCI2E": false
|
|
}
|
|
},
|
|
"peripheral_access": {
|
|
"manual_references": [
|
|
"Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access",
|
|
"Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte",
|
|
"Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP",
|
|
"Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP",
|
|
"Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte"
|
|
],
|
|
"warnings": []
|
|
},
|
|
"indirect_flow": {
|
|
"sites": []
|
|
},
|
|
"dataflow": {
|
|
"blocks": [
|
|
{
|
|
"start": 9920,
|
|
"instructions": [
|
|
9920,
|
|
9924
|
|
],
|
|
"end": 9924,
|
|
"end_exclusive": 9927
|
|
},
|
|
{
|
|
"start": 9927,
|
|
"instructions": [
|
|
9927,
|
|
9931,
|
|
9937,
|
|
9939,
|
|
9942,
|
|
9946
|
|
],
|
|
"end": 9946,
|
|
"end_exclusive": 9948
|
|
},
|
|
{
|
|
"start": 9948,
|
|
"instructions": [
|
|
9948,
|
|
9952
|
|
],
|
|
"end": 9952,
|
|
"end_exclusive": 9954
|
|
},
|
|
{
|
|
"start": 9954,
|
|
"instructions": [
|
|
9954
|
|
],
|
|
"end": 9954,
|
|
"end_exclusive": 9956
|
|
},
|
|
{
|
|
"start": 9956,
|
|
"instructions": [
|
|
9956,
|
|
9959
|
|
],
|
|
"end": 9959,
|
|
"end_exclusive": 9960
|
|
},
|
|
{
|
|
"start": 9960,
|
|
"instructions": [
|
|
9960,
|
|
9964
|
|
],
|
|
"end": 9964,
|
|
"end_exclusive": 9966
|
|
},
|
|
{
|
|
"start": 9966,
|
|
"instructions": [
|
|
9966,
|
|
9970
|
|
],
|
|
"end": 9970,
|
|
"end_exclusive": 9974
|
|
},
|
|
{
|
|
"start": 9974,
|
|
"instructions": [
|
|
9974,
|
|
9980,
|
|
9985,
|
|
9988
|
|
],
|
|
"end": 9988,
|
|
"end_exclusive": 9989
|
|
}
|
|
],
|
|
"registers": [
|
|
"R0",
|
|
"R1",
|
|
"R2",
|
|
"R3",
|
|
"R4",
|
|
"R5",
|
|
"R6",
|
|
"R7"
|
|
],
|
|
"control_registers": [
|
|
"CCR",
|
|
"BR",
|
|
"EP",
|
|
"DP",
|
|
"TP",
|
|
"SR"
|
|
]
|
|
},
|
|
"symbols": {
|
|
"symbols": [
|
|
{
|
|
"address": 59684,
|
|
"name": "mem_E924",
|
|
"region": "program_or_external",
|
|
"kind": "memory",
|
|
"access_count": 1,
|
|
"read_count": 0,
|
|
"write_count": 1,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 9931,
|
|
"last_access": 9931,
|
|
"accesses": [
|
|
{
|
|
"address": 59684,
|
|
"instruction_address": 9931,
|
|
"instruction": "MOV:G.W #H'FF80, @H'E924",
|
|
"mnemonic": "MOV:G.W",
|
|
"direction": "write",
|
|
"width": "word",
|
|
"operand": "@H'E924",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 62468,
|
|
"name": "mem_F404",
|
|
"region": "program_or_external",
|
|
"kind": "memory",
|
|
"access_count": 1,
|
|
"read_count": 1,
|
|
"write_count": 0,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 9948,
|
|
"last_access": 9948,
|
|
"accesses": [
|
|
{
|
|
"address": 62468,
|
|
"instruction_address": 9948,
|
|
"instruction": "BTST.B #4, @H'F404",
|
|
"mnemonic": "BTST.B",
|
|
"direction": "read",
|
|
"width": "byte",
|
|
"operand": "@H'F404",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63222,
|
|
"name": "ram_F6F6",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 2,
|
|
"read_count": 0,
|
|
"write_count": 2,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 9920,
|
|
"last_access": 9927,
|
|
"accesses": [
|
|
{
|
|
"address": 63222,
|
|
"instruction_address": 9920,
|
|
"instruction": "CLR.B @H'F6F6",
|
|
"mnemonic": "CLR.B",
|
|
"direction": "write",
|
|
"width": "byte",
|
|
"operand": "@H'F6F6",
|
|
"operand_index": 0
|
|
},
|
|
{
|
|
"address": 63222,
|
|
"instruction_address": 9927,
|
|
"instruction": "CLR.B @H'F6F6",
|
|
"mnemonic": "CLR.B",
|
|
"direction": "write",
|
|
"width": "byte",
|
|
"operand": "@H'F6F6",
|
|
"operand_index": 0
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63282,
|
|
"name": "ram_F732",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 2,
|
|
"read_count": 1,
|
|
"write_count": 1,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 9966,
|
|
"last_access": 9974,
|
|
"accesses": [
|
|
{
|
|
"address": 63282,
|
|
"instruction_address": 9966,
|
|
"instruction": "MOV:G.W @H'F732, R1",
|
|
"mnemonic": "MOV:G.W",
|
|
"direction": "read",
|
|
"width": "word",
|
|
"operand": "@H'F732",
|
|
"operand_index": 0
|
|
},
|
|
{
|
|
"address": 63282,
|
|
"instruction_address": 9974,
|
|
"instruction": "MOV:G.W #H'1C01, @H'F732",
|
|
"mnemonic": "MOV:G.W",
|
|
"direction": "write",
|
|
"width": "word",
|
|
"operand": "@H'F732",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63284,
|
|
"name": "ram_F734",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 1,
|
|
"read_count": 0,
|
|
"write_count": 1,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 9970,
|
|
"last_access": 9970,
|
|
"accesses": [
|
|
{
|
|
"address": 63284,
|
|
"instruction_address": 9970,
|
|
"instruction": "MOV:G.W R1, @H'F734",
|
|
"mnemonic": "MOV:G.W",
|
|
"direction": "write",
|
|
"width": "word",
|
|
"operand": "@H'F734",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63377,
|
|
"name": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 1,
|
|
"read_count": 1,
|
|
"write_count": 0,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 9942,
|
|
"last_access": 9942,
|
|
"accesses": [
|
|
{
|
|
"address": 63377,
|
|
"instruction_address": 9942,
|
|
"instruction": "BTST.B #7, @H'F791",
|
|
"mnemonic": "BTST.B",
|
|
"direction": "read",
|
|
"width": "byte",
|
|
"operand": "@H'F791",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 64258,
|
|
"name": "ram_FB02",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 1,
|
|
"read_count": 0,
|
|
"write_count": 1,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 9980,
|
|
"last_access": 9980,
|
|
"accesses": [
|
|
{
|
|
"address": 64258,
|
|
"instruction_address": 9980,
|
|
"instruction": "MOV:G.B #H'14, @H'FB02",
|
|
"mnemonic": "MOV:G.B",
|
|
"direction": "write",
|
|
"width": "byte",
|
|
"operand": "@H'FB02",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 64259,
|
|
"name": "ram_FB03",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 1,
|
|
"read_count": 1,
|
|
"write_count": 1,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 9960,
|
|
"last_access": 9960,
|
|
"accesses": [
|
|
{
|
|
"address": 64259,
|
|
"instruction_address": 9960,
|
|
"instruction": "BSET.B #7, @H'FB03",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'FB03",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"by_address": {
|
|
"59684": "mem_E924",
|
|
"62468": "mem_F404",
|
|
"63222": "ram_F6F6",
|
|
"63282": "ram_F732",
|
|
"63284": "ram_F734",
|
|
"63377": "ram_F791",
|
|
"64258": "ram_FB02",
|
|
"64259": "ram_FB03"
|
|
}
|
|
},
|
|
"lcd_text": {
|
|
"strings": [
|
|
{
|
|
"address": 10006,
|
|
"length": 5,
|
|
"text": "FhG~H",
|
|
"trimmed": "FhG~H",
|
|
"kind": "printable_run",
|
|
"score": 0.67,
|
|
"confidence": "low"
|
|
}
|
|
],
|
|
"regions": [],
|
|
"searches": [
|
|
{
|
|
"term": "CONNECT",
|
|
"literal_hits": [],
|
|
"candidate_hits": [],
|
|
"near_matches": [],
|
|
"status": "not_found"
|
|
}
|
|
],
|
|
"notes": [
|
|
"LCD text scan is byte-oriented and conservative; strings may be inline script fields.",
|
|
"Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes."
|
|
]
|
|
},
|
|
"lcd_driver": {
|
|
"addresses": [
|
|
{
|
|
"address": 61952,
|
|
"name": "lcd_status_control",
|
|
"role": "status/control register inferred from busy polling and command writes"
|
|
},
|
|
{
|
|
"address": 61953,
|
|
"name": "lcd_data",
|
|
"role": "data register inferred from paired data reads/writes"
|
|
}
|
|
],
|
|
"accesses": [],
|
|
"polling_loops": [],
|
|
"routines": [],
|
|
"instructions": {}
|
|
},
|
|
"instructions": [
|
|
{
|
|
"address": 9920,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F6F613",
|
|
"text": "CLR.B @H'F6F6",
|
|
"mnemonic": "CLR.B",
|
|
"operands": "@H'F6F6",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
"base_cycles": 8,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63222,
|
|
"name": null,
|
|
"symbol": "ram_F6F6",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9920,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9924,
|
|
"address_region": "program_or_external",
|
|
"bytes": "30FF0C",
|
|
"text": "BRA loc_25D3",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_25D3",
|
|
"kind": "jump",
|
|
"targets": [
|
|
9683
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"cycles": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9920,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9927,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F6F613",
|
|
"text": "CLR.B @H'F6F6",
|
|
"mnemonic": "CLR.B",
|
|
"operands": "@H'F6F6",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 8,
|
|
"base_cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63222,
|
|
"name": null,
|
|
"symbol": "ram_F6F6",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9927,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9931,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DE92407FF80",
|
|
"text": "MOV:G.W #H'FF80, @H'E924",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "#H'FF80, @H'E924",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
"base_cycles": 9,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 59684,
|
|
"name": null,
|
|
"symbol": "mem_E924",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9927,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9937,
|
|
"address_region": "program_or_external",
|
|
"bytes": "5280",
|
|
"text": "MOV:E.B #H'80, R2",
|
|
"mnemonic": "MOV:E.B",
|
|
"operands": "#H'80, R2",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 2,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9927,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R2",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R2 = 0x80"
|
|
],
|
|
"known_after": {
|
|
"registers": {
|
|
"R2": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"address": 9939,
|
|
"address_region": "program_or_external",
|
|
"bytes": "5B0092",
|
|
"text": "MOV:I.W #H'0092, R3",
|
|
"mnemonic": "MOV:I.W",
|
|
"operands": "#H'0092, R3",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 3,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9927,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R3",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": true,
|
|
"value": 146,
|
|
"hex": "0x0092",
|
|
"width": 16,
|
|
"source": "MOV:I.W #H'0092, R3"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R3 = 0x0092"
|
|
],
|
|
"known_after": {
|
|
"registers": {
|
|
"R2": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
},
|
|
"R3": {
|
|
"known": true,
|
|
"value": 146,
|
|
"hex": "0x0092",
|
|
"width": 16,
|
|
"source": "MOV:I.W #H'0092, R3"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"address": 9942,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F791F7",
|
|
"text": "BTST.B #7, @H'F791",
|
|
"mnemonic": "BTST.B",
|
|
"operands": "#7, @H'F791",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 7,
|
|
"base_cycles": 6,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63377,
|
|
"name": null,
|
|
"symbol": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9927,
|
|
"changes": [],
|
|
"notes": [],
|
|
"known_after": {
|
|
"registers": {
|
|
"R2": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
},
|
|
"R3": {
|
|
"known": true,
|
|
"value": 146,
|
|
"hex": "0x0092",
|
|
"width": 16,
|
|
"source": "MOV:I.W #H'0092, R3"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"address": 9946,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2708",
|
|
"text": "BEQ loc_26E4",
|
|
"mnemonic": "BEQ",
|
|
"operands": "loc_26E4",
|
|
"kind": "branch",
|
|
"targets": [
|
|
9956
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9927,
|
|
"changes": [],
|
|
"notes": [],
|
|
"known_after": {
|
|
"registers": {
|
|
"R2": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
},
|
|
"R3": {
|
|
"known": true,
|
|
"value": 146,
|
|
"hex": "0x0092",
|
|
"width": 16,
|
|
"source": "MOV:I.W #H'0092, R3"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"address": 9948,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F404F4",
|
|
"text": "BTST.B #4, @H'F404",
|
|
"mnemonic": "BTST.B",
|
|
"operands": "#4, @H'F404",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 7,
|
|
"base_cycles": 6,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 62468,
|
|
"name": null,
|
|
"symbol": "mem_F404",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9948,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9952,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2702",
|
|
"text": "BEQ loc_26E4",
|
|
"mnemonic": "BEQ",
|
|
"operands": "loc_26E4",
|
|
"kind": "branch",
|
|
"targets": [
|
|
9956
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9948,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9954,
|
|
"address_region": "program_or_external",
|
|
"bytes": "ABCE",
|
|
"text": "BSET.W #14, R3",
|
|
"mnemonic": "BSET.W",
|
|
"operands": "#14, R3",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 3,
|
|
"base_cycles": 3,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9954,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R3",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "unsupported:BSET.W"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"unsupported operation invalidated R3"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 9956,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1E176D",
|
|
"text": "BSR loc_3E54",
|
|
"mnemonic": "BSR",
|
|
"operands": "loc_3E54",
|
|
"kind": "call",
|
|
"targets": [
|
|
15956
|
|
],
|
|
"cycles": {
|
|
"cycles": 13,
|
|
"base_cycles": 9,
|
|
"stack_adjustment": 4,
|
|
"note": "PC word push to stack",
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9956,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R0",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R1",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R2",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R3",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R4",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R5",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R6",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R7",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "BR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "EP",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "DP",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "TP",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "SR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"call clobbers tracked register state"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 9959,
|
|
"address_region": "program_or_external",
|
|
"bytes": "19",
|
|
"text": "RTS",
|
|
"mnemonic": "RTS",
|
|
"operands": "",
|
|
"kind": "return",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 13,
|
|
"base_cycles": 8,
|
|
"alignment_adjustment": 1,
|
|
"stack_adjustment": 4,
|
|
"note": "PC word pop from stack",
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9956,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9960,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15FB03C7",
|
|
"text": "BSET.B #7, @H'FB03",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#7, @H'FB03",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
"base_cycles": 8,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 64259,
|
|
"name": null,
|
|
"symbol": "ram_FB03",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9960,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9964,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2608",
|
|
"text": "BNE loc_26F6",
|
|
"mnemonic": "BNE",
|
|
"operands": "loc_26F6",
|
|
"kind": "branch",
|
|
"targets": [
|
|
9974
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9960,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9966,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DF73281",
|
|
"text": "MOV:G.W @H'F732, R1",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "@H'F732, R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 7,
|
|
"base_cycles": 6,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63282,
|
|
"name": null,
|
|
"symbol": "ram_F732",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9966,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R1",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "memory_load"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R1 unknown after memory load"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 9970,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DF73491",
|
|
"text": "MOV:G.W R1, @H'F734",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "R1, @H'F734",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 7,
|
|
"base_cycles": 6,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63284,
|
|
"name": null,
|
|
"symbol": "ram_F734",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9966,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9974,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DF732071C01",
|
|
"text": "MOV:G.W #H'1C01, @H'F732",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "#H'1C01, @H'F732",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 11,
|
|
"base_cycles": 9,
|
|
"alignment_adjustment": 2,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63282,
|
|
"name": null,
|
|
"symbol": "ram_F732",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9974,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9980,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15FB020614",
|
|
"text": "MOV:G.B #H'14, @H'FB02",
|
|
"mnemonic": "MOV:G.B",
|
|
"operands": "#H'14, @H'FB02",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
"base_cycles": 8,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 64258,
|
|
"name": null,
|
|
"symbol": "ram_FB02",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9974,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 9985,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1E21F6",
|
|
"text": "BSR loc_48FA",
|
|
"mnemonic": "BSR",
|
|
"operands": "loc_48FA",
|
|
"kind": "call",
|
|
"targets": [
|
|
18682
|
|
],
|
|
"cycles": {
|
|
"cycles": 14,
|
|
"base_cycles": 9,
|
|
"alignment_adjustment": 1,
|
|
"stack_adjustment": 4,
|
|
"note": "PC word push to stack",
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9974,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R0",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R1",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R2",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R3",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R4",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R5",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R6",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "register",
|
|
"name": "R7",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "BR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "EP",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "DP",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "TP",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "SR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "call"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"call clobbers tracked register state"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 9988,
|
|
"address_region": "program_or_external",
|
|
"bytes": "19",
|
|
"text": "RTS",
|
|
"mnemonic": "RTS",
|
|
"operands": "",
|
|
"kind": "return",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 12,
|
|
"base_cycles": 8,
|
|
"stack_adjustment": 4,
|
|
"note": "PC word pop from stack",
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 9974,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
}
|
|
],
|
|
"decompiler_consistency": {
|
|
"kind": "decompiler_pseudocode_consistency",
|
|
"summary": "No byte-immediate-to-word destination cases found.",
|
|
"checks": []
|
|
},
|
|
"serial_semantics": {
|
|
"kind": "serial_semantics",
|
|
"protocol_semantics": [],
|
|
"fields": [],
|
|
"command_dispatch": null,
|
|
"commands": [],
|
|
"command_effects": [],
|
|
"response_candidates": [],
|
|
"response_schemas": [],
|
|
"response_schema": [],
|
|
"logical_table_map_candidates": [],
|
|
"table_map_candidates": [],
|
|
"state_variable_candidates": [],
|
|
"retry_error_model": null,
|
|
"gate_queue_model": null,
|
|
"tx_report_model": null,
|
|
"periodic_resend_model": null,
|
|
"timer_interrupt_model": null,
|
|
"confidence": "low",
|
|
"confidence_score": 0.0,
|
|
"caveat": "No protocol semantics are emitted without both RX and TX serial reconstruction candidates."
|
|
}
|
|
} |