179 lines
7.0 KiB
Python
179 lines
7.0 KiB
Python
from __future__ import annotations
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from dataclasses import dataclass
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from typing import Iterable
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from ..formatting import h16
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from ..memory import MEMORY_REGIONS, MemoryRegion, region_for
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from ..rom import Rom
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from .constants import (
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ON_CHIP_RAM_END,
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ON_CHIP_RAM_START,
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P7DDR,
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P7DR,
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P9DDR,
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P9DR,
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REGISTER_FIELD_END,
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REGISTER_FIELD_START,
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SCI1_BRR,
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SCI1_RDR,
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SCI1_SCR,
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SCI1_SMR,
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SCI1_SSR,
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SCI1_TDR,
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)
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from .peripherals.lcd import LCD, LCD_E_CLOCK_DATA, LCD_E_CLOCK_STATUS
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from .peripherals.p9_bus import P9Bus
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from .peripherals.x24164 import factory_default_words_from_rom
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from .sci import SCI1
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@dataclass
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class MemoryAccess:
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address: int
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size: int
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value: int
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kind: str
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region: str
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class MemoryMap:
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def __init__(self, rom_bytes: bytes, sci1: SCI1 | None = None, *, p7_input: int = 0xFF) -> None:
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self.rom = Rom(rom_bytes, base=0)
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self.sci1 = sci1 if sci1 is not None else SCI1()
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self.lcd = LCD()
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self.p9_bus = P9Bus()
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self.ram = bytearray(ON_CHIP_RAM_END - ON_CHIP_RAM_START + 1)
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self.registers = bytearray(REGISTER_FIELD_END - REGISTER_FIELD_START + 1)
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self.external: dict[int, int] = {}
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self.port_inputs: dict[int, int] = {P7DR: p7_input & 0xFF}
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self.access_log: list[MemoryAccess] = []
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self._set_register(SCI1_SMR, self.sci1.smr)
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self._set_register(SCI1_BRR, self.sci1.brr)
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self._set_register(SCI1_SCR, self.sci1.scr)
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self._set_register(SCI1_TDR, self.sci1.tdr)
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self._set_register(SCI1_SSR, self.sci1.ssr)
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self._set_register(SCI1_RDR, self.sci1.rdr)
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def region(self, address: int) -> MemoryRegion:
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return region_for(address & 0xFFFF)
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def read8(self, address: int) -> int:
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address &= 0xFFFF
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if address in (SCI1_SMR, SCI1_BRR, SCI1_SCR, SCI1_TDR, SCI1_SSR, SCI1_RDR):
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value = self.sci1.read(address)
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self._set_register(address, value)
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elif address == LCD_E_CLOCK_STATUS:
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value = self.lcd.read_status()
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elif address == LCD_E_CLOCK_DATA:
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value = self.lcd.read_data()
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elif address == P7DR:
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value = self._read_port_data(P7DDR, P7DR)
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elif address in self.external:
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value = self.external[address]
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elif ON_CHIP_RAM_START <= address <= ON_CHIP_RAM_END:
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value = self.ram[address - ON_CHIP_RAM_START]
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elif address == P9DDR:
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value = self.p9_bus.read_ddr()
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self._set_register(address, value)
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elif address == P9DR:
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value = self.p9_bus.read_dr()
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elif REGISTER_FIELD_START <= address <= REGISTER_FIELD_END:
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value = self.registers[address - REGISTER_FIELD_START]
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elif self.rom.contains(address):
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value = self.rom.u8(address)
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else:
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value = self.external.get(address, 0xFF)
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self._log("read", address, 1, value)
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return value
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def read16(self, address: int) -> int:
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high = self.read8(address)
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low = self.read8((address + 1) & 0xFFFF)
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return (high << 8) | low
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def write8(self, address: int, value: int) -> None:
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address &= 0xFFFF
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value &= 0xFF
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if address in (SCI1_SMR, SCI1_BRR, SCI1_SCR, SCI1_TDR, SCI1_SSR, SCI1_RDR):
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self.sci1.write(address, value)
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self._set_register(address, self.sci1.read(address))
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elif address == LCD_E_CLOCK_STATUS:
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self.lcd.write_command(value)
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self.external[address] = value
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elif address == LCD_E_CLOCK_DATA:
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self.lcd.write_data(value)
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self.external[address] = value
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elif ON_CHIP_RAM_START <= address <= ON_CHIP_RAM_END:
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self.ram[address - ON_CHIP_RAM_START] = value
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elif address in (P7DDR, P7DR):
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self._set_register(address, value)
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elif address == P9DDR:
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self._set_register(address, self.p9_bus.write_ddr(value))
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elif address == P9DR:
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self._set_register(address, self.p9_bus.write_dr(value))
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elif REGISTER_FIELD_START <= address <= REGISTER_FIELD_END:
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self._set_register(address, value)
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elif self.rom.contains(address):
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# The ROM image spans the whole address space, but the H8/536 map
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# can place external RAM/peripherals in these ranges. Keep writes
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# as external overrides while leaving instruction fetch immutable.
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self.external[address] = value
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else:
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self.external[address] = value
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self._log("write", address, 1, value)
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def write16(self, address: int, value: int) -> None:
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self.write8(address, (value >> 8) & 0xFF)
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self.write8((address + 1) & 0xFFFF, value & 0xFF)
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def inject_sci1_rx_byte(self, value: int) -> None:
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self.sci1.inject_rx(value)
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self._set_register(SCI1_RDR, self.sci1.read(SCI1_RDR))
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self._set_register(SCI1_SSR, self.sci1.read(SCI1_SSR))
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def register8(self, address: int) -> int:
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return self.registers[(address & 0xFFFF) - REGISTER_FIELD_START]
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def register16(self, address: int) -> int:
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address &= 0xFFFF
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return (self.register8(address) << 8) | self.register8((address + 1) & 0xFFFF)
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def set_register8(self, address: int, value: int) -> None:
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self._set_register(address & 0xFFFF, value)
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def set_register16(self, address: int, value: int) -> None:
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address &= 0xFFFF
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self._set_register(address, (value >> 8) & 0xFF)
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self._set_register((address + 1) & 0xFFFF, value & 0xFF)
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def set_port_input(self, data_register: int, value: int, *, mask: int = 0xFF) -> None:
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data_register &= 0xFFFF
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old = self.port_inputs.get(data_register, 0xFF)
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self.port_inputs[data_register] = ((old & ~mask) | (value & mask)) & 0xFF
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def seed_factory_eeprom_and_shadow(self) -> None:
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for offset, word in factory_default_words_from_rom(self.rom.data):
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address = 0xF400 + offset
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self.external[address & 0xFFFF] = (word >> 8) & 0xFF
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self.external[(address + 1) & 0xFFFF] = word & 0xFF
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self.p9_bus.x24164_bus.seed_factory_defaults_from_rom(self.rom.data)
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self.p9_bus.clear_x24164_trace()
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def _set_register(self, address: int, value: int) -> None:
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self.registers[address - REGISTER_FIELD_START] = value & 0xFF
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def _read_port_data(self, direction_register: int, data_register: int) -> int:
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ddr = self.registers[direction_register - REGISTER_FIELD_START]
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latch = self.registers[data_register - REGISTER_FIELD_START]
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pins = self.port_inputs.get(data_register, 0xFF)
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return ((latch & ddr) | (pins & ~ddr)) & 0xFF
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def _log(self, kind: str, address: int, size: int, value: int) -> None:
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self.access_log.append(MemoryAccess(address, size, value, kind, self.region(address).name))
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def describe_regions(regions: Iterable[MemoryRegion] = MEMORY_REGIONS) -> str:
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return "\n".join(f"{h16(region.start)}-{h16(region.end)} {region.name} {region.kind}" for region in regions)
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