645 lines
25 KiB
Python
645 lines
25 KiB
Python
from __future__ import annotations
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from dataclasses import dataclass, field
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from ..decoder import H8536Decoder
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from ..formatting import h16
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from ..rom import DecodeError
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from ..vectors import read_vectors_min
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from .constants import (
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FRT_TCR_OCIEA,
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FRT_TCSR_OCFA,
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FRT1_TCR,
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FRT1_TCSR,
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FRT2_TCR,
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FRT2_TCSR,
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IPRA,
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IPRC,
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IPRE,
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SCI_SCR_TIE,
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SCI_SSR_TDRE,
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VECTOR_FRT1_OCIA,
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VECTOR_FRT2_OCIA,
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VECTOR_INTERVAL_TIMER,
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VECTOR_SCI1_TXI,
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)
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from .cpu import CPUState, mask, s8, s16, sign_bit
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from .errors import EmulatorError, UnsupportedInstruction
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from .fast_paths import P9FastPath, P9FastPathConfig
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from .memory import MemoryMap
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from .sci import SCI1
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@dataclass
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class RunReport:
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steps: int
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cycles: int
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pc: int
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stopped_reason: str
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tx_bytes: bytes
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tx_frames: list[bytes]
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heartbeat_seen: bool
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unsupported: str | None = None
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trace: list[str] = field(default_factory=list)
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def summary_lines(self) -> list[str]:
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lines = [
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f"steps={self.steps}",
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f"cycles={self.cycles}",
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f"pc={h16(self.pc)}",
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f"stopped={self.stopped_reason}",
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"tx_bytes=" + self.tx_bytes.hex(" ").upper(),
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"tx_frames=" + ", ".join(frame.hex(" ").upper() for frame in self.tx_frames),
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f"heartbeat_seen={self.heartbeat_seen}",
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]
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if self.unsupported:
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lines.append(f"unsupported={self.unsupported}")
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lines.append(
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"next_todo=implement the stopped opcode, then add interrupt scheduling for SCI1 TXI and interval/watchdog timer overflow"
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)
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return lines
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class H8536Emulator:
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def __init__(
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self,
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rom_bytes: bytes,
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*,
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interval_steps: int = 2048,
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frt1_ocia_steps: int = 1024,
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frt2_ocia_steps: int = 1024,
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p9_fast_path: P9FastPath | None = None,
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p9_fast_path_enabled: bool = False,
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p9_fast_default_input_byte: int = 0xFF,
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) -> None:
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if not rom_bytes:
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raise ValueError("ROM image is empty")
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self.sci1 = SCI1()
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self.memory = MemoryMap(rom_bytes, self.sci1)
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self.p9_fast_path = p9_fast_path or P9FastPath(
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P9FastPathConfig(enabled=p9_fast_path_enabled, default_input_byte=p9_fast_default_input_byte)
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)
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self.cpu = CPUState()
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self.vectors = read_vectors_min(self.memory.rom)
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self.interval_steps = max(1, interval_steps)
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self.frt1_ocia_steps = max(1, frt1_ocia_steps)
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self.frt2_ocia_steps = max(1, frt2_ocia_steps)
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self._interval_counter = 0
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self._frt1_ocia_counter = 0
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self._frt2_ocia_counter = 0
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self.reset()
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def reset(self) -> None:
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self.cpu = CPUState(pc=self.reset_vector())
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def reset_vector(self) -> int:
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if self.memory.rom.contains(0, 2):
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return self.memory.rom.u16(0)
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raise DecodeError("ROM does not contain a reset vector at H'0000")
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def step(self) -> str:
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pc = self.cpu.pc
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if self.p9_fast_path.try_handle(self):
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self._tick_peripherals()
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return f"{h16(pc)}: {'<p9-fast-path>':<17} P9 fast-path"
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decoder = H8536Decoder(self.memory.rom, br=self.cpu.br)
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ins = decoder.decode(pc)
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if not ins.valid:
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raise UnsupportedInstruction(pc, ins.raw, ins.text)
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next_pc = (pc + ins.size) & 0xFFFF
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raw = ins.raw
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text = ins.text
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if raw[0] == 0x00:
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pass
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elif raw[0] == 0x02 and len(raw) == 2:
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self._pop_register_mask(raw[1])
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elif raw[0] == 0x12 and len(raw) == 2:
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self._push_register_mask(raw[1])
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elif raw[0] in (0x01, 0x06, 0x07) and len(raw) == 3 and 0xB8 <= raw[1] <= 0xBF:
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next_pc = self._scb(raw, pc, next_pc)
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elif raw[0] in (0x04, 0x0C):
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next_pc = self._execute_general(pc, next_pc)
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elif 0x40 <= raw[0] <= 0x47 and len(raw) == 2:
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reg = raw[0] & 0x07
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self._cmp(self._reg_read(reg, 1), raw[1], 1)
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elif 0x48 <= raw[0] <= 0x4F and len(raw) == 3:
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reg = raw[0] & 0x07
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self._cmp(self.cpu.regs[reg], int.from_bytes(raw[1:3], "big"), 2)
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elif 0x50 <= raw[0] <= 0x57 and len(raw) == 2:
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self._reg_write(raw[0] & 0x07, raw[1], 1)
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self._set_logic_flags(raw[1], 1)
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elif 0x58 <= raw[0] <= 0x5F and len(raw) == 3:
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self.cpu.regs[raw[0] & 0x07] = int.from_bytes(raw[1:3], "big")
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self._set_logic_flags(self.cpu.regs[raw[0] & 0x07], 2)
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elif raw[0] in (0x0E, 0x1E, 0x18):
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next_pc = self._direct_call(raw, next_pc)
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elif raw[0] == 0x19:
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next_pc = self._pop16()
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elif raw[0] == 0x0A:
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next_pc = self._return_from_interrupt()
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elif raw[0] in (0x15, 0x1D) and len(raw) >= 4:
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next_pc = self._execute_general(pc, next_pc)
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elif raw[0] in range(0xA0, 0x100):
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next_pc = self._execute_general(pc, next_pc)
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elif raw[0] in range(0x20, 0x30) and len(raw) == 2:
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next_pc = self._branch8(raw, pc, next_pc)
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elif raw[0] in range(0x30, 0x40) and len(raw) == 3:
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next_pc = self._branch16(raw, pc, next_pc)
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else:
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raise UnsupportedInstruction(pc, raw, text)
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self.cpu.pc = next_pc
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self.cpu.steps += 1
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self.cpu.cycles += self._rough_cycles(raw)
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self._tick_peripherals()
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return f"{h16(pc)}: {' '.join(f'{byte:02X}' for byte in raw):<17} {text}"
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def run(self, max_steps: int, trace: bool = False, stop_on_heartbeat: bool = False) -> RunReport:
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trace_lines: list[str] = []
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stopped_reason = "max_steps"
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unsupported: str | None = None
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for _ in range(max_steps):
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try:
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line = self.step()
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except UnsupportedInstruction as exc:
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stopped_reason = "unsupported_instruction"
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unsupported = str(exc)
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break
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if trace:
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trace_lines.append(line)
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if stop_on_heartbeat and self.sci1.saw_heartbeat():
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stopped_reason = "heartbeat"
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break
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return RunReport(
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steps=self.cpu.steps,
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cycles=self.cpu.cycles,
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pc=self.cpu.pc,
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stopped_reason=stopped_reason,
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tx_bytes=bytes(self.sci1.tx_bytes),
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tx_frames=list(self.sci1.tx_frames),
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heartbeat_seen=self.sci1.saw_heartbeat(),
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unsupported=unsupported,
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trace=trace_lines,
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)
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def _execute_general(self, pc: int, next_pc: int) -> int:
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ea = self._decode_ea(pc)
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op = self.memory.rom.u8(pc + int(ea["length"]))
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size = int(ea["size"])
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raw = self.memory.rom.slice(pc, self._general_length(pc, ea, op))
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if op == 0x00:
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ext = self.memory.rom.u8(pc + int(ea["length"]) + 1)
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ext_base = ext & 0xF8
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reg = ext & 0x07
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if ext_base == 0x80:
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value = self._read_ea(ea, 1)
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self._reg_write(reg, value, 1)
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self._set_logic_flags(value, 1)
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elif ext_base == 0x90:
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self._write_ea(ea, self._reg_read(reg, 1), 1)
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else:
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raise UnsupportedInstruction(pc, raw, H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
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return next_pc
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if op in (0x06, 0x07):
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value = raw[-1] if op == 0x06 else int.from_bytes(raw[-2:], "big")
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self._write_ea(ea, value, 1 if op == 0x06 else 2)
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self._set_logic_flags(value, 1 if op == 0x06 else 2)
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return next_pc
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base = op & 0xF8
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rd = op & 0x07
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if ea["mode"] == "imm" and base in (0x48, 0x58, 0x68):
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value = self._read_ea(ea, size)
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if base == 0x48:
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self.cpu.sr |= value
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elif base == 0x58:
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self.cpu.sr &= value
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else:
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self.cpu.sr ^= value
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elif base == 0x80:
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value = self._read_ea(ea, size)
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self._reg_write(rd, value, size)
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self._set_logic_flags(value, size)
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elif base == 0x90:
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self._write_ea(ea, self._reg_read(rd, size), size)
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elif base == 0x20:
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lhs = self._reg_read(rd, size)
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rhs = self._read_ea(ea, size)
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result = lhs + rhs
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self._reg_write(rd, result, size)
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self._set_add_flags(lhs, rhs, result, size)
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elif base == 0x30:
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lhs = self._reg_read(rd, size)
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rhs = self._read_ea(ea, size)
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result = lhs - rhs
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self._reg_write(rd, result, size)
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self._set_sub_flags(lhs, rhs, result, size)
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elif base == 0x50:
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result = self._reg_read(rd, size) & self._read_ea(ea, size)
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self._reg_write(rd, result, size)
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self._set_logic_flags(result, size)
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elif base == 0x40:
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result = self._reg_read(rd, size) | self._read_ea(ea, size)
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self._reg_write(rd, result, size)
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self._set_logic_flags(result, size)
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elif base == 0x60:
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result = self._reg_read(rd, size) ^ self._read_ea(ea, size)
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self._reg_write(rd, result, size)
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self._set_logic_flags(result, size)
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elif base == 0x70:
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self._cmp(self._reg_read(rd, size), self._read_ea(ea, size), size)
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elif base == 0xA8:
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if size != 1:
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raise UnsupportedInstruction(pc, raw, H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
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result = (self._reg_read(rd, 1) * self._read_ea(ea, 1)) & 0xFFFF
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self.cpu.regs[rd] = result
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self._set_logic_flags(result, 2)
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self.cpu.c = False
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elif op in (0x08, 0x09, 0x0C, 0x0D):
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delta = {0x08: 1, 0x09: 2, 0x0C: -1, 0x0D: -2}[op]
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old = self._read_ea(ea, size)
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result = old + delta
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self._write_ea(ea, result, size)
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if delta >= 0:
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self._set_add_flags(old, delta, result, size)
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else:
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self._set_sub_flags(old, -delta, result, size)
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elif op == 0x13:
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self._write_ea(ea, 0, size)
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self._set_logic_flags(0, size)
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elif op == 0x15:
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result = (~self._read_ea(ea, size)) & mask(size)
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self._write_ea(ea, result, size)
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self._set_logic_flags(result, size)
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elif op == 0x16:
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self._set_logic_flags(self._read_ea(ea, size), size)
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elif op in (0x10, 0x11, 0x12) and ea["mode"] == "reg" and size == 1:
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reg = int(ea["reg"])
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value = self.cpu.regs[reg] & 0xFFFF
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if op == 0x10:
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result = ((value & 0x00FF) << 8) | ((value >> 8) & 0x00FF)
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elif op == 0x11:
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result = s8(value & 0xFF) & 0xFFFF
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else:
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result = value & 0x00FF
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self.cpu.regs[reg] = result
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self._set_logic_flags(result, 2)
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elif op == 0x1A:
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value = self._read_ea(ea, size)
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result = (value << 1) & mask(size)
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self.cpu.c = bool(value & sign_bit(size))
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self._write_ea(ea, result, size)
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self._set_logic_flags(result, size)
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elif op == 0x1B:
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value = self._read_ea(ea, size)
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result = value >> 1
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self.cpu.c = bool(value & 1)
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self._write_ea(ea, result, size)
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self._set_logic_flags(result, size)
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elif 0xC0 <= op <= 0xFF:
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bit = op & 0x0F
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self._bit_operation(ea, size, op & 0xF0, bit)
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elif base in (0x48, 0x58, 0x68, 0x78):
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bit = self._reg_read(rd, 1) & 0x0F
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self._bit_operation(ea, size, base + 0x80, bit)
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elif base == 0x88:
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value = self._read_ea(ea, size)
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if size == 2 and rd == 0:
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self.cpu.sr = value & 0xFFFF
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elif size == 1 and rd == 1:
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self.cpu.br = value & 0xFF
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else:
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raise UnsupportedInstruction(pc, raw, H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
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elif base == 0x98:
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if size == 2 and rd == 0:
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self._write_ea(ea, self.cpu.sr, 2)
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elif size == 1 and rd == 1:
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self._write_ea(ea, self.cpu.br, 1)
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else:
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raise UnsupportedInstruction(pc, raw, H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
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elif op in (0x04, 0x05):
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compare_size = 1 if op == 0x04 else 2
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immediate = raw[-1] if op == 0x04 else int.from_bytes(raw[-2:], "big")
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self._cmp(self._read_ea(ea, compare_size), immediate, compare_size)
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else:
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raise UnsupportedInstruction(pc, raw, H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
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return next_pc
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def _branch8(self, raw: bytes, pc: int, next_pc: int) -> int:
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cond = raw[0] & 0x0F
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disp = s8(raw[1])
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target = (pc + 2 + disp) & 0xFFFF
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if self._branch_condition(cond):
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return target
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return next_pc
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def _branch16(self, raw: bytes, pc: int, next_pc: int) -> int:
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cond = raw[0] & 0x0F
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disp = s16(int.from_bytes(raw[1:3], "big"))
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target = (pc + 3 + disp) & 0xFFFF
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if self._branch_condition(cond):
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return target
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return next_pc
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def _rough_cycles(self, raw: bytes) -> int:
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if raw[0] in (0x15, 0x1D):
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return 9
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if raw[0] in (0x0E, 0x1E, 0x18):
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return 14
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if raw[0] in (0x19, 0x0A):
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return 12
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if raw[0] in range(0x20, 0x40):
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return 8 if (raw[0] & 0x0F) == 0 else 4
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return 3
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def _direct_call(self, raw: bytes, next_pc: int) -> int:
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self._push16(next_pc)
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if raw[0] == 0x0E:
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return (next_pc + s8(raw[1])) & 0xFFFF
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if raw[0] == 0x1E:
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return (next_pc + s16(int.from_bytes(raw[1:3], "big"))) & 0xFFFF
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return int.from_bytes(raw[1:3], "big")
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def _scb(self, raw: bytes, pc: int, next_pc: int) -> int:
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reg = raw[1] & 0x07
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condition = {0x01: False, 0x06: not self.cpu.z, 0x07: self.cpu.z}[raw[0]]
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if condition:
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return next_pc
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value = (self.cpu.regs[reg] - 1) & 0xFFFF
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self.cpu.regs[reg] = value
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self.cpu.z = value == 0
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if value != 0:
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return (pc + 3 + s8(raw[2])) & 0xFFFF
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return next_pc
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def _tick_peripherals(self) -> None:
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self.sci1.tick()
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self._interval_counter += 1
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self._frt1_ocia_counter += 1
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self._frt2_ocia_counter += 1
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self._service_pending_interrupt()
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def _service_pending_interrupt(self) -> None:
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if self.cpu.interrupt_depth:
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return
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candidates: list[tuple[int, int, str]] = []
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if self.sci1.scr & SCI_SCR_TIE and self.sci1.ssr & SCI_SSR_TDRE:
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target = self._vector_target(VECTOR_SCI1_TXI)
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if target is not None:
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candidates.append((self._sci1_priority(), target, "sci1_txi"))
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if self._interval_counter >= self.interval_steps:
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target = self._vector_target(VECTOR_INTERVAL_TIMER)
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if target is not None:
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candidates.append((self._interval_priority(), target, "interval_timer"))
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if self._frt1_ocia_pending():
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target = self._vector_target(VECTOR_FRT1_OCIA)
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if target is not None:
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candidates.append((self._frt1_priority(), target, "frt1_ocia"))
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if self._frt2_ocia_pending():
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target = self._vector_target(VECTOR_FRT2_OCIA)
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if target is not None:
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candidates.append((self._frt2_priority(), target, "frt2_ocia"))
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if not candidates:
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return
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priority, target, source = max(candidates, key=lambda item: item[0])
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if priority <= self._interrupt_mask():
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return
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if source == "interval_timer":
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self._interval_counter = 0
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elif source == "frt1_ocia":
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self._frt1_ocia_counter = 0
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self.memory.write8(FRT1_TCSR, self.memory.read8(FRT1_TCSR) | FRT_TCSR_OCFA)
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elif source == "frt2_ocia":
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self._frt2_ocia_counter = 0
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self.memory.write8(FRT2_TCSR, self.memory.read8(FRT2_TCSR) | FRT_TCSR_OCFA)
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self._enter_interrupt(target)
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def _enter_interrupt(self, target: int) -> None:
|
|
self._push16(self.cpu.sr)
|
|
self._push16(self.cpu.pc)
|
|
self.cpu.pc = target & 0xFFFF
|
|
self.cpu.interrupt_depth += 1
|
|
|
|
def _return_from_interrupt(self) -> int:
|
|
pc = self._pop16()
|
|
self.cpu.sr = self._pop16()
|
|
if self.cpu.interrupt_depth:
|
|
self.cpu.interrupt_depth -= 1
|
|
return pc
|
|
|
|
def _vector_target(self, vector_address: int) -> int | None:
|
|
entry = self.vectors.get(vector_address)
|
|
return entry[1] if entry else None
|
|
|
|
def _interrupt_mask(self) -> int:
|
|
return (self.cpu.sr >> 8) & 0x07
|
|
|
|
def _sci1_priority(self) -> int:
|
|
return (self.memory.read8(IPRE) >> 4) & 0x07
|
|
|
|
def _interval_priority(self) -> int:
|
|
return (self.memory.read8(IPRA) >> 4) & 0x07
|
|
|
|
def _frt1_ocia_pending(self) -> bool:
|
|
if self._frt1_ocia_counter < self.frt1_ocia_steps:
|
|
return False
|
|
return bool(self.memory.read8(FRT1_TCR) & FRT_TCR_OCIEA)
|
|
|
|
def _frt1_priority(self) -> int:
|
|
return (self.memory.read8(IPRC) >> 4) & 0x07
|
|
|
|
def _frt2_ocia_pending(self) -> bool:
|
|
if self._frt2_ocia_counter < self.frt2_ocia_steps:
|
|
return False
|
|
return bool(self.memory.read8(FRT2_TCR) & FRT_TCR_OCIEA)
|
|
|
|
def _frt2_priority(self) -> int:
|
|
# H8/536 IPRC assigns bits 6..4 to FRT1 and bits 2..0 to FRT2;
|
|
# the ROM's IPRC=H'66 therefore gives both timers priority 6.
|
|
return self.memory.read8(IPRC) & 0x07
|
|
|
|
def _push16(self, value: int) -> None:
|
|
sp = (self.cpu.regs[7] - 2) & 0xFFFF
|
|
self.cpu.regs[7] = sp
|
|
self.memory.write16(sp, value)
|
|
|
|
def _pop16(self) -> int:
|
|
sp = self.cpu.regs[7] & 0xFFFF
|
|
value = self.memory.read16(sp)
|
|
self.cpu.regs[7] = (sp + 2) & 0xFFFF
|
|
return value
|
|
|
|
def _push_register_mask(self, mask_value: int) -> None:
|
|
for reg in range(8):
|
|
if mask_value & (1 << reg):
|
|
self._push16(self.cpu.regs[reg])
|
|
|
|
def _pop_register_mask(self, mask_value: int) -> None:
|
|
for reg in reversed(range(8)):
|
|
if mask_value & (1 << reg):
|
|
self.cpu.regs[reg] = self._pop16()
|
|
|
|
def _decode_ea(self, pc: int) -> dict[str, int | str | None]:
|
|
first = self.memory.rom.u8(pc)
|
|
if 0xA0 <= first <= 0xAF:
|
|
return {"mode": "reg", "reg": first & 0x07, "size": 2 if first & 0x08 else 1, "length": 1, "value": None}
|
|
if 0xB0 <= first <= 0xBF:
|
|
return {"mode": "predec", "reg": first & 0x07, "size": 2 if first & 0x08 else 1, "length": 1, "value": None}
|
|
if 0xC0 <= first <= 0xCF:
|
|
return {"mode": "postinc", "reg": first & 0x07, "size": 2 if first & 0x08 else 1, "length": 1, "value": None}
|
|
if 0xD0 <= first <= 0xDF:
|
|
return {"mode": "indirect", "reg": first & 0x07, "size": 2 if first & 0x08 else 1, "length": 1, "value": None}
|
|
if 0xE0 <= first <= 0xEF:
|
|
return {"mode": "disp", "reg": first & 0x07, "size": 2 if first & 0x08 else 1, "length": 2, "value": s8(self.memory.rom.u8(pc + 1))}
|
|
if 0xF0 <= first <= 0xFF:
|
|
return {"mode": "disp", "reg": first & 0x07, "size": 2 if first & 0x08 else 1, "length": 3, "value": s16(self.memory.rom.u16(pc + 1))}
|
|
if first in (0x04, 0x0C):
|
|
size = 2 if first == 0x0C else 1
|
|
value = self.memory.rom.u16(pc + 1) if size == 2 else self.memory.rom.u8(pc + 1)
|
|
return {"mode": "imm", "reg": None, "size": size, "length": 3 if size == 2 else 2, "value": value}
|
|
if first in (0x15, 0x1D):
|
|
return {"mode": "abs16", "reg": None, "size": 2 if first == 0x1D else 1, "length": 3, "value": self.memory.rom.u16(pc + 1)}
|
|
raise UnsupportedInstruction(pc, self.memory.rom.slice(pc, 1), H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
|
|
|
|
def _general_length(self, pc: int, ea: dict[str, int | str | None], op: int) -> int:
|
|
length = int(ea["length"]) + 1
|
|
if op == 0x00:
|
|
return length + 1
|
|
if op == 0x06:
|
|
return length + 1
|
|
if op in (0x07, 0x05):
|
|
return length + 2
|
|
if op == 0x04:
|
|
return length + 1
|
|
return length
|
|
|
|
def _ea_address(self, ea: dict[str, int | str | None], size: int, *, write: bool = False) -> int:
|
|
mode = ea["mode"]
|
|
reg = ea.get("reg")
|
|
if mode == "abs16":
|
|
return int(ea["value"]) & 0xFFFF
|
|
if mode == "indirect":
|
|
return self.cpu.regs[int(reg)] & 0xFFFF
|
|
if mode == "disp":
|
|
return (self.cpu.regs[int(reg)] + int(ea["value"])) & 0xFFFF
|
|
if mode == "predec":
|
|
self.cpu.regs[int(reg)] = (self.cpu.regs[int(reg)] - size) & 0xFFFF
|
|
return self.cpu.regs[int(reg)]
|
|
if mode == "postinc":
|
|
address = self.cpu.regs[int(reg)] & 0xFFFF
|
|
if not write:
|
|
self.cpu.regs[int(reg)] = (self.cpu.regs[int(reg)] + size) & 0xFFFF
|
|
return address
|
|
raise EmulatorError(f"EA mode {mode} does not have an address")
|
|
|
|
def _read_ea(self, ea: dict[str, int | str | None], size: int) -> int:
|
|
mode = ea["mode"]
|
|
if mode == "imm":
|
|
return int(ea["value"]) & mask(size)
|
|
if mode == "reg":
|
|
return self._reg_read(int(ea["reg"]), size)
|
|
address = self._ea_address(ea, size)
|
|
return self.memory.read16(address) if size == 2 else self.memory.read8(address)
|
|
|
|
def _write_ea(self, ea: dict[str, int | str | None], value: int, size: int) -> None:
|
|
if ea["mode"] == "reg":
|
|
self._reg_write(int(ea["reg"]), value, size)
|
|
return
|
|
address = self._ea_address(ea, size, write=True)
|
|
if size == 2:
|
|
self.memory.write16(address, value)
|
|
else:
|
|
self.memory.write8(address, value)
|
|
|
|
def _reg_read(self, reg: int, size: int) -> int:
|
|
value = self.cpu.regs[reg] & 0xFFFF
|
|
return value if size == 2 else value & 0xFF
|
|
|
|
def _reg_write(self, reg: int, value: int, size: int) -> None:
|
|
if size == 2:
|
|
self.cpu.regs[reg] = value & 0xFFFF
|
|
else:
|
|
self.cpu.regs[reg] = (self.cpu.regs[reg] & 0xFF00) | (value & 0xFF)
|
|
|
|
def _cmp(self, lhs: int, rhs: int, size: int) -> None:
|
|
self._set_sub_flags(lhs, rhs, lhs - rhs, size)
|
|
|
|
def _set_logic_flags(self, value: int, size: int) -> None:
|
|
value &= mask(size)
|
|
self.cpu.z = value == 0
|
|
self.cpu.n = bool(value & sign_bit(size))
|
|
self.cpu.v = False
|
|
|
|
def _set_add_flags(self, lhs: int, rhs: int, result: int, size: int) -> None:
|
|
max_value = mask(size)
|
|
sign = sign_bit(size)
|
|
result &= max_value
|
|
lhs &= max_value
|
|
rhs &= max_value
|
|
self.cpu.z = result == 0
|
|
self.cpu.n = bool(result & sign)
|
|
self.cpu.c = lhs + rhs > max_value
|
|
self.cpu.v = bool((~(lhs ^ rhs) & (lhs ^ result) & sign) != 0)
|
|
|
|
def _set_sub_flags(self, lhs: int, rhs: int, result: int, size: int) -> None:
|
|
max_value = mask(size)
|
|
sign = sign_bit(size)
|
|
result &= max_value
|
|
lhs &= max_value
|
|
rhs &= max_value
|
|
self.cpu.z = result == 0
|
|
self.cpu.n = bool(result & sign)
|
|
self.cpu.c = lhs < rhs
|
|
self.cpu.v = bool(((lhs ^ rhs) & (lhs ^ result) & sign) != 0)
|
|
|
|
def _bit_operation(self, ea: dict[str, int | str | None], size: int, op_base: int, bit: int) -> None:
|
|
value = self._read_ea(ea, size)
|
|
bit &= 15 if size == 2 else 7
|
|
bit_mask = 1 << bit
|
|
self.cpu.z = not bool(value & bit_mask)
|
|
if op_base == 0xC0:
|
|
self._write_ea(ea, value | bit_mask, size)
|
|
elif op_base == 0xD0:
|
|
self._write_ea(ea, value & ~bit_mask, size)
|
|
elif op_base == 0xE0:
|
|
self._write_ea(ea, value ^ bit_mask, size)
|
|
|
|
def _branch_condition(self, cond: int) -> bool:
|
|
if cond == 0x0:
|
|
return True
|
|
if cond == 0x1:
|
|
return False
|
|
if cond == 0x2:
|
|
return not self.cpu.c and not self.cpu.z
|
|
if cond == 0x3:
|
|
return self.cpu.c or self.cpu.z
|
|
if cond == 0x4:
|
|
return not self.cpu.c
|
|
if cond == 0x5:
|
|
return self.cpu.c
|
|
if cond == 0x6:
|
|
return not self.cpu.z
|
|
if cond == 0x7:
|
|
return self.cpu.z
|
|
if cond == 0x8:
|
|
return not self.cpu.v
|
|
if cond == 0x9:
|
|
return self.cpu.v
|
|
if cond == 0xA:
|
|
return not self.cpu.n
|
|
if cond == 0xB:
|
|
return self.cpu.n
|
|
if cond == 0xC:
|
|
return self.cpu.n == self.cpu.v
|
|
if cond == 0xD:
|
|
return self.cpu.n != self.cpu.v
|
|
if cond == 0xE:
|
|
return not self.cpu.z and self.cpu.n == self.cpu.v
|
|
return self.cpu.z or self.cpu.n != self.cpu.v
|