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UART simulation

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Aiden
2026-05-25 22:22:05 +10:00
parent 4b50d0e98f
commit c3eb09ddc8
8 changed files with 198 additions and 15 deletions
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5
h8536/emulator/sci.py
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@@ -105,6 +105,11 @@ class SCI1:
self.ssr = (self.ssr & (writable_zero_flags & value)) | (value & ~writable_zero_flags)
def inject_rx(self, value: int) -> None:
if self.ssr & SCI_SSR_ORER:
return
if self.ssr & SCI_SSR_RDRF:
self.ssr |= SCI_SSR_ORER
return
self.rdr = value & 0xFF
self.ssr |= SCI_SSR_RDRF