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UART simulation

This commit is contained in:
Aiden
2026-05-25 22:22:05 +10:00
parent 4b50d0e98f
commit c3eb09ddc8
8 changed files with 198 additions and 15 deletions

View File

@@ -58,6 +58,7 @@ from .memory import MemoryAccess, MemoryMap, describe_regions
from .peripherals import LCD
from .runner import H8536Emulator, RunReport
from .sci import SCI1, SciTxEvent
from .uart import UartTiming
__all__ = [
"CPUState",
@@ -114,6 +115,7 @@ __all__ = [
"SCI_SSR_TDRE",
"SciTxEvent",
"UnsupportedInstruction",
"UartTiming",
"VECTOR_FRT1_OCIA",
"VECTOR_INTERVAL_TIMER",
"VECTOR_FRT2_OCIA",