aiden/h8-536-decoder
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more serial improvements

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Aiden
2026-05-25 16:32:58 +10:00
parent 6ceed81765
commit 56829b6e0b
10 changed files with 16843 additions and 122 deletions
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12
build/rom_decompiled.asm
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@@ -3130,15 +3130,15 @@ loc_BB56:
BB56: 19 RTS ; cycles=12 BB56: 19 RTS ; cycles=12
vec_sci1_eri_BB57: vec_sci1_eri_BB57:
BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=8 BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; refs ram_FAA4 in on_chip_ram; cycles=8
BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; clear SCI1 overrun error flag (ORER); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; clear SCI1 overrun error flag (ORER); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8
BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; clear SCI1 framing error flag (FER); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; clear SCI1 framing error flag (FER); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8
BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; clear SCI1 parity error flag (PER); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; clear SCI1 parity error flag (PER); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8
vec_sci1_rxi_BB67: vec_sci1_rxi_BB67:
BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12
BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 receive-data-full flag (RDRF); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 receive-data-full flag (RDRF); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8
BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR in register_field; cycles=6 BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR in register_field; cycles=6
BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=6 BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=6
BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t
BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8

14914
build/rom_decompiled.json
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File diff suppressed because it is too large Load Diff

12
build/rom_pseudocode.c
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@@ -2944,18 +2944,18 @@ loc_BB56:
void vec_sci1_eri_BB57(void) void vec_sci1_eri_BB57(void)
{ {
/* vector sources: sci1_eri */ /* vector sources: sci1_eri */
MEM8[0xFAA4] |= BIT(7); /* BB57; BSET.B #7, @H'FAA4; refs ram_FAA4; cycles=8 */ MEM8[0xFAA4] |= BIT(7); /* BB57; BSET.B #7, @H'FAA4; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; refs ram_FAA4; cycles=8 */
SCI1_SSR &= ~BIT(5); /* BB5B; BCLR.B #5, @SCI1_SSR; clear ORER (bit 5) of SCI1_SSR; clear SCI1 overrun error flag (ORER); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */ SCI1_SSR &= ~BIT(5); /* BB5B; BCLR.B #5, @SCI1_SSR; clear ORER (bit 5) of SCI1_SSR; clear SCI1 overrun error flag (ORER); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */
SCI1_SSR &= ~BIT(4); /* BB5F; BCLR.B #4, @SCI1_SSR; clear FER (bit 4) of SCI1_SSR; clear SCI1 framing error flag (FER); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */ SCI1_SSR &= ~BIT(4); /* BB5F; BCLR.B #4, @SCI1_SSR; clear FER (bit 4) of SCI1_SSR; clear SCI1 framing error flag (FER); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */
SCI1_SSR &= ~BIT(3); /* BB63; BCLR.B #3, @SCI1_SSR; clear PER (bit 3) of SCI1_SSR; clear SCI1 parity error flag (PER); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */ SCI1_SSR &= ~BIT(3); /* BB63; BCLR.B #3, @SCI1_SSR; clear PER (bit 3) of SCI1_SSR; clear SCI1 parity error flag (PER); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */
} }
void vec_sci1_rxi_BB67(void) void vec_sci1_rxi_BB67(void)
{ {
/* vector sources: sci1_rxi */ /* vector sources: sci1_rxi */
push_registers(R0, R1); /* BB67; STM.W {R0,R1}, @-SP; cycles=12 */ push_registers(R0, R1); /* BB67; STM.W {R0,R1}, @-SP; cycles=12 */
SCI1_SSR &= ~BIT(6); /* BB69; BCLR.B #6, @SCI1_SSR; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 receive-data-full flag (RDRF); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */ SCI1_SSR &= ~BIT(6); /* BB69; BCLR.B #6, @SCI1_SSR; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 receive-data-full flag (RDRF); candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR; cycles=8 */
R0 = (uint8_t)(SCI1_RDR); /* BB6D; MOV:G.B @SCI1_RDR, R0; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR; cycles=6 */ R0 = (uint8_t)(SCI1_RDR); /* BB6D; MOV:G.B @SCI1_RDR, R0; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR; cycles=6 */
set_flags_tst8(MEM8[0xF9C1]); /* BB71; TST.B @H'F9C1; refs ram_F9C1; cycles=6 */ set_flags_tst8(MEM8[0xF9C1]); /* BB71; TST.B @H'F9C1; refs ram_F9C1; cycles=6 */
if (!Z) goto loc_BB7D; /* BB75; BNE loc_BB7D; cycles=3/8 nt/t */ if (!Z) goto loc_BB7D; /* BB75; BNE loc_BB7D; cycles=3/8 nt/t */
MEM8[0xF9C3] = 0; /* BB77; CLR.B @H'F9C3; refs ram_F9C3; cycles=8 */ MEM8[0xF9C3] = 0; /* BB77; CLR.B @H'F9C3; refs ram_F9C3; cycles=8 */

94
build/rom_serial_pseudocode.c
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@@ -55,6 +55,12 @@
* - Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94 * - Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94
*/ */
/* SCI1 link layer:
* - 8E1 SCI characters carry the 6 protocol bytes; async 8-bit even parity 1 stop, clock internal, SMR=H'24, BRR=H'07, SCR=H'3C
* - baud is clock-dependent; pass --clock-hz on the decompiler for bps.
* - No SCI1 RXI/TXI DTC vector entries are present in JSON; RX/TX are modeled as CPU ISR paths.
*/
#include <stdbool.h> #include <stdbool.h>
#include <stdint.h> #include <stdint.h>
@@ -88,6 +94,8 @@ extern volatile u8 MEM8[0x10000];
#define RX_INDEX MEM8[0xF9C3u] #define RX_INDEX MEM8[0xF9C3u]
#define RX_INTERBYTE_TIMEOUT MEM8[0xF9C1u] #define RX_INTERBYTE_TIMEOUT MEM8[0xF9C1u]
#define RX_COMPLETE_TIMER MEM8[0xF9C5u] #define RX_COMPLETE_TIMER MEM8[0xF9C5u]
#define RX_ERROR_LATCH MEM8[0xFAA4u]
#define RX_ERROR_LATCH_PHYSICAL_ERROR 0x80u
/* Candidate Protocol Semantics /* Candidate Protocol Semantics
* confidence: medium-high (0.9) * confidence: medium-high (0.9)
@@ -110,6 +118,72 @@ extern volatile u8 MEM8[0x10000];
* - H'05 ack_or_clear_pending: candidate pending/event acknowledgement path; handler H'BD80; responses none * - H'05 ack_or_clear_pending: candidate pending/event acknowledgement path; handler H'BD80; responses none
* - H'06 set_secondary_value: candidate secondary-table value write path; handler H'BDDB; responses none * - H'06 set_secondary_value: candidate secondary-table value write path; handler H'BDDB; responses none
* - H'07 retransmit_or_error_reply: candidate retransmit/NAK-style path; error handling also builds command 0x07 responses; handler H'BE05; responses response_at_BE22 * - H'07 retransmit_or_error_reply: candidate retransmit/NAK-style path; error handling also builds command 0x07 responses; handler H'BE05; responses response_at_BE22
* command effects:
* - H'00 set_value_acked: Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.
* effect: table_write_candidate; target primary_value_table_candidate; source RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero; table H'E000
* effect: table_write_candidate; target current_value_table_candidate; source same candidate value written to the primary table; table H'E800
* effect: flag_update_candidate; target per_index_flag_table_candidate; set bit 7; table H'EC00
* evidence: H'BC08, H'BC0C, H'BC20, H'BC22, H'BCB0, H'BCB9, H'BCC1, H'BCC9, H'BCB5, H'BCBD, H'BCC5, H'BCCD
* - H'01 read_value: Candidate read: reads the primary table and stages a value response.
* effect: table_read_candidate; target primary_value_table_candidate; table H'E000
* effect: response_staging_candidate; stage F850-F854 and call loc_BA26
* evidence: H'BC08, H'BC0C, H'BC24, H'BC26, H'BCB0, H'BCB9, H'BCC1, H'BCC9, H'BCD7, H'BCE0, H'BCE8, H'BCF0, H'BCF6, H'BCB5, H'BCBD, H'BCC5, H'BCDC, H'BCE4, H'BCFA
* - H'02 clear_or_abort: Candidate clear/abort: clears serial session state without an observed immediate response.
* effect: state_clear_candidate; target serial_session_flags_candidate; clear bit 7; state H'FAA2
* evidence: H'BC08, H'BC0C, H'BC29, H'BC2B
* - H'04 set_value_no_immediate_reply: Candidate deferred set: writes value bytes and flags the index without an observed immediate response.
* effect: table_write_candidate; target primary_value_table_candidate; source RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero; table H'E000
* effect: flag_update_candidate; target per_index_flag_table_candidate; set bit 7; table H'EC00
* evidence: H'BC08, H'BC0C, H'BC45, H'BC47
* - H'05 ack_or_clear_pending: Candidate acknowledgement/clear: updates pending/event state without an observed immediate response.
* effect: pending_acknowledgement_candidate; target selected event/pending state; clear selected pending flags and then clear serial session state
* evidence: H'BC08, H'BC0C, H'BC4A, H'BC4C
* - H'06 set_secondary_value: Candidate secondary set: writes value bytes to the secondary table and flags the index.
* effect: table_write_candidate; target secondary_value_table_candidate; source RX[3:4] value bytes; table H'E400
* effect: flag_update_candidate; target per_index_flag_table_candidate; set bit 6; table H'EC00
* evidence: H'BC08, H'BC0C, H'BC4F, H'BC51
* - H'07 retransmit_or_error_reply: Candidate retransmit/error reply: reuses prior TX bytes or builds an explicit 0x07 retry/error response.
* effect: retransmit_candidate; target TX staging bytes H'F850-H'F854 before loc_BA26; source previous TX frame bytes H'F858-H'F85C
* effect: response_staging_candidate; stage F850-F854 and call loc_BA26
* evidence: H'BC08, H'BC0C, H'BC2E, H'BC30, H'BC54, H'BC56, H'BE09, H'BE11, H'BE19, H'BE22
* response schemas:
* - response_at_BB43: byte0=computed; byte1=computed; byte2=computed; byte3=current_value_table_candidate; byte4=current_value_table_candidate
* evidence: H'BB1C, H'BB2B, H'BB20, H'BB3F, H'BB39
* - response_at_BCCD: byte0=0x04; byte1=rx[1]; byte2=rx[2]; byte3=rx[3]; byte4=rx[4]
* evidence: H'BCB0, H'BCB9, H'BCC1, H'BCC9
* - response_at_BCFA: byte0=0x04; byte1=rx[2]; byte2=rx[2]; byte3=primary_value_table_candidate; byte4=primary_value_table_candidate
* evidence: H'BCD7, H'BCE8, H'BCC1, H'BCF6, H'BCF0
* - response_at_BE22: byte0=tx[0]; byte1=tx[1]; byte2=tx[2]; byte3=tx[3]; byte4=tx[4]
* evidence: H'BE09, H'BE11, H'BE19
* - ... 1 more candidate response schemas
* table map candidates:
* - primary_value_table_candidate at H'E000 (word_value); observed read, write
* evidence: H'19E3, H'1A03, H'1A3D, H'1A6B, H'3F8C, H'4077, H'BC75, H'BC95, H'BCEC, H'BD1A, H'BD35
* - secondary_value_table_candidate at H'E400 (word_value); observed read, write
* evidence: H'19AA, H'1A4B, H'1A5B, H'1A81, H'1AB4, H'1AC1, H'407B, H'BDE5
* - current_value_table_candidate at H'E800 (word_value); observed read, write
* evidence: H'1A09, H'1A71, H'3F90, H'407F, H'BB35, H'BC79, H'BC99, H'BD1E
* - flag_table_candidate at H'EC00 (bit_flags); observed write
* evidence: H'4088, H'BC82, H'BC9D, H'BD22, H'BD39, H'BDE9
* state variable candidates:
* - event_queue_read_cursor_candidate H'F9B4: reads 1, writes 2; bits 5
* evidence: H'BE78, H'BE95, H'BE99
* - event_queue_write_or_pending_cursor_candidate H'F9B5: reads 1, writes 6; bits 7
* evidence: H'BAF2, H'BD6D, H'BD71, H'BDC8, H'BDCC, H'BDF3, H'BDF7
* - event_queue_base_or_current_slot_candidate H'F9B9: reads 1, writes 0
* evidence: H'BE70
* - serial_tx_busy_timer_candidate H'F9C0: reads 2, writes 8
* evidence: H'BA26, H'BA2C, H'BAA2, H'BADA, H'BAE1, H'BAE8, H'BE1D, H'BE3E, H'BEEE, H'BEF4
* - serial_session_flags_candidate H'FAA2: reads 5, writes 13; bits 3, 7
* evidence: H'BA84, H'BA96, H'BB00, H'BC0F, H'BC15, H'BC33, H'BC5C, H'BCD0, H'BCFD, H'BD04, H'BD67, H'BD79, H'BDC2, H'BDD4, H'BDED, H'BDFF, H'BE47, H'BEAF
* - serial_pending_mask_candidate H'FAA3: reads 1, writes 9; bits 7
* evidence: H'BA9A, H'BB51, H'BC63, H'BD75, H'BDD0, H'BDFB, H'BE43, H'BEA5, H'BEA9, H'BECB
* - ... 3 more state-variable candidates
* retry/error model candidate:
* - checksum path: 0x5A-seeded XOR over RX[0..4] differs from RX[5] -> loc_BE29
* - retry path: counter H'FAA6, threshold 2; Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit stages a command 0x07 response.
* - command 0x07 path: Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.
* - evidence: H'BBD8, H'BBDC, H'BBE0, H'BBE4, H'BBE8, H'BBEC, H'BBF0, H'BE4D, H'BE56, H'BE5E, H'BE66, H'BE52, H'BE5A, H'BE62, H'BE6A, H'BE29, H'BE2D, H'BE33, H'BE37, H'BE43, H'BE47, H'BE05, H'BE0D, H'BE15, H'BE09, H'BE11, H'BE19, H'BE22
*/ */
static u8 sci1_rx_candidate_command(void) static u8 sci1_rx_candidate_command(void)
@@ -148,42 +222,55 @@ void sci1_process_candidate_protocol_command(void)
switch (command) { switch (command) {
case 0x00u: case 0x00u:
/* set_value_acked: candidate write of RX[3:4] into primary/current tables, followed by a response /* set_value_acked: candidate write of RX[3:4] into primary/current tables, followed by a response
* candidate effect: table_write_candidate; target primary_value_table_candidate; source RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero; table H'E000
* candidate effect: table_write_candidate; target current_value_table_candidate; source same candidate value written to the primary table; table H'E800
* candidate effect: flag_update_candidate; target per_index_flag_table_candidate; set bit 7; table H'EC00
* evidence: H'BC08, H'BC0C, H'BC20, H'BC22, H'BCB0, H'BCB9, H'BCC1, H'BCC9, H'BCB5, H'BCBD, H'BCC5, H'BCCD * evidence: H'BC08, H'BC0C, H'BC20, H'BC22, H'BCB0, H'BCB9, H'BCC1, H'BCC9, H'BCB5, H'BCBD, H'BCC5, H'BCCD
*/ */
candidate_set_value_acked(logical_index, value); candidate_set_value_acked(logical_index, value);
break; break;
case 0x01u: case 0x01u:
/* read_value: candidate read from the primary table, followed by a response carrying the value /* read_value: candidate read from the primary table, followed by a response carrying the value
* candidate effect: table_read_candidate; target primary_value_table_candidate; table H'E000
* candidate effect: response_staging_candidate; stage F850-F854 and call loc_BA26
* evidence: H'BC08, H'BC0C, H'BC24, H'BC26, H'BCB0, H'BCB9, H'BCC1, H'BCC9, H'BCD7, H'BCE0, H'BCE8, H'BCF0, H'BCF6, H'BCB5, H'BCBD, H'BCC5, H'BCDC, H'BCE4, H'BCFA * evidence: H'BC08, H'BC0C, H'BC24, H'BC26, H'BCB0, H'BCB9, H'BCC1, H'BCC9, H'BCD7, H'BCE0, H'BCE8, H'BCF0, H'BCF6, H'BCB5, H'BCBD, H'BCC5, H'BCDC, H'BCE4, H'BCFA
*/ */
candidate_read_value(logical_index, value); candidate_read_value(logical_index, value);
break; break;
case 0x02u: case 0x02u:
/* clear_or_abort: candidate clear/abort path with no immediate response builder /* clear_or_abort: candidate clear/abort path with no immediate response builder
* candidate effect: state_clear_candidate; target serial_session_flags_candidate; clear bit 7; state H'FAA2
* evidence: H'BC08, H'BC0C, H'BC29, H'BC2B * evidence: H'BC08, H'BC0C, H'BC29, H'BC2B
*/ */
candidate_clear_or_abort(logical_index, value); candidate_clear_or_abort(logical_index, value);
break; break;
case 0x04u: case 0x04u:
/* set_value_no_immediate_reply: candidate write/update path that stores a value without an immediate serial response /* set_value_no_immediate_reply: candidate write/update path that stores a value without an immediate serial response
* candidate effect: table_write_candidate; target primary_value_table_candidate; source RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero; table H'E000
* candidate effect: flag_update_candidate; target per_index_flag_table_candidate; set bit 7; table H'EC00
* evidence: H'BC08, H'BC0C, H'BC45, H'BC47 * evidence: H'BC08, H'BC0C, H'BC45, H'BC47
*/ */
candidate_set_value_no_immediate_reply(logical_index, value); candidate_set_value_no_immediate_reply(logical_index, value);
break; break;
case 0x05u: case 0x05u:
/* ack_or_clear_pending: candidate pending/event acknowledgement path /* ack_or_clear_pending: candidate pending/event acknowledgement path
* candidate effect: pending_acknowledgement_candidate; target selected event/pending state; clear selected pending flags and then clear serial session state
* evidence: H'BC08, H'BC0C, H'BC4A, H'BC4C * evidence: H'BC08, H'BC0C, H'BC4A, H'BC4C
*/ */
candidate_ack_or_clear_pending(logical_index, value); candidate_ack_or_clear_pending(logical_index, value);
break; break;
case 0x06u: case 0x06u:
/* set_secondary_value: candidate secondary-table value write path /* set_secondary_value: candidate secondary-table value write path
* candidate effect: table_write_candidate; target secondary_value_table_candidate; source RX[3:4] value bytes; table H'E400
* candidate effect: flag_update_candidate; target per_index_flag_table_candidate; set bit 6; table H'EC00
* evidence: H'BC08, H'BC0C, H'BC4F, H'BC51 * evidence: H'BC08, H'BC0C, H'BC4F, H'BC51
*/ */
candidate_set_secondary_value(logical_index, value); candidate_set_secondary_value(logical_index, value);
break; break;
case 0x07u: case 0x07u:
/* retransmit_or_error_reply: candidate retransmit/NAK-style path; error handling also builds command 0x07 responses /* retransmit_or_error_reply: candidate retransmit/NAK-style path; error handling also builds command 0x07 responses
* candidate effect: retransmit_candidate; target TX staging bytes H'F850-H'F854 before loc_BA26; source previous TX frame bytes H'F858-H'F85C
* candidate effect: response_staging_candidate; stage F850-F854 and call loc_BA26
* evidence: H'BC08, H'BC0C, H'BC2E, H'BC30, H'BC54, H'BC56, H'BE09, H'BE11, H'BE19, H'BE22 * evidence: H'BC08, H'BC0C, H'BC2E, H'BC30, H'BC54, H'BC56, H'BE09, H'BE11, H'BE19, H'BE22
*/ */
candidate_retransmit_or_error_reply(logical_index, value); candidate_retransmit_or_error_reply(logical_index, value);
@@ -252,15 +339,19 @@ void sci1_txi_candidate_isr(void)
* RX reconstruction evidence * RX reconstruction evidence
* candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A * candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A
* checksum formula: checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4 * checksum formula: checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4
* RX error handling: SCI1 ERI appears to mark a physical receive error and continue into the RXI byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order.
* RX error caveat: Manual text distinguishes ORER from FER/PER data transfer into RDR and describes the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order.
* evidence addresses: * evidence addresses:
* - rx_checksum_seed: H'BBD6 * - rx_checksum_seed: H'BBD6
* - rx_complete_timer: H'BB9E * - rx_complete_timer: H'BB9E
* - rx_copy_capture_to_frame_buffer: H'BBB3, H'BBBB, H'BBC3, H'BBB7, H'BBBF, H'BBC7 * - rx_copy_capture_to_frame_buffer: H'BBB3, H'BBBB, H'BBC3, H'BBB7, H'BBBF, H'BBC7
* - rx_eri_falls_through_to_rxi: H'BB57, H'BB5B, H'BB5F, H'BB63, H'BB69, H'BB6D
* - rx_index_increment_store: H'BB94, H'BB96 * - rx_index_increment_store: H'BB94, H'BB96
* - rx_indexed_store: H'BB90 * - rx_indexed_store: H'BB90
* - rx_isr_compare_frame_length: H'BB9A * - rx_isr_compare_frame_length: H'BB9A
* - rx_processor_requires_six_bytes: H'BBAB * - rx_processor_requires_six_bytes: H'BBAB
* - rx_rdr_read: H'BB6D * - rx_rdr_read: H'BB6D
* - rx_rdrf_clear_before_rdr_read: H'BB69, H'BB6D
* - rx_xor_checksum_validation: H'BBD6, H'BBD8, H'BBDC, H'BBE0, H'BBE4, H'BBE8, H'BBEC * - rx_xor_checksum_validation: H'BBD6, H'BBD8, H'BBDC, H'BBE0, H'BBE4, H'BBE8, H'BBEC
*/ */
static u8 sci1_rx_candidate_checksum(void) static u8 sci1_rx_candidate_checksum(void)
@@ -320,6 +411,7 @@ bool sci1_rx_byte_received_candidate_isr(void)
void sci1_rx_error_candidate_isr(void) void sci1_rx_error_candidate_isr(void)
{ {
RX_ERROR_LATCH |= RX_ERROR_LATCH_PHYSICAL_ERROR;
SCI1_SSR &= (u8)~(SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER); SCI1_SSR &= (u8)~(SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER);
RX_INDEX = 0u; sci1_rx_byte_received_candidate_isr();
} }

294
h8536/serial_pseudocode.py
View File

@@ -40,6 +40,7 @@ def generate_serial_pseudocode(
lines.extend(_board_comment_lines(payload)) lines.extend(_board_comment_lines(payload))
if opts.include_manual: if opts.include_manual:
lines.extend(_manual_reference_lines(payload)) lines.extend(_manual_reference_lines(payload))
lines.extend(_sci_link_lines(payload))
lines.extend(_declarations(tx_candidate, rx_candidate)) lines.extend(_declarations(tx_candidate, rx_candidate))
if opts.include_semantics: if opts.include_semantics:
lines.extend(_semantics_lines(serial_semantics, opts)) lines.extend(_semantics_lines(serial_semantics, opts))
@@ -196,6 +197,72 @@ def _manual_reference_lines(payload: JsonObject) -> list[str]:
return lines return lines
def _sci_link_lines(payload: JsonObject) -> list[str]:
config = _first_sci1_configuration(payload)
dtc_note = _dtc_sci_note(payload)
if not config and not dtc_note:
return []
lines = ["/* SCI1 link layer:"]
if config:
mode_summary = str(config.get("mode_summary") or config.get("mode") or "SCI mode")
char_format = "8E1" if "8-bit even parity 1 stop" in mode_summary else mode_summary
smr = config.get("smr_hex") or _optional_hex(config.get("smr"), width=2)
brr = config.get("brr_hex") or _optional_hex(config.get("brr"), width=2)
scr = config.get("scr_hex") or _optional_hex(config.get("scr"), width=2)
clock_source = config.get("clock_source") or "clock source unknown"
lines.append(
" * - "
+ _comment_text(
f"{char_format} SCI characters carry the 6 protocol bytes; "
f"{mode_summary}, clock {clock_source}, SMR={smr}, BRR={brr}, SCR={scr}",
),
)
baud = config.get("baud_bps")
if isinstance(baud, (int, float)):
lines.append(f" * - candidate baud: {_comment_text(str(baud))} bps")
else:
lines.append(" * - baud is clock-dependent; pass --clock-hz on the decompiler for bps.")
if dtc_note:
lines.append(f" * - {_comment_text(dtc_note)}")
lines.append(" */")
lines.append("")
return lines
def _first_sci1_configuration(payload: JsonObject) -> JsonObject | None:
sci = payload.get("sci")
if not isinstance(sci, dict):
return None
channels = sci.get("channels")
if not isinstance(channels, dict):
return None
sci1 = channels.get("SCI1")
if not isinstance(sci1, dict):
return None
configurations = sci1.get("configurations")
if not isinstance(configurations, list):
return None
for item in configurations:
if isinstance(item, dict):
return item
return None
def _dtc_sci_note(payload: JsonObject) -> str:
vectors = payload.get("dtc_vectors")
if not isinstance(vectors, list):
return ""
sources = {
str(item.get("source", "")).lower()
for item in vectors
if isinstance(item, dict)
}
if "sci1_rxi" in sources or "sci1_txi" in sources:
return "SCI1 DTC vector entries are present; review DTC metadata before treating RX/TX as CPU-only."
return "No SCI1 RXI/TXI DTC vector entries are present in JSON; RX/TX are modeled as CPU ISR paths."
def _declarations(tx_candidate: JsonObject | None, rx_candidate: JsonObject | None) -> list[str]: def _declarations(tx_candidate: JsonObject | None, rx_candidate: JsonObject | None) -> list[str]:
candidate = tx_candidate or rx_candidate or {} candidate = tx_candidate or rx_candidate or {}
channel = str(candidate.get("channel") or "SCI1") channel = str(candidate.get("channel") or "SCI1")
@@ -250,6 +317,10 @@ def _declarations(tx_candidate: JsonObject | None, rx_candidate: JsonObject | No
timeout = _int_field(rx_candidate, "interbyte_timeout_address", 0xF9C1) timeout = _int_field(rx_candidate, "interbyte_timeout_address", 0xF9C1)
complete = _int_field(rx_candidate, "complete_timer_address", 0xF9C5) complete = _int_field(rx_candidate, "complete_timer_address", 0xF9C5)
length = _int_field(rx_candidate, "frame_length", 6) length = _int_field(rx_candidate, "frame_length", 6)
error_handling = rx_candidate.get("rx_error_handling")
error_latch = 0xFAA4
if isinstance(error_handling, dict):
error_latch = _int_field(error_handling, "error_latch_address", 0xFAA4)
lines.extend( lines.extend(
[ [
f"#define RX_FRAME_LENGTH {length}u", f"#define RX_FRAME_LENGTH {length}u",
@@ -258,6 +329,8 @@ def _declarations(tx_candidate: JsonObject | None, rx_candidate: JsonObject | No
f"#define RX_INDEX MEM8[{_c_hex(rx_index)}]", f"#define RX_INDEX MEM8[{_c_hex(rx_index)}]",
f"#define RX_INTERBYTE_TIMEOUT MEM8[{_c_hex(timeout)}]", f"#define RX_INTERBYTE_TIMEOUT MEM8[{_c_hex(timeout)}]",
f"#define RX_COMPLETE_TIMER MEM8[{_c_hex(complete)}]", f"#define RX_COMPLETE_TIMER MEM8[{_c_hex(complete)}]",
f"#define RX_ERROR_LATCH MEM8[{_c_hex(error_latch)}]",
"#define RX_ERROR_LATCH_PHYSICAL_ERROR 0x80u",
"", "",
], ],
) )
@@ -326,6 +399,11 @@ def _semantics_lines(
handler = command.get("handler_start_hex") or "multiple" handler = command.get("handler_start_hex") or "multiple"
responses = ", ".join(str(item) for item in command.get("response_candidates", [])) or "none" responses = ", ".join(str(item) for item in command.get("response_candidates", [])) or "none"
lines.append(f" * - {value} {name}: {summary}; handler {handler}; responses {responses}") lines.append(f" * - {value} {name}: {summary}; handler {handler}; responses {responses}")
lines.extend(_command_effect_comment_lines(protocol.get("command_effects"), opts, prefix=" * "))
lines.extend(_response_schema_comment_lines(_schema_list(protocol), opts, prefix=" * "))
lines.extend(_table_map_comment_lines(_table_map_list(protocol), opts, prefix=" * "))
lines.extend(_state_variable_comment_lines(protocol.get("state_variable_candidates"), opts, prefix=" * "))
lines.extend(_retry_error_comment_lines(protocol.get("retry_error_model"), opts, prefix=" * "))
lines.append(" */") lines.append(" */")
lines.append("") lines.append("")
@@ -376,6 +454,8 @@ def _semantics_lines(
evidence = _hex_join(command.get("evidence_addresses_hex")) evidence = _hex_join(command.get("evidence_addresses_hex"))
lines.append(f" case 0x{value:02X}u:") lines.append(f" case 0x{value:02X}u:")
lines.append(f" /* {name}: {summary}") lines.append(f" /* {name}: {summary}")
for effect_line in _command_effect_switch_lines(command):
lines.append(f" * {effect_line}")
if opts.include_evidence and evidence: if opts.include_evidence and evidence:
lines.append(f" * evidence: {evidence}") lines.append(f" * evidence: {evidence}")
lines.append(" */") lines.append(" */")
@@ -394,6 +474,203 @@ def _semantics_lines(
return lines return lines
def _command_effect_comment_lines(
value: object,
opts: SerialPseudocodeOptions,
*,
prefix: str,
) -> list[str]:
effects = [item for item in _object_list(value) if item.get("effects") or item.get("summary")]
if not effects:
return []
lines = [f"{prefix}command effects:"]
for item in effects:
command = item.get("command_value_hex") or _command_hex(item.get("command_value"))
name = item.get("name_candidate") or "unknown_command"
summary = _comment_text(str(item.get("summary") or "candidate effects"))
lines.append(f"{prefix}- {command} {name}: {summary}")
for effect in _object_list(item.get("effects"))[:3]:
effect_text = _effect_summary(effect)
if effect_text:
lines.append(f"{prefix} effect: {effect_text}")
evidence = _hex_join(item.get("evidence_addresses_hex"))
if opts.include_evidence and evidence:
lines.append(f"{prefix} evidence: {evidence}")
return lines
def _response_schema_comment_lines(
schemas: list[JsonObject],
opts: SerialPseudocodeOptions,
*,
prefix: str,
) -> list[str]:
if not schemas:
return []
lines = [f"{prefix}response schemas:"]
for schema in schemas[:4]:
response_id = schema.get("response_id") or schema.get("call_address_hex") or "candidate_response"
byte_text = _response_schema_summary(schema)
lines.append(f"{prefix}- {response_id}: {byte_text}")
evidence = _hex_join(schema.get("evidence_addresses_hex"))
if opts.include_evidence and evidence:
lines.append(f"{prefix} evidence: {evidence}")
if len(schemas) > 4:
lines.append(f"{prefix}- ... {len(schemas) - 4} more candidate response schemas")
return lines
def _table_map_comment_lines(
tables: list[JsonObject],
opts: SerialPseudocodeOptions,
*,
prefix: str,
) -> list[str]:
if not tables:
return []
lines = [f"{prefix}table map candidates:"]
for table in tables[:6]:
name = table.get("name_candidate") or "unnamed_table_candidate"
address = table.get("logical_base_address_hex") or table.get("address_hex") or "?"
element = table.get("element_candidate")
accesses = ", ".join(str(item) for item in table.get("observed_accesses", []) if item) or "access?"
detail = f"{name} at {address}"
if element:
detail += f" ({element})"
lines.append(f"{prefix}- {_comment_text(detail)}; observed {accesses}")
evidence = _hex_join(table.get("evidence_addresses_hex"))
if opts.include_evidence and evidence:
lines.append(f"{prefix} evidence: {evidence}")
if len(tables) > 6:
lines.append(f"{prefix}- ... {len(tables) - 6} more table candidates")
return lines
def _state_variable_comment_lines(
value: object,
opts: SerialPseudocodeOptions,
*,
prefix: str,
) -> list[str]:
states = sorted(
_object_list(value),
key=lambda item: item.get("address") if isinstance(item.get("address"), int) else 0x10000,
)
if not states:
return []
lines = [f"{prefix}state variable candidates:"]
for state in states[:6]:
name = state.get("name_candidate") or "unnamed_state_candidate"
address = state.get("address_hex") or _command_hex(state.get("address"))
reads = state.get("read_count", "?")
writes = state.get("write_count", "?")
bits = ", ".join(str(item) for item in state.get("bit_candidates", []))
suffix = f"; bits {bits}" if bits else ""
lines.append(f"{prefix}- {_comment_text(str(name))} {address}: reads {reads}, writes {writes}{suffix}")
evidence = _hex_join(state.get("evidence_addresses_hex"))
if opts.include_evidence and evidence:
lines.append(f"{prefix} evidence: {evidence}")
if len(states) > 6:
lines.append(f"{prefix}- ... {len(states) - 6} more state-variable candidates")
return lines
def _retry_error_comment_lines(
value: object,
opts: SerialPseudocodeOptions,
*,
prefix: str,
) -> list[str]:
if not isinstance(value, dict):
return []
checksum = value.get("checksum_failure_path")
retry = value.get("retry_path")
command_07 = value.get("command_0x07_path")
lines = [f"{prefix}retry/error model candidate:"]
if isinstance(checksum, dict):
condition = _comment_text(str(checksum.get("condition_candidate") or "checksum failure"))
target = checksum.get("error_target") or checksum.get("error_target_address_hex") or "error target"
lines.append(f"{prefix}- checksum path: {condition} -> {target}")
if isinstance(retry, dict):
counter = retry.get("counter_address_hex") or "counter?"
threshold = retry.get("threshold_candidate", "?")
summary = _comment_text(str(retry.get("summary") or "candidate retry path"))
lines.append(f"{prefix}- retry path: counter {counter}, threshold {threshold}; {summary}")
if isinstance(command_07, dict):
summary = _comment_text(str(command_07.get("summary") or "candidate command 0x07 path"))
lines.append(f"{prefix}- command 0x07 path: {summary}")
evidence = _hex_join(value.get("evidence_addresses_hex"))
if opts.include_evidence and evidence:
lines.append(f"{prefix}- evidence: {evidence}")
return lines
def _command_effect_switch_lines(command: JsonObject) -> list[str]:
effects = _object_list(command.get("effects"))[:3]
lines = []
for effect in effects:
text = _effect_summary(effect)
if text:
lines.append(f"candidate effect: {text}")
return lines
def _effect_summary(effect: JsonObject) -> str:
kind = str(effect.get("kind") or "effect_candidate")
parts = [kind]
target = effect.get("target_candidate") or effect.get("destination_candidate")
source = effect.get("source_candidate")
operation = effect.get("operation_candidate")
table = effect.get("table_base_hex")
state = effect.get("state_address_hex")
if target:
parts.append(f"target {target}")
if source:
parts.append(f"source {source}")
if operation:
parts.append(str(operation))
if table:
parts.append(f"table {table}")
if state:
parts.append(f"state {state}")
return _comment_text("; ".join(parts))
def _schema_list(protocol: JsonObject) -> list[JsonObject]:
schemas = _object_list(protocol.get("response_schemas"))
if schemas:
return schemas
return _object_list(protocol.get("response_schema"))
def _table_map_list(protocol: JsonObject) -> list[JsonObject]:
tables = _object_list(protocol.get("logical_table_map_candidates"))
if tables:
return tables
return _object_list(protocol.get("table_map_candidates"))
def _response_schema_summary(schema: JsonObject) -> str:
parts = []
for item in _object_list(schema.get("bytes")):
label = item.get("byte") or f"byte{item.get('offset', '?')}"
source = item.get("source_expression") or item.get("source_kind") or "unknown"
parts.append(f"{label}={source}")
return _comment_text("; ".join(parts) if parts else "candidate byte sources unknown")
def _object_list(value: object) -> list[JsonObject]:
if not isinstance(value, list):
return []
return [item for item in value if isinstance(item, dict)]
def _command_hex(value: object) -> str:
if isinstance(value, int):
return f"0x{value:02X}"
return "?"
def _tx_functions(candidate: JsonObject, opts: SerialPseudocodeOptions) -> list[str]: def _tx_functions(candidate: JsonObject, opts: SerialPseudocodeOptions) -> list[str]:
length = _int_field(candidate, "frame_length", 6) length = _int_field(candidate, "frame_length", 6)
seed = _int_field(candidate, "checksum_seed", 0x5A) seed = _int_field(candidate, "checksum_seed", 0x5A)
@@ -511,8 +788,9 @@ def _rx_functions(candidate: JsonObject, opts: SerialPseudocodeOptions) -> list[
"", "",
"void sci1_rx_error_candidate_isr(void)", "void sci1_rx_error_candidate_isr(void)",
"{", "{",
" RX_ERROR_LATCH |= RX_ERROR_LATCH_PHYSICAL_ERROR;",
" SCI1_SSR &= (u8)~(SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER);", " SCI1_SSR &= (u8)~(SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER);",
" RX_INDEX = 0u;", " sci1_rx_byte_received_candidate_isr();",
"}", "}",
"", "",
], ],
@@ -532,6 +810,14 @@ def _candidate_comment_block(
formula = str(candidate.get("checksum_formula") or "").strip() formula = str(candidate.get("checksum_formula") or "").strip()
if formula: if formula:
lines.append(f" * checksum formula: {_comment_text(formula)}") lines.append(f" * checksum formula: {_comment_text(formula)}")
error_handling = candidate.get("rx_error_handling")
if isinstance(error_handling, dict):
summary = str(error_handling.get("summary") or "").strip()
if summary:
lines.append(f" * RX error handling: {_comment_text(summary)}")
caveat = str(error_handling.get("manual_caveat") or "").strip()
if caveat:
lines.append(f" * RX error caveat: {_comment_text(caveat)}")
if opts.include_evidence: if opts.include_evidence:
evidence = candidate.get("evidence_addresses_hex") evidence = candidate.get("evidence_addresses_hex")
if isinstance(evidence, dict): if isinstance(evidence, dict):
@@ -596,6 +882,12 @@ def _c_hex(value: int, *, width: int = 4) -> str:
return f"0x{value & 0xFFFF:0{width}X}u" return f"0x{value & 0xFFFF:0{width}X}u"
def _optional_hex(value: object, *, width: int = 4) -> str:
if isinstance(value, int):
return f"H'{value & 0xFFFF:0{width}X}"
return "unknown"
def _h(value: int) -> str: def _h(value: int) -> str:
return f"H'{value & 0xFFFF:04X}" return f"H'{value & 0xFFFF:04X}"

163
h8536/serial_reconstruction.py
View File

@@ -7,6 +7,7 @@ from .model import Instruction
SCI1_TDR_ADDRESS = 0xFEDB SCI1_TDR_ADDRESS = 0xFEDB
SCI1_SSR_ADDRESS = 0xFEDC
SCI1_RDR_ADDRESS = 0xFEDD SCI1_RDR_ADDRESS = 0xFEDD
TX_BUFFER_START = 0xF858 TX_BUFFER_START = 0xF858
TX_CHECKSUM_ADDRESS = 0xF85D TX_CHECKSUM_ADDRESS = 0xF85D
@@ -24,6 +25,7 @@ RX_INDEX_ADDRESS = 0xF9C3
RX_INTERBYTE_TIMEOUT_ADDRESS = 0xF9C1 RX_INTERBYTE_TIMEOUT_ADDRESS = 0xF9C1
RX_COMPLETE_TIMER_ADDRESS = 0xF9C5 RX_COMPLETE_TIMER_ADDRESS = 0xF9C5
RX_FRAME_LENGTH = 6 RX_FRAME_LENGTH = 6
RX_ERROR_LATCH_ADDRESS = 0xFAA4
_BUFFER_DATA_END = TX_CHECKSUM_ADDRESS - 1 _BUFFER_DATA_END = TX_CHECKSUM_ADDRESS - 1
_MIN_BUFFER_REFERENCES = 3 _MIN_BUFFER_REFERENCES = 3
@@ -265,6 +267,41 @@ def _collect_rx_evidence(ordered: list[Instruction]) -> list[dict[str, object]]:
), ),
) )
rdrf_before_rdr = _rx_rdrf_clear_before_rdr_read(ordered)
if rdrf_before_rdr:
evidence.append(
_evidence(
"rx_rdrf_clear_before_rdr_read",
rdrf_before_rdr,
summary=(
"ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed "
"ordering even though the manual describes the canonical RDR-read then "
"RDRF-clear sequence"
),
manual_references=[
"Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF",
"Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence",
],
),
)
eri_fallthrough = _rx_eri_fallthrough_sequence(ordered)
if eri_fallthrough:
evidence.append(
_evidence(
"rx_eri_falls_through_to_rxi",
eri_fallthrough,
summary=(
"SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into "
"the same RXI byte-capture path"
),
manual_references=[
"Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not",
"Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER",
],
),
)
indexed_stores = [ins for ins in ordered if _is_indexed_capture_store(ins)] indexed_stores = [ins for ins in ordered if _is_indexed_capture_store(ins)]
if indexed_stores: if indexed_stores:
evidence.append( evidence.append(
@@ -435,6 +472,17 @@ def _rx_candidate_from_evidence(evidence: list[dict[str, object]]) -> dict[str,
key: list(evidence_by_key[key]["addresses"]) key: list(evidence_by_key[key]["addresses"])
for key in _RX_REQUIRED_EVIDENCE for key in _RX_REQUIRED_EVIDENCE
} }
optional_evidence_keys = [
key
for key in (
"rx_rdrf_clear_before_rdr_read",
"rx_eri_falls_through_to_rxi",
)
if key in evidence_by_key
]
for key in optional_evidence_keys:
evidence_addresses[key] = list(evidence_by_key[key]["addresses"])
return { return {
"id": "sci1_rx_frame_f868_len6_candidate", "id": "sci1_rx_frame_f868_len6_candidate",
"kind": "candidate_sci1_rx_frame", "kind": "candidate_sci1_rx_frame",
@@ -469,13 +517,18 @@ def _rx_candidate_from_evidence(evidence: list[dict[str, object]]) -> dict[str,
"caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet", "caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet",
"required_evidence_count": len(_RX_REQUIRED_EVIDENCE), "required_evidence_count": len(_RX_REQUIRED_EVIDENCE),
"observed_evidence_count": len(_RX_REQUIRED_EVIDENCE), "observed_evidence_count": len(_RX_REQUIRED_EVIDENCE),
"optional_evidence_count": len(optional_evidence_keys),
"missing_evidence": [], "missing_evidence": [],
"evidence_addresses": evidence_addresses, "evidence_addresses": evidence_addresses,
"evidence_addresses_hex": { "evidence_addresses_hex": {
key: [h16(address) for address in addresses] key: [h16(address) for address in addresses]
for key, addresses in evidence_addresses.items() for key, addresses in evidence_addresses.items()
}, },
"evidence": [evidence_by_key[key] for key in _RX_REQUIRED_EVIDENCE], "evidence": [
evidence_by_key[key]
for key in [*_RX_REQUIRED_EVIDENCE, *optional_evidence_keys]
],
"rx_error_handling": _rx_error_handling_candidate(evidence_by_key),
"short_comment": ( "short_comment": (
f"candidate/evidence-supported SCI1 {RX_FRAME_LENGTH}-byte RX frame; " f"candidate/evidence-supported SCI1 {RX_FRAME_LENGTH}-byte RX frame; "
f"capture {h16(RX_CAPTURE_START)}-{h16(RX_CAPTURE_END)}, validate " f"capture {h16(RX_CAPTURE_START)}-{h16(RX_CAPTURE_END)}, validate "
@@ -708,6 +761,100 @@ def _rx_xor_checksum_validation(ordered: list[Instruction]) -> list[Instruction]
return [] return []
def _rx_rdrf_clear_before_rdr_read(ordered: list[Instruction]) -> list[Instruction]:
for index, ins in enumerate(ordered):
if not _is_bclr_bit(ins, SCI1_SSR_ADDRESS, 6):
continue
window = ordered[index + 1:index + 5]
for candidate in window:
if _mnemonic_root(candidate.mnemonic) in {"RTE", "RTS"}:
break
if _is_read_from_address(candidate, SCI1_RDR_ADDRESS):
return [ins, candidate]
return []
def _rx_eri_fallthrough_sequence(ordered: list[Instruction]) -> list[Instruction]:
for index, ins in enumerate(ordered):
if not _is_bset_bit(ins, RX_ERROR_LATCH_ADDRESS, 7):
continue
window = ordered[index:index + 18]
if any(_mnemonic_root(candidate.mnemonic) in {"RTE", "RTS"} for candidate in window[:6]):
continue
error_clears: list[Instruction] = []
for bit in (5, 4, 3):
clear = next(
(
candidate for candidate in window
if _is_bclr_bit(candidate, SCI1_SSR_ADDRESS, bit)
),
None,
)
if clear is not None:
error_clears.append(clear)
if len(error_clears) != 3:
continue
after_error = [
candidate for candidate in window
if candidate.address > max(clear.address for clear in error_clears)
]
byte_path = _rx_rdrf_clear_before_rdr_read(after_error)
if byte_path:
return _dedupe_instructions([ins, *error_clears, *byte_path])
return []
def _rx_error_handling_candidate(evidence_by_key: Mapping[str, dict[str, object]]) -> dict[str, object] | None:
fallthrough = evidence_by_key.get("rx_eri_falls_through_to_rxi")
clear_order = evidence_by_key.get("rx_rdrf_clear_before_rdr_read")
if fallthrough is None and clear_order is None:
return None
evidence_items = [
item for item in (fallthrough, clear_order) if isinstance(item, Mapping)
]
evidence_addresses = _dedupe_ints(
int(address)
for item in evidence_items
for address in item.get("addresses", [])
if isinstance(address, int)
)
return {
"kind": "sci1_rx_error_handling_candidate",
"error_latch_address": RX_ERROR_LATCH_ADDRESS,
"error_latch_address_hex": h16(RX_ERROR_LATCH_ADDRESS),
"error_latch_bit": 7,
"fallthrough_to_rx_byte_path": fallthrough is not None,
"rdrf_clear_before_rdr_read": clear_order is not None,
"summary": (
"SCI1 ERI appears to mark a physical receive error and continue into the RXI "
"byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order."
),
"manual_caveat": (
"Manual text distinguishes ORER from FER/PER data transfer into RDR and describes "
"the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order."
),
"evidence_addresses": evidence_addresses,
"evidence_addresses_hex": [h16(address) for address in evidence_addresses],
"confidence": "candidate-medium" if fallthrough else "candidate-low",
}
def _is_bclr_bit(ins: Instruction, address: int, bit: int) -> bool:
return (
_mnemonic_root(ins.mnemonic) == "BCLR"
and _is_write_to_address(ins, address)
and _immediate_source_value(ins.operands) == bit
)
def _is_bset_bit(ins: Instruction, address: int, bit: int) -> bool:
return (
_mnemonic_root(ins.mnemonic) == "BSET"
and _is_write_to_address(ins, address)
and _immediate_source_value(ins.operands) == bit
)
def _is_read_from_address(ins: Instruction, address: int) -> bool: def _is_read_from_address(ins: Instruction, address: int) -> bool:
source, destination = _source_destination_operands(ins.operands) source, destination = _source_destination_operands(ins.operands)
if _operand_mentions_address(source, address): if _operand_mentions_address(source, address):
@@ -792,6 +939,17 @@ def _dedupe_instructions(instructions: list[Instruction]) -> list[Instruction]:
return output return output
def _dedupe_ints(values: Iterable[int]) -> list[int]:
output: list[int] = []
seen: set[int] = set()
for value in values:
if value in seen:
continue
seen.add(value)
output.append(value)
return output
def _instruction_sequence( def _instruction_sequence(
instructions: Mapping[int, Instruction] | Iterable[Instruction], instructions: Mapping[int, Instruction] | Iterable[Instruction],
) -> list[Instruction]: ) -> list[Instruction]:
@@ -837,9 +995,12 @@ def _operand_mentions_address(operand: str, address: int) -> bool:
operand_upper = operand.upper().replace(" ", "") operand_upper = operand.upper().replace(" ", "")
names = { names = {
SCI1_TDR_ADDRESS: ("SCI1_TDR",), SCI1_TDR_ADDRESS: ("SCI1_TDR",),
SCI1_SSR_ADDRESS: ("SCI1_SSR",),
SCI1_RDR_ADDRESS: ("SCI1_RDR",),
TX_BUFFER_START: ("TX_BUFFER",), TX_BUFFER_START: ("TX_BUFFER",),
TX_CHECKSUM_ADDRESS: ("TX_CHECKSUM",), TX_CHECKSUM_ADDRESS: ("TX_CHECKSUM",),
TX_INDEX_ADDRESS: ("TX_INDEX",), TX_INDEX_ADDRESS: ("TX_INDEX",),
RX_ERROR_LATCH_ADDRESS: ("RX_ERROR_LATCH",),
} }
if any(name in operand_upper for name in names.get(address, ())): if any(name in operand_upper for name in names.get(address, ())):
return True return True

1157
h8536/serial_semantics.py
View File

File diff suppressed because it is too large Load Diff

144
tests/test_serial_pseudocode.py
View File

@@ -2,6 +2,7 @@ import json
import tempfile import tempfile
import unittest import unittest
from pathlib import Path from pathlib import Path
from unittest.mock import patch
from h8536.serial_pseudocode import ( from h8536.serial_pseudocode import (
SerialPseudocodeOptions, SerialPseudocodeOptions,
@@ -13,6 +14,27 @@ from h8536.serial_pseudocode import (
def candidate_payload() -> dict: def candidate_payload() -> dict:
return { return {
"instructions": [], "instructions": [],
"dtc_vectors": [],
"sci": {
"channels": {
"SCI1": {
"configurations": [
{
"mode": "async",
"mode_summary": "async 8-bit even parity 1 stop",
"smr": 0x24,
"smr_hex": "H'24",
"brr": 0x07,
"brr_hex": "H'07",
"scr": 0x3C,
"scr_hex": "H'3C",
"clock_source": "internal",
"baud_bps": None,
},
],
},
},
},
"sci_protocol": { "sci_protocol": {
"manual_references": [ "manual_references": [
"Manual/0900766b802125d0.md:15794 RDR receive data register", "Manual/0900766b802125d0.md:15794 RDR receive data register",
@@ -87,8 +109,20 @@ def candidate_payload() -> dict:
"confidence_reason": "RX count, copy, and checksum-validation evidence were observed", "confidence_reason": "RX count, copy, and checksum-validation evidence were observed",
"caveat": "candidate frame means six consecutive bytes, not a proven delimited packet", "caveat": "candidate frame means six consecutive bytes, not a proven delimited packet",
"comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis", "comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis",
"rx_error_handling": {
"error_latch_address": 0xFAA4,
"error_latch_address_hex": "H'FAA4",
"error_latch_bit": 7,
"fallthrough_to_rx_byte_path": True,
"rdrf_clear_before_rdr_read": True,
"summary": "SCI1 ERI marks a physical receive error and continues into RXI byte capture.",
"manual_caveat": "The ROM clears RDRF before reading RDR; preserve that observed order.",
"evidence_addresses_hex": ["H'BB57", "H'BB69", "H'BB6D"],
},
"evidence_addresses_hex": { "evidence_addresses_hex": {
"rx_rdr_read": ["H'BB6D"], "rx_rdr_read": ["H'BB6D"],
"rx_rdrf_clear_before_rdr_read": ["H'BB69", "H'BB6D"],
"rx_eri_falls_through_to_rxi": ["H'BB57", "H'BB5B", "H'BB5F", "H'BB63", "H'BB69", "H'BB6D"],
"rx_xor_checksum_validation": ["H'BBD6", "H'BBEC"], "rx_xor_checksum_validation": ["H'BBD6", "H'BBEC"],
}, },
}, },
@@ -121,6 +155,9 @@ class SerialPseudocodeTest(unittest.TestCase):
self.assertIn("focused SCI RX/TX pseudocode from rom.json", text) self.assertIn("focused SCI RX/TX pseudocode from rom.json", text)
self.assertIn("SCI1 TX 6-byte frame at H'F858-H'F85D", text) self.assertIn("SCI1 TX 6-byte frame at H'F858-H'F85D", text)
self.assertIn("SCI1 RX 6-byte frame captured at H'F868-H'F86D", text) self.assertIn("SCI1 RX 6-byte frame captured at H'F868-H'F86D", text)
self.assertIn("8E1 SCI characters carry the 6 protocol bytes", text)
self.assertIn("SMR=H'24, BRR=H'07, SCR=H'3C", text)
self.assertIn("No SCI1 RXI/TXI DTC vector entries are present", text)
self.assertIn("MAX202 pin 11 traces to H8 pin 66", text) self.assertIn("MAX202 pin 11 traces to H8 pin 66", text)
self.assertIn("Manual/0900766b802125d0.md:15823 TDR transmit data register", text) self.assertIn("Manual/0900766b802125d0.md:15823 TDR transmit data register", text)
self.assertIn("#define TX_FRAME(n) MEM8[(u16)(0xF858u + (n))]", text) self.assertIn("#define TX_FRAME(n) MEM8[(u16)(0xF858u + (n))]", text)
@@ -132,6 +169,9 @@ class SerialPseudocodeTest(unittest.TestCase):
self.assertIn("SCI1_SSR &= (u8)~SCI_SSR_RDRF;\n byte = SCI1_RDR;", text) self.assertIn("SCI1_SSR &= (u8)~SCI_SSR_RDRF;\n byte = SCI1_RDR;", text)
self.assertIn("RX_CAPTURE(RX_INDEX) = byte;", text) self.assertIn("RX_CAPTURE(RX_INDEX) = byte;", text)
self.assertIn("return sci1_process_rx_candidate_frame();", text) self.assertIn("return sci1_process_rx_candidate_frame();", text)
self.assertIn("RX_ERROR_LATCH |= RX_ERROR_LATCH_PHYSICAL_ERROR;", text)
self.assertIn("sci1_rx_byte_received_candidate_isr();", text)
self.assertIn("RX error handling: SCI1 ERI marks a physical receive error", text)
self.assertIn("rx_xor_checksum_validation: H'BBD6, H'BBEC", text) self.assertIn("rx_xor_checksum_validation: H'BBD6, H'BBEC", text)
def test_generates_candidate_protocol_semantics_switch(self): def test_generates_candidate_protocol_semantics_switch(self):
@@ -145,6 +185,110 @@ class SerialPseudocodeTest(unittest.TestCase):
self.assertIn("case 0x01u:", text) self.assertIn("case 0x01u:", text)
self.assertIn("candidate_read_value(logical_index, value);", text) self.assertIn("candidate_read_value(logical_index, value);", text)
def test_surfaces_refined_semantic_candidates(self):
analysis = {
"protocol_semantics": [
{
"confidence": "medium",
"confidence_score": 0.7,
"commands": [
{
"command_value": 0,
"command_value_hex": "0x00",
"name_candidate": "set_value_acked",
"summary": "candidate acknowledged set",
"effects": [
{
"kind": "table_write_candidate",
"target_candidate": "primary_value_table_candidate",
"source_candidate": "RX[3:4] value bytes",
"table_base_hex": "H'E000",
}
],
}
],
"command_effects": [
{
"command_value": 0,
"command_value_hex": "0x00",
"name_candidate": "set_value_acked",
"summary": "Candidate acknowledged set writes value bytes.",
"effects": [
{
"kind": "table_write_candidate",
"target_candidate": "primary_value_table_candidate",
"source_candidate": "RX[3:4] value bytes",
"table_base_hex": "H'E000",
"evidence_addresses_hex": ["H'C010"],
}
],
"evidence_addresses_hex": ["H'C000"],
}
],
"response_schemas": [
{
"response_id": "response_at_C030",
"bytes": [
{"byte": "byte0", "source_expression": "0x04"},
{"byte": "byte1", "source_expression": "RX[1]"},
],
"evidence_addresses_hex": ["H'C01C", "H'C024"],
}
],
"logical_table_map_candidates": [
{
"name_candidate": "primary_value_table_candidate",
"logical_base_address_hex": "H'E000",
"element_candidate": "word_value",
"observed_accesses": ["write"],
"evidence_addresses_hex": ["H'C010"],
}
],
"state_variable_candidates": [
{
"name_candidate": "serial_session_flags_candidate",
"address": 0xFAA2,
"address_hex": "H'FAA2",
"read_count": 1,
"write_count": 2,
"bit_candidates": [7],
"evidence_addresses_hex": ["H'C018"],
}
],
"retry_error_model": {
"checksum_failure_path": {
"condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]",
"error_target": "loc_BE29",
},
"retry_path": {
"counter_address_hex": "H'FAA6",
"threshold_candidate": 2,
"summary": "Candidate retry path stages a command 0x07 response.",
},
"command_0x07_path": {
"summary": "Candidate explicit command 0x07 path copies previous TX frame bytes.",
},
"evidence_addresses_hex": ["H'BBD6", "H'BE29"],
},
}
]
}
with patch("h8536.serial_pseudocode.analyze_serial_semantics", return_value=analysis):
text = generate_serial_pseudocode(candidate_payload())
self.assertIn("command effects:", text)
self.assertIn("effect: table_write_candidate; target primary_value_table_candidate", text)
self.assertIn("response schemas:", text)
self.assertIn("response_at_C030: byte0=0x04; byte1=RX[1]", text)
self.assertIn("table map candidates:", text)
self.assertIn("primary_value_table_candidate at H'E000", text)
self.assertIn("state variable candidates:", text)
self.assertIn("serial_session_flags_candidate H'FAA2: reads 1, writes 2; bits 7", text)
self.assertIn("retry/error model candidate:", text)
self.assertIn("checksum path: 0x5A-seeded XOR over RX[0..4] differs from RX[5] -> loc_BE29", text)
self.assertIn("candidate effect: table_write_candidate; target primary_value_table_candidate", text)
def test_tx_only_option_omits_rx_functions(self): def test_tx_only_option_omits_rx_functions(self):
text = generate_serial_pseudocode( text = generate_serial_pseudocode(
candidate_payload(), candidate_payload(),

18
tests/test_serial_reconstruction.py
View File

@@ -88,6 +88,11 @@ class SerialReconstructionTest(unittest.TestCase):
def test_candidate_sci1_rx_frame_length_and_checksum_validation_pattern(self): def test_candidate_sci1_rx_frame_length_and_checksum_validation_pattern(self):
instructions = { instructions = {
0x4FF0: ins(0x4FF0, "BSET.B", "#7, @H'FAA4", [0xFAA4]),
0x4FF4: ins(0x4FF4, "BCLR.B", "#5, @SCI1_SSR", [0xFEDC]),
0x4FF8: ins(0x4FF8, "BCLR.B", "#4, @SCI1_SSR", [0xFEDC]),
0x4FFC: ins(0x4FFC, "BCLR.B", "#3, @SCI1_SSR", [0xFEDC]),
0x4FFE: ins(0x4FFE, "BCLR.B", "#6, @SCI1_SSR", [0xFEDC]),
0x5000: ins(0x5000, "MOV:G.B", "@SCI1_RDR, R0", [0xFEDD]), 0x5000: ins(0x5000, "MOV:G.B", "@SCI1_RDR, R0", [0xFEDD]),
0x5004: ins(0x5004, "MOV:G.B", "R0, @(-H'0798,R1)", []), 0x5004: ins(0x5004, "MOV:G.B", "R0, @(-H'0798,R1)", []),
0x5008: ins(0x5008, "ADD:Q.B", "#1, R1", []), 0x5008: ins(0x5008, "ADD:Q.B", "#1, R1", []),
@@ -119,11 +124,24 @@ class SerialReconstructionTest(unittest.TestCase):
self.assertEqual(candidate["checksum_address"], 0xF865) self.assertEqual(candidate["checksum_address"], 0xF865)
self.assertEqual(candidate["checksum_seed"], 0x5A) self.assertEqual(candidate["checksum_seed"], 0x5A)
self.assertIn("no explicit header", candidate["confidence_reason"]) self.assertIn("no explicit header", candidate["confidence_reason"])
self.assertIn("rx_rdrf_clear_before_rdr_read", candidate["evidence_addresses"])
self.assertIn("rx_eri_falls_through_to_rxi", candidate["evidence_addresses"])
self.assertTrue(candidate["rx_error_handling"]["fallthrough_to_rx_byte_path"])
self.assertTrue(candidate["rx_error_handling"]["rdrf_clear_before_rdr_read"])
self.assertEqual(candidate["rx_error_handling"]["error_latch_address"], 0xFAA4)
comment = serial_reconstruction_comment_for_instruction(analysis, 0x5138) comment = serial_reconstruction_comment_for_instruction(analysis, 0x5138)
self.assertIn("candidate/evidence-supported SCI1 6-byte RX frame", comment) self.assertIn("candidate/evidence-supported SCI1 6-byte RX frame", comment)
self.assertIn("checksum H'F865", comment) self.assertIn("checksum H'F865", comment)
self.assertIn("confidence high", comment) self.assertIn("confidence high", comment)
self.assertIn(
"ROM clears SCI1 SSR.RDRF before reading SCI1_RDR",
serial_reconstruction_comment_for_instruction(analysis, 0x4FFE),
)
self.assertIn(
"SCI1 ERI latches FAA4.bit7",
serial_reconstruction_comment_for_instruction(analysis, 0x4FF0),
)
def test_lone_tdr_write_does_not_emit_reconstruction(self): def test_lone_tdr_write_does_not_emit_reconstruction(self):
instructions = { instructions = {

157
tests/test_serial_semantics.py
View File

@@ -1,4 +1,5 @@
import unittest import unittest
from typing import Any
from h8536.serial_semantics import analyze_serial_semantics from h8536.serial_semantics import analyze_serial_semantics
@@ -60,6 +61,92 @@ def only_semantics(testcase: unittest.TestCase, payload: dict) -> dict:
return analysis["protocol_semantics"][0] return analysis["protocol_semantics"][0]
def semantic_items(value: Any) -> list[Any]:
if isinstance(value, list):
return value
if isinstance(value, dict):
return list(value.values())
return []
def command_item(items: list[Any], command: int) -> Any:
for item in items:
if not isinstance(item, dict):
continue
command_value = item.get("command_value", item.get("command"))
if command_value == command:
return item
if isinstance(command_value, str) and command_value.lower() == f"0x{command:02x}":
return item
return None
def semantic_text(value: Any) -> str:
if isinstance(value, dict):
return " ".join(
f"{key} {semantic_text(item)}"
for key, item in value.items()
).lower()
if isinstance(value, list):
return " ".join(semantic_text(item) for item in value).lower()
return str(value).lower()
def planned_semantics_payload() -> dict:
return base_payload(
[
instruction(0xBF00, "MOV:G.B", "@H'F860, R0", [0xF860]),
instruction(0xBF04, "AND.B", "#H'07, R0"),
instruction(0xBF08, "CMP:E.B", "#H'00, R0"),
instruction(0xBF0C, "BEQ", "loc_C000", targets=[0xC000]),
instruction(0xBF10, "CMP:E.B", "#H'01, R0"),
instruction(0xBF14, "BEQ", "loc_C100", targets=[0xC100]),
instruction(0xBF18, "CMP:E.B", "#H'06, R0"),
instruction(0xBF1C, "BEQ", "loc_C600", targets=[0xC600]),
instruction(0xBF20, "CMP:E.B", "#H'07, R0"),
instruction(0xBF24, "BEQ", "loc_C700", targets=[0xC700]),
instruction(0xC000, "MOV:G.B", "@H'F861, R1", [0xF861]),
instruction(0xC004, "MOV:G.B", "@H'F862, R2", [0xF862]),
instruction(0xC008, "BSR", "loc_622B", targets=[0x622B]),
instruction(0xC00C, "MOV:G.W", "@H'F863, R3", [0xF863]),
instruction(0xC010, "MOV:G.W", "R3, @H'F900", [0xF900]),
instruction(0xC014, "MOV:G.W", "R3, @H'F920", [0xF920]),
instruction(0xC018, "MOV:G.B", "#H'01, @H'FAA2", [0xFAA2]),
instruction(0xC01C, "MOV:G.B", "#H'04, @H'F850", [0xF850]),
instruction(0xC020, "MOV:G.B", "@H'F861, R4", [0xF861]),
instruction(0xC024, "MOV:G.B", "R4, @H'F851", [0xF851]),
instruction(0xC028, "MOV:G.B", "@H'F862, R5", [0xF862]),
instruction(0xC02C, "MOV:G.B", "R5, @H'F852", [0xF852]),
instruction(0xC030, "BSR", "loc_BA26", targets=[0xBA26]),
instruction(0xC100, "MOV:G.B", "@H'F861, R1", [0xF861]),
instruction(0xC104, "MOV:G.B", "@H'F862, R2", [0xF862]),
instruction(0xC108, "BSR", "loc_622B", targets=[0x622B]),
instruction(0xC10C, "MOV:G.W", "@H'F900, R3", [0xF900]),
instruction(0xC110, "MOV:G.B", "#H'04, @H'F850", [0xF850]),
instruction(0xC114, "MOV:G.B", "@H'F861, R4", [0xF861]),
instruction(0xC118, "MOV:G.B", "R4, @H'F851", [0xF851]),
instruction(0xC11C, "MOV:G.B", "@H'F862, R5", [0xF862]),
instruction(0xC120, "MOV:G.B", "R5, @H'F852", [0xF852]),
instruction(0xC124, "MOV:G.W", "R3, @H'F853", [0xF853]),
instruction(0xC128, "MOV:G.B", "@H'F9B5, R6", [0xF9B5]),
instruction(0xC12C, "BSR", "loc_BA26", targets=[0xBA26]),
instruction(0xC600, "MOV:G.B", "@H'F861, R1", [0xF861]),
instruction(0xC604, "MOV:G.B", "@H'F862, R2", [0xF862]),
instruction(0xC608, "BSR", "loc_622B", targets=[0x622B]),
instruction(0xC60C, "MOV:G.W", "@H'F863, R3", [0xF863]),
instruction(0xC610, "MOV:G.W", "R3, @H'F940", [0xF940]),
instruction(0xC614, "MOV:G.B", "#H'01, @H'F980", [0xF980]),
instruction(0xC618, "MOV:G.B", "#H'01, @H'F9C0", [0xF9C0]),
instruction(0xC700, "MOV:G.B", "#H'07, @H'F850", [0xF850]),
instruction(0xC704, "MOV:G.B", "@H'F861, R1", [0xF861]),
instruction(0xC708, "MOV:G.B", "R1, @H'F851", [0xF851]),
instruction(0xC70C, "BSR", "loc_BA26", targets=[0xBA26]),
instruction(0xC800, "CMP:E.B", "@H'F865, R7", [0xF865]),
instruction(0xC804, "BNE", "loc_C700", targets=[0xC700]),
]
)
class SerialSemanticsTest(unittest.TestCase): class SerialSemanticsTest(unittest.TestCase):
def test_detects_low_three_bit_command_dispatch(self): def test_detects_low_three_bit_command_dispatch(self):
payload = base_payload( payload = base_payload(
@@ -139,6 +226,76 @@ class SerialSemanticsTest(unittest.TestCase):
[0xF850, 0xF851, 0xF852, 0xF853, 0xF854], [0xF850, 0xF851, 0xF852, 0xF853, 0xF854],
) )
def test_planned_command_effects_include_core_command_behaviors(self):
semantics = only_semantics(self, planned_semantics_payload())
self.assertIn("command_effects", semantics)
effects = semantic_items(semantics["command_effects"])
command_0 = command_item(effects, 0x00)
self.assertIsNotNone(command_0)
command_0_text = semantic_text(command_0)
self.assertIn("write", command_0_text)
self.assertIn("primary_value_table", command_0_text)
self.assertIn("current_value_table", command_0_text)
command_1 = command_item(effects, 0x01)
self.assertIsNotNone(command_1)
command_1_text = semantic_text(command_1)
self.assertIn("read", command_1_text)
self.assertIn("response", command_1_text)
command_6 = command_item(effects, 0x06)
self.assertIsNotNone(command_6)
command_6_text = semantic_text(command_6)
self.assertIn("write", command_6_text)
self.assertIn("secondary_value_table", command_6_text)
def test_planned_response_schema_tracks_immediates_and_rx_copies(self):
semantics = only_semantics(self, planned_semantics_payload())
self.assertIn("response_schema", semantics)
schema_text = semantic_text(semantics["response_schema"])
self.assertIn("tx", schema_text)
self.assertIn("byte0", schema_text)
self.assertIn("0x04", schema_text)
self.assertIn("byte1", schema_text)
self.assertIn("rx[1]", schema_text)
self.assertIn("byte2", schema_text)
self.assertIn("rx[2]", schema_text)
def test_planned_table_map_candidates_name_known_tables(self):
semantics = only_semantics(self, planned_semantics_payload())
self.assertIn("table_map_candidates", semantics)
table_text = semantic_text(semantics["table_map_candidates"])
self.assertIn("primary_value_table", table_text)
self.assertIn("current_value_table", table_text)
self.assertIn("secondary_value_table", table_text)
self.assertIn("flag_table", table_text)
def test_planned_state_variable_candidates_include_known_addresses(self):
semantics = only_semantics(self, planned_semantics_payload())
self.assertIn("state_variable_candidates", semantics)
state_text = semantic_text(semantics["state_variable_candidates"])
self.assertIn("faa2", state_text)
self.assertIn("f9b5", state_text)
self.assertIn("f9c0", state_text)
def test_planned_retry_error_model_identifies_retransmit_and_checksum_error(self):
semantics = only_semantics(self, planned_semantics_payload())
self.assertIn("retry_error_model", semantics)
retry_text = semantic_text(semantics["retry_error_model"])
self.assertIn("retransmit", retry_text)
self.assertIn("0x07", retry_text)
self.assertIn("checksum_error_response", retry_text)
def test_missing_serial_reconstruction_candidates_emit_no_protocol_semantics(self): def test_missing_serial_reconstruction_candidates_emit_no_protocol_semantics(self):
payload = { payload = {
"serial_reconstruction": {"candidates": []}, "serial_reconstruction": {"candidates": []},