317 lines
15 KiB
Python
317 lines
15 KiB
Python
import json
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import tempfile
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import unittest
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from pathlib import Path
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from unittest.mock import patch
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from h8536.serial_pseudocode import (
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SerialPseudocodeOptions,
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generate_serial_pseudocode,
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write_serial_pseudocode,
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)
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def candidate_payload() -> dict:
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return {
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"instructions": [],
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"dtc_vectors": [],
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"sci": {
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"channels": {
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"SCI1": {
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"configurations": [
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{
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"mode": "async",
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"mode_summary": "async 8-bit even parity 1 stop",
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"smr": 0x24,
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"smr_hex": "H'24",
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"brr": 0x07,
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"brr_hex": "H'07",
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"scr": 0x3C,
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"scr_hex": "H'3C",
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"clock_source": "internal",
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"baud_bps": None,
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},
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],
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},
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},
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},
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"sci_protocol": {
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"manual_references": [
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"Manual/0900766b802125d0.md:15794 RDR receive data register",
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"Manual/0900766b802125d0.md:15823 TDR transmit data register",
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],
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},
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"board_profile": {
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"summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.",
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"manual_references": [
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"Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD",
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],
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"traces": [
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{
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"signal": "TXD",
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"h8_pin": 66,
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"h8_pin_name": "P95/TXD",
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"max202_pin": 11,
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"evidence": "MAX202 pin 11 traces to H8 pin 66",
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},
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{
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"signal": "RXD",
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"h8_pin": 67,
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"h8_pin_name": "P96/RXD",
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"max202_pin": 12,
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"evidence": "MAX202 pin 12 traces to H8 pin 67",
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},
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],
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},
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"serial_reconstruction": {
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"candidates": [
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{
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"kind": "candidate_sci1_tx_frame",
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"channel": "SCI1",
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"frame_length": 6,
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"buffer_start": 0xF858,
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"buffer_start_hex": "H'F858",
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"buffer_end": 0xF85D,
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"buffer_end_hex": "H'F85D",
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"checksum_address": 0xF85D,
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"tx_index_address": 0xF9C2,
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"tdr_address": 0xFEDB,
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"checksum_seed": 0x5A,
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"checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
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"confidence": "high",
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"confidence_score": 0.95,
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"confidence_reason": "all required independent evidence groups were observed",
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"comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis",
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"evidence_addresses_hex": {
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"tx_checksum_seed": ["H'BA4E"],
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"xor_checksum_chain": ["H'BA50", "H'BA54"],
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},
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},
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{
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"kind": "candidate_sci1_rx_frame",
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"channel": "SCI1",
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"frame_length": 6,
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"capture_buffer_start": 0xF868,
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"capture_buffer_start_hex": "H'F868",
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"capture_buffer_end": 0xF86D,
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"capture_buffer_end_hex": "H'F86D",
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"validation_buffer_start": 0xF860,
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"validation_buffer_end": 0xF865,
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"checksum_address": 0xF865,
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"rx_index_address": 0xF9C3,
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"rdr_address": 0xFEDD,
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"interbyte_timeout_address": 0xF9C1,
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"complete_timer_address": 0xF9C5,
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"checksum_seed": 0x5A,
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"checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
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"confidence": "high",
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"confidence_score": 0.9,
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"confidence_reason": "RX count, copy, and checksum-validation evidence were observed",
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"caveat": "candidate frame means six consecutive bytes, not a proven delimited packet",
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"comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis",
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"rx_error_handling": {
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"error_latch_address": 0xFAA4,
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"error_latch_address_hex": "H'FAA4",
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"error_latch_bit": 7,
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"fallthrough_to_rx_byte_path": True,
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"rdrf_clear_before_rdr_read": True,
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"summary": "SCI1 ERI marks a physical receive error and continues into RXI byte capture.",
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"manual_caveat": "The ROM clears RDRF before reading RDR; preserve that observed order.",
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"evidence_addresses_hex": ["H'BB57", "H'BB69", "H'BB6D"],
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},
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"evidence_addresses_hex": {
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"rx_rdr_read": ["H'BB6D"],
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"rx_rdrf_clear_before_rdr_read": ["H'BB69", "H'BB6D"],
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"rx_eri_falls_through_to_rxi": ["H'BB57", "H'BB5B", "H'BB5F", "H'BB63", "H'BB69", "H'BB6D"],
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"rx_xor_checksum_validation": ["H'BBD6", "H'BBEC"],
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},
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},
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],
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},
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}
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def semantic_payload() -> dict:
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payload = candidate_payload()
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payload["instructions"] = [
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{"address": 0xBC08, "mnemonic": "MOV:G.B", "operands": "@H'F860, R0", "references": [{"address": 0xF860}], "targets": []},
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{"address": 0xBC0C, "mnemonic": "AND.B", "operands": "#H'07, R0", "references": [], "targets": []},
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{"address": 0xBC20, "mnemonic": "CMP:E.B", "operands": "#H'00, R0", "references": [], "targets": []},
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{"address": 0xBC22, "mnemonic": "BEQ", "operands": "loc_BC69", "references": [], "targets": [0xBC69]},
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{"address": 0xBC24, "mnemonic": "CMP:E.B", "operands": "#H'01, R0", "references": [], "targets": []},
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{"address": 0xBC26, "mnemonic": "BEQ", "operands": "loc_BCD7", "references": [], "targets": [0xBCD7]},
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{"address": 0xBCB0, "mnemonic": "MOV:G.B", "operands": "#H'04, @H'F850", "references": [{"address": 0xF850}], "targets": []},
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{"address": 0xBCB5, "mnemonic": "MOV:G.B", "operands": "@H'F861, R0", "references": [{"address": 0xF861}], "targets": []},
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{"address": 0xBCB9, "mnemonic": "MOV:G.B", "operands": "R0, @H'F851", "references": [{"address": 0xF851}], "targets": []},
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{"address": 0xBCCD, "mnemonic": "BSR", "operands": "loc_BA26", "references": [], "targets": [0xBA26]},
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]
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return payload
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class SerialPseudocodeTest(unittest.TestCase):
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def test_generates_focused_tx_and_rx_candidate_paths(self):
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text = generate_serial_pseudocode(candidate_payload(), source_name="rom.json")
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self.assertIn("focused SCI RX/TX pseudocode from rom.json", text)
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self.assertIn("SCI1 TX 6-byte frame at H'F858-H'F85D", text)
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self.assertIn("SCI1 RX 6-byte frame captured at H'F868-H'F86D", text)
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self.assertIn("8E1 SCI characters carry the 6 protocol bytes", text)
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self.assertIn("SMR=H'24, BRR=H'07, SCR=H'3C", text)
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self.assertIn("No SCI1 RXI/TXI DTC vector entries are present", text)
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self.assertIn("MAX202 pin 11 traces to H8 pin 66", text)
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self.assertIn("Manual/0900766b802125d0.md:15823 TDR transmit data register", text)
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self.assertIn("#define TX_FRAME(n) MEM8[(u16)(0xF858u + (n))]", text)
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self.assertIn("#define RX_CAPTURE(n) MEM8[(u16)(0xF868u + (n))]", text)
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self.assertIn("checksum ^= TX_FRAME(4);", text)
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self.assertIn("TX_FRAME(5) = sci1_tx_candidate_checksum();", text)
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self.assertIn("SCI1_TDR = TX_FRAME(0);", text)
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self.assertIn("void sci1_txi_candidate_isr(void)", text)
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self.assertIn("SCI1_SSR &= (u8)~SCI_SSR_RDRF;\n byte = SCI1_RDR;", text)
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self.assertIn("RX_CAPTURE(RX_INDEX) = byte;", text)
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self.assertIn("return sci1_process_rx_candidate_frame();", text)
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self.assertIn("RX_ERROR_LATCH |= RX_ERROR_LATCH_PHYSICAL_ERROR;", text)
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self.assertIn("sci1_rx_byte_received_candidate_isr();", text)
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self.assertIn("RX error handling: SCI1 ERI marks a physical receive error", text)
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self.assertIn("rx_xor_checksum_validation: H'BBD6, H'BBEC", text)
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def test_generates_candidate_protocol_semantics_switch(self):
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text = generate_serial_pseudocode(semantic_payload())
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self.assertIn("Candidate Protocol Semantics", text)
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self.assertIn("byte0: op_flags", text)
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self.assertIn("dispatch: command_low3 = RX_FRAME(0) & 0x07", text)
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self.assertIn("case 0x00u:", text)
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self.assertIn("candidate_set_value_acked(logical_index, value);", text)
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self.assertIn("case 0x01u:", text)
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self.assertIn("candidate_read_value(logical_index, value);", text)
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def test_surfaces_refined_semantic_candidates(self):
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analysis = {
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"protocol_semantics": [
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{
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"confidence": "medium",
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"confidence_score": 0.7,
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"commands": [
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{
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"command_value": 0,
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"command_value_hex": "0x00",
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"name_candidate": "set_value_acked",
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"summary": "candidate acknowledged set",
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"effects": [
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{
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"kind": "table_write_candidate",
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"target_candidate": "primary_value_table_candidate",
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"source_candidate": "RX[3:4] value bytes",
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"table_base_hex": "H'E000",
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}
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],
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}
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],
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"command_effects": [
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{
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"command_value": 0,
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"command_value_hex": "0x00",
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"name_candidate": "set_value_acked",
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"summary": "Candidate acknowledged set writes value bytes.",
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"effects": [
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{
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"kind": "table_write_candidate",
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"target_candidate": "primary_value_table_candidate",
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"source_candidate": "RX[3:4] value bytes",
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"table_base_hex": "H'E000",
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"evidence_addresses_hex": ["H'C010"],
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}
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],
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"evidence_addresses_hex": ["H'C000"],
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}
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],
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"response_schemas": [
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{
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"response_id": "response_at_C030",
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"bytes": [
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{"byte": "byte0", "source_expression": "0x04"},
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{"byte": "byte1", "source_expression": "RX[1]"},
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],
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"evidence_addresses_hex": ["H'C01C", "H'C024"],
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}
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],
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"logical_table_map_candidates": [
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{
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"name_candidate": "primary_value_table_candidate",
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"logical_base_address_hex": "H'E000",
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"element_candidate": "word_value",
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"observed_accesses": ["write"],
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"evidence_addresses_hex": ["H'C010"],
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}
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],
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"state_variable_candidates": [
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{
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"name_candidate": "serial_session_flags_candidate",
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"address": 0xFAA2,
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"address_hex": "H'FAA2",
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"read_count": 1,
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"write_count": 2,
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"bit_candidates": [7],
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"evidence_addresses_hex": ["H'C018"],
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}
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],
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"retry_error_model": {
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"checksum_failure_path": {
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"condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]",
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"error_target": "loc_BE29",
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},
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"retry_path": {
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"counter_address_hex": "H'FAA6",
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"threshold_candidate": 2,
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"summary": "Candidate retry path stages a command 0x07 response.",
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},
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"command_0x07_path": {
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"summary": "Candidate explicit command 0x07 path copies previous TX frame bytes.",
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},
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"evidence_addresses_hex": ["H'BBD6", "H'BE29"],
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},
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}
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]
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}
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with patch("h8536.serial_pseudocode.analyze_serial_semantics", return_value=analysis):
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text = generate_serial_pseudocode(candidate_payload())
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self.assertIn("command effects:", text)
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self.assertIn("effect: table_write_candidate; target primary_value_table_candidate", text)
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self.assertIn("response schemas:", text)
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self.assertIn("response_at_C030: byte0=0x04; byte1=RX[1]", text)
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self.assertIn("table map candidates:", text)
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self.assertIn("primary_value_table_candidate at H'E000", text)
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self.assertIn("state variable candidates:", text)
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self.assertIn("serial_session_flags_candidate H'FAA2: reads 1, writes 2; bits 7", text)
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self.assertIn("retry/error model candidate:", text)
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self.assertIn("checksum path: 0x5A-seeded XOR over RX[0..4] differs from RX[5] -> loc_BE29", text)
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self.assertIn("candidate effect: table_write_candidate; target primary_value_table_candidate", text)
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def test_tx_only_option_omits_rx_functions(self):
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text = generate_serial_pseudocode(
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candidate_payload(),
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options=SerialPseudocodeOptions(include_rx=False),
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)
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self.assertIn("void sci1_tx_start_candidate_frame(void)", text)
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self.assertNotIn("sci1_rx_byte_received_candidate_isr", text)
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def test_write_serial_pseudocode_writes_output_file(self):
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with tempfile.TemporaryDirectory() as tmp:
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input_path = Path(tmp) / "rom.json"
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output_path = Path(tmp) / "serial.c"
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input_path.write_text(
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json.dumps(candidate_payload()),
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encoding="utf-8",
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)
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write_serial_pseudocode(input_path, output_path, SerialPseudocodeOptions())
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self.assertIn("sci1_process_rx_candidate_frame", output_path.read_text(encoding="utf-8"))
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if __name__ == "__main__":
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unittest.main()
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