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timing adjustments

This commit is contained in:
Aiden
2026-05-25 22:17:36 +10:00
parent 6d4d9f0027
commit 4b50d0e98f
11 changed files with 313 additions and 40 deletions

View File

@@ -125,6 +125,21 @@ class MemoryMap:
self._set_register(SCI1_RDR, self.sci1.read(SCI1_RDR))
self._set_register(SCI1_SSR, self.sci1.read(SCI1_SSR))
def register8(self, address: int) -> int:
return self.registers[(address & 0xFFFF) - REGISTER_FIELD_START]
def register16(self, address: int) -> int:
address &= 0xFFFF
return (self.register8(address) << 8) | self.register8((address + 1) & 0xFFFF)
def set_register8(self, address: int, value: int) -> None:
self._set_register(address & 0xFFFF, value)
def set_register16(self, address: int, value: int) -> None:
address &= 0xFFFF
self._set_register(address, (value >> 8) & 0xFF)
self._set_register((address + 1) & 0xFFFF, value & 0xFF)
def _set_register(self, address: int, value: int) -> None:
self.registers[address - REGISTER_FIELD_START] = value & 0xFF