timing adjustments
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@@ -125,6 +125,21 @@ class MemoryMap:
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self._set_register(SCI1_RDR, self.sci1.read(SCI1_RDR))
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self._set_register(SCI1_SSR, self.sci1.read(SCI1_SSR))
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def register8(self, address: int) -> int:
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return self.registers[(address & 0xFFFF) - REGISTER_FIELD_START]
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def register16(self, address: int) -> int:
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address &= 0xFFFF
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return (self.register8(address) << 8) | self.register8((address + 1) & 0xFFFF)
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def set_register8(self, address: int, value: int) -> None:
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self._set_register(address & 0xFFFF, value)
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def set_register16(self, address: int, value: int) -> None:
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address &= 0xFFFF
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self._set_register(address, (value >> 8) & 0xFF)
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self._set_register((address + 1) & 0xFFFF, value & 0xFF)
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def _set_register(self, address: int, value: int) -> None:
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self.registers[address - REGISTER_FIELD_START] = value & 0xFF
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