Cycle states
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@@ -3,6 +3,7 @@ from __future__ import annotations
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import json
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from pathlib import Path
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from .cycles import cycle_comment
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from .formatting import h16, label_for
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from .memory import MEMORY_REGIONS, region_for
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from .model import Instruction
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@@ -30,6 +31,7 @@ def format_listing(
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traced: bool,
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dtc_vectors: dict[int, DtcVectorEntry] | None = None,
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data_candidates: dict[str, list[dict[str, object]]] | None = None,
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show_cycles: bool = False,
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) -> str:
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lines: list[str] = []
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lines.append("; H8/536 ROM disassembly")
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@@ -43,6 +45,8 @@ def format_listing(
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lines.append("; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC.")
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lines.append("; - The register field is H'FE80-H'FFFF; names below come from appendix B.")
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lines.append("; - @aa:8 short absolute operands use BR as the upper address byte.")
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if show_cycles:
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lines.append("; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states.")
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lines.append("")
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lines.append("; Memory Map")
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for region in MEMORY_REGIONS:
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@@ -84,7 +88,15 @@ def format_listing(
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lines.append(f"{labels[address]}:")
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raw = " ".join(f"{byte:02X}" for byte in ins.raw)
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padded_raw = raw.ljust(14)
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comment_parts = [part for part in (ins.comment, _reference_comment(ins) if not ins.comment else "") if part]
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comment_parts = [
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part
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for part in (
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ins.comment,
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_reference_comment(ins) if not ins.comment else "",
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cycle_comment(ins.cycles) if show_cycles else "",
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)
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if part
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]
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comment = f" ; {'; '.join(comment_parts)}" if comment_parts else ""
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lines.append(f"{address:04X}: {padded_raw} {ins.text}{comment}")
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lines.append("")
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@@ -128,6 +140,7 @@ def write_json(
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"operands": ins.operands,
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"kind": ins.kind,
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"targets": ins.targets,
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"cycles": ins.cycles,
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"references": [
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{
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"address": address,
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