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Cycle states

This commit is contained in:
Aiden
2026-05-25 13:54:34 +10:00
parent 5ad90ade49
commit 4649cf530f
8 changed files with 20317 additions and 2554 deletions

View File

@@ -3,6 +3,7 @@ from __future__ import annotations
import json
from pathlib import Path
from .cycles import cycle_comment
from .formatting import h16, label_for
from .memory import MEMORY_REGIONS, region_for
from .model import Instruction
@@ -30,6 +31,7 @@ def format_listing(
traced: bool,
dtc_vectors: dict[int, DtcVectorEntry] | None = None,
data_candidates: dict[str, list[dict[str, object]]] | None = None,
show_cycles: bool = False,
) -> str:
lines: list[str] = []
lines.append("; H8/536 ROM disassembly")
@@ -43,6 +45,8 @@ def format_listing(
lines.append("; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC.")
lines.append("; - The register field is H'FE80-H'FFFF; names below come from appendix B.")
lines.append("; - @aa:8 short absolute operands use BR as the upper address byte.")
if show_cycles:
lines.append("; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states.")
lines.append("")
lines.append("; Memory Map")
for region in MEMORY_REGIONS:
@@ -84,7 +88,15 @@ def format_listing(
lines.append(f"{labels[address]}:")
raw = " ".join(f"{byte:02X}" for byte in ins.raw)
padded_raw = raw.ljust(14)
comment_parts = [part for part in (ins.comment, _reference_comment(ins) if not ins.comment else "") if part]
comment_parts = [
part
for part in (
ins.comment,
_reference_comment(ins) if not ins.comment else "",
cycle_comment(ins.cycles) if show_cycles else "",
)
if part
]
comment = f" ; {'; '.join(comment_parts)}" if comment_parts else ""
lines.append(f"{address:04X}: {padded_raw} {ins.text}{comment}")
lines.append("")
@@ -128,6 +140,7 @@ def write_json(
"operands": ins.operands,
"kind": ins.kind,
"targets": ins.targets,
"cycles": ins.cycles,
"references": [
{
"address": address,