From 4649cf530fc412f721e3da77c800668defb9a9b8 Mon Sep 17 00:00:00 2001 From: Aiden <68633820+awils27@users.noreply.github.com> Date: Mon, 25 May 2026 13:54:34 +1000 Subject: [PATCH] Cycle states --- README.md | 5 +- build/rom_decompiled.asm | 5105 ++++---- build/rom_decompiled.json | 17317 +++++++++++++++++++++++++ h8536/cli.py | 4 + h8536/cycles.py | 376 + h8536/model.py | 1 + h8536/render.py | 15 +- tests/test_cycles_manual_examples.py | 48 + 8 files changed, 20317 insertions(+), 2554 deletions(-) create mode 100644 h8536/cycles.py create mode 100644 tests/test_cycles_manual_examples.py diff --git a/README.md b/README.md index 45cdd25..fecfb3e 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ python h8536_decompiler.py ROM\M27C512@DIP28_1.BIN --out build\rom_decompiled.as If you are using the repo-local venv: ```powershell -.\.venv\Scripts\python.exe h8536_decompiler.py --out build\rom_decompiled.asm --json build\rom_decompiled.json --callgraph-dot build\callgraph.dot +.\.venv\Scripts\python.exe h8536_decompiler.py --out build\rom_decompiled.asm --json build\rom_decompiled.json --cycles --callgraph-dot build\callgraph.dot ``` ## What It Does @@ -25,6 +25,7 @@ If you are using the repo-local venv: - Parses the DTC vector table described by the manual. - Scans unreached ROM ranges for ASCII strings and pointer-table candidates. - Emits function summaries and a direct-call graph in JSON, with optional Graphviz DOT output. +- Adds Appendix A cycle estimates to JSON and can append them to ASM comments. - Handles the E-clock transfer instructions `MOVFPE` and `MOVTPE`. The generated listing is written to: @@ -50,6 +51,7 @@ python h8536_decompiler.py --help - `--linear`: linear-sweep the selected range instead of tracing from vectors. - `--start H'1000 --end H'D100`: constrain the decode range. - `--br H'FE`: resolve short absolute `@aa:8` operands through a known base-register value. +- `--cycles`: append Appendix A cycle estimates to assembly comments. - `--callgraph-dot build\callgraph.dot`: write a Graphviz DOT call graph. ## Code Layout @@ -62,5 +64,6 @@ python h8536_decompiler.py --help - `h8536/analysis.py`: recursive tracing, linear sweep, labels, function grouping, and call graph analysis. - `h8536/data_analysis.py`: unreached string and pointer-table candidate scans. - `h8536/memory.py`: manual-derived memory-region tagging. +- `h8536/cycles.py`: Appendix A cycle estimate tables. - `h8536/render.py`: assembly and JSON output. - `h8536/model.py`, `h8536/rom.py`, `h8536/formatting.py`: shared data structures and helpers. diff --git a/build/rom_decompiled.asm b/build/rom_decompiled.asm index 6b53ab9..900b1c8 100644 --- a/build/rom_decompiled.asm +++ b/build/rom_decompiled.asm @@ -9,6 +9,7 @@ ; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC. ; - The register field is H'FE80-H'FFFF; names below come from appendix B. ; - @aa:8 short absolute operands use BR as the upper address byte. +; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states. ; Memory Map ; H'0000-H'009F exception_vectors vectors @@ -139,3403 +140,3403 @@ vec_reset_1000: -1000: 5F FE 80 MOV:I.W #H'FE80, R7 -1003: 0C 07 00 88 LDC.W #H'0700, SR -1007: 15 FE 80 06 FF MOV:G.B #H'FF, @P1DDR ; P1DDR = H'FF -100C: 15 FE 82 06 00 MOV:G.B #H'00, @P1DR ; P1DR = H'00 -1011: 15 FE 89 06 F9 MOV:G.B #H'F9, @P6DDR ; P6DDR = H'F9 -1016: 15 FE 8B 06 F1 MOV:G.B #H'F1, @P6DR ; P6DR = H'F1 -101B: 15 FE 8C 06 00 MOV:G.B #H'00, @P7DDR ; P7DDR = H'00 -1020: 15 FE 8E 06 00 MOV:G.B #H'00, @P7DR ; P7DR = H'00 -1025: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93 -102A: 15 FE FF 06 00 MOV:G.B #H'00, @P9DR ; P9DR = H'00 -102F: 15 FE FC 06 87 MOV:G.B #H'87, @SYSCR1 ; SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled) -1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM) -1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0) -103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1) -1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00 -1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_L ; FRT1_OCRA_L = H'9C -104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0) -1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1) -1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00 -105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12 -1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0) -1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0) -106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0) -1072: 15 FE D1 06 10 MOV:G.B #H'10, @TMR_TCSR ; TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0) -1077: 15 FE C0 06 38 MOV:G.B #H'38, @PWM1_TCR ; PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0) -107C: 15 FE C1 06 FF MOV:G.B #H'FF, @PWM1_DTR ; PWM1_DTR = H'FF -1081: 15 FE C4 06 38 MOV:G.B #H'38, @PWM2_TCR ; PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0) -1086: 15 FE C5 06 FF MOV:G.B #H'FF, @PWM2_DTR ; PWM2_DTR = H'FF -108B: 15 FE C8 06 3B MOV:G.B #H'3B, @PWM3_TCR ; PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1) -1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D -1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi) -109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock) -109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07 -10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi) -10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock) -10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07 -10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled) -10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field -10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits) -10C2: 15 FF 11 06 FF MOV:G.B #H'FF, @RAMCR ; RAMCR = H'FF (RAME=1; on-chip RAM enabled) -10C7: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR -10CB: 30 2E A8 BRA loc_3F76 +1000: 5F FE 80 MOV:I.W #H'FE80, R7 ; cycles=3 +1003: 0C 07 00 88 LDC.W #H'0700, SR ; cycles=6 +1007: 15 FE 80 06 FF MOV:G.B #H'FF, @P1DDR ; P1DDR = H'FF; cycles=9 +100C: 15 FE 82 06 00 MOV:G.B #H'00, @P1DR ; P1DR = H'00; cycles=9 +1011: 15 FE 89 06 F9 MOV:G.B #H'F9, @P6DDR ; P6DDR = H'F9; cycles=9 +1016: 15 FE 8B 06 F1 MOV:G.B #H'F1, @P6DR ; P6DR = H'F1; cycles=9 +101B: 15 FE 8C 06 00 MOV:G.B #H'00, @P7DDR ; P7DDR = H'00; cycles=9 +1020: 15 FE 8E 06 00 MOV:G.B #H'00, @P7DR ; P7DR = H'00; cycles=9 +1025: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +102A: 15 FE FF 06 00 MOV:G.B #H'00, @P9DR ; P9DR = H'00; cycles=9 +102F: 15 FE FC 06 87 MOV:G.B #H'87, @SYSCR1 ; SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled); cycles=9 +1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); cycles=9 +1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; cycles=9 +1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_L ; FRT1_OCRA_L = H'9C; cycles=11 +104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; cycles=11 +105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; cycles=9 +1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 +1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 +106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1072: 15 FE D1 06 10 MOV:G.B #H'10, @TMR_TCSR ; TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0); cycles=9 +1077: 15 FE C0 06 38 MOV:G.B #H'38, @PWM1_TCR ; PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +107C: 15 FE C1 06 FF MOV:G.B #H'FF, @PWM1_DTR ; PWM1_DTR = H'FF; cycles=9 +1081: 15 FE C4 06 38 MOV:G.B #H'38, @PWM2_TCR ; PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1086: 15 FE C5 06 FF MOV:G.B #H'FF, @PWM2_DTR ; PWM2_DTR = H'FF; cycles=9 +108B: 15 FE C8 06 3B MOV:G.B #H'3B, @PWM3_TCR ; PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1); cycles=9 +1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D; cycles=9 +1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9 +109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); cycles=9 +109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; cycles=9 +10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9 +10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); cycles=9 +10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; cycles=9 +10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 +10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field; cycles=9 +10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 +10C2: 15 FF 11 06 FF MOV:G.B #H'FF, @RAMCR ; RAMCR = H'FF (RAME=1; on-chip RAM enabled); cycles=9 +10C7: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=8 +10CB: 30 2E A8 BRA loc_3F76 ; cycles=8 loc_10CE: -10CE: 5C 00 40 MOV:I.W #H'0040, R4 -10D1: 5D 00 04 MOV:I.W #H'0004, R5 -10D4: 1E 2D F5 BSR loc_3ECC -10D7: 5C 02 00 MOV:I.W #H'0200, R4 -10DA: 5D 00 04 MOV:I.W #H'0004, R5 -10DD: 1E 2D EC BSR loc_3ECC -10E0: 5C 02 00 MOV:I.W #H'0200, R4 -10E3: 5D 00 04 MOV:I.W #H'0004, R5 -10E6: 1E 2D E3 BSR loc_3ECC -10E9: 5C 02 00 MOV:I.W #H'0200, R4 -10EC: 5D 00 04 MOV:I.W #H'0004, R5 -10EF: 1E 2D DA BSR loc_3ECC -10F2: 5C 02 07 MOV:I.W #H'0207, R4 -10F5: 5D 00 04 MOV:I.W #H'0004, R5 -10F8: 1E 2D D1 BSR loc_3ECC -10FB: 5C 02 04 MOV:I.W #H'0204, R4 -10FE: 5D 00 04 MOV:I.W #H'0004, R5 -1101: 1E 2D C8 BSR loc_3ECC -1104: 5C 02 04 MOV:I.W #H'0204, R4 -1107: 5D 00 04 MOV:I.W #H'0004, R5 -110A: 1E 2D BF BSR loc_3ECC -110D: 5C 02 04 MOV:I.W #H'0204, R4 -1110: 5D 00 04 MOV:I.W #H'0004, R5 -1113: 1E 2D B6 BSR loc_3ECC -1116: 5C 02 04 MOV:I.W #H'0204, R4 -1119: 5D 00 04 MOV:I.W #H'0004, R5 -111C: 1E 2D AD BSR loc_3ECC -111F: 5C 00 48 MOV:I.W #H'0048, R4 -1122: 5D 00 04 MOV:I.W #H'0004, R5 -1125: 1E 2D A4 BSR loc_3ECC -1128: 5C 02 00 MOV:I.W #H'0200, R4 -112B: 5D 00 04 MOV:I.W #H'0004, R5 -112E: 1E 2D 9B BSR loc_3ECC -1131: 5C 02 00 MOV:I.W #H'0200, R4 -1134: 5D 00 04 MOV:I.W #H'0004, R5 -1137: 1E 2D 92 BSR loc_3ECC -113A: 5C 02 00 MOV:I.W #H'0200, R4 -113D: 5D 00 04 MOV:I.W #H'0004, R5 -1140: 1E 2D 89 BSR loc_3ECC -1143: 5C 02 1B MOV:I.W #H'021B, R4 -1146: 5D 00 04 MOV:I.W #H'0004, R5 -1149: 1E 2D 80 BSR loc_3ECC -114C: 5C 02 00 MOV:I.W #H'0200, R4 -114F: 5D 00 04 MOV:I.W #H'0004, R5 -1152: 1E 2D 77 BSR loc_3ECC -1155: 5C 02 00 MOV:I.W #H'0200, R4 -1158: 5D 00 04 MOV:I.W #H'0004, R5 -115B: 1E 2D 6E BSR loc_3ECC -115E: 5C 02 00 MOV:I.W #H'0200, R4 -1161: 5D 00 04 MOV:I.W #H'0004, R5 -1164: 1E 2D 65 BSR loc_3ECC -1167: 5C 02 00 MOV:I.W #H'0200, R4 -116A: 5D 00 04 MOV:I.W #H'0004, R5 -116D: 1E 2D 5C BSR loc_3ECC -1170: 5C 00 50 MOV:I.W #H'0050, R4 -1173: 5D 00 04 MOV:I.W #H'0004, R5 -1176: 1E 2D 53 BSR loc_3ECC -1179: 5C 02 00 MOV:I.W #H'0200, R4 -117C: 5D 00 04 MOV:I.W #H'0004, R5 -117F: 1E 2D 4A BSR loc_3ECC -1182: 5C 02 00 MOV:I.W #H'0200, R4 -1185: 5D 00 04 MOV:I.W #H'0004, R5 -1188: 1E 2D 41 BSR loc_3ECC -118B: 5C 02 00 MOV:I.W #H'0200, R4 -118E: 5D 00 04 MOV:I.W #H'0004, R5 -1191: 1E 2D 38 BSR loc_3ECC -1194: 5C 02 1C MOV:I.W #H'021C, R4 -1197: 5D 00 04 MOV:I.W #H'0004, R5 -119A: 1E 2D 2F BSR loc_3ECC -119D: 5C 02 04 MOV:I.W #H'0204, R4 -11A0: 5D 00 04 MOV:I.W #H'0004, R5 -11A3: 1E 2D 26 BSR loc_3ECC -11A6: 5C 02 04 MOV:I.W #H'0204, R4 -11A9: 5D 00 04 MOV:I.W #H'0004, R5 -11AC: 1E 2D 1D BSR loc_3ECC -11AF: 5C 02 04 MOV:I.W #H'0204, R4 -11B2: 5D 00 04 MOV:I.W #H'0004, R5 -11B5: 1E 2D 14 BSR loc_3ECC -11B8: 5C 02 04 MOV:I.W #H'0204, R4 -11BB: 5D 00 04 MOV:I.W #H'0004, R5 -11BE: 1E 2D 0B BSR loc_3ECC -11C1: 5C 00 58 MOV:I.W #H'0058, R4 -11C4: 5D 00 04 MOV:I.W #H'0004, R5 -11C7: 1E 2D 02 BSR loc_3ECC -11CA: 5C 02 04 MOV:I.W #H'0204, R4 -11CD: 5D 00 04 MOV:I.W #H'0004, R5 -11D0: 1E 2C F9 BSR loc_3ECC -11D3: 5C 02 04 MOV:I.W #H'0204, R4 -11D6: 5D 00 04 MOV:I.W #H'0004, R5 -11D9: 1E 2C F0 BSR loc_3ECC -11DC: 5C 02 04 MOV:I.W #H'0204, R4 -11DF: 5D 00 04 MOV:I.W #H'0004, R5 -11E2: 1E 2C E7 BSR loc_3ECC -11E5: 5C 02 07 MOV:I.W #H'0207, R4 -11E8: 5D 00 04 MOV:I.W #H'0004, R5 -11EB: 1E 2C DE BSR loc_3ECC -11EE: 5C 02 00 MOV:I.W #H'0200, R4 -11F1: 5D 00 04 MOV:I.W #H'0004, R5 -11F4: 1E 2C D5 BSR loc_3ECC -11F7: 5C 02 00 MOV:I.W #H'0200, R4 -11FA: 5D 00 04 MOV:I.W #H'0004, R5 -11FD: 1E 2C CC BSR loc_3ECC -1200: 5C 02 00 MOV:I.W #H'0200, R4 -1203: 5D 00 04 MOV:I.W #H'0004, R5 -1206: 1E 2C C3 BSR loc_3ECC -1209: 5C 02 00 MOV:I.W #H'0200, R4 -120C: 5D 00 04 MOV:I.W #H'0004, R5 -120F: 1E 2C BA BSR loc_3ECC -1212: 5C 00 60 MOV:I.W #H'0060, R4 -1215: 5D 00 04 MOV:I.W #H'0004, R5 -1218: 1E 2C B1 BSR loc_3ECC -121B: 5C 02 00 MOV:I.W #H'0200, R4 -121E: 5D 00 04 MOV:I.W #H'0004, R5 -1221: 1E 2C A8 BSR loc_3ECC -1224: 5C 02 00 MOV:I.W #H'0200, R4 -1227: 5D 00 04 MOV:I.W #H'0004, R5 -122A: 1E 2C 9F BSR loc_3ECC -122D: 5C 02 00 MOV:I.W #H'0200, R4 -1230: 5D 00 04 MOV:I.W #H'0004, R5 -1233: 1E 2C 96 BSR loc_3ECC -1236: 5C 02 1B MOV:I.W #H'021B, R4 -1239: 5D 00 04 MOV:I.W #H'0004, R5 -123C: 1E 2C 8D BSR loc_3ECC -123F: 5C 02 00 MOV:I.W #H'0200, R4 -1242: 5D 00 04 MOV:I.W #H'0004, R5 -1245: 1E 2C 84 BSR loc_3ECC -1248: 5C 02 00 MOV:I.W #H'0200, R4 -124B: 5D 00 04 MOV:I.W #H'0004, R5 -124E: 1E 2C 7B BSR loc_3ECC -1251: 5C 02 00 MOV:I.W #H'0200, R4 -1254: 5D 00 04 MOV:I.W #H'0004, R5 -1257: 1E 2C 72 BSR loc_3ECC -125A: 5C 02 00 MOV:I.W #H'0200, R4 -125D: 5D 00 04 MOV:I.W #H'0004, R5 -1260: 1E 2C 69 BSR loc_3ECC -1263: 5C 00 68 MOV:I.W #H'0068, R4 -1266: 5D 00 04 MOV:I.W #H'0004, R5 -1269: 1E 2C 60 BSR loc_3ECC -126C: 5C 02 04 MOV:I.W #H'0204, R4 -126F: 5D 00 04 MOV:I.W #H'0004, R5 -1272: 1E 2C 57 BSR loc_3ECC -1275: 5C 02 04 MOV:I.W #H'0204, R4 -1278: 5D 00 04 MOV:I.W #H'0004, R5 -127B: 1E 2C 4E BSR loc_3ECC -127E: 5C 02 04 MOV:I.W #H'0204, R4 -1281: 5D 00 04 MOV:I.W #H'0004, R5 -1284: 1E 2C 45 BSR loc_3ECC -1287: 5C 02 1C MOV:I.W #H'021C, R4 -128A: 5D 00 04 MOV:I.W #H'0004, R5 -128D: 1E 2C 3C BSR loc_3ECC -1290: 5C 02 00 MOV:I.W #H'0200, R4 -1293: 5D 00 04 MOV:I.W #H'0004, R5 -1296: 1E 2C 33 BSR loc_3ECC -1299: 5C 02 00 MOV:I.W #H'0200, R4 -129C: 5D 00 04 MOV:I.W #H'0004, R5 -129F: 1E 2C 2A BSR loc_3ECC -12A2: 5C 02 00 MOV:I.W #H'0200, R4 -12A5: 5D 00 04 MOV:I.W #H'0004, R5 -12A8: 1E 2C 21 BSR loc_3ECC -12AB: 5C 02 00 MOV:I.W #H'0200, R4 -12AE: 5D 00 04 MOV:I.W #H'0004, R5 -12B1: 1E 2C 18 BSR loc_3ECC -12B4: 5C 00 70 MOV:I.W #H'0070, R4 -12B7: 5D 00 04 MOV:I.W #H'0004, R5 -12BA: 1E 2C 0F BSR loc_3ECC -12BD: 5C 02 04 MOV:I.W #H'0204, R4 -12C0: 5D 00 04 MOV:I.W #H'0004, R5 -12C3: 1E 2C 06 BSR loc_3ECC -12C6: 5C 02 04 MOV:I.W #H'0204, R4 -12C9: 5D 00 04 MOV:I.W #H'0004, R5 -12CC: 1E 2B FD BSR loc_3ECC -12CF: 5C 02 00 MOV:I.W #H'0200, R4 -12D2: 5D 00 04 MOV:I.W #H'0004, R5 -12D5: 1E 2B F4 BSR loc_3ECC -12D8: 5C 02 04 MOV:I.W #H'0204, R4 -12DB: 5D 00 04 MOV:I.W #H'0004, R5 -12DE: 1E 2B EB BSR loc_3ECC -12E1: 5C 02 04 MOV:I.W #H'0204, R4 -12E4: 5D 00 04 MOV:I.W #H'0004, R5 -12E7: 1E 2B E2 BSR loc_3ECC -12EA: 5C 02 00 MOV:I.W #H'0200, R4 -12ED: 5D 00 04 MOV:I.W #H'0004, R5 -12F0: 1E 2B D9 BSR loc_3ECC -12F3: 5C 02 04 MOV:I.W #H'0204, R4 -12F6: 5D 00 04 MOV:I.W #H'0004, R5 -12F9: 1E 2B D0 BSR loc_3ECC -12FC: 5C 02 04 MOV:I.W #H'0204, R4 -12FF: 5D 00 04 MOV:I.W #H'0004, R5 -1302: 1E 2B C7 BSR loc_3ECC -1305: 5C 00 78 MOV:I.W #H'0078, R4 -1308: 5D 00 04 MOV:I.W #H'0004, R5 -130B: 1E 2B BE BSR loc_3ECC -130E: 5C 02 04 MOV:I.W #H'0204, R4 -1311: 5D 00 04 MOV:I.W #H'0004, R5 -1314: 1E 2B B5 BSR loc_3ECC -1317: 5C 02 04 MOV:I.W #H'0204, R4 -131A: 5D 00 04 MOV:I.W #H'0004, R5 -131D: 1E 2B AC BSR loc_3ECC -1320: 5C 02 00 MOV:I.W #H'0200, R4 -1323: 5D 00 04 MOV:I.W #H'0004, R5 -1326: 1E 2B A3 BSR loc_3ECC -1329: 5C 02 04 MOV:I.W #H'0204, R4 -132C: 5D 00 04 MOV:I.W #H'0004, R5 -132F: 1E 2B 9A BSR loc_3ECC -1332: 5C 02 04 MOV:I.W #H'0204, R4 -1335: 5D 00 04 MOV:I.W #H'0004, R5 -1338: 1E 2B 91 BSR loc_3ECC -133B: 5C 02 00 MOV:I.W #H'0200, R4 -133E: 5D 00 04 MOV:I.W #H'0004, R5 -1341: 1E 2B 88 BSR loc_3ECC -1344: 5C 02 04 MOV:I.W #H'0204, R4 -1347: 5D 00 04 MOV:I.W #H'0004, R5 -134A: 1E 2B 7F BSR loc_3ECC -134D: 5C 02 04 MOV:I.W #H'0204, R4 -1350: 5D 00 04 MOV:I.W #H'0004, R5 -1353: 1E 2B 76 BSR loc_3ECC -1356: 19 RTS +10CE: 5C 00 40 MOV:I.W #H'0040, R4 ; cycles=3 +10D1: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +10D4: 1E 2D F5 BSR loc_3ECC ; cycles=13 +10D7: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +10DA: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +10DD: 1E 2D EC BSR loc_3ECC ; cycles=14 +10E0: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +10E3: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +10E6: 1E 2D E3 BSR loc_3ECC ; cycles=13 +10E9: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +10EC: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +10EF: 1E 2D DA BSR loc_3ECC ; cycles=14 +10F2: 5C 02 07 MOV:I.W #H'0207, R4 ; cycles=3 +10F5: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +10F8: 1E 2D D1 BSR loc_3ECC ; cycles=13 +10FB: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +10FE: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1101: 1E 2D C8 BSR loc_3ECC ; cycles=14 +1104: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1107: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +110A: 1E 2D BF BSR loc_3ECC ; cycles=13 +110D: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1110: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1113: 1E 2D B6 BSR loc_3ECC ; cycles=14 +1116: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1119: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +111C: 1E 2D AD BSR loc_3ECC ; cycles=13 +111F: 5C 00 48 MOV:I.W #H'0048, R4 ; cycles=3 +1122: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1125: 1E 2D A4 BSR loc_3ECC ; cycles=14 +1128: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +112B: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +112E: 1E 2D 9B BSR loc_3ECC ; cycles=13 +1131: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1134: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1137: 1E 2D 92 BSR loc_3ECC ; cycles=14 +113A: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +113D: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1140: 1E 2D 89 BSR loc_3ECC ; cycles=13 +1143: 5C 02 1B MOV:I.W #H'021B, R4 ; cycles=3 +1146: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1149: 1E 2D 80 BSR loc_3ECC ; cycles=14 +114C: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +114F: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1152: 1E 2D 77 BSR loc_3ECC ; cycles=13 +1155: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1158: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +115B: 1E 2D 6E BSR loc_3ECC ; cycles=14 +115E: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1161: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1164: 1E 2D 65 BSR loc_3ECC ; cycles=13 +1167: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +116A: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +116D: 1E 2D 5C BSR loc_3ECC ; cycles=14 +1170: 5C 00 50 MOV:I.W #H'0050, R4 ; cycles=3 +1173: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1176: 1E 2D 53 BSR loc_3ECC ; cycles=13 +1179: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +117C: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +117F: 1E 2D 4A BSR loc_3ECC ; cycles=14 +1182: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1185: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1188: 1E 2D 41 BSR loc_3ECC ; cycles=13 +118B: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +118E: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1191: 1E 2D 38 BSR loc_3ECC ; cycles=14 +1194: 5C 02 1C MOV:I.W #H'021C, R4 ; cycles=3 +1197: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +119A: 1E 2D 2F BSR loc_3ECC ; cycles=13 +119D: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11A0: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11A3: 1E 2D 26 BSR loc_3ECC ; cycles=14 +11A6: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11A9: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11AC: 1E 2D 1D BSR loc_3ECC ; cycles=13 +11AF: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11B2: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11B5: 1E 2D 14 BSR loc_3ECC ; cycles=14 +11B8: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11BB: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11BE: 1E 2D 0B BSR loc_3ECC ; cycles=13 +11C1: 5C 00 58 MOV:I.W #H'0058, R4 ; cycles=3 +11C4: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11C7: 1E 2D 02 BSR loc_3ECC ; cycles=14 +11CA: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11CD: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11D0: 1E 2C F9 BSR loc_3ECC ; cycles=13 +11D3: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11D6: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11D9: 1E 2C F0 BSR loc_3ECC ; cycles=14 +11DC: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +11DF: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11E2: 1E 2C E7 BSR loc_3ECC ; cycles=13 +11E5: 5C 02 07 MOV:I.W #H'0207, R4 ; cycles=3 +11E8: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11EB: 1E 2C DE BSR loc_3ECC ; cycles=14 +11EE: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +11F1: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11F4: 1E 2C D5 BSR loc_3ECC ; cycles=13 +11F7: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +11FA: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +11FD: 1E 2C CC BSR loc_3ECC ; cycles=14 +1200: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1203: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1206: 1E 2C C3 BSR loc_3ECC ; cycles=13 +1209: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +120C: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +120F: 1E 2C BA BSR loc_3ECC ; cycles=14 +1212: 5C 00 60 MOV:I.W #H'0060, R4 ; cycles=3 +1215: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1218: 1E 2C B1 BSR loc_3ECC ; cycles=13 +121B: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +121E: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1221: 1E 2C A8 BSR loc_3ECC ; cycles=14 +1224: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1227: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +122A: 1E 2C 9F BSR loc_3ECC ; cycles=13 +122D: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1230: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1233: 1E 2C 96 BSR loc_3ECC ; cycles=14 +1236: 5C 02 1B MOV:I.W #H'021B, R4 ; cycles=3 +1239: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +123C: 1E 2C 8D BSR loc_3ECC ; cycles=13 +123F: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1242: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1245: 1E 2C 84 BSR loc_3ECC ; cycles=14 +1248: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +124B: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +124E: 1E 2C 7B BSR loc_3ECC ; cycles=13 +1251: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1254: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1257: 1E 2C 72 BSR loc_3ECC ; cycles=14 +125A: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +125D: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1260: 1E 2C 69 BSR loc_3ECC ; cycles=13 +1263: 5C 00 68 MOV:I.W #H'0068, R4 ; cycles=3 +1266: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1269: 1E 2C 60 BSR loc_3ECC ; cycles=14 +126C: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +126F: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1272: 1E 2C 57 BSR loc_3ECC ; cycles=13 +1275: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1278: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +127B: 1E 2C 4E BSR loc_3ECC ; cycles=14 +127E: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1281: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1284: 1E 2C 45 BSR loc_3ECC ; cycles=13 +1287: 5C 02 1C MOV:I.W #H'021C, R4 ; cycles=3 +128A: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +128D: 1E 2C 3C BSR loc_3ECC ; cycles=14 +1290: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1293: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1296: 1E 2C 33 BSR loc_3ECC ; cycles=13 +1299: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +129C: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +129F: 1E 2C 2A BSR loc_3ECC ; cycles=14 +12A2: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +12A5: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12A8: 1E 2C 21 BSR loc_3ECC ; cycles=13 +12AB: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +12AE: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12B1: 1E 2C 18 BSR loc_3ECC ; cycles=14 +12B4: 5C 00 70 MOV:I.W #H'0070, R4 ; cycles=3 +12B7: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12BA: 1E 2C 0F BSR loc_3ECC ; cycles=13 +12BD: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +12C0: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12C3: 1E 2C 06 BSR loc_3ECC ; cycles=14 +12C6: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +12C9: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12CC: 1E 2B FD BSR loc_3ECC ; cycles=13 +12CF: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +12D2: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12D5: 1E 2B F4 BSR loc_3ECC ; cycles=14 +12D8: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +12DB: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12DE: 1E 2B EB BSR loc_3ECC ; cycles=13 +12E1: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +12E4: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12E7: 1E 2B E2 BSR loc_3ECC ; cycles=14 +12EA: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +12ED: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12F0: 1E 2B D9 BSR loc_3ECC ; cycles=13 +12F3: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +12F6: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +12F9: 1E 2B D0 BSR loc_3ECC ; cycles=14 +12FC: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +12FF: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1302: 1E 2B C7 BSR loc_3ECC ; cycles=13 +1305: 5C 00 78 MOV:I.W #H'0078, R4 ; cycles=3 +1308: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +130B: 1E 2B BE BSR loc_3ECC ; cycles=14 +130E: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1311: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1314: 1E 2B B5 BSR loc_3ECC ; cycles=13 +1317: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +131A: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +131D: 1E 2B AC BSR loc_3ECC ; cycles=14 +1320: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +1323: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1326: 1E 2B A3 BSR loc_3ECC ; cycles=13 +1329: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +132C: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +132F: 1E 2B 9A BSR loc_3ECC ; cycles=14 +1332: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1335: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1338: 1E 2B 91 BSR loc_3ECC ; cycles=13 +133B: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +133E: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1341: 1E 2B 88 BSR loc_3ECC ; cycles=14 +1344: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1347: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +134A: 1E 2B 7F BSR loc_3ECC ; cycles=13 +134D: 5C 02 04 MOV:I.W #H'0204, R4 ; cycles=3 +1350: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +1353: 1E 2B 76 BSR loc_3ECC ; cycles=14 +1356: 19 RTS ; cycles=12 loc_15E0: -15E0: 1E 10 6D BSR loc_2650 -15E3: 15 F6 89 D7 BCLR.B #7, @H'F689 ; refs H'F689 in on_chip_ram -15E7: 27 10 BEQ loc_15F9 -15E9: 1D F6 8E 81 MOV:G.W @H'F68E, R1 ; refs H'F68E in on_chip_ram -15ED: 1D E9 02 91 MOV:G.W R1, @H'E902 ; refs H'E902 in program_or_external -15F1: 52 80 MOV:E.B #H'80, R2 -15F3: 5B 00 81 MOV:I.W #H'0081, R3 -15F6: 1E 28 5B BSR loc_3E54 +15E0: 1E 10 6D BSR loc_2650 ; cycles=13 +15E3: 15 F6 89 D7 BCLR.B #7, @H'F689 ; refs H'F689 in on_chip_ram; cycles=8 +15E7: 27 10 BEQ loc_15F9 ; cycles=3/8 nt/t +15E9: 1D F6 8E 81 MOV:G.W @H'F68E, R1 ; refs H'F68E in on_chip_ram; cycles=6 +15ED: 1D E9 02 91 MOV:G.W R1, @H'E902 ; refs H'E902 in program_or_external; cycles=6 +15F1: 52 80 MOV:E.B #H'80, R2 ; cycles=2 +15F3: 5B 00 81 MOV:I.W #H'0081, R3 ; cycles=3 +15F6: 1E 28 5B BSR loc_3E54 ; cycles=13 loc_15F9: -15F9: 15 F6 F0 16 TST.B @H'F6F0 ; refs H'F6F0 in on_chip_ram -15FD: 27 3E BEQ loc_163D -15FF: 15 F6 F0 D7 BCLR.B #7, @H'F6F0 ; refs H'F6F0 in on_chip_ram -1603: 27 03 BEQ loc_1608 -1605: 18 43 94 JSR @loc_4394 +15F9: 15 F6 F0 16 TST.B @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=6 +15FD: 27 3E BEQ loc_163D ; cycles=3/8 nt/t +15FF: 15 F6 F0 D7 BCLR.B #7, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +1603: 27 03 BEQ loc_1608 ; cycles=3/8 nt/t +1605: 18 43 94 JSR @loc_4394 ; cycles=14 loc_1608: -1608: 15 F6 F0 D6 BCLR.B #6, @H'F6F0 ; refs H'F6F0 in on_chip_ram -160C: 27 03 BEQ loc_1611 -160E: 18 44 57 JSR @loc_4457 +1608: 15 F6 F0 D6 BCLR.B #6, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=9 +160C: 27 03 BEQ loc_1611 ; cycles=3/7 nt/t +160E: 18 44 57 JSR @loc_4457 ; cycles=13 loc_1611: -1611: 15 F6 F0 D5 BCLR.B #5, @H'F6F0 ; refs H'F6F0 in on_chip_ram -1615: 27 03 BEQ loc_161A -1617: 18 45 1A JSR @loc_451A +1611: 15 F6 F0 D5 BCLR.B #5, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +1615: 27 03 BEQ loc_161A ; cycles=3/8 nt/t +1617: 18 45 1A JSR @loc_451A ; cycles=14 loc_161A: -161A: 15 F6 F0 D4 BCLR.B #4, @H'F6F0 ; refs H'F6F0 in on_chip_ram -161E: 15 F6 F0 D3 BCLR.B #3, @H'F6F0 ; refs H'F6F0 in on_chip_ram -1622: 27 03 BEQ loc_1627 -1624: 18 17 05 JSR @loc_1705 +161A: 15 F6 F0 D4 BCLR.B #4, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=9 +161E: 15 F6 F0 D3 BCLR.B #3, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=9 +1622: 27 03 BEQ loc_1627 ; cycles=3/7 nt/t +1624: 18 17 05 JSR @loc_1705 ; cycles=13 loc_1627: -1627: 15 F6 F0 D2 BCLR.B #2, @H'F6F0 ; refs H'F6F0 in on_chip_ram -162B: 27 03 BEQ loc_1630 -162D: 18 17 4D JSR @loc_174D +1627: 15 F6 F0 D2 BCLR.B #2, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +162B: 27 03 BEQ loc_1630 ; cycles=3/8 nt/t +162D: 18 17 4D JSR @loc_174D ; cycles=14 loc_1630: -1630: 15 F6 F0 D1 BCLR.B #1, @H'F6F0 ; refs H'F6F0 in on_chip_ram -1634: 27 03 BEQ loc_1639 -1636: 18 17 95 JSR @loc_1795 +1630: 15 F6 F0 D1 BCLR.B #1, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=9 +1634: 27 03 BEQ loc_1639 ; cycles=3/7 nt/t +1636: 18 17 95 JSR @loc_1795 ; cycles=13 loc_1639: -1639: 15 F6 F0 D0 BCLR.B #0, @H'F6F0 ; refs H'F6F0 in on_chip_ram +1639: 15 F6 F0 D0 BCLR.B #0, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 loc_163D: -163D: 15 F6 F1 16 TST.B @H'F6F1 ; refs H'F6F1 in on_chip_ram -1641: 27 43 BEQ loc_1686 -1643: 15 F6 F1 D7 BCLR.B #7, @H'F6F1 ; refs H'F6F1 in on_chip_ram -1647: 27 03 BEQ loc_164C -1649: 18 17 C9 JSR @loc_17C9 +163D: 15 F6 F1 16 TST.B @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=6 +1641: 27 43 BEQ loc_1686 ; cycles=3/8 nt/t +1643: 15 F6 F1 D7 BCLR.B #7, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=8 +1647: 27 03 BEQ loc_164C ; cycles=3/8 nt/t +1649: 18 17 C9 JSR @loc_17C9 ; cycles=14 loc_164C: -164C: 15 F6 F1 D6 BCLR.B #6, @H'F6F1 ; refs H'F6F1 in on_chip_ram -1650: 27 03 BEQ loc_1655 -1652: 18 17 FB JSR @loc_17FB +164C: 15 F6 F1 D6 BCLR.B #6, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +1650: 27 03 BEQ loc_1655 ; cycles=3/7 nt/t +1652: 18 17 FB JSR @loc_17FB ; cycles=13 loc_1655: -1655: 15 F6 F1 D5 BCLR.B #5, @H'F6F1 ; refs H'F6F1 in on_chip_ram -1659: 27 03 BEQ loc_165E -165B: 18 18 2D JSR @loc_182D +1655: 15 F6 F1 D5 BCLR.B #5, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=8 +1659: 27 03 BEQ loc_165E ; cycles=3/8 nt/t +165B: 18 18 2D JSR @loc_182D ; cycles=14 loc_165E: -165E: 15 F6 F1 D4 BCLR.B #4, @H'F6F1 ; refs H'F6F1 in on_chip_ram -1662: 27 03 BEQ loc_1667 -1664: 18 18 91 JSR @loc_1891 +165E: 15 F6 F1 D4 BCLR.B #4, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +1662: 27 03 BEQ loc_1667 ; cycles=3/7 nt/t +1664: 18 18 91 JSR @loc_1891 ; cycles=13 loc_1667: -1667: 15 F6 F1 D3 BCLR.B #3, @H'F6F1 ; refs H'F6F1 in on_chip_ram -166B: 27 03 BEQ loc_1670 -166D: 18 18 E7 JSR @loc_18E7 +1667: 15 F6 F1 D3 BCLR.B #3, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=8 +166B: 27 03 BEQ loc_1670 ; cycles=3/8 nt/t +166D: 18 18 E7 JSR @loc_18E7 ; cycles=14 loc_1670: -1670: 15 F6 F1 D2 BCLR.B #2, @H'F6F1 ; refs H'F6F1 in on_chip_ram -1674: 27 03 BEQ loc_1679 -1676: 18 19 4A JSR @loc_194A +1670: 15 F6 F1 D2 BCLR.B #2, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +1674: 27 03 BEQ loc_1679 ; cycles=3/7 nt/t +1676: 18 19 4A JSR @loc_194A ; cycles=13 loc_1679: -1679: 15 F6 F1 D1 BCLR.B #1, @H'F6F1 ; refs H'F6F1 in on_chip_ram -167D: 27 03 BEQ loc_1682 -167F: 18 19 79 JSR @loc_1979 +1679: 15 F6 F1 D1 BCLR.B #1, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=8 +167D: 27 03 BEQ loc_1682 ; cycles=3/8 nt/t +167F: 18 19 79 JSR @loc_1979 ; cycles=14 loc_1682: -1682: 15 F6 F1 D0 BCLR.B #0, @H'F6F1 ; refs H'F6F1 in on_chip_ram +1682: 15 F6 F1 D0 BCLR.B #0, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 loc_1686: -1686: 15 F6 F2 16 TST.B @H'F6F2 ; refs H'F6F2 in on_chip_ram -168A: 27 48 BEQ loc_16D4 -168C: 15 F6 F2 D7 BCLR.B #7, @H'F6F2 ; refs H'F6F2 in on_chip_ram -1690: 27 03 BEQ loc_1695 -1692: 18 1B 2D JSR @loc_1B2D +1686: 15 F6 F2 16 TST.B @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=7 +168A: 27 48 BEQ loc_16D4 ; cycles=3/7 nt/t +168C: 15 F6 F2 D7 BCLR.B #7, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=9 +1690: 27 03 BEQ loc_1695 ; cycles=3/7 nt/t +1692: 18 1B 2D JSR @loc_1B2D ; cycles=13 loc_1695: -1695: 15 F6 F2 D6 BCLR.B #6, @H'F6F2 ; refs H'F6F2 in on_chip_ram -1699: 27 03 BEQ loc_169E -169B: 18 1B 44 JSR @loc_1B44 +1695: 15 F6 F2 D6 BCLR.B #6, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +1699: 27 03 BEQ loc_169E ; cycles=3/8 nt/t +169B: 18 1B 44 JSR @loc_1B44 ; cycles=14 loc_169E: -169E: 15 F6 F2 D5 BCLR.B #5, @H'F6F2 ; refs H'F6F2 in on_chip_ram -16A2: 27 03 BEQ loc_16A7 -16A4: 18 1B 5B JSR @loc_1B5B +169E: 15 F6 F2 D5 BCLR.B #5, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=9 +16A2: 27 03 BEQ loc_16A7 ; cycles=3/7 nt/t +16A4: 18 1B 5B JSR @loc_1B5B ; cycles=13 loc_16A7: -16A7: 15 F6 F2 D4 BCLR.B #4, @H'F6F2 ; refs H'F6F2 in on_chip_ram -16AB: 27 03 BEQ loc_16B0 -16AD: 18 1B A0 JSR @loc_1BA0 +16A7: 15 F6 F2 D4 BCLR.B #4, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +16AB: 27 03 BEQ loc_16B0 ; cycles=3/8 nt/t +16AD: 18 1B A0 JSR @loc_1BA0 ; cycles=14 loc_16B0: -16B0: 15 F6 F2 D3 BCLR.B #3, @H'F6F2 ; refs H'F6F2 in on_chip_ram -16B4: 27 03 BEQ loc_16B9 -16B6: 18 1B B6 JSR @loc_1BB6 +16B0: 15 F6 F2 D3 BCLR.B #3, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=9 +16B4: 27 03 BEQ loc_16B9 ; cycles=3/7 nt/t +16B6: 18 1B B6 JSR @loc_1BB6 ; cycles=13 loc_16B9: -16B9: 15 F6 F2 D2 BCLR.B #2, @H'F6F2 ; refs H'F6F2 in on_chip_ram -16BD: 27 03 BEQ loc_16C2 -16BF: 18 1B CC JSR @loc_1BCC +16B9: 15 F6 F2 D2 BCLR.B #2, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +16BD: 27 03 BEQ loc_16C2 ; cycles=3/8 nt/t +16BF: 18 1B CC JSR @loc_1BCC ; cycles=14 loc_16C2: -16C2: 15 F6 F2 D1 BCLR.B #1, @H'F6F2 ; refs H'F6F2 in on_chip_ram -16C6: 27 03 BEQ loc_16CB -16C8: 18 1B 72 JSR @loc_1B72 +16C2: 15 F6 F2 D1 BCLR.B #1, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=9 +16C6: 27 03 BEQ loc_16CB ; cycles=3/7 nt/t +16C8: 18 1B 72 JSR @loc_1B72 ; cycles=13 loc_16CB: -16CB: 15 F6 F2 D0 BCLR.B #0, @H'F6F2 ; refs H'F6F2 in on_chip_ram -16CF: 27 03 BEQ loc_16D4 -16D1: 18 1B 89 JSR @loc_1B89 +16CB: 15 F6 F2 D0 BCLR.B #0, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +16CF: 27 03 BEQ loc_16D4 ; cycles=3/8 nt/t +16D1: 18 1B 89 JSR @loc_1B89 ; cycles=14 loc_16D4: -16D4: 15 F6 F3 16 TST.B @H'F6F3 ; refs H'F6F3 in on_chip_ram -16D8: 27 2A BEQ loc_1704 -16DA: 15 F6 F3 D7 BCLR.B #7, @H'F6F3 ; refs H'F6F3 in on_chip_ram -16DE: 15 F6 F3 D6 BCLR.B #6, @H'F6F3 ; refs H'F6F3 in on_chip_ram -16E2: 15 F6 F3 D5 BCLR.B #5, @H'F6F3 ; refs H'F6F3 in on_chip_ram -16E6: 15 F6 F3 D4 BCLR.B #4, @H'F6F3 ; refs H'F6F3 in on_chip_ram -16EA: 27 03 BEQ loc_16EF -16EC: 18 1B E2 JSR @loc_1BE2 +16D4: 15 F6 F3 16 TST.B @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=7 +16D8: 27 2A BEQ loc_1704 ; cycles=3/7 nt/t +16DA: 15 F6 F3 D7 BCLR.B #7, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +16DE: 15 F6 F3 D6 BCLR.B #6, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +16E2: 15 F6 F3 D5 BCLR.B #5, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +16E6: 15 F6 F3 D4 BCLR.B #4, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +16EA: 27 03 BEQ loc_16EF ; cycles=3/7 nt/t +16EC: 18 1B E2 JSR @loc_1BE2 ; cycles=13 loc_16EF: -16EF: 15 F6 F3 D3 BCLR.B #3, @H'F6F3 ; refs H'F6F3 in on_chip_ram -16F3: 27 03 BEQ loc_16F8 -16F5: 18 1B F8 JSR @loc_1BF8 +16EF: 15 F6 F3 D3 BCLR.B #3, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=8 +16F3: 27 03 BEQ loc_16F8 ; cycles=3/8 nt/t +16F5: 18 1B F8 JSR @loc_1BF8 ; cycles=14 loc_16F8: -16F8: 15 F6 F3 D2 BCLR.B #2, @H'F6F3 ; refs H'F6F3 in on_chip_ram -16FC: 15 F6 F3 D1 BCLR.B #1, @H'F6F3 ; refs H'F6F3 in on_chip_ram -1700: 15 F6 F3 D0 BCLR.B #0, @H'F6F3 ; refs H'F6F3 in on_chip_ram +16F8: 15 F6 F3 D2 BCLR.B #2, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +16FC: 15 F6 F3 D1 BCLR.B #1, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +1700: 15 F6 F3 D0 BCLR.B #0, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 loc_1704: -1704: 19 RTS +1704: 19 RTS ; cycles=12 loc_1705: -1705: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -170A: 22 38 BHI loc_1744 -170C: 1D E1 4E FF BTST.W #15, @H'E14E ; refs H'E14E in program_or_external -1710: 26 24 BNE loc_1736 -1712: 15 F7 30 F6 BTST.B #6, @H'F730 ; refs H'F730 in on_chip_ram -1716: 26 1E BNE loc_1736 -1718: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -171C: 26 08 BNE loc_1726 -171E: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs H'F732 in on_chip_ram -1722: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs H'F734 in on_chip_ram +1705: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +170A: 22 38 BHI loc_1744 ; cycles=3/7 nt/t +170C: 1D E1 4E FF BTST.W #15, @H'E14E ; refs H'E14E in program_or_external; cycles=7 +1710: 26 24 BNE loc_1736 ; cycles=3/7 nt/t +1712: 15 F7 30 F6 BTST.B #6, @H'F730 ; refs H'F730 in on_chip_ram; cycles=7 +1716: 26 1E BNE loc_1736 ; cycles=3/7 nt/t +1718: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=9 +171C: 26 08 BNE loc_1726 ; cycles=3/7 nt/t +171E: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs H'F732 in on_chip_ram; cycles=7 +1722: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs H'F734 in on_chip_ram; cycles=7 loc_1726: -1726: 1D F7 32 07 1C 07 MOV:G.W #H'1C07, @H'F732 ; refs H'F732 in on_chip_ram -172C: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs H'FB02 in on_chip_ram -1731: 1E 31 C6 BSR loc_48FA -1734: 20 0E BRA loc_1744 +1726: 1D F7 32 07 1C 07 MOV:G.W #H'1C07, @H'F732 ; refs H'F732 in on_chip_ram; cycles=11 +172C: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=9 +1731: 1E 31 C6 BSR loc_48FA ; cycles=14 +1734: 20 0E BRA loc_1744 ; cycles=7 loc_1736: -1736: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs H'F696 in on_chip_ram -173A: 1D F6 B6 34 SUB.W @H'F6B6, R4 ; refs H'F6B6 in on_chip_ram -173E: 5B 00 A9 MOV:I.W #H'00A9, R3 -1741: 1E 02 5E BSR loc_19A2 +1736: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs H'F696 in on_chip_ram; cycles=7 +173A: 1D F6 B6 34 SUB.W @H'F6B6, R4 ; refs H'F6B6 in on_chip_ram; cycles=7 +173E: 5B 00 A9 MOV:I.W #H'00A9, R3 ; cycles=3 +1741: 1E 02 5E BSR loc_19A2 ; cycles=14 loc_1744: -1744: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs H'F696 in on_chip_ram -1748: 1D F6 B6 94 MOV:G.W R4, @H'F6B6 ; refs H'F6B6 in on_chip_ram -174C: 19 RTS +1744: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs H'F696 in on_chip_ram; cycles=7 +1748: 1D F6 B6 94 MOV:G.W R4, @H'F6B6 ; refs H'F6B6 in on_chip_ram; cycles=7 +174C: 19 RTS ; cycles=12 loc_174D: -174D: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -1752: 22 38 BHI loc_178C -1754: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs H'F730 in on_chip_ram -1758: 27 32 BEQ loc_178C -175A: 1D E1 6E FD BTST.W #13, @H'E16E ; refs H'E16E in program_or_external -175E: 26 1E BNE loc_177E -1760: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -1764: 26 08 BNE loc_176E -1766: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs H'F732 in on_chip_ram -176A: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs H'F734 in on_chip_ram +174D: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +1752: 22 38 BHI loc_178C ; cycles=3/7 nt/t +1754: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs H'F730 in on_chip_ram; cycles=7 +1758: 27 32 BEQ loc_178C ; cycles=3/7 nt/t +175A: 1D E1 6E FD BTST.W #13, @H'E16E ; refs H'E16E in program_or_external; cycles=7 +175E: 26 1E BNE loc_177E ; cycles=3/7 nt/t +1760: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=9 +1764: 26 08 BNE loc_176E ; cycles=3/7 nt/t +1766: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs H'F732 in on_chip_ram; cycles=7 +176A: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs H'F734 in on_chip_ram; cycles=7 loc_176E: -176E: 1D F7 32 07 1C 06 MOV:G.W #H'1C06, @H'F732 ; refs H'F732 in on_chip_ram -1774: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs H'FB02 in on_chip_ram -1779: 1E 31 7E BSR loc_48FA -177C: 20 0E BRA loc_178C +176E: 1D F7 32 07 1C 06 MOV:G.W #H'1C06, @H'F732 ; refs H'F732 in on_chip_ram; cycles=11 +1774: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=9 +1779: 1E 31 7E BSR loc_48FA ; cycles=14 +177C: 20 0E BRA loc_178C ; cycles=7 loc_177E: -177E: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs H'F694 in on_chip_ram -1782: 1D F6 B4 34 SUB.W @H'F6B4, R4 ; refs H'F6B4 in on_chip_ram -1786: 5B 00 C5 MOV:I.W #H'00C5, R3 -1789: 1E 02 16 BSR loc_19A2 +177E: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs H'F694 in on_chip_ram; cycles=7 +1782: 1D F6 B4 34 SUB.W @H'F6B4, R4 ; refs H'F6B4 in on_chip_ram; cycles=7 +1786: 5B 00 C5 MOV:I.W #H'00C5, R3 ; cycles=3 +1789: 1E 02 16 BSR loc_19A2 ; cycles=14 loc_178C: -178C: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs H'F694 in on_chip_ram -1790: 1D F6 B4 94 MOV:G.W R4, @H'F6B4 ; refs H'F6B4 in on_chip_ram -1794: 19 RTS +178C: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs H'F694 in on_chip_ram; cycles=7 +1790: 1D F6 B4 94 MOV:G.W R4, @H'F6B4 ; refs H'F6B4 in on_chip_ram; cycles=7 +1794: 19 RTS ; cycles=12 loc_1795: -1795: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -179A: 22 24 BHI loc_17C0 -179C: 1D E1 72 FD BTST.W #13, @H'E172 ; refs H'E172 in program_or_external -17A0: 26 05 BNE loc_17A7 -17A2: 1E 09 82 BSR loc_2127 -17A5: 20 19 BRA loc_17C0 +1795: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +179A: 22 24 BHI loc_17C0 ; cycles=3/7 nt/t +179C: 1D E1 72 FD BTST.W #13, @H'E172 ; refs H'E172 in program_or_external; cycles=7 +17A0: 26 05 BNE loc_17A7 ; cycles=3/7 nt/t +17A2: 1E 09 82 BSR loc_2127 ; cycles=13 +17A5: 20 19 BRA loc_17C0 ; cycles=8 loc_17A7: -17A7: 1D E2 20 FF BTST.W #15, @H'E220 ; refs H'E220 in program_or_external -17AB: 27 05 BEQ loc_17B2 -17AD: 1E 09 77 BSR loc_2127 -17B0: 20 0E BRA loc_17C0 +17A7: 1D E2 20 FF BTST.W #15, @H'E220 ; refs H'E220 in program_or_external; cycles=6 +17AB: 27 05 BEQ loc_17B2 ; cycles=3/8 nt/t +17AD: 1E 09 77 BSR loc_2127 ; cycles=14 +17B0: 20 0E BRA loc_17C0 ; cycles=7 loc_17B2: -17B2: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs H'F692 in on_chip_ram -17B6: 1D F6 B2 34 SUB.W @H'F6B2, R4 ; refs H'F6B2 in on_chip_ram -17BA: 5B 00 BC MOV:I.W #H'00BC, R3 -17BD: 1E 01 E2 BSR loc_19A2 +17B2: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs H'F692 in on_chip_ram; cycles=7 +17B6: 1D F6 B2 34 SUB.W @H'F6B2, R4 ; refs H'F6B2 in on_chip_ram; cycles=7 +17BA: 5B 00 BC MOV:I.W #H'00BC, R3 ; cycles=3 +17BD: 1E 01 E2 BSR loc_19A2 ; cycles=14 loc_17C0: -17C0: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs H'F692 in on_chip_ram -17C4: 1D F6 B2 94 MOV:G.W R4, @H'F6B2 ; refs H'F6B2 in on_chip_ram -17C8: 19 RTS +17C0: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs H'F692 in on_chip_ram; cycles=7 +17C4: 1D F6 B2 94 MOV:G.W R4, @H'F6B2 ; refs H'F6B2 in on_chip_ram; cycles=7 +17C8: 19 RTS ; cycles=12 loc_17C9: -17C9: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -17CE: 22 22 BHI loc_17F2 -17D0: 1D E1 26 FC BTST.W #12, @H'E126 ; refs H'E126 in program_or_external -17D4: 27 1C BEQ loc_17F2 -17D6: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs H'F6AE in on_chip_ram -17DA: 1D F6 CE 34 SUB.W @H'F6CE, R4 ; refs H'F6CE in on_chip_ram -17DE: 5B 00 A3 MOV:I.W #H'00A3, R3 -17E1: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -17E5: 27 08 BEQ loc_17EF -17E7: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs H'F404 in program_or_external -17EB: 27 02 BEQ loc_17EF -17ED: AB CE BSET.W #14, R3 +17C9: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +17CE: 22 22 BHI loc_17F2 ; cycles=3/7 nt/t +17D0: 1D E1 26 FC BTST.W #12, @H'E126 ; refs H'E126 in program_or_external; cycles=7 +17D4: 27 1C BEQ loc_17F2 ; cycles=3/7 nt/t +17D6: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs H'F6AE in on_chip_ram; cycles=7 +17DA: 1D F6 CE 34 SUB.W @H'F6CE, R4 ; refs H'F6CE in on_chip_ram; cycles=7 +17DE: 5B 00 A3 MOV:I.W #H'00A3, R3 ; cycles=3 +17E1: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +17E5: 27 08 BEQ loc_17EF ; cycles=3/8 nt/t +17E7: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +17EB: 27 02 BEQ loc_17EF ; cycles=3/8 nt/t +17ED: AB CE BSET.W #14, R3 ; cycles=3 loc_17EF: -17EF: 1E 01 B0 BSR loc_19A2 +17EF: 1E 01 B0 BSR loc_19A2 ; cycles=14 loc_17F2: -17F2: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs H'F6AE in on_chip_ram -17F6: 1D F6 CE 94 MOV:G.W R4, @H'F6CE ; refs H'F6CE in on_chip_ram -17FA: 19 RTS +17F2: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs H'F6AE in on_chip_ram; cycles=7 +17F6: 1D F6 CE 94 MOV:G.W R4, @H'F6CE ; refs H'F6CE in on_chip_ram; cycles=7 +17FA: 19 RTS ; cycles=12 loc_17FB: -17FB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -1800: 22 22 BHI loc_1824 -1802: 1D E1 26 FC BTST.W #12, @H'E126 ; refs H'E126 in program_or_external -1806: 27 1C BEQ loc_1824 -1808: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs H'F6AC in on_chip_ram -180C: 1D F6 CC 34 SUB.W @H'F6CC, R4 ; refs H'F6CC in on_chip_ram -1810: 5B 00 A4 MOV:I.W #H'00A4, R3 -1813: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -1817: 27 08 BEQ loc_1821 -1819: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs H'F404 in program_or_external -181D: 27 02 BEQ loc_1821 -181F: AB CE BSET.W #14, R3 +17FB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +1800: 22 22 BHI loc_1824 ; cycles=3/7 nt/t +1802: 1D E1 26 FC BTST.W #12, @H'E126 ; refs H'E126 in program_or_external; cycles=7 +1806: 27 1C BEQ loc_1824 ; cycles=3/7 nt/t +1808: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs H'F6AC in on_chip_ram; cycles=7 +180C: 1D F6 CC 34 SUB.W @H'F6CC, R4 ; refs H'F6CC in on_chip_ram; cycles=7 +1810: 5B 00 A4 MOV:I.W #H'00A4, R3 ; cycles=3 +1813: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +1817: 27 08 BEQ loc_1821 ; cycles=3/8 nt/t +1819: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +181D: 27 02 BEQ loc_1821 ; cycles=3/8 nt/t +181F: AB CE BSET.W #14, R3 ; cycles=3 loc_1821: -1821: 1E 01 7E BSR loc_19A2 +1821: 1E 01 7E BSR loc_19A2 ; cycles=14 loc_1824: -1824: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs H'F6AC in on_chip_ram -1828: 1D F6 CC 94 MOV:G.W R4, @H'F6CC ; refs H'F6CC in on_chip_ram -182C: 19 RTS +1824: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs H'F6AC in on_chip_ram; cycles=7 +1828: 1D F6 CC 94 MOV:G.W R4, @H'F6CC ; refs H'F6CC in on_chip_ram; cycles=7 +182C: 19 RTS ; cycles=12 loc_182D: -182D: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs H'F717 in on_chip_ram -1831: 26 32 BNE loc_1865 -1833: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -1838: 22 22 BHI loc_185C -183A: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs H'E126 in program_or_external -183E: 27 1C BEQ loc_185C -1840: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram -1844: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs H'F6CA in on_chip_ram -1848: 5B 00 A5 MOV:I.W #H'00A5, R3 -184B: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -184F: 27 08 BEQ loc_1859 -1851: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs H'F404 in program_or_external -1855: 27 02 BEQ loc_1859 -1857: AB CE BSET.W #14, R3 +182D: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs H'F717 in on_chip_ram; cycles=6 +1831: 26 32 BNE loc_1865 ; cycles=3/8 nt/t +1833: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +1838: 22 22 BHI loc_185C ; cycles=3/7 nt/t +183A: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs H'E126 in program_or_external; cycles=7 +183E: 27 1C BEQ loc_185C ; cycles=3/7 nt/t +1840: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram; cycles=7 +1844: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs H'F6CA in on_chip_ram; cycles=7 +1848: 5B 00 A5 MOV:I.W #H'00A5, R3 ; cycles=3 +184B: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +184F: 27 08 BEQ loc_1859 ; cycles=3/8 nt/t +1851: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +1855: 27 02 BEQ loc_1859 ; cycles=3/8 nt/t +1857: AB CE BSET.W #14, R3 ; cycles=3 loc_1859: -1859: 1E 01 46 BSR loc_19A2 +1859: 1E 01 46 BSR loc_19A2 ; cycles=14 loc_185C: -185C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram -1860: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs H'F6CA in on_chip_ram -1864: 19 RTS +185C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram; cycles=7 +1860: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs H'F6CA in on_chip_ram; cycles=7 +1864: 19 RTS ; cycles=12 loc_1865: -1865: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -186A: 22 1C BHI loc_1888 -186C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram -1870: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs H'F6CA in on_chip_ram -1874: 5B 00 D8 MOV:I.W #H'00D8, R3 -1877: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -187B: 27 08 BEQ loc_1885 -187D: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs H'F404 in program_or_external -1881: 27 02 BEQ loc_1885 -1883: AB CE BSET.W #14, R3 +1865: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +186A: 22 1C BHI loc_1888 ; cycles=3/7 nt/t +186C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram; cycles=7 +1870: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs H'F6CA in on_chip_ram; cycles=7 +1874: 5B 00 D8 MOV:I.W #H'00D8, R3 ; cycles=3 +1877: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +187B: 27 08 BEQ loc_1885 ; cycles=3/8 nt/t +187D: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +1881: 27 02 BEQ loc_1885 ; cycles=3/8 nt/t +1883: AB CE BSET.W #14, R3 ; cycles=3 loc_1885: -1885: 1E 01 1A BSR loc_19A2 +1885: 1E 01 1A BSR loc_19A2 ; cycles=14 loc_1888: -1888: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram -188C: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs H'F6CA in on_chip_ram -1890: 19 RTS +1888: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs H'F6AA in on_chip_ram; cycles=7 +188C: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs H'F6CA in on_chip_ram; cycles=7 +1890: 19 RTS ; cycles=12 loc_1891: -1891: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs H'F717 in on_chip_ram -1895: 26 24 BNE loc_18BB -1897: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -189C: 22 14 BHI loc_18B2 -189E: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs H'E126 in program_or_external -18A2: 27 0E BEQ loc_18B2 -18A4: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram -18A8: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs H'F6C8 in on_chip_ram -18AC: 5B 00 80 MOV:I.W #H'0080, R3 -18AF: 1E 00 F0 BSR loc_19A2 +1891: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs H'F717 in on_chip_ram; cycles=6 +1895: 26 24 BNE loc_18BB ; cycles=3/8 nt/t +1897: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +189C: 22 14 BHI loc_18B2 ; cycles=3/7 nt/t +189E: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs H'E126 in program_or_external; cycles=7 +18A2: 27 0E BEQ loc_18B2 ; cycles=3/7 nt/t +18A4: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram; cycles=7 +18A8: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs H'F6C8 in on_chip_ram; cycles=7 +18AC: 5B 00 80 MOV:I.W #H'0080, R3 ; cycles=3 +18AF: 1E 00 F0 BSR loc_19A2 ; cycles=14 loc_18B2: -18B2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram -18B6: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs H'F6C8 in on_chip_ram -18BA: 19 RTS +18B2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram; cycles=7 +18B6: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs H'F6C8 in on_chip_ram; cycles=7 +18BA: 19 RTS ; cycles=12 loc_18BB: -18BB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -18C0: 22 1C BHI loc_18DE -18C2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram -18C6: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs H'F6C8 in on_chip_ram -18CA: 5B 00 D9 MOV:I.W #H'00D9, R3 -18CD: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -18D1: 27 08 BEQ loc_18DB -18D3: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs H'F404 in program_or_external -18D7: 27 02 BEQ loc_18DB -18D9: AB CE BSET.W #14, R3 +18BB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +18C0: 22 1C BHI loc_18DE ; cycles=3/7 nt/t +18C2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram; cycles=7 +18C6: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs H'F6C8 in on_chip_ram; cycles=7 +18CA: 5B 00 D9 MOV:I.W #H'00D9, R3 ; cycles=3 +18CD: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +18D1: 27 08 BEQ loc_18DB ; cycles=3/8 nt/t +18D3: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +18D7: 27 02 BEQ loc_18DB ; cycles=3/8 nt/t +18D9: AB CE BSET.W #14, R3 ; cycles=3 loc_18DB: -18DB: 1E 00 C4 BSR loc_19A2 +18DB: 1E 00 C4 BSR loc_19A2 ; cycles=14 loc_18DE: -18DE: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram -18E2: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs H'F6C8 in on_chip_ram -18E6: 19 RTS +18DE: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs H'F6A8 in on_chip_ram; cycles=7 +18E2: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs H'F6C8 in on_chip_ram; cycles=7 +18E6: 19 RTS ; cycles=12 loc_18E7: -18E7: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs H'F717 in on_chip_ram -18EB: 26 32 BNE loc_191F -18ED: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -18F2: 22 22 BHI loc_1916 -18F4: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs H'E126 in program_or_external -18F8: 27 1C BEQ loc_1916 -18FA: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram -18FE: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs H'F6C6 in on_chip_ram -1902: 5B 00 A6 MOV:I.W #H'00A6, R3 -1905: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -1909: 27 08 BEQ loc_1913 -190B: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs H'F404 in program_or_external -190F: 27 02 BEQ loc_1913 -1911: AB CE BSET.W #14, R3 +18E7: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs H'F717 in on_chip_ram; cycles=6 +18EB: 26 32 BNE loc_191F ; cycles=3/8 nt/t +18ED: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +18F2: 22 22 BHI loc_1916 ; cycles=3/7 nt/t +18F4: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs H'E126 in program_or_external; cycles=7 +18F8: 27 1C BEQ loc_1916 ; cycles=3/7 nt/t +18FA: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram; cycles=7 +18FE: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs H'F6C6 in on_chip_ram; cycles=7 +1902: 5B 00 A6 MOV:I.W #H'00A6, R3 ; cycles=3 +1905: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +1909: 27 08 BEQ loc_1913 ; cycles=3/8 nt/t +190B: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +190F: 27 02 BEQ loc_1913 ; cycles=3/8 nt/t +1911: AB CE BSET.W #14, R3 ; cycles=3 loc_1913: -1913: 1E 00 8C BSR loc_19A2 +1913: 1E 00 8C BSR loc_19A2 ; cycles=14 loc_1916: -1916: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram -191A: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs H'F6C6 in on_chip_ram -191E: 19 RTS +1916: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram; cycles=7 +191A: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs H'F6C6 in on_chip_ram; cycles=7 +191E: 19 RTS ; cycles=12 loc_191F: -191F: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram -1924: 22 1B BHI loc_1941 -1926: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram -192A: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs H'F6C6 in on_chip_ram -192E: 5B 00 DA MOV:I.W #H'00DA, R3 -1931: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -1935: 27 08 BEQ loc_193F -1937: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs H'F404 in program_or_external -193B: 27 02 BEQ loc_193F -193D: AB CE BSET.W #14, R3 +191F: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +1924: 22 1B BHI loc_1941 ; cycles=3/7 nt/t +1926: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram; cycles=7 +192A: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs H'F6C6 in on_chip_ram; cycles=7 +192E: 5B 00 DA MOV:I.W #H'00DA, R3 ; cycles=3 +1931: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +1935: 27 08 BEQ loc_193F ; cycles=3/8 nt/t +1937: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs H'F404 in program_or_external; cycles=6 +193B: 27 02 BEQ loc_193F ; cycles=3/8 nt/t +193D: AB CE BSET.W #14, R3 ; cycles=3 loc_193F: -193F: 0E 61 BSR loc_19A2 +193F: 0E 61 BSR loc_19A2 ; cycles=14 loc_1941: -1941: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram -1945: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs H'F6C6 in on_chip_ram -1949: 19 RTS +1941: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs H'F6A6 in on_chip_ram; cycles=6 +1945: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs H'F6C6 in on_chip_ram; cycles=6 +1949: 19 RTS ; cycles=13 loc_194A: -194A: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs H'F731 in on_chip_ram -194F: 22 1F BHI loc_1970 -1951: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs H'F6A4 in on_chip_ram -1955: 1D F6 C4 34 SUB.W @H'F6C4, R4 ; refs H'F6C4 in on_chip_ram -1959: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field -195D: 26 00 BNE loc_195F +194A: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs H'F731 in on_chip_ram; cycles=7 +194F: 22 1F BHI loc_1970 ; cycles=3/8 nt/t +1951: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs H'F6A4 in on_chip_ram; cycles=6 +1955: 1D F6 C4 34 SUB.W @H'F6C4, R4 ; refs H'F6C4 in on_chip_ram; cycles=6 +1959: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +195D: 26 00 BNE loc_195F ; cycles=3/8 nt/t loc_195F: -195F: 5B 00 80 MOV:I.W #H'0080, R3 -1962: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs H'F791 in on_chip_ram -1966: 27 02 BEQ loc_196A -1968: AB CE BSET.W #14, R3 +195F: 5B 00 80 MOV:I.W #H'0080, R3 ; cycles=3 +1962: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs H'F791 in on_chip_ram; cycles=7 +1966: 27 02 BEQ loc_196A ; cycles=3/7 nt/t +1968: AB CE BSET.W #14, R3 ; cycles=3 loc_196A: -196A: 0E 36 BSR loc_19A2 -196C: 15 F7 6D C7 BSET.B #7, @H'F76D ; refs H'F76D in on_chip_ram +196A: 0E 36 BSR loc_19A2 ; cycles=13 +196C: 15 F7 6D C7 BSET.B #7, @H'F76D ; refs H'F76D in on_chip_ram; cycles=9 loc_1970: -1970: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs H'F6A4 in on_chip_ram -1974: 1D F6 C4 94 MOV:G.W R4, @H'F6C4 ; refs H'F6C4 in on_chip_ram -1978: 19 RTS +1970: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs H'F6A4 in on_chip_ram; cycles=7 +1974: 1D F6 C4 94 MOV:G.W R4, @H'F6C4 ; refs H'F6C4 in on_chip_ram; cycles=7 +1978: 19 RTS ; cycles=12 loc_1979: -1979: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs H'F731 in on_chip_ram -197E: 22 19 BHI loc_1999 -1980: 1D F6 A2 80 MOV:G.W @H'F6A2, R0 ; refs H'F6A2 in on_chip_ram -1984: 1D F6 C2 30 SUB.W @H'F6C2, R0 ; refs H'F6C2 in on_chip_ram -1988: 1D F6 8C A8 MULXU.W @H'F68C, R0 ; refs H'F68C in on_chip_ram -198C: 5B 00 81 MOV:I.W #H'0081, R3 -198F: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs H'F791 in on_chip_ram -1993: 27 02 BEQ loc_1997 -1995: AB CE BSET.W #14, R3 +1979: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +197E: 22 19 BHI loc_1999 ; cycles=3/7 nt/t +1980: 1D F6 A2 80 MOV:G.W @H'F6A2, R0 ; refs H'F6A2 in on_chip_ram; cycles=7 +1984: 1D F6 C2 30 SUB.W @H'F6C2, R0 ; refs H'F6C2 in on_chip_ram; cycles=7 +1988: 1D F6 8C A8 MULXU.W @H'F68C, R0 ; refs H'F68C in on_chip_ram; cycles=26 +198C: 5B 00 81 MOV:I.W #H'0081, R3 ; cycles=3 +198F: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs H'F791 in on_chip_ram; cycles=6 +1993: 27 02 BEQ loc_1997 ; cycles=3/8 nt/t +1995: AB CE BSET.W #14, R3 ; cycles=3 loc_1997: -1997: 0E 42 BSR loc_19DB +1997: 0E 42 BSR loc_19DB ; cycles=14 loc_1999: -1999: 1D F6 A2 84 MOV:G.W @H'F6A2, R4 ; refs H'F6A2 in on_chip_ram -199D: 1D F6 C2 94 MOV:G.W R4, @H'F6C2 ; refs H'F6C2 in on_chip_ram -19A1: 19 RTS +1999: 1D F6 A2 84 MOV:G.W @H'F6A2, R4 ; refs H'F6A2 in on_chip_ram; cycles=6 +199D: 1D F6 C2 94 MOV:G.W R4, @H'F6C2 ; refs H'F6C2 in on_chip_ram; cycles=6 +19A1: 19 RTS ; cycles=13 loc_19A2: -19A2: AB 85 MOV:G.W R3, R5 -19A4: 0C 01 FF 53 AND.W #H'01FF, R3 -19A8: AB 1A SHLL.W R3 -19AA: FB E4 00 80 MOV:G.W @(-H'1C00,R3), R0 -19AE: 48 FC 00 CMP:I #H'FC00, R0 -19B1: 22 03 BHI loc_19B6 -19B3: 58 FE 00 MOV:I.W #H'FE00, R0 +19A2: AB 85 MOV:G.W R3, R5 ; cycles=3 +19A4: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19A8: AB 1A SHLL.W R3 ; cycles=3 +19AA: FB E4 00 80 MOV:G.W @(-H'1C00,R3), R0 ; cycles=7 +19AE: 48 FC 00 CMP:I #H'FC00, R0 ; cycles=3 +19B1: 22 03 BHI loc_19B6 ; cycles=3/8 nt/t +19B3: 58 FE 00 MOV:I.W #H'FE00, R0 ; cycles=3 loc_19B6: -19B6: A8 15 NOT.W R0 -19B8: A8 08 ADD:Q.W #1, R0 -19BA: 4C 00 0F CMP:I #H'000F, R4 -19BD: 23 14 BLS loc_19D3 -19BF: 4C FF F0 CMP:I #H'FFF0, R4 -19C2: 24 0F BCC loc_19D3 -19C4: 4C 80 00 CMP:I #H'8000, R4 -19C7: 24 05 BCC loc_19CE -19C9: 5C 00 1A MOV:I.W #H'001A, R4 -19CC: 20 09 BRA loc_19D7 +19B6: A8 15 NOT.W R0 ; cycles=3 +19B8: A8 08 ADD:Q.W #1, R0 ; cycles=4 +19BA: 4C 00 0F CMP:I #H'000F, R4 ; cycles=3 +19BD: 23 14 BLS loc_19D3 ; cycles=3/8 nt/t +19BF: 4C FF F0 CMP:I #H'FFF0, R4 ; cycles=3 +19C2: 24 0F BCC loc_19D3 ; cycles=3/7 nt/t +19C4: 4C 80 00 CMP:I #H'8000, R4 ; cycles=3 +19C7: 24 05 BCC loc_19CE ; cycles=3/8 nt/t +19C9: 5C 00 1A MOV:I.W #H'001A, R4 ; cycles=3 +19CC: 20 09 BRA loc_19D7 ; cycles=7 loc_19CE: -19CE: 5C FF 1C MOV:I.W #H'FF1C, R4 -19D1: 20 04 BRA loc_19D7 +19CE: 5C FF 1C MOV:I.W #H'FF1C, R4 ; cycles=3 +19D1: 20 04 BRA loc_19D7 ; cycles=8 loc_19D3: -19D3: F4 1A 25 84 MOV:G.B @(H'1A25,R4), R4 +19D3: F4 1A 25 84 MOV:G.B @(H'1A25,R4), R4 ; cycles=6 loc_19D7: -19D7: AC A8 MULXU.W R4, R0 -19D9: 20 08 BRA loc_19E3 +19D7: AC A8 MULXU.W R4, R0 ; cycles=25 +19D9: 20 08 BRA loc_19E3 ; cycles=8 loc_19DB: -19DB: AB 85 MOV:G.W R3, R5 -19DD: 0C 01 FF 53 AND.W #H'01FF, R3 -19E1: AB 1A SHLL.W R3 +19DB: AB 85 MOV:G.W R3, R5 ; cycles=3 +19DD: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19E1: AB 1A SHLL.W R3 ; cycles=3 loc_19E3: -19E3: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 -19E7: A8 21 ADD:G.W R0, R1 -19E9: A9 82 MOV:G.W R1, R2 -19EB: 25 0C BCS loc_19F9 -19ED: A8 32 SUB.W R0, R2 -19EF: 4A 80 00 CMP:I #H'8000, R2 -19F2: 23 0F BLS loc_1A03 -19F4: 59 00 00 MOV:I.W #H'0000, R1 -19F7: 20 0A BRA loc_1A03 +19E3: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +19E7: A8 21 ADD:G.W R0, R1 ; cycles=3 +19E9: A9 82 MOV:G.W R1, R2 ; cycles=3 +19EB: 25 0C BCS loc_19F9 ; cycles=3/8 nt/t +19ED: A8 32 SUB.W R0, R2 ; cycles=3 +19EF: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +19F2: 23 0F BLS loc_1A03 ; cycles=3/7 nt/t +19F4: 59 00 00 MOV:I.W #H'0000, R1 ; cycles=3 +19F7: 20 0A BRA loc_1A03 ; cycles=8 loc_19F9: -19F9: AA 30 SUB.W R2, R0 -19FB: 48 80 00 CMP:I #H'8000, R0 -19FE: 23 03 BLS loc_1A03 -1A00: 59 FF FF MOV:I.W #H'FFFF, R1 +19F9: AA 30 SUB.W R2, R0 ; cycles=3 +19FB: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +19FE: 23 03 BLS loc_1A03 ; cycles=3/7 nt/t +1A00: 59 FF FF MOV:I.W #H'FFFF, R1 ; cycles=3 loc_1A03: -1A03: FB E0 00 71 CMP:G.W @(-H'2000,R3), R1 -1A07: 27 0B BEQ loc_1A14 -1A09: FB E8 00 91 MOV:G.W R1, @(-H'1800,R3) -1A0D: 52 80 MOV:E.B #H'80, R2 -1A0F: AD 83 MOV:G.W R5, R3 -1A11: 1E 24 40 BSR loc_3E54 +1A03: FB E0 00 71 CMP:G.W @(-H'2000,R3), R1 ; cycles=6 +1A07: 27 0B BEQ loc_1A14 ; cycles=3/8 nt/t +1A09: FB E8 00 91 MOV:G.W R1, @(-H'1800,R3) ; cycles=6 +1A0D: 52 80 MOV:E.B #H'80, R2 ; cycles=2 +1A0F: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A11: 1E 24 40 BSR loc_3E54 ; cycles=14 loc_1A14: -1A14: 19 RTS +1A14: 19 RTS ; cycles=12 loc_1A35: -1A35: AB 85 MOV:G.W R3, R5 -1A37: 0C 01 FF 53 AND.W #H'01FF, R3 -1A3B: AB 1A SHLL.W R3 -1A3D: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 -1A41: 27 3A BEQ loc_1A7D -1A43: 0E 48 BSR loc_1A8D +1A35: AB 85 MOV:G.W R3, R5 ; cycles=3 +1A37: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +1A3B: AB 1A SHLL.W R3 ; cycles=3 +1A3D: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +1A41: 27 3A BEQ loc_1A7D ; cycles=3/8 nt/t +1A43: 0E 48 BSR loc_1A8D ; cycles=14 loc_1A45: -1A45: AC 16 TST.W R4 -1A47: 26 10 BNE loc_1A59 -1A49: A8 82 MOV:G.W R0, R2 +1A45: AC 16 TST.W R4 ; cycles=3 +1A47: 26 10 BNE loc_1A59 ; cycles=3/8 nt/t +1A49: A8 82 MOV:G.W R0, R2 ; cycles=3 loc_1A4B: -1A4B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 -1A4F: A8 1B SHLR.W R0 -1A51: 27 16 BEQ loc_1A69 -1A53: A8 51 AND.W R0, R1 -1A55: 27 F4 BEQ loc_1A4B -1A57: 20 12 BRA loc_1A6B +1A4B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A4F: A8 1B SHLR.W R0 ; cycles=3 +1A51: 27 16 BEQ loc_1A69 ; cycles=3/8 nt/t +1A53: A8 51 AND.W R0, R1 ; cycles=3 +1A55: 27 F4 BEQ loc_1A4B ; cycles=3/8 nt/t +1A57: 20 12 BRA loc_1A6B ; cycles=8 loc_1A59: -1A59: A8 82 MOV:G.W R0, R2 +1A59: A8 82 MOV:G.W R0, R2 ; cycles=3 loc_1A5B: -1A5B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 -1A5F: A8 1A SHLL.W R0 -1A61: 27 06 BEQ loc_1A69 -1A63: A8 51 AND.W R0, R1 -1A65: 27 F4 BEQ loc_1A5B -1A67: 20 02 BRA loc_1A6B +1A5B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A5F: A8 1A SHLL.W R0 ; cycles=3 +1A61: 27 06 BEQ loc_1A69 ; cycles=3/8 nt/t +1A63: A8 51 AND.W R0, R1 ; cycles=3 +1A65: 27 F4 BEQ loc_1A5B ; cycles=3/8 nt/t +1A67: 20 02 BRA loc_1A6B ; cycles=8 loc_1A69: -1A69: AA 80 MOV:G.W R2, R0 +1A69: AA 80 MOV:G.W R2, R0 ; cycles=3 loc_1A6B: -1A6B: FB E0 00 70 CMP:G.W @(-H'2000,R3), R0 -1A6F: 27 0B BEQ loc_1A7C -1A71: FB E8 00 90 MOV:G.W R0, @(-H'1800,R3) -1A75: 52 80 MOV:E.B #H'80, R2 -1A77: AD 83 MOV:G.W R5, R3 -1A79: 1E 23 D8 BSR loc_3E54 +1A6B: FB E0 00 70 CMP:G.W @(-H'2000,R3), R0 ; cycles=6 +1A6F: 27 0B BEQ loc_1A7C ; cycles=3/8 nt/t +1A71: FB E8 00 90 MOV:G.W R0, @(-H'1800,R3) ; cycles=6 +1A75: 52 80 MOV:E.B #H'80, R2 ; cycles=2 +1A77: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A79: 1E 23 D8 BSR loc_3E54 ; cycles=14 loc_1A7C: -1A7C: 19 RTS +1A7C: 19 RTS ; cycles=12 loc_1A7D: -1A7D: A8 CF BSET.W #15, R0 +1A7D: A8 CF BSET.W #15, R0 ; cycles=3 loc_1A7F: -1A7F: A8 81 MOV:G.W R0, R1 -1A81: FB E4 00 51 AND.W @(-H'1C00,R3), R1 -1A85: 26 04 BNE loc_1A8B -1A87: A8 1B SHLR.W R0 -1A89: 20 F4 BRA loc_1A7F +1A7F: A8 81 MOV:G.W R0, R1 ; cycles=3 +1A81: FB E4 00 51 AND.W @(-H'1C00,R3), R1 ; cycles=6 +1A85: 26 04 BNE loc_1A8B ; cycles=3/8 nt/t +1A87: A8 1B SHLR.W R0 ; cycles=3 +1A89: 20 F4 BRA loc_1A7F ; cycles=8 loc_1A8B: -1A8B: 20 B8 BRA loc_1A45 +1A8B: 20 B8 BRA loc_1A45 ; cycles=8 loc_1A8D: -1A8D: 59 00 0F MOV:I.W #H'000F, R1 +1A8D: 59 00 0F MOV:I.W #H'000F, R1 ; cycles=3 loc_1A90: -1A90: A8 79 BTST.W R1, R0 -1A92: 26 03 BNE loc_1A97 -1A94: 01 B9 F9 SCB/F R1, loc_1A90 +1A90: A8 79 BTST.W R1, R0 ; cycles=3 +1A92: 26 03 BNE loc_1A97 ; cycles=3/7 nt/t +1A94: 01 B9 F9 SCB/F R1, loc_1A90 ; cycles=3/4/8 false/-1/t loc_1A97: -1A97: A8 13 CLR.W R0 -1A99: A8 49 BSET.W R1, R0 -1A9B: 19 RTS +1A97: A8 13 CLR.W R0 ; cycles=3 +1A99: A8 49 BSET.W R1, R0 ; cycles=3 +1A9B: 19 RTS ; cycles=13 loc_1A9C: -1A9C: AB 16 TST.W R3 -1A9E: 27 32 BEQ loc_1AD2 -1AA0: AB 1A SHLL.W R3 -1AA2: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs H'F733 in on_chip_ram -1AA6: A0 15 NOT.B R0 -1AA8: 04 0F 50 AND.B #H'0F, R0 -1AAB: AC 16 TST.W R4 -1AAD: 26 0D BNE loc_1ABC +1A9C: AB 16 TST.W R3 ; cycles=3 +1A9E: 27 32 BEQ loc_1AD2 ; cycles=3/7 nt/t +1AA0: AB 1A SHLL.W R3 ; cycles=3 +1AA2: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs H'F733 in on_chip_ram; cycles=7 +1AA6: A0 15 NOT.B R0 ; cycles=2 +1AA8: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AAB: AC 16 TST.W R4 ; cycles=3 +1AAD: 26 0D BNE loc_1ABC ; cycles=3/8 nt/t loc_1AAF: -1AAF: A0 0C ADD:Q.B #-1, R0 -1AB1: 04 0F 50 AND.B #H'0F, R0 -1AB4: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) -1AB8: 27 F5 BEQ loc_1AAF -1ABA: 20 0B BRA loc_1AC7 +1AAF: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1AB1: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AB4: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=7 +1AB8: 27 F5 BEQ loc_1AAF ; cycles=3/7 nt/t +1ABA: 20 0B BRA loc_1AC7 ; cycles=7 loc_1ABC: -1ABC: A0 08 ADD:Q.B #1, R0 -1ABE: 04 0F 50 AND.B #H'0F, R0 -1AC1: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) -1AC5: 27 F5 BEQ loc_1ABC +1ABC: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1ABE: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AC1: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=6 +1AC5: 27 F5 BEQ loc_1ABC ; cycles=3/8 nt/t loc_1AC7: -1AC7: A0 15 NOT.B R0 -1AC9: 04 0F 50 AND.B #H'0F, R0 -1ACC: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs H'F733 in on_chip_ram -1AD0: 20 0E BRA loc_1AE0 +1AC7: A0 15 NOT.B R0 ; cycles=2 +1AC9: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1ACC: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs H'F733 in on_chip_ram; cycles=7 +1AD0: 20 0E BRA loc_1AE0 ; cycles=7 loc_1AD2: -1AD2: AC 16 TST.W R4 -1AD4: 26 06 BNE loc_1ADC -1AD6: 15 F7 33 08 ADD:Q.B #1, @H'F733 ; refs H'F733 in on_chip_ram -1ADA: 20 04 BRA loc_1AE0 +1AD2: AC 16 TST.W R4 ; cycles=3 +1AD4: 26 06 BNE loc_1ADC ; cycles=3/7 nt/t +1AD6: 15 F7 33 08 ADD:Q.B #1, @H'F733 ; refs H'F733 in on_chip_ram; cycles=9 +1ADA: 20 04 BRA loc_1AE0 ; cycles=7 loc_1ADC: -1ADC: 15 F7 33 0C ADD:Q.B #-1, @H'F733 ; refs H'F733 in on_chip_ram +1ADC: 15 F7 33 0C ADD:Q.B #-1, @H'F733 ; refs H'F733 in on_chip_ram; cycles=9 loc_1AE0: -1AE0: 1E 2E 17 BSR loc_48FA -1AE3: 19 RTS +1AE0: 1E 2E 17 BSR loc_48FA ; cycles=13 +1AE3: 19 RTS ; cycles=13 loc_1AE4: -1AE4: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs H'F75B in on_chip_ram -1AE8: A0 12 EXTU.B R0 -1AEA: F0 F7 5D 81 MOV:G.B @(-H'08A3,R0), R1 -1AEE: AC 16 TST.W R4 -1AF0: 26 0A BNE loc_1AFC -1AF2: A1 08 ADD:Q.B #1, R1 -1AF4: 41 2E CMP:E #H'2E, R1 -1AF6: 23 0B BLS loc_1B03 -1AF8: 51 00 MOV:E.B #H'00, R1 -1AFA: 20 07 BRA loc_1B03 +1AE4: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs H'F75B in on_chip_ram; cycles=7 +1AE8: A0 12 EXTU.B R0 ; cycles=3 +1AEA: F0 F7 5D 81 MOV:G.B @(-H'08A3,R0), R1 ; cycles=7 +1AEE: AC 16 TST.W R4 ; cycles=3 +1AF0: 26 0A BNE loc_1AFC ; cycles=3/7 nt/t +1AF2: A1 08 ADD:Q.B #1, R1 ; cycles=4 +1AF4: 41 2E CMP:E #H'2E, R1 ; cycles=2 +1AF6: 23 0B BLS loc_1B03 ; cycles=3/7 nt/t +1AF8: 51 00 MOV:E.B #H'00, R1 ; cycles=2 +1AFA: 20 07 BRA loc_1B03 ; cycles=7 loc_1AFC: -1AFC: 04 01 31 SUB.B #H'01, R1 -1AFF: 24 02 BCC loc_1B03 -1B01: 51 2E MOV:E.B #H'2E, R1 +1AFC: 04 01 31 SUB.B #H'01, R1 ; cycles=3 +1AFF: 24 02 BCC loc_1B03 ; cycles=3/8 nt/t +1B01: 51 2E MOV:E.B #H'2E, R1 ; cycles=2 loc_1B03: -1B03: F0 F7 5D 91 MOV:G.B R1, @(-H'08A3,R0) -1B07: 1E 2D F0 BSR loc_48FA -1B0A: 19 RTS +1B03: F0 F7 5D 91 MOV:G.B R1, @(-H'08A3,R0) ; cycles=6 +1B07: 1E 2D F0 BSR loc_48FA ; cycles=14 +1B0A: 19 RTS ; cycles=12 loc_1B0B: -1B0B: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs H'F75B in on_chip_ram -1B0F: AC 16 TST.W R4 -1B11: 26 0A BNE loc_1B1D -1B13: A0 08 ADD:Q.B #1, R0 -1B15: 40 08 CMP:E #H'08, R0 -1B17: 23 0C BLS loc_1B25 -1B19: 50 08 MOV:E.B #H'08, R0 -1B1B: 20 08 BRA loc_1B25 +1B0B: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs H'F75B in on_chip_ram; cycles=6 +1B0F: AC 16 TST.W R4 ; cycles=3 +1B11: 26 0A BNE loc_1B1D ; cycles=3/8 nt/t +1B13: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1B15: 40 08 CMP:E #H'08, R0 ; cycles=2 +1B17: 23 0C BLS loc_1B25 ; cycles=3/8 nt/t +1B19: 50 08 MOV:E.B #H'08, R0 ; cycles=2 +1B1B: 20 08 BRA loc_1B25 ; cycles=8 loc_1B1D: -1B1D: A0 0C ADD:Q.B #-1, R0 -1B1F: 40 01 CMP:E #H'01, R0 -1B21: 24 02 BCC loc_1B25 -1B23: 50 01 MOV:E.B #H'01, R0 +1B1D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1B1F: 40 01 CMP:E #H'01, R0 ; cycles=2 +1B21: 24 02 BCC loc_1B25 ; cycles=3/8 nt/t +1B23: 50 01 MOV:E.B #H'01, R0 ; cycles=2 loc_1B25: -1B25: 15 F7 5B 90 MOV:G.B R0, @H'F75B ; refs H'F75B in on_chip_ram -1B29: 1E 2D CE BSR loc_48FA -1B2C: 19 RTS +1B25: 15 F7 5B 90 MOV:G.B R0, @H'F75B ; refs H'F75B in on_chip_ram; cycles=6 +1B29: 1E 2D CE BSR loc_48FA ; cycles=14 +1B2C: 19 RTS ; cycles=12 loc_1B2D: -1B2D: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs H'F6D7 in on_chip_ram -1B31: 15 F6 E7 64 XOR.B @H'F6E7, R4 ; refs H'F6E7 in on_chip_ram -1B35: 5D 00 7E MOV:I.W #H'007E, R5 -1B38: 1E 00 D3 BSR loc_1C0E -1B3B: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs H'F6D7 in on_chip_ram -1B3F: 15 F6 E7 94 MOV:G.B R4, @H'F6E7 ; refs H'F6E7 in on_chip_ram -1B43: 19 RTS +1B2D: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs H'F6D7 in on_chip_ram; cycles=6 +1B31: 15 F6 E7 64 XOR.B @H'F6E7, R4 ; refs H'F6E7 in on_chip_ram; cycles=6 +1B35: 5D 00 7E MOV:I.W #H'007E, R5 ; cycles=3 +1B38: 1E 00 D3 BSR loc_1C0E ; cycles=13 +1B3B: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs H'F6D7 in on_chip_ram; cycles=6 +1B3F: 15 F6 E7 94 MOV:G.B R4, @H'F6E7 ; refs H'F6E7 in on_chip_ram; cycles=6 +1B43: 19 RTS ; cycles=13 loc_1B44: -1B44: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs H'F6D6 in on_chip_ram -1B48: 15 F6 E6 64 XOR.B @H'F6E6, R4 ; refs H'F6E6 in on_chip_ram -1B4C: 5D 00 6E MOV:I.W #H'006E, R5 -1B4F: 1E 00 BC BSR loc_1C0E -1B52: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs H'F6D6 in on_chip_ram -1B56: 15 F6 E6 94 MOV:G.B R4, @H'F6E6 ; refs H'F6E6 in on_chip_ram -1B5A: 19 RTS +1B44: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs H'F6D6 in on_chip_ram; cycles=7 +1B48: 15 F6 E6 64 XOR.B @H'F6E6, R4 ; refs H'F6E6 in on_chip_ram; cycles=7 +1B4C: 5D 00 6E MOV:I.W #H'006E, R5 ; cycles=3 +1B4F: 1E 00 BC BSR loc_1C0E ; cycles=14 +1B52: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs H'F6D6 in on_chip_ram; cycles=7 +1B56: 15 F6 E6 94 MOV:G.B R4, @H'F6E6 ; refs H'F6E6 in on_chip_ram; cycles=7 +1B5A: 19 RTS ; cycles=12 loc_1B5B: -1B5B: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs H'F6D5 in on_chip_ram -1B5F: 15 F6 E5 64 XOR.B @H'F6E5, R4 ; refs H'F6E5 in on_chip_ram -1B63: 5D 00 5E MOV:I.W #H'005E, R5 -1B66: 1E 00 A5 BSR loc_1C0E -1B69: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs H'F6D5 in on_chip_ram -1B6D: 15 F6 E5 94 MOV:G.B R4, @H'F6E5 ; refs H'F6E5 in on_chip_ram -1B71: 19 RTS +1B5B: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs H'F6D5 in on_chip_ram; cycles=6 +1B5F: 15 F6 E5 64 XOR.B @H'F6E5, R4 ; refs H'F6E5 in on_chip_ram; cycles=6 +1B63: 5D 00 5E MOV:I.W #H'005E, R5 ; cycles=3 +1B66: 1E 00 A5 BSR loc_1C0E ; cycles=13 +1B69: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs H'F6D5 in on_chip_ram; cycles=6 +1B6D: 15 F6 E5 94 MOV:G.B R4, @H'F6E5 ; refs H'F6E5 in on_chip_ram; cycles=6 +1B71: 19 RTS ; cycles=13 loc_1B72: -1B72: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs H'F6D1 in on_chip_ram -1B76: 15 F6 E1 64 XOR.B @H'F6E1, R4 ; refs H'F6E1 in on_chip_ram -1B7A: 5D 00 1E MOV:I.W #H'001E, R5 -1B7D: 1E 00 8E BSR loc_1C0E -1B80: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs H'F6D1 in on_chip_ram -1B84: 15 F6 E1 94 MOV:G.B R4, @H'F6E1 ; refs H'F6E1 in on_chip_ram -1B88: 19 RTS +1B72: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs H'F6D1 in on_chip_ram; cycles=7 +1B76: 15 F6 E1 64 XOR.B @H'F6E1, R4 ; refs H'F6E1 in on_chip_ram; cycles=7 +1B7A: 5D 00 1E MOV:I.W #H'001E, R5 ; cycles=3 +1B7D: 1E 00 8E BSR loc_1C0E ; cycles=14 +1B80: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs H'F6D1 in on_chip_ram; cycles=7 +1B84: 15 F6 E1 94 MOV:G.B R4, @H'F6E1 ; refs H'F6E1 in on_chip_ram; cycles=7 +1B88: 19 RTS ; cycles=12 loc_1B89: -1B89: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs H'F6D0 in on_chip_ram -1B8D: 15 F6 E0 64 XOR.B @H'F6E0, R4 ; refs H'F6E0 in on_chip_ram -1B91: 5D 00 0E MOV:I.W #H'000E, R5 -1B94: 1E 00 77 BSR loc_1C0E -1B97: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs H'F6D0 in on_chip_ram -1B9B: 15 F6 E0 94 MOV:G.B R4, @H'F6E0 ; refs H'F6E0 in on_chip_ram -1B9F: 19 RTS +1B89: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs H'F6D0 in on_chip_ram; cycles=6 +1B8D: 15 F6 E0 64 XOR.B @H'F6E0, R4 ; refs H'F6E0 in on_chip_ram; cycles=6 +1B91: 5D 00 0E MOV:I.W #H'000E, R5 ; cycles=3 +1B94: 1E 00 77 BSR loc_1C0E ; cycles=13 +1B97: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs H'F6D0 in on_chip_ram; cycles=6 +1B9B: 15 F6 E0 94 MOV:G.B R4, @H'F6E0 ; refs H'F6E0 in on_chip_ram; cycles=6 +1B9F: 19 RTS ; cycles=13 loc_1BA0: -1BA0: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs H'F6D4 in on_chip_ram -1BA4: 15 F6 E4 64 XOR.B @H'F6E4, R4 ; refs H'F6E4 in on_chip_ram -1BA8: 5D 00 4E MOV:I.W #H'004E, R5 -1BAB: 0E 61 BSR loc_1C0E -1BAD: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs H'F6D4 in on_chip_ram -1BB1: 15 F6 E4 94 MOV:G.B R4, @H'F6E4 ; refs H'F6E4 in on_chip_ram -1BB5: 19 RTS +1BA0: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs H'F6D4 in on_chip_ram; cycles=7 +1BA4: 15 F6 E4 64 XOR.B @H'F6E4, R4 ; refs H'F6E4 in on_chip_ram; cycles=7 +1BA8: 5D 00 4E MOV:I.W #H'004E, R5 ; cycles=3 +1BAB: 0E 61 BSR loc_1C0E ; cycles=14 +1BAD: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs H'F6D4 in on_chip_ram; cycles=6 +1BB1: 15 F6 E4 94 MOV:G.B R4, @H'F6E4 ; refs H'F6E4 in on_chip_ram; cycles=6 +1BB5: 19 RTS ; cycles=13 loc_1BB6: -1BB6: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs H'F6D3 in on_chip_ram -1BBA: 15 F6 E3 64 XOR.B @H'F6E3, R4 ; refs H'F6E3 in on_chip_ram -1BBE: 5D 00 3E MOV:I.W #H'003E, R5 -1BC1: 0E 4B BSR loc_1C0E -1BC3: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs H'F6D3 in on_chip_ram -1BC7: 15 F6 E3 94 MOV:G.B R4, @H'F6E3 ; refs H'F6E3 in on_chip_ram -1BCB: 19 RTS +1BB6: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs H'F6D3 in on_chip_ram; cycles=7 +1BBA: 15 F6 E3 64 XOR.B @H'F6E3, R4 ; refs H'F6E3 in on_chip_ram; cycles=7 +1BBE: 5D 00 3E MOV:I.W #H'003E, R5 ; cycles=3 +1BC1: 0E 4B BSR loc_1C0E ; cycles=14 +1BC3: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs H'F6D3 in on_chip_ram; cycles=6 +1BC7: 15 F6 E3 94 MOV:G.B R4, @H'F6E3 ; refs H'F6E3 in on_chip_ram; cycles=6 +1BCB: 19 RTS ; cycles=13 loc_1BCC: -1BCC: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs H'F6D2 in on_chip_ram -1BD0: 15 F6 E2 64 XOR.B @H'F6E2, R4 ; refs H'F6E2 in on_chip_ram -1BD4: 5D 00 2E MOV:I.W #H'002E, R5 -1BD7: 0E 35 BSR loc_1C0E -1BD9: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs H'F6D2 in on_chip_ram -1BDD: 15 F6 E2 94 MOV:G.B R4, @H'F6E2 ; refs H'F6E2 in on_chip_ram -1BE1: 19 RTS +1BCC: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs H'F6D2 in on_chip_ram; cycles=7 +1BD0: 15 F6 E2 64 XOR.B @H'F6E2, R4 ; refs H'F6E2 in on_chip_ram; cycles=7 +1BD4: 5D 00 2E MOV:I.W #H'002E, R5 ; cycles=3 +1BD7: 0E 35 BSR loc_1C0E ; cycles=14 +1BD9: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs H'F6D2 in on_chip_ram; cycles=6 +1BDD: 15 F6 E2 94 MOV:G.B R4, @H'F6E2 ; refs H'F6E2 in on_chip_ram; cycles=6 +1BE1: 19 RTS ; cycles=13 loc_1BE2: -1BE2: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs H'F6DC in on_chip_ram -1BE6: 15 F6 EC 64 XOR.B @H'F6EC, R4 ; refs H'F6EC in on_chip_ram -1BEA: 5D 00 CE MOV:I.W #H'00CE, R5 -1BED: 0E 1F BSR loc_1C0E -1BEF: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs H'F6DC in on_chip_ram -1BF3: 15 F6 EC 94 MOV:G.B R4, @H'F6EC ; refs H'F6EC in on_chip_ram -1BF7: 19 RTS +1BE2: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs H'F6DC in on_chip_ram; cycles=7 +1BE6: 15 F6 EC 64 XOR.B @H'F6EC, R4 ; refs H'F6EC in on_chip_ram; cycles=7 +1BEA: 5D 00 CE MOV:I.W #H'00CE, R5 ; cycles=3 +1BED: 0E 1F BSR loc_1C0E ; cycles=14 +1BEF: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs H'F6DC in on_chip_ram; cycles=6 +1BF3: 15 F6 EC 94 MOV:G.B R4, @H'F6EC ; refs H'F6EC in on_chip_ram; cycles=6 +1BF7: 19 RTS ; cycles=13 loc_1BF8: -1BF8: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs H'F6DB in on_chip_ram -1BFC: 15 F6 EB 64 XOR.B @H'F6EB, R4 ; refs H'F6EB in on_chip_ram -1C00: 5D 00 BE MOV:I.W #H'00BE, R5 -1C03: 0E 09 BSR loc_1C0E -1C05: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs H'F6DB in on_chip_ram -1C09: 15 F6 EB 94 MOV:G.B R4, @H'F6EB ; refs H'F6EB in on_chip_ram -1C0D: 19 RTS +1BF8: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs H'F6DB in on_chip_ram; cycles=7 +1BFC: 15 F6 EB 64 XOR.B @H'F6EB, R4 ; refs H'F6EB in on_chip_ram; cycles=7 +1C00: 5D 00 BE MOV:I.W #H'00BE, R5 ; cycles=3 +1C03: 0E 09 BSR loc_1C0E ; cycles=14 +1C05: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs H'F6DB in on_chip_ram; cycles=6 +1C09: 15 F6 EB 94 MOV:G.B R4, @H'F6EB ; refs H'F6EB in on_chip_ram; cycles=6 +1C0D: 19 RTS ; cycles=13 loc_1C0E: -1C0E: A4 1A SHLL.B R4 -1C10: 24 0A BCC loc_1C1C -1C12: FD 27 06 80 MOV:G.W @(H'2706,R5), R0 -1C16: 12 30 STM.W {R4,R5}, @-SP -1C18: 11 D8 JSR @R0 -1C1A: 02 30 LDM.W @SP+, {R4,R5} +1C0E: A4 1A SHLL.B R4 ; cycles=2 +1C10: 24 0A BCC loc_1C1C ; cycles=3/7 nt/t +1C12: FD 27 06 80 MOV:G.W @(H'2706,R5), R0 ; cycles=7 +1C16: 12 30 STM.W {R4,R5}, @-SP ; cycles=12 +1C18: 11 D8 JSR @R0 ; cycles=13 +1C1A: 02 30 LDM.W @SP+, {R4,R5} ; cycles=14 loc_1C1C: -1C1C: A4 16 TST.B R4 -1C1E: 27 04 BEQ loc_1C24 -1C20: AD 0D ADD:Q.W #-2, R5 -1C22: 20 EA BRA loc_1C0E +1C1C: A4 16 TST.B R4 ; cycles=2 +1C1E: 27 04 BEQ loc_1C24 ; cycles=3/7 nt/t +1C20: AD 0D ADD:Q.W #-2, R5 ; cycles=4 +1C22: 20 EA BRA loc_1C0E ; cycles=7 loc_1C24: -1C24: 19 RTS +1C24: 19 RTS ; cycles=12 loc_2127: -2127: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -212B: 26 08 BNE loc_2135 -212D: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs H'F732 in on_chip_ram -2131: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs H'F734 in on_chip_ram +2127: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=8 +212B: 26 08 BNE loc_2135 ; cycles=3/8 nt/t +212D: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs H'F732 in on_chip_ram; cycles=6 +2131: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs H'F734 in on_chip_ram; cycles=6 loc_2135: -2135: 1D F7 32 07 1C 03 MOV:G.W #H'1C03, @H'F732 ; refs H'F732 in on_chip_ram -213B: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs H'FB02 in on_chip_ram -2140: 1E 27 B7 BSR loc_48FA -2143: 19 RTS +2135: 1D F7 32 07 1C 03 MOV:G.W #H'1C03, @H'F732 ; refs H'F732 in on_chip_ram; cycles=9 +213B: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=9 +2140: 1E 27 B7 BSR loc_48FA ; cycles=13 +2143: 19 RTS ; cycles=13 loc_2650: -2650: 15 F6 F6 D5 BCLR.B #5, @H'F6F6 ; refs H'F6F6 in on_chip_ram -2654: 37 00 68 BEQ loc_26BF -2657: 1D E1 24 80 MOV:G.W @H'E124, R0 ; refs H'E124 in program_or_external -265B: A8 1A SHLL.W R0 -265D: A0 10 SWAP.B R0 -265F: 15 F6 F6 F6 BTST.B #6, @H'F6F6 ; refs H'F6F6 in on_chip_ram -2663: 26 08 BNE loc_266D -2665: A0 08 ADD:Q.B #1, R0 -2667: 24 1A BCC loc_2683 -2669: 50 FF MOV:E.B #H'FF, R0 -266B: 20 16 BRA loc_2683 +2650: 15 F6 F6 D5 BCLR.B #5, @H'F6F6 ; refs H'F6F6 in on_chip_ram; cycles=9 +2654: 37 00 68 BEQ loc_26BF ; cycles=3/7 nt/t +2657: 1D E1 24 80 MOV:G.W @H'E124, R0 ; refs H'E124 in program_or_external; cycles=6 +265B: A8 1A SHLL.W R0 ; cycles=3 +265D: A0 10 SWAP.B R0 ; cycles=3 +265F: 15 F6 F6 F6 BTST.B #6, @H'F6F6 ; refs H'F6F6 in on_chip_ram; cycles=6 +2663: 26 08 BNE loc_266D ; cycles=3/8 nt/t +2665: A0 08 ADD:Q.B #1, R0 ; cycles=4 +2667: 24 1A BCC loc_2683 ; cycles=3/8 nt/t +2669: 50 FF MOV:E.B #H'FF, R0 ; cycles=2 +266B: 20 16 BRA loc_2683 ; cycles=8 loc_266D: -266D: A0 0C ADD:Q.B #-1, R0 -266F: 1D E0 04 FD BTST.W #13, @H'E004 ; refs H'E004 in program_or_external -2673: 26 08 BNE loc_267D -2675: 40 49 CMP:E #H'49, R0 -2677: 24 0A BCC loc_2683 -2679: 50 49 MOV:E.B #H'49, R0 -267B: 20 06 BRA loc_2683 +266D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +266F: 1D E0 04 FD BTST.W #13, @H'E004 ; refs H'E004 in program_or_external; cycles=6 +2673: 26 08 BNE loc_267D ; cycles=3/8 nt/t +2675: 40 49 CMP:E #H'49, R0 ; cycles=2 +2677: 24 0A BCC loc_2683 ; cycles=3/8 nt/t +2679: 50 49 MOV:E.B #H'49, R0 ; cycles=2 +267B: 20 06 BRA loc_2683 ; cycles=8 loc_267D: -267D: 40 16 CMP:E #H'16, R0 -267F: 24 02 BCC loc_2683 -2681: 50 16 MOV:E.B #H'16, R0 +267D: 40 16 CMP:E #H'16, R0 ; cycles=2 +267F: 24 02 BCC loc_2683 ; cycles=3/8 nt/t +2681: 50 16 MOV:E.B #H'16, R0 ; cycles=2 loc_2683: -2683: A0 12 EXTU.B R0 -2685: A0 10 SWAP.B R0 -2687: A8 1B SHLR.W R0 -2689: A8 CF BSET.W #15, R0 -268B: 1D E1 24 70 CMP:G.W @H'E124, R0 ; refs H'E124 in program_or_external -268F: 27 2E BEQ loc_26BF -2691: 1D E9 24 90 MOV:G.W R0, @H'E924 ; refs H'E924 in program_or_external -2695: 52 80 MOV:E.B #H'80, R2 -2697: 5B 00 92 MOV:I.W #H'0092, R3 -269A: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -269E: 27 08 BEQ loc_26A8 -26A0: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs H'F404 in program_or_external -26A4: 27 02 BEQ loc_26A8 -26A6: AB CE BSET.W #14, R3 +2683: A0 12 EXTU.B R0 ; cycles=3 +2685: A0 10 SWAP.B R0 ; cycles=3 +2687: A8 1B SHLR.W R0 ; cycles=3 +2689: A8 CF BSET.W #15, R0 ; cycles=3 +268B: 1D E1 24 70 CMP:G.W @H'E124, R0 ; refs H'E124 in program_or_external; cycles=6 +268F: 27 2E BEQ loc_26BF ; cycles=3/8 nt/t +2691: 1D E9 24 90 MOV:G.W R0, @H'E924 ; refs H'E924 in program_or_external; cycles=6 +2695: 52 80 MOV:E.B #H'80, R2 ; cycles=2 +2697: 5B 00 92 MOV:I.W #H'0092, R3 ; cycles=3 +269A: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=7 +269E: 27 08 BEQ loc_26A8 ; cycles=3/7 nt/t +26A0: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs H'F404 in program_or_external; cycles=7 +26A4: 27 02 BEQ loc_26A8 ; cycles=3/7 nt/t +26A6: AB CE BSET.W #14, R3 ; cycles=3 loc_26A8: -26A8: 1E 17 A9 BSR loc_3E54 -26AB: 15 F6 F6 C0 BSET.B #0, @H'F6F6 ; refs H'F6F6 in on_chip_ram -26AF: 26 08 BNE loc_26B9 -26B1: 1D F6 F4 07 07 D0 MOV:G.W #H'07D0, @H'F6F4 ; refs H'F6F4 in on_chip_ram -26B7: 20 06 BRA loc_26BF +26A8: 1E 17 A9 BSR loc_3E54 ; cycles=13 +26AB: 15 F6 F6 C0 BSET.B #0, @H'F6F6 ; refs H'F6F6 in on_chip_ram; cycles=8 +26AF: 26 08 BNE loc_26B9 ; cycles=3/8 nt/t +26B1: 1D F6 F4 07 07 D0 MOV:G.W #H'07D0, @H'F6F4 ; refs H'F6F4 in on_chip_ram; cycles=9 +26B7: 20 06 BRA loc_26BF ; cycles=8 loc_26B9: -26B9: 1D F6 F4 07 00 C8 MOV:G.W #H'00C8, @H'F6F4 ; refs H'F6F4 in on_chip_ram +26B9: 1D F6 F4 07 00 C8 MOV:G.W #H'00C8, @H'F6F4 ; refs H'F6F4 in on_chip_ram; cycles=9 loc_26BF: -26BF: 19 RTS +26BF: 19 RTS ; cycles=13 loc_2806: -2806: 15 F9 B9 81 MOV:G.B @H'F9B9, R1 ; refs H'F9B9 in on_chip_ram -280A: A1 12 EXTU.B R1 -280C: 15 F9 B4 71 CMP:G.B @H'F9B4, R1 ; refs H'F9B4 in on_chip_ram -2810: 26 03 BNE loc_2815 -2812: 30 04 91 BRA loc_2CA6 +2806: 15 F9 B9 81 MOV:G.B @H'F9B9, R1 ; refs H'F9B9 in on_chip_ram; cycles=7 +280A: A1 12 EXTU.B R1 ; cycles=3 +280C: 15 F9 B4 71 CMP:G.B @H'F9B4, R1 ; refs H'F9B4 in on_chip_ram; cycles=7 +2810: 26 03 BNE loc_2815 ; cycles=3/7 nt/t +2812: 30 04 91 BRA loc_2CA6 ; cycles=7 loc_2815: -2815: A9 80 MOV:G.W R1, R0 -2817: A8 1A SHLL.W R0 -2819: F8 F9 70 80 MOV:G.W @(-H'0690,R0), R0 -281D: A1 08 ADD:Q.B #1, R1 -281F: 04 1F 51 AND.B #H'1F, R1 -2822: 15 F9 B9 91 MOV:G.B R1, @H'F9B9 ; refs H'F9B9 in on_chip_ram -2826: 0C 01 FF 50 AND.W #H'01FF, R0 -282A: A8 85 MOV:G.W R0, R5 -282C: 1E 39 D7 BSR loc_6206 -282F: A8 84 MOV:G.W R0, R4 -2831: AC 1A SHLL.W R4 -2833: A8 16 TST.W R0 -2835: 27 68 BEQ loc_289F -2837: 1D F7 36 81 MOV:G.W @H'F736, R1 ; refs H'F736 in on_chip_ram -283B: 0C 01 FF 51 AND.W #H'01FF, R1 -283F: A9 70 CMP:G.W R1, R0 -2841: 37 04 67 BEQ loc_2CAB -2844: 1D F7 38 81 MOV:G.W @H'F738, R1 ; refs H'F738 in on_chip_ram -2848: 0C 01 FF 51 AND.W #H'01FF, R1 -284C: A9 70 CMP:G.W R1, R0 -284E: 37 04 5A BEQ loc_2CAB -2851: 1D F7 3A 81 MOV:G.W @H'F73A, R1 ; refs H'F73A in on_chip_ram -2855: 0C 01 FF 51 AND.W #H'01FF, R1 -2859: A9 70 CMP:G.W R1, R0 -285B: 37 04 4D BEQ loc_2CAB -285E: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs H'F73C in on_chip_ram -2862: 0C 01 FF 51 AND.W #H'01FF, R1 -2866: A9 70 CMP:G.W R1, R0 -2868: 37 04 40 BEQ loc_2CAB -286B: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs H'F73E in on_chip_ram -286F: 0C 01 FF 51 AND.W #H'01FF, R1 -2873: A9 70 CMP:G.W R1, R0 -2875: 37 04 33 BEQ loc_2CAB -2878: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs H'F740 in on_chip_ram -287C: 0C 01 FF 51 AND.W #H'01FF, R1 -2880: A9 70 CMP:G.W R1, R0 -2882: 37 04 26 BEQ loc_2CAB -2885: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs H'F742 in on_chip_ram -2889: 0C 01 FF 51 AND.W #H'01FF, R1 -288D: A9 70 CMP:G.W R1, R0 -288F: 37 04 19 BEQ loc_2CAB -2892: 1D F7 54 81 MOV:G.W @H'F754, R1 ; refs H'F754 in on_chip_ram -2896: 0C 01 FF 51 AND.W #H'01FF, R1 -289A: A9 70 CMP:G.W R1, R0 -289C: 37 04 0C BEQ loc_2CAB +2815: A9 80 MOV:G.W R1, R0 ; cycles=3 +2817: A8 1A SHLL.W R0 ; cycles=3 +2819: F8 F9 70 80 MOV:G.W @(-H'0690,R0), R0 ; cycles=6 +281D: A1 08 ADD:Q.B #1, R1 ; cycles=4 +281F: 04 1F 51 AND.B #H'1F, R1 ; cycles=3 +2822: 15 F9 B9 91 MOV:G.B R1, @H'F9B9 ; refs H'F9B9 in on_chip_ram; cycles=7 +2826: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +282A: A8 85 MOV:G.W R0, R5 ; cycles=3 +282C: 1E 39 D7 BSR loc_6206 ; cycles=13 +282F: A8 84 MOV:G.W R0, R4 ; cycles=3 +2831: AC 1A SHLL.W R4 ; cycles=3 +2833: A8 16 TST.W R0 ; cycles=3 +2835: 27 68 BEQ loc_289F ; cycles=3/8 nt/t +2837: 1D F7 36 81 MOV:G.W @H'F736, R1 ; refs H'F736 in on_chip_ram; cycles=6 +283B: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +283F: A9 70 CMP:G.W R1, R0 ; cycles=3 +2841: 37 04 67 BEQ loc_2CAB ; cycles=3/8 nt/t +2844: 1D F7 38 81 MOV:G.W @H'F738, R1 ; refs H'F738 in on_chip_ram; cycles=7 +2848: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +284C: A9 70 CMP:G.W R1, R0 ; cycles=3 +284E: 37 04 5A BEQ loc_2CAB ; cycles=3/7 nt/t +2851: 1D F7 3A 81 MOV:G.W @H'F73A, R1 ; refs H'F73A in on_chip_ram; cycles=6 +2855: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2859: A9 70 CMP:G.W R1, R0 ; cycles=3 +285B: 37 04 4D BEQ loc_2CAB ; cycles=3/8 nt/t +285E: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs H'F73C in on_chip_ram; cycles=7 +2862: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2866: A9 70 CMP:G.W R1, R0 ; cycles=3 +2868: 37 04 40 BEQ loc_2CAB ; cycles=3/7 nt/t +286B: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs H'F73E in on_chip_ram; cycles=6 +286F: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2873: A9 70 CMP:G.W R1, R0 ; cycles=3 +2875: 37 04 33 BEQ loc_2CAB ; cycles=3/8 nt/t +2878: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs H'F740 in on_chip_ram; cycles=7 +287C: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2880: A9 70 CMP:G.W R1, R0 ; cycles=3 +2882: 37 04 26 BEQ loc_2CAB ; cycles=3/7 nt/t +2885: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs H'F742 in on_chip_ram; cycles=6 +2889: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +288D: A9 70 CMP:G.W R1, R0 ; cycles=3 +288F: 37 04 19 BEQ loc_2CAB ; cycles=3/8 nt/t +2892: 1D F7 54 81 MOV:G.W @H'F754, R1 ; refs H'F754 in on_chip_ram; cycles=7 +2896: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +289A: A9 70 CMP:G.W R1, R0 ; cycles=3 +289C: 37 04 0C BEQ loc_2CAB ; cycles=3/7 nt/t loc_289F: -289F: FC 28 A6 81 MOV:G.W @(H'28A6,R4), R1 -28A3: 11 D1 JMP @R1 +289F: FC 28 A6 81 MOV:G.W @(H'28A6,R4), R1 ; cycles=6 +28A3: 11 D1 JMP @R1 ; cycles=7 loc_2CA6: -2CA6: 15 F7 69 D7 BCLR.B #7, @H'F769 ; refs H'F769 in on_chip_ram -2CAA: 19 RTS +2CA6: 15 F7 69 D7 BCLR.B #7, @H'F769 ; refs H'F769 in on_chip_ram; cycles=9 +2CAA: 19 RTS ; cycles=12 loc_2CAB: -2CAB: 12 31 STM.W {R0,R4,R5}, @-SP -2CAD: 1E 1C 4A BSR loc_48FA -2CB0: 02 31 LDM.W @SP+, {R0,R4,R5} -2CB2: 15 F7 69 C7 BSET.B #7, @H'F769 ; refs H'F769 in on_chip_ram -2CB6: 30 FB E6 BRA loc_289F +2CAB: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +2CAD: 1E 1C 4A BSR loc_48FA ; cycles=14 +2CB0: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 +2CB2: 15 F7 69 C7 BSET.B #7, @H'F769 ; refs H'F769 in on_chip_ram; cycles=9 +2CB6: 30 FB E6 BRA loc_289F ; cycles=7 loc_3930: -3930: 58 00 07 MOV:I.W #H'0007, R0 +3930: 58 00 07 MOV:I.W #H'0007, R0 ; cycles=3 loc_3933: -3933: 15 FE 8E 78 BTST.B R0, @P7DR ; refs P7DR in register_field -3937: 27 0A BEQ loc_3943 -3939: F0 F6 80 1A SHLL.B @(-H'0980,R0) -393D: F0 F6 80 C0 BSET.B #0, @(-H'0980,R0) -3941: 20 04 BRA loc_3947 +3933: 15 FE 8E 78 BTST.B R0, @P7DR ; refs P7DR in register_field; cycles=6 +3937: 27 0A BEQ loc_3943 ; cycles=3/8 nt/t +3939: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 +393D: F0 F6 80 C0 BSET.B #0, @(-H'0980,R0) ; cycles=8 +3941: 20 04 BRA loc_3947 ; cycles=8 loc_3943: -3943: F0 F6 80 1A SHLL.B @(-H'0980,R0) +3943: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 loc_3947: -3947: F0 F6 80 04 FF CMP:G.B #H'FF, @(-H'0980,R0) -394C: 26 06 BNE loc_3954 -394E: 15 F6 88 48 BSET.B R0, @H'F688 ; refs H'F688 in on_chip_ram -3952: 20 0B BRA loc_395F +3947: F0 F6 80 04 FF CMP:G.B #H'FF, @(-H'0980,R0) ; cycles=6 +394C: 26 06 BNE loc_3954 ; cycles=3/7 nt/t +394E: 15 F6 88 48 BSET.B R0, @H'F688 ; refs H'F688 in on_chip_ram; cycles=9 +3952: 20 0B BRA loc_395F ; cycles=7 loc_3954: -3954: F0 F6 80 04 00 CMP:G.B #H'00, @(-H'0980,R0) -3959: 26 04 BNE loc_395F -395B: 15 F6 88 58 BCLR.B R0, @H'F688 ; refs H'F688 in on_chip_ram +3954: F0 F6 80 04 00 CMP:G.B #H'00, @(-H'0980,R0) ; cycles=7 +3959: 26 04 BNE loc_395F ; cycles=3/8 nt/t +395B: 15 F6 88 58 BCLR.B R0, @H'F688 ; refs H'F688 in on_chip_ram; cycles=8 loc_395F: -395F: 01 B8 D1 SCB/F R0, loc_3933 -3962: 15 F7 22 08 ADD:Q.B #1, @H'F722 ; refs H'F722 in on_chip_ram -3966: 15 F7 22 04 3C CMP:G.B #H'3C, @H'F722 ; refs H'F722 in on_chip_ram -396B: 27 0F BEQ loc_397C -396D: 15 F7 22 04 78 CMP:G.B #H'78, @H'F722 ; refs H'F722 in on_chip_ram -3972: 27 0B BEQ loc_397F -3974: 15 F7 22 04 B4 CMP:G.B #H'B4, @H'F722 ; refs H'F722 in on_chip_ram -3979: 27 08 BEQ loc_3983 -397B: 19 RTS +395F: 01 B8 D1 SCB/F R0, loc_3933 ; cycles=3/4/9 false/-1/t +3962: 15 F7 22 08 ADD:Q.B #1, @H'F722 ; refs H'F722 in on_chip_ram; cycles=9 +3966: 15 F7 22 04 3C CMP:G.B #H'3C, @H'F722 ; refs H'F722 in on_chip_ram; cycles=7 +396B: 27 0F BEQ loc_397C ; cycles=3/8 nt/t +396D: 15 F7 22 04 78 CMP:G.B #H'78, @H'F722 ; refs H'F722 in on_chip_ram; cycles=6 +3972: 27 0B BEQ loc_397F ; cycles=3/7 nt/t +3974: 15 F7 22 04 B4 CMP:G.B #H'B4, @H'F722 ; refs H'F722 in on_chip_ram; cycles=7 +3979: 27 08 BEQ loc_3983 ; cycles=3/8 nt/t +397B: 19 RTS ; cycles=13 loc_397C: -397C: 0E 17 BSR loc_3995 -397E: 19 RTS +397C: 0E 17 BSR loc_3995 ; cycles=13 +397E: 19 RTS ; cycles=12 loc_397F: -397F: 1E 00 AC BSR loc_3A2E -3982: 19 RTS +397F: 1E 00 AC BSR loc_3A2E ; cycles=14 +3982: 19 RTS ; cycles=12 loc_3983: -3983: 0E 05 BSR loc_398A -3985: 15 F7 22 13 CLR.B @H'F722 ; refs H'F722 in on_chip_ram -3989: 19 RTS +3983: 0E 05 BSR loc_398A ; cycles=14 +3985: 15 F7 22 13 CLR.B @H'F722 ; refs H'F722 in on_chip_ram; cycles=8 +3989: 19 RTS ; cycles=13 loc_398A: -398A: 15 FE E8 F7 BTST.B #7, @ADCSR ; refs ADCSR in register_field -398E: 26 04 BNE loc_3994 -3990: 15 FE E8 C5 BSET.B #5, @ADCSR ; set ADST (bit 5) of ADCSR +398A: 15 FE E8 F7 BTST.B #7, @ADCSR ; refs ADCSR in register_field; cycles=7 +398E: 26 04 BNE loc_3994 ; cycles=3/7 nt/t +3990: 15 FE E8 C5 BSET.B #5, @ADCSR ; set ADST (bit 5) of ADCSR; cycles=9 loc_3994: -3994: 19 RTS +3994: 19 RTS ; cycles=12 loc_3995: -3995: 15 F7 20 16 TST.B @H'F720 ; refs H'F720 in on_chip_ram -3999: 36 00 91 BNE loc_3A2D -399C: 15 F1 01 06 A0 MOV:G.B #H'A0, @H'F101 ; refs H'F101 in program_or_external -39A1: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs H'F100 in program_or_external -39A5: 37 00 85 BEQ loc_3A2D -39A8: 15 F7 1B 80 MOV:G.B @H'F71B, R0 ; refs H'F71B in on_chip_ram -39AC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -39B0: 15 F7 13 50 AND.B @H'F713, R0 ; refs H'F713 in on_chip_ram -39B4: 15 F1 02 90 MOV:G.B R0, @H'F102 ; refs H'F102 in program_or_external -39B8: 15 F7 1A 80 MOV:G.B @H'F71A, R0 ; refs H'F71A in on_chip_ram -39BC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -39C0: 15 F7 12 50 AND.B @H'F712, R0 ; refs H'F712 in on_chip_ram -39C4: 15 F1 03 90 MOV:G.B R0, @H'F103 ; refs H'F103 in program_or_external -39C8: 15 F7 19 80 MOV:G.B @H'F719, R0 ; refs H'F719 in on_chip_ram -39CC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -39D0: 15 F7 11 50 AND.B @H'F711, R0 ; refs H'F711 in on_chip_ram -39D4: 15 F1 04 90 MOV:G.B R0, @H'F104 ; refs H'F104 in program_or_external -39D8: 15 F7 18 80 MOV:G.B @H'F718, R0 ; refs H'F718 in on_chip_ram -39DC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -39E0: 15 F7 10 50 AND.B @H'F710, R0 ; refs H'F710 in on_chip_ram -39E4: 15 F1 05 90 MOV:G.B R0, @H'F105 ; refs H'F105 in program_or_external -39E8: 15 F7 02 80 MOV:G.B @H'F702, R0 ; refs H'F702 in on_chip_ram -39EC: 15 F1 09 90 MOV:G.B R0, @H'F109 ; refs H'F109 in program_or_external -39F0: 15 F7 03 80 MOV:G.B @H'F703, R0 ; refs H'F703 in on_chip_ram -39F4: 15 F1 0A 90 MOV:G.B R0, @H'F10A ; refs H'F10A in program_or_external -39F8: 15 F7 04 80 MOV:G.B @H'F704, R0 ; refs H'F704 in on_chip_ram -39FC: 15 F1 0B 90 MOV:G.B R0, @H'F10B ; refs H'F10B in program_or_external -3A00: 15 F7 05 80 MOV:G.B @H'F705, R0 ; refs H'F705 in on_chip_ram -3A04: 15 F1 0C 90 MOV:G.B R0, @H'F10C ; refs H'F10C in program_or_external -3A08: 15 F7 00 80 MOV:G.B @H'F700, R0 ; refs H'F700 in on_chip_ram -3A0C: 15 F1 0D 90 MOV:G.B R0, @H'F10D ; refs H'F10D in program_or_external -3A10: 15 F7 01 80 MOV:G.B @H'F701, R0 ; refs H'F701 in on_chip_ram -3A14: 15 F1 0E 90 MOV:G.B R0, @H'F10E ; refs H'F10E in program_or_external -3A18: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field -3A1C: A0 15 NOT.B R0 -3A1E: 04 03 50 AND.B #H'03, R0 -3A21: 04 A0 40 OR.B #H'A0, R0 -3A24: 15 F1 0F 90 MOV:G.B R0, @H'F10F ; refs H'F10F in program_or_external -3A28: 15 F7 20 06 03 MOV:G.B #H'03, @H'F720 ; refs H'F720 in on_chip_ram +3995: 15 F7 20 16 TST.B @H'F720 ; refs H'F720 in on_chip_ram; cycles=6 +3999: 36 00 91 BNE loc_3A2D ; cycles=3/8 nt/t +399C: 15 F1 01 06 A0 MOV:G.B #H'A0, @H'F101 ; refs H'F101 in program_or_external; cycles=9 +39A1: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs H'F100 in program_or_external; cycles=6 +39A5: 37 00 85 BEQ loc_3A2D ; cycles=3/8 nt/t +39A8: 15 F7 1B 80 MOV:G.B @H'F71B, R0 ; refs H'F71B in on_chip_ram; cycles=7 +39AC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=7 +39B0: 15 F7 13 50 AND.B @H'F713, R0 ; refs H'F713 in on_chip_ram; cycles=7 +39B4: 15 F1 02 90 MOV:G.B R0, @H'F102 ; refs H'F102 in program_or_external; cycles=7 +39B8: 15 F7 1A 80 MOV:G.B @H'F71A, R0 ; refs H'F71A in on_chip_ram; cycles=7 +39BC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=7 +39C0: 15 F7 12 50 AND.B @H'F712, R0 ; refs H'F712 in on_chip_ram; cycles=7 +39C4: 15 F1 03 90 MOV:G.B R0, @H'F103 ; refs H'F103 in program_or_external; cycles=7 +39C8: 15 F7 19 80 MOV:G.B @H'F719, R0 ; refs H'F719 in on_chip_ram; cycles=7 +39CC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=7 +39D0: 15 F7 11 50 AND.B @H'F711, R0 ; refs H'F711 in on_chip_ram; cycles=7 +39D4: 15 F1 04 90 MOV:G.B R0, @H'F104 ; refs H'F104 in program_or_external; cycles=7 +39D8: 15 F7 18 80 MOV:G.B @H'F718, R0 ; refs H'F718 in on_chip_ram; cycles=7 +39DC: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=7 +39E0: 15 F7 10 50 AND.B @H'F710, R0 ; refs H'F710 in on_chip_ram; cycles=7 +39E4: 15 F1 05 90 MOV:G.B R0, @H'F105 ; refs H'F105 in program_or_external; cycles=7 +39E8: 15 F7 02 80 MOV:G.B @H'F702, R0 ; refs H'F702 in on_chip_ram; cycles=7 +39EC: 15 F1 09 90 MOV:G.B R0, @H'F109 ; refs H'F109 in program_or_external; cycles=7 +39F0: 15 F7 03 80 MOV:G.B @H'F703, R0 ; refs H'F703 in on_chip_ram; cycles=7 +39F4: 15 F1 0A 90 MOV:G.B R0, @H'F10A ; refs H'F10A in program_or_external; cycles=7 +39F8: 15 F7 04 80 MOV:G.B @H'F704, R0 ; refs H'F704 in on_chip_ram; cycles=7 +39FC: 15 F1 0B 90 MOV:G.B R0, @H'F10B ; refs H'F10B in program_or_external; cycles=7 +3A00: 15 F7 05 80 MOV:G.B @H'F705, R0 ; refs H'F705 in on_chip_ram; cycles=7 +3A04: 15 F1 0C 90 MOV:G.B R0, @H'F10C ; refs H'F10C in program_or_external; cycles=7 +3A08: 15 F7 00 80 MOV:G.B @H'F700, R0 ; refs H'F700 in on_chip_ram; cycles=7 +3A0C: 15 F1 0D 90 MOV:G.B R0, @H'F10D ; refs H'F10D in program_or_external; cycles=7 +3A10: 15 F7 01 80 MOV:G.B @H'F701, R0 ; refs H'F701 in on_chip_ram; cycles=7 +3A14: 15 F1 0E 90 MOV:G.B R0, @H'F10E ; refs H'F10E in program_or_external; cycles=7 +3A18: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=7 +3A1C: A0 15 NOT.B R0 ; cycles=2 +3A1E: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3A21: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3A24: 15 F1 0F 90 MOV:G.B R0, @H'F10F ; refs H'F10F in program_or_external; cycles=7 +3A28: 15 F7 20 06 03 MOV:G.B #H'03, @H'F720 ; refs H'F720 in on_chip_ram; cycles=9 loc_3A2D: -3A2D: 19 RTS +3A2D: 19 RTS ; cycles=13 loc_3A2E: -3A2E: 15 F7 21 16 TST.B @H'F721 ; refs H'F721 in on_chip_ram -3A32: 36 00 91 BNE loc_3AC6 -3A35: 15 F0 01 06 A0 MOV:G.B #H'A0, @H'F001 ; refs H'F001 in program_or_external -3A3A: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs H'F000 in program_or_external -3A3E: 37 00 85 BEQ loc_3AC6 -3A41: 15 F7 1F 80 MOV:G.B @H'F71F, R0 ; refs H'F71F in on_chip_ram -3A45: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -3A49: 15 F7 17 50 AND.B @H'F717, R0 ; refs H'F717 in on_chip_ram -3A4D: 15 F0 02 90 MOV:G.B R0, @H'F002 ; refs H'F002 in program_or_external -3A51: 15 F7 1E 80 MOV:G.B @H'F71E, R0 ; refs H'F71E in on_chip_ram -3A55: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -3A59: 15 F7 16 50 AND.B @H'F716, R0 ; refs H'F716 in on_chip_ram -3A5D: 15 F0 03 90 MOV:G.B R0, @H'F003 ; refs H'F003 in program_or_external -3A61: 15 F7 1D 80 MOV:G.B @H'F71D, R0 ; refs H'F71D in on_chip_ram -3A65: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -3A69: 15 F7 15 50 AND.B @H'F715, R0 ; refs H'F715 in on_chip_ram -3A6D: 15 F0 04 90 MOV:G.B R0, @H'F004 ; refs H'F004 in program_or_external -3A71: 15 F7 1C 80 MOV:G.B @H'F71C, R0 ; refs H'F71C in on_chip_ram -3A75: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram -3A79: 15 F7 14 50 AND.B @H'F714, R0 ; refs H'F714 in on_chip_ram -3A7D: 15 F0 05 90 MOV:G.B R0, @H'F005 ; refs H'F005 in program_or_external -3A81: 15 F7 08 80 MOV:G.B @H'F708, R0 ; refs H'F708 in on_chip_ram -3A85: 15 F0 09 90 MOV:G.B R0, @H'F009 ; refs H'F009 in program_or_external -3A89: 15 F7 09 80 MOV:G.B @H'F709, R0 ; refs H'F709 in on_chip_ram -3A8D: 15 F0 0A 90 MOV:G.B R0, @H'F00A ; refs H'F00A in program_or_external -3A91: 15 F7 0A 80 MOV:G.B @H'F70A, R0 ; refs H'F70A in on_chip_ram -3A95: 15 F0 0B 90 MOV:G.B R0, @H'F00B ; refs H'F00B in program_or_external -3A99: 15 F7 0B 80 MOV:G.B @H'F70B, R0 ; refs H'F70B in on_chip_ram -3A9D: 15 F0 0C 90 MOV:G.B R0, @H'F00C ; refs H'F00C in program_or_external -3AA1: 15 F7 06 80 MOV:G.B @H'F706, R0 ; refs H'F706 in on_chip_ram -3AA5: 15 F0 0D 90 MOV:G.B R0, @H'F00D ; refs H'F00D in program_or_external -3AA9: 15 F7 07 80 MOV:G.B @H'F707, R0 ; refs H'F707 in on_chip_ram -3AAD: 15 F0 0E 90 MOV:G.B R0, @H'F00E ; refs H'F00E in program_or_external -3AB1: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field -3AB5: A0 15 NOT.B R0 -3AB7: 04 03 50 AND.B #H'03, R0 -3ABA: 04 A0 40 OR.B #H'A0, R0 -3ABD: 15 F0 0F 90 MOV:G.B R0, @H'F00F ; refs H'F00F in program_or_external -3AC1: 15 F7 21 06 03 MOV:G.B #H'03, @H'F721 ; refs H'F721 in on_chip_ram +3A2E: 15 F7 21 16 TST.B @H'F721 ; refs H'F721 in on_chip_ram; cycles=7 +3A32: 36 00 91 BNE loc_3AC6 ; cycles=3/7 nt/t +3A35: 15 F0 01 06 A0 MOV:G.B #H'A0, @H'F001 ; refs H'F001 in program_or_external; cycles=9 +3A3A: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs H'F000 in program_or_external; cycles=7 +3A3E: 37 00 85 BEQ loc_3AC6 ; cycles=3/7 nt/t +3A41: 15 F7 1F 80 MOV:G.B @H'F71F, R0 ; refs H'F71F in on_chip_ram; cycles=6 +3A45: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=6 +3A49: 15 F7 17 50 AND.B @H'F717, R0 ; refs H'F717 in on_chip_ram; cycles=6 +3A4D: 15 F0 02 90 MOV:G.B R0, @H'F002 ; refs H'F002 in program_or_external; cycles=6 +3A51: 15 F7 1E 80 MOV:G.B @H'F71E, R0 ; refs H'F71E in on_chip_ram; cycles=6 +3A55: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=6 +3A59: 15 F7 16 50 AND.B @H'F716, R0 ; refs H'F716 in on_chip_ram; cycles=6 +3A5D: 15 F0 03 90 MOV:G.B R0, @H'F003 ; refs H'F003 in program_or_external; cycles=6 +3A61: 15 F7 1D 80 MOV:G.B @H'F71D, R0 ; refs H'F71D in on_chip_ram; cycles=6 +3A65: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=6 +3A69: 15 F7 15 50 AND.B @H'F715, R0 ; refs H'F715 in on_chip_ram; cycles=6 +3A6D: 15 F0 04 90 MOV:G.B R0, @H'F004 ; refs H'F004 in program_or_external; cycles=6 +3A71: 15 F7 1C 80 MOV:G.B @H'F71C, R0 ; refs H'F71C in on_chip_ram; cycles=6 +3A75: 15 F7 23 40 OR.B @H'F723, R0 ; refs H'F723 in on_chip_ram; cycles=6 +3A79: 15 F7 14 50 AND.B @H'F714, R0 ; refs H'F714 in on_chip_ram; cycles=6 +3A7D: 15 F0 05 90 MOV:G.B R0, @H'F005 ; refs H'F005 in program_or_external; cycles=6 +3A81: 15 F7 08 80 MOV:G.B @H'F708, R0 ; refs H'F708 in on_chip_ram; cycles=6 +3A85: 15 F0 09 90 MOV:G.B R0, @H'F009 ; refs H'F009 in program_or_external; cycles=6 +3A89: 15 F7 09 80 MOV:G.B @H'F709, R0 ; refs H'F709 in on_chip_ram; cycles=6 +3A8D: 15 F0 0A 90 MOV:G.B R0, @H'F00A ; refs H'F00A in program_or_external; cycles=6 +3A91: 15 F7 0A 80 MOV:G.B @H'F70A, R0 ; refs H'F70A in on_chip_ram; cycles=6 +3A95: 15 F0 0B 90 MOV:G.B R0, @H'F00B ; refs H'F00B in program_or_external; cycles=6 +3A99: 15 F7 0B 80 MOV:G.B @H'F70B, R0 ; refs H'F70B in on_chip_ram; cycles=6 +3A9D: 15 F0 0C 90 MOV:G.B R0, @H'F00C ; refs H'F00C in program_or_external; cycles=6 +3AA1: 15 F7 06 80 MOV:G.B @H'F706, R0 ; refs H'F706 in on_chip_ram; cycles=6 +3AA5: 15 F0 0D 90 MOV:G.B R0, @H'F00D ; refs H'F00D in program_or_external; cycles=6 +3AA9: 15 F7 07 80 MOV:G.B @H'F707, R0 ; refs H'F707 in on_chip_ram; cycles=6 +3AAD: 15 F0 0E 90 MOV:G.B R0, @H'F00E ; refs H'F00E in program_or_external; cycles=6 +3AB1: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=6 +3AB5: A0 15 NOT.B R0 ; cycles=2 +3AB7: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3ABA: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3ABD: 15 F0 0F 90 MOV:G.B R0, @H'F00F ; refs H'F00F in program_or_external; cycles=6 +3AC1: 15 F7 21 06 03 MOV:G.B #H'03, @H'F721 ; refs H'F721 in on_chip_ram; cycles=9 loc_3AC6: -3AC6: 19 RTS +3AC6: 19 RTS ; cycles=12 vec_irq4_3AC7: -3AC7: BF 90 MOV:G.W R0, @-R7 -3AC9: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs H'F100 in program_or_external -3ACD: 36 01 5D BNE loc_3C2D -3AD0: 15 F1 0F 80 MOV:G.B @H'F10F, R0 ; refs H'F10F in program_or_external -3AD4: 40 A9 CMP:E #H'A9, R0 -3AD6: 27 08 BEQ loc_3AE0 -3AD8: 40 A8 CMP:E #H'A8, R0 -3ADA: 37 00 85 BEQ loc_3B62 -3ADD: 30 01 4D BRA loc_3C2D +3AC7: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +3AC9: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs H'F100 in program_or_external; cycles=6 +3ACD: 36 01 5D BNE loc_3C2D ; cycles=3/8 nt/t +3AD0: 15 F1 0F 80 MOV:G.B @H'F10F, R0 ; refs H'F10F in program_or_external; cycles=7 +3AD4: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3AD6: 27 08 BEQ loc_3AE0 ; cycles=3/7 nt/t +3AD8: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3ADA: 37 00 85 BEQ loc_3B62 ; cycles=3/7 nt/t +3ADD: 30 01 4D BRA loc_3C2D ; cycles=8 loc_3AE0: -3AE0: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs H'F6F0 in on_chip_ram -3AE4: 04 C0 50 AND.B #H'C0, R0 -3AE7: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3AEB: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs H'F10C in program_or_external -3AEF: 1D F6 9A 70 CMP:G.W @H'F69A, R0 ; refs H'F69A in on_chip_ram -3AF3: 27 08 BEQ loc_3AFD -3AF5: 15 F6 F0 C5 BSET.B #5, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3AF9: 1D F6 9A 90 MOV:G.W R0, @H'F69A ; refs H'F69A in on_chip_ram +3AE0: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs H'F6F0 in on_chip_ram; cycles=7 +3AE4: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3AE7: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=6 +3AEB: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs H'F10C in program_or_external; cycles=6 +3AEF: 1D F6 9A 70 CMP:G.W @H'F69A, R0 ; refs H'F69A in on_chip_ram; cycles=6 +3AF3: 27 08 BEQ loc_3AFD ; cycles=3/8 nt/t +3AF5: 15 F6 F0 C5 BSET.B #5, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3AF9: 1D F6 9A 90 MOV:G.W R0, @H'F69A ; refs H'F69A in on_chip_ram; cycles=6 loc_3AFD: -3AFD: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs H'F10A in program_or_external -3B01: 1D F6 98 70 CMP:G.W @H'F698, R0 ; refs H'F698 in on_chip_ram -3B05: 27 08 BEQ loc_3B0F -3B07: 15 F6 F0 C4 BSET.B #4, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B0B: 1D F6 98 90 MOV:G.W R0, @H'F698 ; refs H'F698 in on_chip_ram +3AFD: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs H'F10A in program_or_external; cycles=6 +3B01: 1D F6 98 70 CMP:G.W @H'F698, R0 ; refs H'F698 in on_chip_ram; cycles=6 +3B05: 27 08 BEQ loc_3B0F ; cycles=3/8 nt/t +3B07: 15 F6 F0 C4 BSET.B #4, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B0B: 1D F6 98 90 MOV:G.W R0, @H'F698 ; refs H'F698 in on_chip_ram; cycles=6 loc_3B0F: -3B0F: 1D F1 08 80 MOV:G.W @H'F108, R0 ; refs H'F108 in program_or_external -3B13: 1D F6 96 70 CMP:G.W @H'F696, R0 ; refs H'F696 in on_chip_ram -3B17: 27 08 BEQ loc_3B21 -3B19: 15 F6 F0 C3 BSET.B #3, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B1D: 1D F6 96 90 MOV:G.W R0, @H'F696 ; refs H'F696 in on_chip_ram +3B0F: 1D F1 08 80 MOV:G.W @H'F108, R0 ; refs H'F108 in program_or_external; cycles=6 +3B13: 1D F6 96 70 CMP:G.W @H'F696, R0 ; refs H'F696 in on_chip_ram; cycles=6 +3B17: 27 08 BEQ loc_3B21 ; cycles=3/8 nt/t +3B19: 15 F6 F0 C3 BSET.B #3, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B1D: 1D F6 96 90 MOV:G.W R0, @H'F696 ; refs H'F696 in on_chip_ram; cycles=6 loc_3B21: -3B21: 1D F1 06 80 MOV:G.W @H'F106, R0 ; refs H'F106 in program_or_external -3B25: 1D F6 94 70 CMP:G.W @H'F694, R0 ; refs H'F694 in on_chip_ram -3B29: 27 08 BEQ loc_3B33 -3B2B: 15 F6 F0 C2 BSET.B #2, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B2F: 1D F6 94 90 MOV:G.W R0, @H'F694 ; refs H'F694 in on_chip_ram +3B21: 1D F1 06 80 MOV:G.W @H'F106, R0 ; refs H'F106 in program_or_external; cycles=6 +3B25: 1D F6 94 70 CMP:G.W @H'F694, R0 ; refs H'F694 in on_chip_ram; cycles=6 +3B29: 27 08 BEQ loc_3B33 ; cycles=3/8 nt/t +3B2B: 15 F6 F0 C2 BSET.B #2, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B2F: 1D F6 94 90 MOV:G.W R0, @H'F694 ; refs H'F694 in on_chip_ram; cycles=6 loc_3B33: -3B33: 1D F1 04 80 MOV:G.W @H'F104, R0 ; refs H'F104 in program_or_external -3B37: 1D F6 92 70 CMP:G.W @H'F692, R0 ; refs H'F692 in on_chip_ram -3B3B: 27 08 BEQ loc_3B45 -3B3D: 15 F6 F0 C1 BSET.B #1, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B41: 1D F6 92 90 MOV:G.W R0, @H'F692 ; refs H'F692 in on_chip_ram +3B33: 1D F1 04 80 MOV:G.W @H'F104, R0 ; refs H'F104 in program_or_external; cycles=6 +3B37: 1D F6 92 70 CMP:G.W @H'F692, R0 ; refs H'F692 in on_chip_ram; cycles=6 +3B3B: 27 08 BEQ loc_3B45 ; cycles=3/8 nt/t +3B3D: 15 F6 F0 C1 BSET.B #1, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B41: 1D F6 92 90 MOV:G.W R0, @H'F692 ; refs H'F692 in on_chip_ram; cycles=6 loc_3B45: -3B45: 1D F1 02 80 MOV:G.W @H'F102, R0 ; refs H'F102 in program_or_external -3B49: 1D F6 90 70 CMP:G.W @H'F690, R0 ; refs H'F690 in on_chip_ram -3B4D: 27 08 BEQ loc_3B57 -3B4F: 15 F6 F0 C0 BSET.B #0, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B53: 1D F6 90 90 MOV:G.W R0, @H'F690 ; refs H'F690 in on_chip_ram +3B45: 1D F1 02 80 MOV:G.W @H'F102, R0 ; refs H'F102 in program_or_external; cycles=6 +3B49: 1D F6 90 70 CMP:G.W @H'F690, R0 ; refs H'F690 in on_chip_ram; cycles=6 +3B4D: 27 08 BEQ loc_3B57 ; cycles=3/8 nt/t +3B4F: 15 F6 F0 C0 BSET.B #0, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B53: 1D F6 90 90 MOV:G.W R0, @H'F690 ; refs H'F690 in on_chip_ram; cycles=6 loc_3B57: -3B57: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs H'F101 in program_or_external -3B5B: 15 F7 20 D0 BCLR.B #0, @H'F720 ; refs H'F720 in on_chip_ram -3B5F: 30 00 CB BRA loc_3C2D +3B57: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs H'F101 in program_or_external; cycles=6 +3B5B: 15 F7 20 D0 BCLR.B #0, @H'F720 ; refs H'F720 in on_chip_ram; cycles=8 +3B5F: 30 00 CB BRA loc_3C2D ; cycles=8 loc_3B62: -3B62: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs H'F6F0 in on_chip_ram -3B66: 04 3F 50 AND.B #H'3F, R0 -3B69: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B6D: 15 F6 F2 13 CLR.B @H'F6F2 ; refs H'F6F2 in on_chip_ram -3B71: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs H'F10C in program_or_external -3B75: 1D F6 9E 70 CMP:G.W @H'F69E, R0 ; refs H'F69E in on_chip_ram -3B79: 27 08 BEQ loc_3B83 -3B7B: 15 F6 F0 C7 BSET.B #7, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B7F: 1D F6 9E 90 MOV:G.W R0, @H'F69E ; refs H'F69E in on_chip_ram +3B62: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs H'F6F0 in on_chip_ram; cycles=7 +3B66: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3B69: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=6 +3B6D: 15 F6 F2 13 CLR.B @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3B71: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs H'F10C in program_or_external; cycles=6 +3B75: 1D F6 9E 70 CMP:G.W @H'F69E, R0 ; refs H'F69E in on_chip_ram; cycles=6 +3B79: 27 08 BEQ loc_3B83 ; cycles=3/8 nt/t +3B7B: 15 F6 F0 C7 BSET.B #7, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B7F: 1D F6 9E 90 MOV:G.W R0, @H'F69E ; refs H'F69E in on_chip_ram; cycles=6 loc_3B83: -3B83: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs H'F10A in program_or_external -3B87: 1D F6 9C 70 CMP:G.W @H'F69C, R0 ; refs H'F69C in on_chip_ram -3B8B: 27 08 BEQ loc_3B95 -3B8D: 15 F6 F0 C6 BSET.B #6, @H'F6F0 ; refs H'F6F0 in on_chip_ram -3B91: 1D F6 9C 90 MOV:G.W R0, @H'F69C ; refs H'F69C in on_chip_ram +3B83: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs H'F10A in program_or_external; cycles=6 +3B87: 1D F6 9C 70 CMP:G.W @H'F69C, R0 ; refs H'F69C in on_chip_ram; cycles=6 +3B8B: 27 08 BEQ loc_3B95 ; cycles=3/8 nt/t +3B8D: 15 F6 F0 C6 BSET.B #6, @H'F6F0 ; refs H'F6F0 in on_chip_ram; cycles=8 +3B91: 1D F6 9C 90 MOV:G.W R0, @H'F69C ; refs H'F69C in on_chip_ram; cycles=6 loc_3B95: -3B95: 15 F1 09 80 MOV:G.B @H'F109, R0 ; refs H'F109 in program_or_external -3B99: 15 F6 D0 70 CMP:G.B @H'F6D0, R0 ; refs H'F6D0 in on_chip_ram -3B9D: 27 08 BEQ loc_3BA7 -3B9F: 15 F6 F2 C0 BSET.B #0, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3BA3: 15 F6 D0 90 MOV:G.B R0, @H'F6D0 ; refs H'F6D0 in on_chip_ram +3B95: 15 F1 09 80 MOV:G.B @H'F109, R0 ; refs H'F109 in program_or_external; cycles=6 +3B99: 15 F6 D0 70 CMP:G.B @H'F6D0, R0 ; refs H'F6D0 in on_chip_ram; cycles=6 +3B9D: 27 08 BEQ loc_3BA7 ; cycles=3/8 nt/t +3B9F: 15 F6 F2 C0 BSET.B #0, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3BA3: 15 F6 D0 90 MOV:G.B R0, @H'F6D0 ; refs H'F6D0 in on_chip_ram; cycles=6 loc_3BA7: -3BA7: 15 F1 08 80 MOV:G.B @H'F108, R0 ; refs H'F108 in program_or_external -3BAB: 15 F6 D1 70 CMP:G.B @H'F6D1, R0 ; refs H'F6D1 in on_chip_ram -3BAF: 27 08 BEQ loc_3BB9 -3BB1: 15 F6 F2 C1 BSET.B #1, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3BB5: 15 F6 D1 90 MOV:G.B R0, @H'F6D1 ; refs H'F6D1 in on_chip_ram +3BA7: 15 F1 08 80 MOV:G.B @H'F108, R0 ; refs H'F108 in program_or_external; cycles=6 +3BAB: 15 F6 D1 70 CMP:G.B @H'F6D1, R0 ; refs H'F6D1 in on_chip_ram; cycles=6 +3BAF: 27 08 BEQ loc_3BB9 ; cycles=3/8 nt/t +3BB1: 15 F6 F2 C1 BSET.B #1, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3BB5: 15 F6 D1 90 MOV:G.B R0, @H'F6D1 ; refs H'F6D1 in on_chip_ram; cycles=6 loc_3BB9: -3BB9: 15 F1 07 80 MOV:G.B @H'F107, R0 ; refs H'F107 in program_or_external -3BBD: 15 F6 D2 70 CMP:G.B @H'F6D2, R0 ; refs H'F6D2 in on_chip_ram -3BC1: 27 08 BEQ loc_3BCB -3BC3: 15 F6 F2 C2 BSET.B #2, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3BC7: 15 F6 D2 90 MOV:G.B R0, @H'F6D2 ; refs H'F6D2 in on_chip_ram +3BB9: 15 F1 07 80 MOV:G.B @H'F107, R0 ; refs H'F107 in program_or_external; cycles=6 +3BBD: 15 F6 D2 70 CMP:G.B @H'F6D2, R0 ; refs H'F6D2 in on_chip_ram; cycles=6 +3BC1: 27 08 BEQ loc_3BCB ; cycles=3/8 nt/t +3BC3: 15 F6 F2 C2 BSET.B #2, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3BC7: 15 F6 D2 90 MOV:G.B R0, @H'F6D2 ; refs H'F6D2 in on_chip_ram; cycles=6 loc_3BCB: -3BCB: 15 F1 06 80 MOV:G.B @H'F106, R0 ; refs H'F106 in program_or_external -3BCF: 15 F6 D3 70 CMP:G.B @H'F6D3, R0 ; refs H'F6D3 in on_chip_ram -3BD3: 27 08 BEQ loc_3BDD -3BD5: 15 F6 F2 C3 BSET.B #3, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3BD9: 15 F6 D3 90 MOV:G.B R0, @H'F6D3 ; refs H'F6D3 in on_chip_ram +3BCB: 15 F1 06 80 MOV:G.B @H'F106, R0 ; refs H'F106 in program_or_external; cycles=6 +3BCF: 15 F6 D3 70 CMP:G.B @H'F6D3, R0 ; refs H'F6D3 in on_chip_ram; cycles=6 +3BD3: 27 08 BEQ loc_3BDD ; cycles=3/8 nt/t +3BD5: 15 F6 F2 C3 BSET.B #3, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3BD9: 15 F6 D3 90 MOV:G.B R0, @H'F6D3 ; refs H'F6D3 in on_chip_ram; cycles=6 loc_3BDD: -3BDD: 15 F1 05 80 MOV:G.B @H'F105, R0 ; refs H'F105 in program_or_external -3BE1: 15 F6 D4 70 CMP:G.B @H'F6D4, R0 ; refs H'F6D4 in on_chip_ram -3BE5: 27 08 BEQ loc_3BEF -3BE7: 15 F6 F2 C4 BSET.B #4, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3BEB: 15 F6 D4 90 MOV:G.B R0, @H'F6D4 ; refs H'F6D4 in on_chip_ram +3BDD: 15 F1 05 80 MOV:G.B @H'F105, R0 ; refs H'F105 in program_or_external; cycles=6 +3BE1: 15 F6 D4 70 CMP:G.B @H'F6D4, R0 ; refs H'F6D4 in on_chip_ram; cycles=6 +3BE5: 27 08 BEQ loc_3BEF ; cycles=3/8 nt/t +3BE7: 15 F6 F2 C4 BSET.B #4, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3BEB: 15 F6 D4 90 MOV:G.B R0, @H'F6D4 ; refs H'F6D4 in on_chip_ram; cycles=6 loc_3BEF: -3BEF: 15 F1 04 80 MOV:G.B @H'F104, R0 ; refs H'F104 in program_or_external -3BF3: 15 F6 D5 70 CMP:G.B @H'F6D5, R0 ; refs H'F6D5 in on_chip_ram -3BF7: 27 08 BEQ loc_3C01 -3BF9: 15 F6 F2 C5 BSET.B #5, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3BFD: 15 F6 D5 90 MOV:G.B R0, @H'F6D5 ; refs H'F6D5 in on_chip_ram +3BEF: 15 F1 04 80 MOV:G.B @H'F104, R0 ; refs H'F104 in program_or_external; cycles=6 +3BF3: 15 F6 D5 70 CMP:G.B @H'F6D5, R0 ; refs H'F6D5 in on_chip_ram; cycles=6 +3BF7: 27 08 BEQ loc_3C01 ; cycles=3/8 nt/t +3BF9: 15 F6 F2 C5 BSET.B #5, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3BFD: 15 F6 D5 90 MOV:G.B R0, @H'F6D5 ; refs H'F6D5 in on_chip_ram; cycles=6 loc_3C01: -3C01: 15 F1 03 80 MOV:G.B @H'F103, R0 ; refs H'F103 in program_or_external -3C05: 15 F6 D6 70 CMP:G.B @H'F6D6, R0 ; refs H'F6D6 in on_chip_ram -3C09: 27 08 BEQ loc_3C13 -3C0B: 15 F6 F2 C6 BSET.B #6, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3C0F: 15 F6 D6 90 MOV:G.B R0, @H'F6D6 ; refs H'F6D6 in on_chip_ram +3C01: 15 F1 03 80 MOV:G.B @H'F103, R0 ; refs H'F103 in program_or_external; cycles=6 +3C05: 15 F6 D6 70 CMP:G.B @H'F6D6, R0 ; refs H'F6D6 in on_chip_ram; cycles=6 +3C09: 27 08 BEQ loc_3C13 ; cycles=3/8 nt/t +3C0B: 15 F6 F2 C6 BSET.B #6, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3C0F: 15 F6 D6 90 MOV:G.B R0, @H'F6D6 ; refs H'F6D6 in on_chip_ram; cycles=6 loc_3C13: -3C13: 15 F1 02 80 MOV:G.B @H'F102, R0 ; refs H'F102 in program_or_external -3C17: 15 F6 D7 70 CMP:G.B @H'F6D7, R0 ; refs H'F6D7 in on_chip_ram -3C1B: 27 08 BEQ loc_3C25 -3C1D: 15 F6 F2 C7 BSET.B #7, @H'F6F2 ; refs H'F6F2 in on_chip_ram -3C21: 15 F6 D7 90 MOV:G.B R0, @H'F6D7 ; refs H'F6D7 in on_chip_ram +3C13: 15 F1 02 80 MOV:G.B @H'F102, R0 ; refs H'F102 in program_or_external; cycles=6 +3C17: 15 F6 D7 70 CMP:G.B @H'F6D7, R0 ; refs H'F6D7 in on_chip_ram; cycles=6 +3C1B: 27 08 BEQ loc_3C25 ; cycles=3/8 nt/t +3C1D: 15 F6 F2 C7 BSET.B #7, @H'F6F2 ; refs H'F6F2 in on_chip_ram; cycles=8 +3C21: 15 F6 D7 90 MOV:G.B R0, @H'F6D7 ; refs H'F6D7 in on_chip_ram; cycles=6 loc_3C25: -3C25: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs H'F101 in program_or_external -3C29: 15 F7 20 D1 BCLR.B #1, @H'F720 ; refs H'F720 in on_chip_ram +3C25: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs H'F101 in program_or_external; cycles=6 +3C29: 15 F7 20 D1 BCLR.B #1, @H'F720 ; refs H'F720 in on_chip_ram; cycles=8 loc_3C2D: -3C2D: CF 80 MOV:G.W @R7+, R0 -3C2F: 0A RTE +3C2D: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +3C2F: 0A RTE ; cycles=14 vec_irq3_3C30: -3C30: BF 90 MOV:G.W R0, @-R7 -3C32: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs H'F000 in program_or_external -3C36: 36 01 5D BNE loc_3D96 -3C39: 15 F0 0F 80 MOV:G.B @H'F00F, R0 ; refs H'F00F in program_or_external -3C3D: 40 A9 CMP:E #H'A9, R0 -3C3F: 27 08 BEQ loc_3C49 -3C41: 40 A8 CMP:E #H'A8, R0 -3C43: 37 00 85 BEQ loc_3CCB -3C46: 30 01 4D BRA loc_3D96 +3C30: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +3C32: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs H'F000 in program_or_external; cycles=7 +3C36: 36 01 5D BNE loc_3D96 ; cycles=3/7 nt/t +3C39: 15 F0 0F 80 MOV:G.B @H'F00F, R0 ; refs H'F00F in program_or_external; cycles=6 +3C3D: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3C3F: 27 08 BEQ loc_3C49 ; cycles=3/8 nt/t +3C41: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3C43: 37 00 85 BEQ loc_3CCB ; cycles=3/8 nt/t +3C46: 30 01 4D BRA loc_3D96 ; cycles=7 loc_3C49: -3C49: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs H'F6F1 in on_chip_ram -3C4D: 04 C0 50 AND.B #H'C0, R0 -3C50: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3C54: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs H'F00C in program_or_external -3C58: 1D F6 AA 70 CMP:G.W @H'F6AA, R0 ; refs H'F6AA in on_chip_ram -3C5C: 27 08 BEQ loc_3C66 -3C5E: 15 F6 F1 C5 BSET.B #5, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3C62: 1D F6 AA 90 MOV:G.W R0, @H'F6AA ; refs H'F6AA in on_chip_ram +3C49: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs H'F6F1 in on_chip_ram; cycles=6 +3C4D: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3C50: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=7 +3C54: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs H'F00C in program_or_external; cycles=7 +3C58: 1D F6 AA 70 CMP:G.W @H'F6AA, R0 ; refs H'F6AA in on_chip_ram; cycles=7 +3C5C: 27 08 BEQ loc_3C66 ; cycles=3/7 nt/t +3C5E: 15 F6 F1 C5 BSET.B #5, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3C62: 1D F6 AA 90 MOV:G.W R0, @H'F6AA ; refs H'F6AA in on_chip_ram; cycles=7 loc_3C66: -3C66: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs H'F00A in program_or_external -3C6A: 1D F6 A8 70 CMP:G.W @H'F6A8, R0 ; refs H'F6A8 in on_chip_ram -3C6E: 27 08 BEQ loc_3C78 -3C70: 15 F6 F1 C4 BSET.B #4, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3C74: 1D F6 A8 90 MOV:G.W R0, @H'F6A8 ; refs H'F6A8 in on_chip_ram +3C66: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs H'F00A in program_or_external; cycles=7 +3C6A: 1D F6 A8 70 CMP:G.W @H'F6A8, R0 ; refs H'F6A8 in on_chip_ram; cycles=7 +3C6E: 27 08 BEQ loc_3C78 ; cycles=3/7 nt/t +3C70: 15 F6 F1 C4 BSET.B #4, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3C74: 1D F6 A8 90 MOV:G.W R0, @H'F6A8 ; refs H'F6A8 in on_chip_ram; cycles=7 loc_3C78: -3C78: 1D F0 08 80 MOV:G.W @H'F008, R0 ; refs H'F008 in program_or_external -3C7C: 1D F6 A6 70 CMP:G.W @H'F6A6, R0 ; refs H'F6A6 in on_chip_ram -3C80: 27 08 BEQ loc_3C8A -3C82: 15 F6 F1 C3 BSET.B #3, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3C86: 1D F6 A6 90 MOV:G.W R0, @H'F6A6 ; refs H'F6A6 in on_chip_ram +3C78: 1D F0 08 80 MOV:G.W @H'F008, R0 ; refs H'F008 in program_or_external; cycles=7 +3C7C: 1D F6 A6 70 CMP:G.W @H'F6A6, R0 ; refs H'F6A6 in on_chip_ram; cycles=7 +3C80: 27 08 BEQ loc_3C8A ; cycles=3/7 nt/t +3C82: 15 F6 F1 C3 BSET.B #3, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3C86: 1D F6 A6 90 MOV:G.W R0, @H'F6A6 ; refs H'F6A6 in on_chip_ram; cycles=7 loc_3C8A: -3C8A: 1D F0 06 80 MOV:G.W @H'F006, R0 ; refs H'F006 in program_or_external -3C8E: 1D F6 A4 70 CMP:G.W @H'F6A4, R0 ; refs H'F6A4 in on_chip_ram -3C92: 27 08 BEQ loc_3C9C -3C94: 15 F6 F1 C2 BSET.B #2, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3C98: 1D F6 A4 90 MOV:G.W R0, @H'F6A4 ; refs H'F6A4 in on_chip_ram +3C8A: 1D F0 06 80 MOV:G.W @H'F006, R0 ; refs H'F006 in program_or_external; cycles=7 +3C8E: 1D F6 A4 70 CMP:G.W @H'F6A4, R0 ; refs H'F6A4 in on_chip_ram; cycles=7 +3C92: 27 08 BEQ loc_3C9C ; cycles=3/7 nt/t +3C94: 15 F6 F1 C2 BSET.B #2, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3C98: 1D F6 A4 90 MOV:G.W R0, @H'F6A4 ; refs H'F6A4 in on_chip_ram; cycles=7 loc_3C9C: -3C9C: 1D F0 04 80 MOV:G.W @H'F004, R0 ; refs H'F004 in program_or_external -3CA0: 1D F6 A2 70 CMP:G.W @H'F6A2, R0 ; refs H'F6A2 in on_chip_ram -3CA4: 27 08 BEQ loc_3CAE -3CA6: 15 F6 F1 C1 BSET.B #1, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3CAA: 1D F6 A2 90 MOV:G.W R0, @H'F6A2 ; refs H'F6A2 in on_chip_ram +3C9C: 1D F0 04 80 MOV:G.W @H'F004, R0 ; refs H'F004 in program_or_external; cycles=7 +3CA0: 1D F6 A2 70 CMP:G.W @H'F6A2, R0 ; refs H'F6A2 in on_chip_ram; cycles=7 +3CA4: 27 08 BEQ loc_3CAE ; cycles=3/7 nt/t +3CA6: 15 F6 F1 C1 BSET.B #1, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3CAA: 1D F6 A2 90 MOV:G.W R0, @H'F6A2 ; refs H'F6A2 in on_chip_ram; cycles=7 loc_3CAE: -3CAE: 1D F0 02 80 MOV:G.W @H'F002, R0 ; refs H'F002 in program_or_external -3CB2: 1D F6 A0 70 CMP:G.W @H'F6A0, R0 ; refs H'F6A0 in on_chip_ram -3CB6: 27 08 BEQ loc_3CC0 -3CB8: 15 F6 F1 C0 BSET.B #0, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3CBC: 1D F6 A0 90 MOV:G.W R0, @H'F6A0 ; refs H'F6A0 in on_chip_ram +3CAE: 1D F0 02 80 MOV:G.W @H'F002, R0 ; refs H'F002 in program_or_external; cycles=7 +3CB2: 1D F6 A0 70 CMP:G.W @H'F6A0, R0 ; refs H'F6A0 in on_chip_ram; cycles=7 +3CB6: 27 08 BEQ loc_3CC0 ; cycles=3/7 nt/t +3CB8: 15 F6 F1 C0 BSET.B #0, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3CBC: 1D F6 A0 90 MOV:G.W R0, @H'F6A0 ; refs H'F6A0 in on_chip_ram; cycles=7 loc_3CC0: -3CC0: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs H'F001 in program_or_external -3CC4: 15 F7 21 D0 BCLR.B #0, @H'F721 ; refs H'F721 in on_chip_ram -3CC8: 30 00 CB BRA loc_3D96 +3CC0: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs H'F001 in program_or_external; cycles=7 +3CC4: 15 F7 21 D0 BCLR.B #0, @H'F721 ; refs H'F721 in on_chip_ram; cycles=9 +3CC8: 30 00 CB BRA loc_3D96 ; cycles=7 loc_3CCB: -3CCB: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs H'F6F1 in on_chip_ram -3CCF: 04 3F 50 AND.B #H'3F, R0 -3CD2: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3CD6: 15 F6 F3 13 CLR.B @H'F6F3 ; refs H'F6F3 in on_chip_ram -3CDA: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs H'F00C in program_or_external -3CDE: 1D F6 AE 70 CMP:G.W @H'F6AE, R0 ; refs H'F6AE in on_chip_ram -3CE2: 27 08 BEQ loc_3CEC -3CE4: 15 F6 F1 C7 BSET.B #7, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3CE8: 1D F6 AE 90 MOV:G.W R0, @H'F6AE ; refs H'F6AE in on_chip_ram +3CCB: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs H'F6F1 in on_chip_ram; cycles=6 +3CCF: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3CD2: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=7 +3CD6: 15 F6 F3 13 CLR.B @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3CDA: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs H'F00C in program_or_external; cycles=7 +3CDE: 1D F6 AE 70 CMP:G.W @H'F6AE, R0 ; refs H'F6AE in on_chip_ram; cycles=7 +3CE2: 27 08 BEQ loc_3CEC ; cycles=3/7 nt/t +3CE4: 15 F6 F1 C7 BSET.B #7, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3CE8: 1D F6 AE 90 MOV:G.W R0, @H'F6AE ; refs H'F6AE in on_chip_ram; cycles=7 loc_3CEC: -3CEC: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs H'F00A in program_or_external -3CF0: 1D F6 AC 70 CMP:G.W @H'F6AC, R0 ; refs H'F6AC in on_chip_ram -3CF4: 27 08 BEQ loc_3CFE -3CF6: 15 F6 F1 C6 BSET.B #6, @H'F6F1 ; refs H'F6F1 in on_chip_ram -3CFA: 1D F6 AC 90 MOV:G.W R0, @H'F6AC ; refs H'F6AC in on_chip_ram +3CEC: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs H'F00A in program_or_external; cycles=7 +3CF0: 1D F6 AC 70 CMP:G.W @H'F6AC, R0 ; refs H'F6AC in on_chip_ram; cycles=7 +3CF4: 27 08 BEQ loc_3CFE ; cycles=3/7 nt/t +3CF6: 15 F6 F1 C6 BSET.B #6, @H'F6F1 ; refs H'F6F1 in on_chip_ram; cycles=9 +3CFA: 1D F6 AC 90 MOV:G.W R0, @H'F6AC ; refs H'F6AC in on_chip_ram; cycles=7 loc_3CFE: -3CFE: 15 F0 09 80 MOV:G.B @H'F009, R0 ; refs H'F009 in program_or_external -3D02: 15 F6 D8 70 CMP:G.B @H'F6D8, R0 ; refs H'F6D8 in on_chip_ram -3D06: 27 08 BEQ loc_3D10 -3D08: 15 F6 F3 C0 BSET.B #0, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D0C: 15 F6 D8 90 MOV:G.B R0, @H'F6D8 ; refs H'F6D8 in on_chip_ram +3CFE: 15 F0 09 80 MOV:G.B @H'F009, R0 ; refs H'F009 in program_or_external; cycles=7 +3D02: 15 F6 D8 70 CMP:G.B @H'F6D8, R0 ; refs H'F6D8 in on_chip_ram; cycles=7 +3D06: 27 08 BEQ loc_3D10 ; cycles=3/7 nt/t +3D08: 15 F6 F3 C0 BSET.B #0, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D0C: 15 F6 D8 90 MOV:G.B R0, @H'F6D8 ; refs H'F6D8 in on_chip_ram; cycles=7 loc_3D10: -3D10: 15 F0 08 80 MOV:G.B @H'F008, R0 ; refs H'F008 in program_or_external -3D14: 15 F6 D9 70 CMP:G.B @H'F6D9, R0 ; refs H'F6D9 in on_chip_ram -3D18: 27 08 BEQ loc_3D22 -3D1A: 15 F6 F3 C1 BSET.B #1, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D1E: 15 F6 D9 90 MOV:G.B R0, @H'F6D9 ; refs H'F6D9 in on_chip_ram +3D10: 15 F0 08 80 MOV:G.B @H'F008, R0 ; refs H'F008 in program_or_external; cycles=7 +3D14: 15 F6 D9 70 CMP:G.B @H'F6D9, R0 ; refs H'F6D9 in on_chip_ram; cycles=7 +3D18: 27 08 BEQ loc_3D22 ; cycles=3/7 nt/t +3D1A: 15 F6 F3 C1 BSET.B #1, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D1E: 15 F6 D9 90 MOV:G.B R0, @H'F6D9 ; refs H'F6D9 in on_chip_ram; cycles=7 loc_3D22: -3D22: 15 F0 07 80 MOV:G.B @H'F007, R0 ; refs H'F007 in program_or_external -3D26: 15 F6 DA 70 CMP:G.B @H'F6DA, R0 ; refs H'F6DA in on_chip_ram -3D2A: 27 08 BEQ loc_3D34 -3D2C: 15 F6 F3 C2 BSET.B #2, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D30: 15 F6 DA 90 MOV:G.B R0, @H'F6DA ; refs H'F6DA in on_chip_ram +3D22: 15 F0 07 80 MOV:G.B @H'F007, R0 ; refs H'F007 in program_or_external; cycles=7 +3D26: 15 F6 DA 70 CMP:G.B @H'F6DA, R0 ; refs H'F6DA in on_chip_ram; cycles=7 +3D2A: 27 08 BEQ loc_3D34 ; cycles=3/7 nt/t +3D2C: 15 F6 F3 C2 BSET.B #2, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D30: 15 F6 DA 90 MOV:G.B R0, @H'F6DA ; refs H'F6DA in on_chip_ram; cycles=7 loc_3D34: -3D34: 15 F0 06 80 MOV:G.B @H'F006, R0 ; refs H'F006 in program_or_external -3D38: 15 F6 DB 70 CMP:G.B @H'F6DB, R0 ; refs H'F6DB in on_chip_ram -3D3C: 27 08 BEQ loc_3D46 -3D3E: 15 F6 F3 C3 BSET.B #3, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D42: 15 F6 DB 90 MOV:G.B R0, @H'F6DB ; refs H'F6DB in on_chip_ram +3D34: 15 F0 06 80 MOV:G.B @H'F006, R0 ; refs H'F006 in program_or_external; cycles=7 +3D38: 15 F6 DB 70 CMP:G.B @H'F6DB, R0 ; refs H'F6DB in on_chip_ram; cycles=7 +3D3C: 27 08 BEQ loc_3D46 ; cycles=3/7 nt/t +3D3E: 15 F6 F3 C3 BSET.B #3, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D42: 15 F6 DB 90 MOV:G.B R0, @H'F6DB ; refs H'F6DB in on_chip_ram; cycles=7 loc_3D46: -3D46: 15 F0 05 80 MOV:G.B @H'F005, R0 ; refs H'F005 in program_or_external -3D4A: 15 F6 DC 70 CMP:G.B @H'F6DC, R0 ; refs H'F6DC in on_chip_ram -3D4E: 27 08 BEQ loc_3D58 -3D50: 15 F6 F3 C4 BSET.B #4, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D54: 15 F6 DC 90 MOV:G.B R0, @H'F6DC ; refs H'F6DC in on_chip_ram +3D46: 15 F0 05 80 MOV:G.B @H'F005, R0 ; refs H'F005 in program_or_external; cycles=7 +3D4A: 15 F6 DC 70 CMP:G.B @H'F6DC, R0 ; refs H'F6DC in on_chip_ram; cycles=7 +3D4E: 27 08 BEQ loc_3D58 ; cycles=3/7 nt/t +3D50: 15 F6 F3 C4 BSET.B #4, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D54: 15 F6 DC 90 MOV:G.B R0, @H'F6DC ; refs H'F6DC in on_chip_ram; cycles=7 loc_3D58: -3D58: 15 F0 04 80 MOV:G.B @H'F004, R0 ; refs H'F004 in program_or_external -3D5C: 15 F6 DD 70 CMP:G.B @H'F6DD, R0 ; refs H'F6DD in on_chip_ram -3D60: 27 08 BEQ loc_3D6A -3D62: 15 F6 F3 C5 BSET.B #5, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D66: 15 F6 DD 90 MOV:G.B R0, @H'F6DD ; refs H'F6DD in on_chip_ram +3D58: 15 F0 04 80 MOV:G.B @H'F004, R0 ; refs H'F004 in program_or_external; cycles=7 +3D5C: 15 F6 DD 70 CMP:G.B @H'F6DD, R0 ; refs H'F6DD in on_chip_ram; cycles=7 +3D60: 27 08 BEQ loc_3D6A ; cycles=3/7 nt/t +3D62: 15 F6 F3 C5 BSET.B #5, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D66: 15 F6 DD 90 MOV:G.B R0, @H'F6DD ; refs H'F6DD in on_chip_ram; cycles=7 loc_3D6A: -3D6A: 15 F0 03 80 MOV:G.B @H'F003, R0 ; refs H'F003 in program_or_external -3D6E: 15 F6 DE 70 CMP:G.B @H'F6DE, R0 ; refs H'F6DE in on_chip_ram -3D72: 27 08 BEQ loc_3D7C -3D74: 15 F6 F3 C6 BSET.B #6, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D78: 15 F6 DE 90 MOV:G.B R0, @H'F6DE ; refs H'F6DE in on_chip_ram +3D6A: 15 F0 03 80 MOV:G.B @H'F003, R0 ; refs H'F003 in program_or_external; cycles=7 +3D6E: 15 F6 DE 70 CMP:G.B @H'F6DE, R0 ; refs H'F6DE in on_chip_ram; cycles=7 +3D72: 27 08 BEQ loc_3D7C ; cycles=3/7 nt/t +3D74: 15 F6 F3 C6 BSET.B #6, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D78: 15 F6 DE 90 MOV:G.B R0, @H'F6DE ; refs H'F6DE in on_chip_ram; cycles=7 loc_3D7C: -3D7C: 15 F0 02 80 MOV:G.B @H'F002, R0 ; refs H'F002 in program_or_external -3D80: 15 F6 DF 70 CMP:G.B @H'F6DF, R0 ; refs H'F6DF in on_chip_ram -3D84: 27 08 BEQ loc_3D8E -3D86: 15 F6 F3 C7 BSET.B #7, @H'F6F3 ; refs H'F6F3 in on_chip_ram -3D8A: 15 F6 DF 90 MOV:G.B R0, @H'F6DF ; refs H'F6DF in on_chip_ram +3D7C: 15 F0 02 80 MOV:G.B @H'F002, R0 ; refs H'F002 in program_or_external; cycles=7 +3D80: 15 F6 DF 70 CMP:G.B @H'F6DF, R0 ; refs H'F6DF in on_chip_ram; cycles=7 +3D84: 27 08 BEQ loc_3D8E ; cycles=3/7 nt/t +3D86: 15 F6 F3 C7 BSET.B #7, @H'F6F3 ; refs H'F6F3 in on_chip_ram; cycles=9 +3D8A: 15 F6 DF 90 MOV:G.B R0, @H'F6DF ; refs H'F6DF in on_chip_ram; cycles=7 loc_3D8E: -3D8E: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs H'F001 in program_or_external -3D92: 15 F7 21 D1 BCLR.B #1, @H'F721 ; refs H'F721 in on_chip_ram +3D8E: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs H'F001 in program_or_external; cycles=7 +3D92: 15 F7 21 D1 BCLR.B #1, @H'F721 ; refs H'F721 in on_chip_ram; cycles=9 loc_3D96: -3D96: CF 80 MOV:G.W @R7+, R0 -3D98: 0A RTE +3D96: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +3D98: 0A RTE ; cycles=13 vec_ad_adi_3D99: -3D99: 15 FE E8 D5 BCLR.B #5, @ADCSR ; clear ADST (bit 5) of ADCSR -3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP -3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs H'F68A in on_chip_ram -3DA3: 04 14 A8 MULXU.B #H'14, R0 -3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; refs ADDRA_H in register_field -3DAA: A1 10 SWAP.B R1 -3DAC: A1 12 EXTU.B R1 -3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 -3DB2: A9 20 ADD:G.W R1, R0 -3DB4: 04 15 B8 DIVXU.B #H'15, R0 -3DB7: 15 F6 8A 70 CMP:G.B @H'F68A, R0 ; refs H'F68A in on_chip_ram -3DBB: 27 4B BEQ loc_3E08 -3DBD: 15 F6 8A 82 MOV:G.B @H'F68A, R2 ; refs H'F68A in on_chip_ram -3DC1: 15 F6 8A 90 MOV:G.B R0, @H'F68A ; refs H'F68A in on_chip_ram -3DC5: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs H'F731 in on_chip_ram -3DCA: 22 3C BHI loc_3E08 -3DCC: A0 12 EXTU.B R0 -3DCE: A2 12 EXTU.B R2 -3DD0: 0C 01 01 A8 MULXU.W #H'0101, R0 -3DD4: 0C 01 01 AA MULXU.W #H'0101, R2 -3DD8: AB 31 SUB.W R3, R1 -3DDA: 1D E1 02 80 MOV:G.W @H'E102, R0 ; refs H'E102 in program_or_external -3DDE: A8 21 ADD:G.W R0, R1 -3DE0: A9 82 MOV:G.W R1, R2 -3DE2: 25 0C BCS loc_3DF0 -3DE4: A8 32 SUB.W R0, R2 -3DE6: 4A 80 00 CMP:I #H'8000, R2 -3DE9: 23 0F BLS loc_3DFA -3DEB: 59 00 00 MOV:I.W #H'0000, R1 -3DEE: 20 0A BRA loc_3DFA +3D99: 15 FE E8 D5 BCLR.B #5, @ADCSR ; clear ADST (bit 5) of ADCSR; cycles=8 +3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs H'F68A in on_chip_ram; cycles=6 +3DA3: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; refs ADDRA_H in register_field; cycles=7 +3DAA: A1 10 SWAP.B R1 ; cycles=3 +3DAC: A1 12 EXTU.B R1 ; cycles=3 +3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 ; cycles=7 +3DB2: A9 20 ADD:G.W R1, R0 ; cycles=3 +3DB4: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3DB7: 15 F6 8A 70 CMP:G.B @H'F68A, R0 ; refs H'F68A in on_chip_ram; cycles=6 +3DBB: 27 4B BEQ loc_3E08 ; cycles=3/8 nt/t +3DBD: 15 F6 8A 82 MOV:G.B @H'F68A, R2 ; refs H'F68A in on_chip_ram; cycles=6 +3DC1: 15 F6 8A 90 MOV:G.B R0, @H'F68A ; refs H'F68A in on_chip_ram; cycles=6 +3DC5: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +3DCA: 22 3C BHI loc_3E08 ; cycles=3/7 nt/t +3DCC: A0 12 EXTU.B R0 ; cycles=3 +3DCE: A2 12 EXTU.B R2 ; cycles=3 +3DD0: 0C 01 01 A8 MULXU.W #H'0101, R0 ; cycles=25 +3DD4: 0C 01 01 AA MULXU.W #H'0101, R2 ; cycles=25 +3DD8: AB 31 SUB.W R3, R1 ; cycles=3 +3DDA: 1D E1 02 80 MOV:G.W @H'E102, R0 ; refs H'E102 in program_or_external; cycles=7 +3DDE: A8 21 ADD:G.W R0, R1 ; cycles=3 +3DE0: A9 82 MOV:G.W R1, R2 ; cycles=3 +3DE2: 25 0C BCS loc_3DF0 ; cycles=3/7 nt/t +3DE4: A8 32 SUB.W R0, R2 ; cycles=3 +3DE6: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +3DE9: 23 0F BLS loc_3DFA ; cycles=3/8 nt/t +3DEB: 59 00 00 MOV:I.W #H'0000, R1 ; cycles=3 +3DEE: 20 0A BRA loc_3DFA ; cycles=7 loc_3DF0: -3DF0: AA 30 SUB.W R2, R0 -3DF2: 48 80 00 CMP:I #H'8000, R0 -3DF5: 23 03 BLS loc_3DFA -3DF7: 59 FF FF MOV:I.W #H'FFFF, R1 +3DF0: AA 30 SUB.W R2, R0 ; cycles=3 +3DF2: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +3DF5: 23 03 BLS loc_3DFA ; cycles=3/8 nt/t +3DF7: 59 FF FF MOV:I.W #H'FFFF, R1 ; cycles=3 loc_3DFA: -3DFA: 1D E1 02 71 CMP:G.W @H'E102, R1 ; refs H'E102 in program_or_external -3DFE: 27 08 BEQ loc_3E08 -3E00: 1D F6 8E 91 MOV:G.W R1, @H'F68E ; refs H'F68E in on_chip_ram -3E04: 15 F6 89 C7 BSET.B #7, @H'F689 ; refs H'F689 in on_chip_ram +3DFA: 1D E1 02 71 CMP:G.W @H'E102, R1 ; refs H'E102 in program_or_external; cycles=7 +3DFE: 27 08 BEQ loc_3E08 ; cycles=3/7 nt/t +3E00: 1D F6 8E 91 MOV:G.W R1, @H'F68E ; refs H'F68E in on_chip_ram; cycles=7 +3E04: 15 F6 89 C7 BSET.B #7, @H'F689 ; refs H'F689 in on_chip_ram; cycles=9 loc_3E08: -3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs H'F68B in on_chip_ram -3E0C: 04 14 A8 MULXU.B #H'14, R0 -3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; refs ADDRB_H in register_field -3E13: A1 10 SWAP.B R1 -3E15: A1 12 EXTU.B R1 -3E17: A9 20 ADD:G.W R1, R0 -3E19: 04 15 B8 DIVXU.B #H'15, R0 -3E1C: 1D F6 8C 16 TST.W @H'F68C ; refs H'F68C in on_chip_ram -3E20: 27 06 BEQ loc_3E28 -3E22: 15 F6 8B 70 CMP:G.B @H'F68B, R0 ; refs H'F68B in on_chip_ram -3E26: 27 25 BEQ loc_3E4D +3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs H'F68B in on_chip_ram; cycles=7 +3E0C: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; refs ADDRB_H in register_field; cycles=6 +3E13: A1 10 SWAP.B R1 ; cycles=3 +3E15: A1 12 EXTU.B R1 ; cycles=3 +3E17: A9 20 ADD:G.W R1, R0 ; cycles=3 +3E19: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3E1C: 1D F6 8C 16 TST.W @H'F68C ; refs H'F68C in on_chip_ram; cycles=7 +3E20: 27 06 BEQ loc_3E28 ; cycles=3/7 nt/t +3E22: 15 F6 8B 70 CMP:G.B @H'F68B, R0 ; refs H'F68B in on_chip_ram; cycles=7 +3E26: 27 25 BEQ loc_3E4D ; cycles=3/7 nt/t loc_3E28: -3E28: 15 F6 8B 90 MOV:G.B R0, @H'F68B ; refs H'F68B in on_chip_ram -3E2C: A0 12 EXTU.B R0 -3E2E: A8 83 MOV:G.W R0, R3 -3E30: A3 AB MULXU.B R3, R3 -3E32: AA 13 CLR.W R2 -3E34: 0C 00 C8 BA DIVXU.W #H'00C8, R2 -3E38: 04 04 A8 MULXU.B #H'04, R0 -3E3B: 0C 00 AB 20 ADD:G.W #H'00AB, R0 -3E3F: AB 20 ADD:G.W R3, R0 -3E41: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field -3E45: 26 02 BNE loc_3E49 -3E47: A8 1B SHLR.W R0 +3E28: 15 F6 8B 90 MOV:G.B R0, @H'F68B ; refs H'F68B in on_chip_ram; cycles=7 +3E2C: A0 12 EXTU.B R0 ; cycles=3 +3E2E: A8 83 MOV:G.W R0, R3 ; cycles=3 +3E30: A3 AB MULXU.B R3, R3 ; cycles=18 +3E32: AA 13 CLR.W R2 ; cycles=3 +3E34: 0C 00 C8 BA DIVXU.W #H'00C8, R2 ; cycles=29 +3E38: 04 04 A8 MULXU.B #H'04, R0 ; cycles=19 +3E3B: 0C 00 AB 20 ADD:G.W #H'00AB, R0 ; cycles=4 +3E3F: AB 20 ADD:G.W R3, R0 ; cycles=3 +3E41: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +3E45: 26 02 BNE loc_3E49 ; cycles=3/8 nt/t +3E47: A8 1B SHLR.W R0 ; cycles=3 loc_3E49: -3E49: 1D F6 8C 90 MOV:G.W R0, @H'F68C ; refs H'F68C in on_chip_ram +3E49: 1D F6 8C 90 MOV:G.W R0, @H'F68C ; refs H'F68C in on_chip_ram; cycles=6 loc_3E4D: -3E4D: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} -3E4F: 15 FE E8 D7 BCLR.B #7, @ADCSR ; clear ADF (bit 7) of ADCSR -3E53: 0A RTE +3E4D: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 +3E4F: 15 FE E8 D7 BCLR.B #7, @ADCSR ; clear ADF (bit 7) of ADCSR; cycles=8 +3E53: 0A RTE ; cycles=14 loc_3E54: -3E54: A2 F7 BTST.B #7, R2 -3E56: 27 42 BEQ loc_3E9A -3E58: 15 F9 B5 80 MOV:G.B @H'F9B5, R0 ; refs H'F9B5 in on_chip_ram -3E5C: A0 12 EXTU.B R0 -3E5E: A8 1A SHLL.W R0 -3E60: 15 F9 B0 81 MOV:G.B @H'F9B0, R1 ; refs H'F9B0 in on_chip_ram -3E64: A1 12 EXTU.B R1 -3E66: A9 1A SHLL.W R1 +3E54: A2 F7 BTST.B #7, R2 ; cycles=2 +3E56: 27 42 BEQ loc_3E9A ; cycles=3/7 nt/t +3E58: 15 F9 B5 80 MOV:G.B @H'F9B5, R0 ; refs H'F9B5 in on_chip_ram; cycles=7 +3E5C: A0 12 EXTU.B R0 ; cycles=3 +3E5E: A8 1A SHLL.W R0 ; cycles=3 +3E60: 15 F9 B0 81 MOV:G.B @H'F9B0, R1 ; refs H'F9B0 in on_chip_ram; cycles=7 +3E64: A1 12 EXTU.B R1 ; cycles=3 +3E66: A9 1A SHLL.W R1 ; cycles=3 loc_3E68: -3E68: A0 71 CMP:G.B R0, R1 -3E6A: 27 0A BEQ loc_3E76 -3E6C: F8 F8 70 73 CMP:G.W @(-H'0790,R0), R3 -3E70: 27 28 BEQ loc_3E9A -3E72: A0 09 ADD:Q.B #2, R0 -3E74: 20 F2 BRA loc_3E68 +3E68: A0 71 CMP:G.B R0, R1 ; cycles=2 +3E6A: 27 0A BEQ loc_3E76 ; cycles=3/7 nt/t +3E6C: F8 F8 70 73 CMP:G.W @(-H'0790,R0), R3 ; cycles=7 +3E70: 27 28 BEQ loc_3E9A ; cycles=3/7 nt/t +3E72: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3E74: 20 F2 BRA loc_3E68 ; cycles=7 loc_3E76: -3E76: F9 F8 70 93 MOV:G.W R3, @(-H'0790,R1) -3E7A: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs H'F9B0 in on_chip_ram -3E7E: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs H'F9B0 in on_chip_ram +3E76: F9 F8 70 93 MOV:G.W R3, @(-H'0790,R1) ; cycles=7 +3E7A: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs H'F9B0 in on_chip_ram; cycles=9 +3E7E: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs H'F9B0 in on_chip_ram; cycles=9 loc_3E82: -3E82: 15 F9 B0 80 MOV:G.B @H'F9B0, R0 ; refs H'F9B0 in on_chip_ram -3E86: A0 08 ADD:Q.B #1, R0 -3E88: 04 7F 50 AND.B #H'7F, R0 -3E8B: 15 F9 B5 70 CMP:G.B @H'F9B5, R0 ; refs H'F9B5 in on_chip_ram -3E8F: 26 09 BNE loc_3E9A -3E91: 12 0C STM.W {R2,R3}, @-SP -3E93: 1E 01 3D BSR loc_3FD3 -3E96: 02 0C LDM.W @SP+, {R2,R3} -3E98: 20 E8 BRA loc_3E82 +3E82: 15 F9 B0 80 MOV:G.B @H'F9B0, R0 ; refs H'F9B0 in on_chip_ram; cycles=7 +3E86: A0 08 ADD:Q.B #1, R0 ; cycles=4 +3E88: 04 7F 50 AND.B #H'7F, R0 ; cycles=3 +3E8B: 15 F9 B5 70 CMP:G.B @H'F9B5, R0 ; refs H'F9B5 in on_chip_ram; cycles=6 +3E8F: 26 09 BNE loc_3E9A ; cycles=3/8 nt/t +3E91: 12 0C STM.W {R2,R3}, @-SP ; cycles=12 +3E93: 1E 01 3D BSR loc_3FD3 ; cycles=14 +3E96: 02 0C LDM.W @SP+, {R2,R3} ; cycles=14 +3E98: 20 E8 BRA loc_3E82 ; cycles=7 loc_3E9A: -3E9A: A2 F6 BTST.B #6, R2 -3E9C: 27 2D BEQ loc_3ECB -3E9E: 15 F9 B9 80 MOV:G.B @H'F9B9, R0 ; refs H'F9B9 in on_chip_ram -3EA2: A0 12 EXTU.B R0 -3EA4: A8 1A SHLL.W R0 -3EA6: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs H'F9B4 in on_chip_ram -3EAA: A1 12 EXTU.B R1 -3EAC: A9 1A SHLL.W R1 +3E9A: A2 F6 BTST.B #6, R2 ; cycles=2 +3E9C: 27 2D BEQ loc_3ECB ; cycles=3/7 nt/t +3E9E: 15 F9 B9 80 MOV:G.B @H'F9B9, R0 ; refs H'F9B9 in on_chip_ram; cycles=7 +3EA2: A0 12 EXTU.B R0 ; cycles=3 +3EA4: A8 1A SHLL.W R0 ; cycles=3 +3EA6: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs H'F9B4 in on_chip_ram; cycles=7 +3EAA: A1 12 EXTU.B R1 ; cycles=3 +3EAC: A9 1A SHLL.W R1 ; cycles=3 loc_3EAE: -3EAE: A0 71 CMP:G.B R0, R1 -3EB0: 27 0D BEQ loc_3EBF -3EB2: F8 F9 70 73 CMP:G.W @(-H'0690,R0), R3 -3EB6: 27 13 BEQ loc_3ECB -3EB8: A0 09 ADD:Q.B #2, R0 -3EBA: 04 3F 50 AND.B #H'3F, R0 -3EBD: 20 EF BRA loc_3EAE +3EAE: A0 71 CMP:G.B R0, R1 ; cycles=2 +3EB0: 27 0D BEQ loc_3EBF ; cycles=3/7 nt/t +3EB2: F8 F9 70 73 CMP:G.W @(-H'0690,R0), R3 ; cycles=7 +3EB6: 27 13 BEQ loc_3ECB ; cycles=3/7 nt/t +3EB8: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3EBA: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3EBD: 20 EF BRA loc_3EAE ; cycles=8 loc_3EBF: -3EBF: F9 F9 70 93 MOV:G.W R3, @(-H'0690,R1) -3EC3: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs H'F9B4 in on_chip_ram -3EC7: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs H'F9B4 in on_chip_ram +3EBF: F9 F9 70 93 MOV:G.W R3, @(-H'0690,R1) ; cycles=6 +3EC3: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs H'F9B4 in on_chip_ram; cycles=8 +3EC7: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs H'F9B4 in on_chip_ram; cycles=8 loc_3ECB: -3ECB: 19 RTS +3ECB: 19 RTS ; cycles=13 loc_3ECC: -3ECC: 12 1F STM.W {R0,R1,R2,R3,R4}, @-SP -3ECE: A5 12 EXTU.B R5 -3ED0: 45 03 CMP:E #H'03, R5 -3ED2: 23 05 BLS loc_3ED9 -3ED4: 1E 00 69 BSR loc_3F40 -3ED7: 20 4C BRA loc_3F25 +3ECC: 12 1F STM.W {R0,R1,R2,R3,R4}, @-SP ; cycles=21 +3ECE: A5 12 EXTU.B R5 ; cycles=3 +3ED0: 45 03 CMP:E #H'03, R5 ; cycles=2 +3ED2: 23 05 BLS loc_3ED9 ; cycles=3/7 nt/t +3ED4: 1E 00 69 BSR loc_3F40 ; cycles=13 +3ED7: 20 4C BRA loc_3F25 ; cycles=8 loc_3ED9: -3ED9: A5 83 MOV:G.B R5, R3 -3EDB: 45 00 CMP:E #H'00, R5 -3EDD: 27 0A BEQ loc_3EE9 -3EDF: 45 01 CMP:E #H'01, R5 -3EE1: 27 0B BEQ loc_3EEE -3EE3: 45 02 CMP:E #H'02, R5 -3EE5: 27 0C BEQ loc_3EF3 -3EE7: 20 0F BRA loc_3EF8 +3ED9: A5 83 MOV:G.B R5, R3 ; cycles=2 +3EDB: 45 00 CMP:E #H'00, R5 ; cycles=2 +3EDD: 27 0A BEQ loc_3EE9 ; cycles=3/8 nt/t +3EDF: 45 01 CMP:E #H'01, R5 ; cycles=2 +3EE1: 27 0B BEQ loc_3EEE ; cycles=3/8 nt/t +3EE3: 45 02 CMP:E #H'02, R5 ; cycles=2 +3EE5: 27 0C BEQ loc_3EF3 ; cycles=3/8 nt/t +3EE7: 20 0F BRA loc_3EF8 ; cycles=8 loc_3EE9: -3EE9: 5D 00 80 MOV:I.W #H'0080, R5 -3EEC: 20 0D BRA loc_3EFB +3EE9: 5D 00 80 MOV:I.W #H'0080, R5 ; cycles=3 +3EEC: 20 0D BRA loc_3EFB ; cycles=7 loc_3EEE: -3EEE: 5D 00 C0 MOV:I.W #H'00C0, R5 -3EF1: 20 08 BRA loc_3EFB +3EEE: 5D 00 C0 MOV:I.W #H'00C0, R5 ; cycles=3 +3EF1: 20 08 BRA loc_3EFB ; cycles=8 loc_3EF3: -3EF3: 5D 00 90 MOV:I.W #H'0090, R5 -3EF6: 20 03 BRA loc_3EFB +3EF3: 5D 00 90 MOV:I.W #H'0090, R5 ; cycles=3 +3EF6: 20 03 BRA loc_3EFB ; cycles=7 loc_3EF8: -3EF8: 5D 00 D0 MOV:I.W #H'00D0, R5 +3EF8: 5D 00 D0 MOV:I.W #H'00D0, R5 ; cycles=3 loc_3EFB: -3EFB: 04 10 AB MULXU.B #H'10, R3 -3EFE: 0C FA B0 23 ADD:G.W #H'FAB0, R3 -3F02: A9 13 CLR.W R1 +3EFB: 04 10 AB MULXU.B #H'10, R3 ; cycles=19 +3EFE: 0C FA B0 23 ADD:G.W #H'FAB0, R3 ; cycles=4 +3F02: A9 13 CLR.W R1 ; cycles=3 loc_3F04: -3F04: F1 FA F0 82 MOV:G.B @(-H'0510,R1), R2 -3F08: D3 72 CMP:G.B @R3, R2 -3F0A: 27 04 BEQ loc_3F10 -3F0C: D3 92 MOV:G.B R2, @R3 -3F0E: 0E 18 BSR loc_3F28 +3F04: F1 FA F0 82 MOV:G.B @(-H'0510,R1), R2 ; cycles=7 +3F08: D3 72 CMP:G.B @R3, R2 ; cycles=6 +3F0A: 27 04 BEQ loc_3F10 ; cycles=3/7 nt/t +3F0C: D3 92 MOV:G.B R2, @R3 ; cycles=6 +3F0E: 0E 18 BSR loc_3F28 ; cycles=13 loc_3F10: -3F10: A1 08 ADD:Q.B #1, R1 -3F12: A3 08 ADD:Q.B #1, R3 -3F14: 41 10 CMP:E #H'10, R1 -3F16: 27 02 BEQ loc_3F1A -3F18: 20 EA BRA loc_3F04 +3F10: A1 08 ADD:Q.B #1, R1 ; cycles=4 +3F12: A3 08 ADD:Q.B #1, R3 ; cycles=4 +3F14: 41 10 CMP:E #H'10, R1 ; cycles=2 +3F16: 27 02 BEQ loc_3F1A ; cycles=3/7 nt/t +3F18: 20 EA BRA loc_3F04 ; cycles=7 loc_3F1A: -3F1A: 1D FB 00 07 00 E0 MOV:G.W #H'00E0, @H'FB00 ; refs H'FB00 in on_chip_ram -3F20: 5C 00 E0 MOV:I.W #H'00E0, R4 -3F23: 0E 1B BSR loc_3F40 +3F1A: 1D FB 00 07 00 E0 MOV:G.W #H'00E0, @H'FB00 ; refs H'FB00 in on_chip_ram; cycles=11 +3F20: 5C 00 E0 MOV:I.W #H'00E0, R4 ; cycles=3 +3F23: 0E 1B BSR loc_3F40 ; cycles=14 loc_3F25: -3F25: 02 1F LDM.W @SP+, {R0,R1,R2,R3,R4} -3F27: 19 RTS +3F25: 02 1F LDM.W @SP+, {R0,R1,R2,R3,R4} ; cycles=26 +3F27: 19 RTS ; cycles=13 loc_3F28: -3F28: AD 84 MOV:G.W R5, R4 -3F2A: A1 24 ADD:G.B R1, R4 -3F2C: 1D FB 00 74 CMP:G.W @H'FB00, R4 ; refs H'FB00 in on_chip_ram -3F30: 27 06 BEQ loc_3F38 -3F32: 1D FB 00 94 MOV:G.W R4, @H'FB00 ; refs H'FB00 in on_chip_ram -3F36: 0E 08 BSR loc_3F40 +3F28: AD 84 MOV:G.W R5, R4 ; cycles=3 +3F2A: A1 24 ADD:G.B R1, R4 ; cycles=2 +3F2C: 1D FB 00 74 CMP:G.W @H'FB00, R4 ; refs H'FB00 in on_chip_ram; cycles=7 +3F30: 27 06 BEQ loc_3F38 ; cycles=3/7 nt/t +3F32: 1D FB 00 94 MOV:G.W R4, @H'FB00 ; refs H'FB00 in on_chip_ram; cycles=7 +3F36: 0E 08 BSR loc_3F40 ; cycles=13 loc_3F38: -3F38: 5C 02 00 MOV:I.W #H'0200, R4 -3F3B: A2 24 ADD:G.B R2, R4 -3F3D: 0E 01 BSR loc_3F40 -3F3F: 19 RTS +3F38: 5C 02 00 MOV:I.W #H'0200, R4 ; cycles=3 +3F3B: A2 24 ADD:G.B R2, R4 ; cycles=2 +3F3D: 0E 01 BSR loc_3F40 ; cycles=14 +3F3F: 19 RTS ; cycles=13 loc_3F40: -3F40: BF 98 STC.W SR, @-R7 -3F42: 0C 00 FF 58 ANDC.W #H'00FF, SR -3F46: 0C 06 00 48 ORC.W #H'0600, SR +3F40: BF 98 STC.W SR, @-R7 ; cycles=8 +3F42: 0C 00 FF 58 ANDC.W #H'00FF, SR ; cycles=4 +3F46: 0C 06 00 48 ORC.W #H'0600, SR ; cycles=4 loc_3F4A: -3F4A: 15 F2 00 00 80 MOVFPE.B @H'F200, R0 ; refs H'F200 in program_or_external -3F4F: A0 F7 BTST.B #7, R0 -3F51: 26 F7 BNE loc_3F4A -3F53: AC F8 BTST.W #8, R4 -3F55: 26 16 BNE loc_3F6D -3F57: AC F9 BTST.W #9, R4 -3F59: 26 07 BNE loc_3F62 -3F5B: 15 F2 00 00 94 MOVTPE.B R4, @H'F200 ; refs H'F200 in program_or_external -3F60: 20 10 BRA loc_3F72 +3F4A: 15 F2 00 00 80 MOVFPE.B @H'F200, R0 ; refs H'F200 in program_or_external; cycles=13 +3F4F: A0 F7 BTST.B #7, R0 ; cycles=2 +3F51: 26 F7 BNE loc_3F4A ; cycles=3/8 nt/t +3F53: AC F8 BTST.W #8, R4 ; cycles=3 +3F55: 26 16 BNE loc_3F6D ; cycles=3/8 nt/t +3F57: AC F9 BTST.W #9, R4 ; cycles=3 +3F59: 26 07 BNE loc_3F62 ; cycles=3/8 nt/t +3F5B: 15 F2 00 00 94 MOVTPE.B R4, @H'F200 ; refs H'F200 in program_or_external; cycles=13 +3F60: 20 10 BRA loc_3F72 ; cycles=7 loc_3F62: -3F62: 15 F2 01 00 94 MOVTPE.B R4, @H'F201 ; refs H'F201 in program_or_external -3F67: 1D FB 00 08 ADD:Q.W #1, @H'FB00 ; refs H'FB00 in on_chip_ram -3F6B: 20 05 BRA loc_3F72 +3F62: 15 F2 01 00 94 MOVTPE.B R4, @H'F201 ; refs H'F201 in program_or_external; cycles=13 +3F67: 1D FB 00 08 ADD:Q.W #1, @H'FB00 ; refs H'FB00 in on_chip_ram; cycles=8 +3F6B: 20 05 BRA loc_3F72 ; cycles=8 loc_3F6D: -3F6D: 15 F2 01 00 84 MOVFPE.B @H'F201, R4 ; refs H'F201 in program_or_external +3F6D: 15 F2 01 00 84 MOVFPE.B @H'F201, R4 ; refs H'F201 in program_or_external; cycles=13 loc_3F72: -3F72: CF 88 LDC.W @R7+, SR -3F74: 19 RTS +3F72: CF 88 LDC.W @R7+, SR ; cycles=7 +3F74: 19 RTS ; cycles=12 loc_3F76: -3F76: 58 27 10 MOV:I.W #H'2710, R0 -3F79: 59 C3 50 MOV:I.W #H'C350, R1 +3F76: 58 27 10 MOV:I.W #H'2710, R0 ; cycles=3 +3F79: 59 C3 50 MOV:I.W #H'C350, R1 ; cycles=3 loc_3F7C: -3F7C: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR -3F80: 01 B8 F9 SCB/F R0, loc_3F7C +3F7C: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=9 +3F80: 01 B8 F9 SCB/F R0, loc_3F7C ; cycles=3/4/8 false/-1/t loc_3F83: -3F83: 15 FE 82 C7 BSET.B #7, @P1DR ; set bit 7 of P1DR -3F87: 01 B9 F9 SCB/F R1, loc_3F83 -3F8A: A8 13 CLR.W R0 +3F83: 15 FE 82 C7 BSET.B #7, @P1DR ; set bit 7 of P1DR; cycles=8 +3F87: 01 B9 F9 SCB/F R1, loc_3F83 ; cycles=3/4/9 false/-1/t +3F8A: A8 13 CLR.W R0 ; cycles=3 loc_3F8C: -3F8C: F8 E0 00 13 CLR.W @(-H'2000,R0) -3F90: F8 E8 00 13 CLR.W @(-H'1800,R0) -3F94: F8 F6 80 13 CLR.W @(-H'0980,R0) -3F98: A8 09 ADD:Q.W #2, R0 -3F9A: 48 08 00 CMP:I #H'0800, R0 -3F9D: 26 ED BNE loc_3F8C -3F9F: 1E 03 6A BSR loc_430C -3FA2: 1E 03 7F BSR loc_4324 -3FA5: 1E 00 EE BSR loc_4096 -3FA8: 1E 01 10 BSR loc_40BB -3FAB: 1E 02 69 BSR loc_4217 -3FAE: 1E 03 9B BSR loc_434C +3F8C: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=9 +3F90: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=9 +3F94: F8 F6 80 13 CLR.W @(-H'0980,R0) ; cycles=9 +3F98: A8 09 ADD:Q.W #2, R0 ; cycles=4 +3F9A: 48 08 00 CMP:I #H'0800, R0 ; cycles=3 +3F9D: 26 ED BNE loc_3F8C ; cycles=3/8 nt/t +3F9F: 1E 03 6A BSR loc_430C ; cycles=14 +3FA2: 1E 03 7F BSR loc_4324 ; cycles=13 +3FA5: 1E 00 EE BSR loc_4096 ; cycles=14 +3FA8: 1E 01 10 BSR loc_40BB ; cycles=13 +3FAB: 1E 02 69 BSR loc_4217 ; cycles=14 +3FAE: 1E 03 9B BSR loc_434C ; cycles=13 loc_3FB1: -3FB1: 1D FE EC 07 5A 00 MOV:G.W #H'5A00, @WDT_TCSR_R ; WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00) -3FB7: 15 F7 94 13 CLR.B @H'F794 ; refs H'F794 in on_chip_ram -3FBB: 0E 16 BSR loc_3FD3 -3FBD: 1E 7B EB BSR loc_BBAB -3FC0: 0E 2D BSR loc_3FEF -3FC2: 1E 00 81 BSR loc_4046 -3FC5: 1E 7E D6 BSR loc_BE9E -3FC8: 1E E8 3B BSR loc_2806 -3FCB: 1E F9 62 BSR loc_3930 -3FCE: 1E D6 0F BSR loc_15E0 -3FD1: 20 DE BRA loc_3FB1 +3FB1: 1D FE EC 07 5A 00 MOV:G.W #H'5A00, @WDT_TCSR_R ; WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00); cycles=9 +3FB7: 15 F7 94 13 CLR.B @H'F794 ; refs H'F794 in on_chip_ram; cycles=8 +3FBB: 0E 16 BSR loc_3FD3 ; cycles=14 +3FBD: 1E 7B EB BSR loc_BBAB ; cycles=14 +3FC0: 0E 2D BSR loc_3FEF ; cycles=13 +3FC2: 1E 00 81 BSR loc_4046 ; cycles=13 +3FC5: 1E 7E D6 BSR loc_BE9E ; cycles=14 +3FC8: 1E E8 3B BSR loc_2806 ; cycles=13 +3FCB: 1E F9 62 BSR loc_3930 ; cycles=14 +3FCE: 1E D6 0F BSR loc_15E0 ; cycles=13 +3FD1: 20 DE BRA loc_3FB1 ; cycles=8 loc_3FD3: -3FD3: 15 FA A2 16 TST.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -3FD7: 26 15 BNE loc_3FEE -3FD9: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram -3FDD: 27 06 BEQ loc_3FE5 -3FDF: 15 F9 C3 16 TST.B @H'F9C3 ; refs H'F9C3 in on_chip_ram -3FE3: 26 09 BNE loc_3FEE +3FD3: 15 FA A2 16 TST.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=6 +3FD7: 26 15 BNE loc_3FEE ; cycles=3/8 nt/t +3FD9: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram; cycles=6 +3FDD: 27 06 BEQ loc_3FE5 ; cycles=3/8 nt/t +3FDF: 15 F9 C3 16 TST.B @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=6 +3FE3: 26 09 BNE loc_3FEE ; cycles=3/8 nt/t loc_3FE5: -3FE5: 15 F9 C0 16 TST.B @H'F9C0 ; refs H'F9C0 in on_chip_ram -3FE9: 26 03 BNE loc_3FEE -3FEB: 1E 7B 04 BSR loc_BAF2 +3FE5: 15 F9 C0 16 TST.B @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=6 +3FE9: 26 03 BNE loc_3FEE ; cycles=3/8 nt/t +3FEB: 1E 7B 04 BSR loc_BAF2 ; cycles=14 loc_3FEE: -3FEE: 19 RTS +3FEE: 19 RTS ; cycles=12 loc_3FEF: -3FEF: 15 F9 C5 16 TST.B @H'F9C5 ; refs H'F9C5 in on_chip_ram -3FF3: 26 12 BNE loc_4007 -3FF5: 15 F9 B5 13 CLR.B @H'F9B5 ; refs H'F9B5 in on_chip_ram -3FF9: 15 F9 B0 13 CLR.B @H'F9B0 ; refs H'F9B0 in on_chip_ram -3FFD: 15 FA A5 D7 BCLR.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram -4001: 27 08 BEQ loc_400B -4003: 0E 07 BSR loc_400C -4005: 20 04 BRA loc_400B +3FEF: 15 F9 C5 16 TST.B @H'F9C5 ; refs H'F9C5 in on_chip_ram; cycles=6 +3FF3: 26 12 BNE loc_4007 ; cycles=3/8 nt/t +3FF5: 15 F9 B5 13 CLR.B @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=8 +3FF9: 15 F9 B0 13 CLR.B @H'F9B0 ; refs H'F9B0 in on_chip_ram; cycles=8 +3FFD: 15 FA A5 D7 BCLR.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram; cycles=8 +4001: 27 08 BEQ loc_400B ; cycles=3/8 nt/t +4003: 0E 07 BSR loc_400C ; cycles=14 +4005: 20 04 BRA loc_400B ; cycles=8 loc_4007: -4007: 15 FA A5 C7 BSET.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram +4007: 15 FA A5 C7 BSET.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram; cycles=8 loc_400B: -400B: 19 RTS +400B: 19 RTS ; cycles=13 loc_400C: -400C: 15 F7 30 13 CLR.B @H'F730 ; refs H'F730 in on_chip_ram -4010: 15 F7 56 13 CLR.B @H'F756 ; refs H'F756 in on_chip_ram -4014: 15 F7 57 13 CLR.B @H'F757 ; refs H'F757 in on_chip_ram -4018: 15 F7 58 13 CLR.B @H'F758 ; refs H'F758 in on_chip_ram -401C: 15 F7 59 13 CLR.B @H'F759 ; refs H'F759 in on_chip_ram -4020: 1D F7 32 13 CLR.W @H'F732 ; refs H'F732 in on_chip_ram -4024: 1D F7 5C 13 CLR.W @H'F75C ; refs H'F75C in on_chip_ram -4028: 15 FB 03 13 CLR.B @H'FB03 ; refs H'FB03 in on_chip_ram -402C: 1D E0 46 13 CLR.W @H'E046 ; refs H'E046 in program_or_external -4030: 1D F7 6A 13 CLR.W @H'F76A ; refs H'F76A in on_chip_ram -4034: 15 F7 91 13 CLR.B @H'F791 ; refs H'F791 in on_chip_ram -4038: 15 F7 95 13 CLR.B @H'F795 ; refs H'F795 in on_chip_ram -403C: 15 F7 6E 13 CLR.B @H'F76E ; refs H'F76E in on_chip_ram -4040: 0E 33 BSR loc_4075 -4042: 1E 01 D2 BSR loc_4217 -4045: 19 RTS +400C: 15 F7 30 13 CLR.B @H'F730 ; refs H'F730 in on_chip_ram; cycles=9 +4010: 15 F7 56 13 CLR.B @H'F756 ; refs H'F756 in on_chip_ram; cycles=9 +4014: 15 F7 57 13 CLR.B @H'F757 ; refs H'F757 in on_chip_ram; cycles=9 +4018: 15 F7 58 13 CLR.B @H'F758 ; refs H'F758 in on_chip_ram; cycles=9 +401C: 15 F7 59 13 CLR.B @H'F759 ; refs H'F759 in on_chip_ram; cycles=9 +4020: 1D F7 32 13 CLR.W @H'F732 ; refs H'F732 in on_chip_ram; cycles=9 +4024: 1D F7 5C 13 CLR.W @H'F75C ; refs H'F75C in on_chip_ram; cycles=9 +4028: 15 FB 03 13 CLR.B @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=9 +402C: 1D E0 46 13 CLR.W @H'E046 ; refs H'E046 in program_or_external; cycles=9 +4030: 1D F7 6A 13 CLR.W @H'F76A ; refs H'F76A in on_chip_ram; cycles=9 +4034: 15 F7 91 13 CLR.B @H'F791 ; refs H'F791 in on_chip_ram; cycles=9 +4038: 15 F7 95 13 CLR.B @H'F795 ; refs H'F795 in on_chip_ram; cycles=9 +403C: 15 F7 6E 13 CLR.B @H'F76E ; refs H'F76E in on_chip_ram; cycles=9 +4040: 0E 33 BSR loc_4075 ; cycles=13 +4042: 1E 01 D2 BSR loc_4217 ; cycles=13 +4045: 19 RTS ; cycles=13 loc_4046: -4046: 15 F9 C4 16 TST.B @H'F9C4 ; refs H'F9C4 in on_chip_ram -404A: 26 0C BNE loc_4058 -404C: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram -4050: 27 07 BEQ loc_4059 -4052: 15 F9 C3 16 TST.B @H'F9C3 ; refs H'F9C3 in on_chip_ram -4056: 27 01 BEQ loc_4059 +4046: 15 F9 C4 16 TST.B @H'F9C4 ; refs H'F9C4 in on_chip_ram; cycles=7 +404A: 26 0C BNE loc_4058 ; cycles=3/7 nt/t +404C: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram; cycles=7 +4050: 27 07 BEQ loc_4059 ; cycles=3/7 nt/t +4052: 15 F9 C3 16 TST.B @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=7 +4056: 27 01 BEQ loc_4059 ; cycles=3/7 nt/t loc_4058: -4058: 19 RTS +4058: 19 RTS ; cycles=12 loc_4059: -4059: 15 F9 B0 82 MOV:G.B @H'F9B0, R2 ; refs H'F9B0 in on_chip_ram -405D: A2 12 EXTU.B R2 -405F: 15 F9 B5 72 CMP:G.B @H'F9B5, R2 ; refs H'F9B5 in on_chip_ram -4063: 26 0F BNE loc_4074 -4065: A2 1A SHLL.B R2 -4067: FA F8 70 06 00 MOV:G.W #H'00, @(-H'0790,R2) -406C: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs H'F9B0 in on_chip_ram -4070: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs H'F9B0 in on_chip_ram +4059: 15 F9 B0 82 MOV:G.B @H'F9B0, R2 ; refs H'F9B0 in on_chip_ram; cycles=6 +405D: A2 12 EXTU.B R2 ; cycles=3 +405F: 15 F9 B5 72 CMP:G.B @H'F9B5, R2 ; refs H'F9B5 in on_chip_ram; cycles=6 +4063: 26 0F BNE loc_4074 ; cycles=3/8 nt/t +4065: A2 1A SHLL.B R2 ; cycles=2 +4067: FA F8 70 06 00 MOV:G.W #H'00, @(-H'0790,R2) ; cycles=11 +406C: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs H'F9B0 in on_chip_ram; cycles=9 +4070: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs H'F9B0 in on_chip_ram; cycles=9 loc_4074: -4074: 19 RTS +4074: 19 RTS ; cycles=12 loc_4075: -4075: A8 13 CLR.W R0 +4075: A8 13 CLR.W R0 ; cycles=3 loc_4077: -4077: F8 E0 00 13 CLR.W @(-H'2000,R0) -407B: F8 E4 00 13 CLR.W @(-H'1C00,R0) -407F: F8 E8 00 13 CLR.W @(-H'1800,R0) -4083: 48 02 00 CMP:I #H'0200, R0 -4086: 24 04 BCC loc_408C -4088: F8 EC 00 13 CLR.W @(-H'1400,R0) +4077: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=8 +407B: F8 E4 00 13 CLR.W @(-H'1C00,R0) ; cycles=8 +407F: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=8 +4083: 48 02 00 CMP:I #H'0200, R0 ; cycles=3 +4086: 24 04 BCC loc_408C ; cycles=3/7 nt/t +4088: F8 EC 00 13 CLR.W @(-H'1400,R0) ; cycles=9 loc_408C: -408C: A8 09 ADD:Q.W #2, R0 -408E: 48 04 00 CMP:I #H'0400, R0 -4091: 26 E4 BNE loc_4077 -4093: 0E 01 BSR loc_4096 -4095: 19 RTS +408C: A8 09 ADD:Q.W #2, R0 ; cycles=4 +408E: 48 04 00 CMP:I #H'0400, R0 ; cycles=3 +4091: 26 E4 BNE loc_4077 ; cycles=3/8 nt/t +4093: 0E 01 BSR loc_4096 ; cycles=14 +4095: 19 RTS ; cycles=13 loc_4096: -4096: 1D E0 00 07 00 80 MOV:G.W #H'0080, @H'E000 ; refs H'E000 in program_or_external -409C: 1D E0 06 07 80 00 MOV:G.W #H'8000, @H'E006 ; refs H'E006 in program_or_external -40A2: 1D E0 80 07 FF FF MOV:G.W #H'FFFF, @H'E080 ; refs H'E080 in program_or_external -40A8: 1D E8 00 07 00 80 MOV:G.W #H'0080, @H'E800 ; refs H'E800 in program_or_external -40AE: 1D E8 06 07 80 00 MOV:G.W #H'8000, @H'E806 ; refs H'E806 in program_or_external -40B4: 1D E8 80 07 FF FF MOV:G.W #H'FFFF, @H'E880 ; refs H'E880 in program_or_external -40BA: 19 RTS +4096: 1D E0 00 07 00 80 MOV:G.W #H'0080, @H'E000 ; refs H'E000 in program_or_external; cycles=11 +409C: 1D E0 06 07 80 00 MOV:G.W #H'8000, @H'E006 ; refs H'E006 in program_or_external; cycles=11 +40A2: 1D E0 80 07 FF FF MOV:G.W #H'FFFF, @H'E080 ; refs H'E080 in program_or_external; cycles=11 +40A8: 1D E8 00 07 00 80 MOV:G.W #H'0080, @H'E800 ; refs H'E800 in program_or_external; cycles=11 +40AE: 1D E8 06 07 80 00 MOV:G.W #H'8000, @H'E806 ; refs H'E806 in program_or_external; cycles=11 +40B4: 1D E8 80 07 FF FF MOV:G.W #H'FFFF, @H'E880 ; refs H'E880 in program_or_external; cycles=11 +40BA: 19 RTS ; cycles=12 loc_40BB: -40BB: 58 00 40 MOV:I.W #H'0040, R0 +40BB: 58 00 40 MOV:I.W #H'0040, R0 ; cycles=3 loc_40BE: -40BE: F8 F8 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0792,R0) -40C4: F8 F8 AE 07 FF FF MOV:G.W #H'FFFF, @(-H'0752,R0) -40CA: F8 F8 EE 07 FF FF MOV:G.W #H'FFFF, @(-H'0712,R0) -40D0: F8 F9 2E 07 FF FF MOV:G.W #H'FFFF, @(-H'06D2,R0) -40D6: F8 F9 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0692,R0) -40DC: A8 0D ADD:Q.W #-2, R0 -40DE: 26 DE BNE loc_40BE -40E0: 15 F9 C4 06 14 MOV:G.B #H'14, @H'F9C4 ; refs H'F9C4 in on_chip_ram -40E5: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs H'F6F7 in on_chip_ram -40EA: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs H'F6F8 in on_chip_ram -40EF: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs H'F6F9 in on_chip_ram -40F4: 15 FE 8E F7 BTST.B #7, @P7DR ; refs P7DR in register_field -40F8: 27 09 BEQ loc_4103 -40FA: 1D F4 02 05 6B 6F CMP:G.W #H'6B6F, @H'F402 ; refs H'F402 in program_or_external -4100: 37 00 AD BEQ loc_41B0 +40BE: F8 F8 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0792,R0) ; cycles=9 +40C4: F8 F8 AE 07 FF FF MOV:G.W #H'FFFF, @(-H'0752,R0) ; cycles=9 +40CA: F8 F8 EE 07 FF FF MOV:G.W #H'FFFF, @(-H'0712,R0) ; cycles=9 +40D0: F8 F9 2E 07 FF FF MOV:G.W #H'FFFF, @(-H'06D2,R0) ; cycles=9 +40D6: F8 F9 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0692,R0) ; cycles=9 +40DC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +40DE: 26 DE BNE loc_40BE ; cycles=3/7 nt/t +40E0: 15 F9 C4 06 14 MOV:G.B #H'14, @H'F9C4 ; refs H'F9C4 in on_chip_ram; cycles=9 +40E5: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs H'F6F7 in on_chip_ram; cycles=9 +40EA: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs H'F6F8 in on_chip_ram; cycles=9 +40EF: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs H'F6F9 in on_chip_ram; cycles=9 +40F4: 15 FE 8E F7 BTST.B #7, @P7DR ; refs P7DR in register_field; cycles=7 +40F8: 27 09 BEQ loc_4103 ; cycles=3/7 nt/t +40FA: 1D F4 02 05 6B 6F CMP:G.W #H'6B6F, @H'F402 ; refs H'F402 in program_or_external; cycles=7 +4100: 37 00 AD BEQ loc_41B0 ; cycles=3/7 nt/t loc_4103: -4103: 58 01 00 MOV:I.W #H'0100, R0 +4103: 58 01 00 MOV:I.W #H'0100, R0 ; cycles=3 loc_4106: -4106: A8 0D ADD:Q.W #-2, R0 -4108: F8 C9 64 85 MOV:G.W @(-H'369C,R0), R5 -410C: F8 F4 00 95 MOV:G.W R5, @(-H'0C00,R0) -4110: BF 90 MOV:G.W R0, @-R7 -4112: A8 84 MOV:G.W R0, R4 -4114: 18 BF E0 JSR @loc_BFE0 -4117: 0C 01 00 24 ADD:G.W #H'0100, R4 -411B: 18 BF E0 JSR @loc_BFE0 -411E: 0C 01 00 24 ADD:G.W #H'0100, R4 -4122: 18 BF E0 JSR @loc_BFE0 -4125: 0C 01 00 24 ADD:G.W #H'0100, R4 -4129: 18 BF E0 JSR @loc_BFE0 -412C: 0C 01 00 24 ADD:G.W #H'0100, R4 -4130: 18 BF E0 JSR @loc_BFE0 -4133: 0C 01 00 24 ADD:G.W #H'0100, R4 -4137: 18 BF E0 JSR @loc_BFE0 -413A: 0C 01 00 24 ADD:G.W #H'0100, R4 -413E: 18 BF E0 JSR @loc_BFE0 -4141: 0C 01 00 24 ADD:G.W #H'0100, R4 -4145: 18 BF E0 JSR @loc_BFE0 -4148: 0C 01 00 24 ADD:G.W #H'0100, R4 -414C: 18 BF E0 JSR @loc_BFE0 -414F: 0C 01 00 24 ADD:G.W #H'0100, R4 -4153: 18 BF E0 JSR @loc_BFE0 -4156: 0C 01 00 24 ADD:G.W #H'0100, R4 -415A: 18 BF E0 JSR @loc_BFE0 -415D: 0C 01 00 24 ADD:G.W #H'0100, R4 -4161: 18 BF E0 JSR @loc_BFE0 -4164: 0C 01 00 24 ADD:G.W #H'0100, R4 -4168: 18 BF E0 JSR @loc_BFE0 -416B: 0C 01 00 24 ADD:G.W #H'0100, R4 -416F: 18 BF E0 JSR @loc_BFE0 -4172: 0C 01 00 24 ADD:G.W #H'0100, R4 -4176: 18 BF E0 JSR @loc_BFE0 -4179: 0C 01 00 24 ADD:G.W #H'0100, R4 -417D: 18 BF E0 JSR @loc_BFE0 -4180: CF 80 MOV:G.W @R7+, R0 -4182: 26 82 BNE loc_4106 -4184: 58 00 0F MOV:I.W #H'000F, R0 +4106: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +4108: F8 C9 64 85 MOV:G.W @(-H'369C,R0), R5 ; cycles=7 +410C: F8 F4 00 95 MOV:G.W R5, @(-H'0C00,R0) ; cycles=7 +4110: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +4112: A8 84 MOV:G.W R0, R4 ; cycles=3 +4114: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4117: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +411B: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +411E: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4122: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4125: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4129: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +412C: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4130: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4133: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4137: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +413A: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +413E: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4141: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4145: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4148: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +414C: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +414F: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4153: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4156: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +415A: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +415D: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4161: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4164: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4168: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +416B: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +416F: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4172: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4176: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4179: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +417D: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4180: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +4182: 26 82 BNE loc_4106 ; cycles=3/7 nt/t +4184: 58 00 0F MOV:I.W #H'000F, R0 ; cycles=3 loc_4187: -4187: BF 90 MOV:G.W R0, @-R7 -4189: A8 84 MOV:G.W R0, R4 -418B: A4 10 SWAP.B R4 -418D: 5D 20 20 MOV:I.W #H'2020, R5 -4190: 18 BF E0 JSR @loc_BFE0 -4193: AC 09 ADD:Q.W #2, R4 -4195: 5D 20 20 MOV:I.W #H'2020, R5 -4198: 18 BF E0 JSR @loc_BFE0 -419B: AC 09 ADD:Q.W #2, R4 -419D: 5D 20 20 MOV:I.W #H'2020, R5 -41A0: 18 BF E0 JSR @loc_BFE0 -41A3: AC 09 ADD:Q.W #2, R4 -41A5: 5D 20 20 MOV:I.W #H'2020, R5 -41A8: 18 BF E0 JSR @loc_BFE0 -41AB: CF 80 MOV:G.W @R7+, R0 -41AD: 01 B8 D7 SCB/F R0, loc_4187 +4187: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +4189: A8 84 MOV:G.W R0, R4 ; cycles=3 +418B: A4 10 SWAP.B R4 ; cycles=3 +418D: 5D 20 20 MOV:I.W #H'2020, R5 ; cycles=3 +4190: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4193: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4195: 5D 20 20 MOV:I.W #H'2020, R5 ; cycles=3 +4198: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +419B: AC 09 ADD:Q.W #2, R4 ; cycles=4 +419D: 5D 20 20 MOV:I.W #H'2020, R5 ; cycles=3 +41A0: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41A3: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41A5: 5D 20 20 MOV:I.W #H'2020, R5 ; cycles=3 +41A8: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41AB: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +41AD: 01 B8 D7 SCB/F R0, loc_4187 ; cycles=3/4/9 false/-1/t loc_41B0: -41B0: 20 20 BRA loc_41D2 +41B0: 20 20 BRA loc_41D2 ; cycles=7 loc_41D2: -41D2: 58 00 0F MOV:I.W #H'000F, R0 +41D2: 58 00 0F MOV:I.W #H'000F, R0 ; cycles=3 loc_41D5: -41D5: A8 81 MOV:G.W R0, R1 -41D7: A1 1A SHLL.B R1 -41D9: A1 1A SHLL.B R1 -41DB: A1 1A SHLL.B R1 -41DD: A8 84 MOV:G.W R0, R4 -41DF: A4 10 SWAP.B R4 -41E1: 12 03 STM.W {R0,R1}, @-SP -41E3: 18 BF FE JSR @loc_BFFE -41E6: 02 03 LDM.W @SP+, {R0,R1} -41E8: F9 F7 B0 95 MOV:G.W R5, @(-H'0850,R1) -41EC: AC 09 ADD:Q.W #2, R4 -41EE: 12 03 STM.W {R0,R1}, @-SP -41F0: 18 BF FE JSR @loc_BFFE -41F3: 02 03 LDM.W @SP+, {R0,R1} -41F5: F9 F7 B2 95 MOV:G.W R5, @(-H'084E,R1) -41F9: AC 09 ADD:Q.W #2, R4 -41FB: 12 03 STM.W {R0,R1}, @-SP -41FD: 18 BF FE JSR @loc_BFFE -4200: 02 03 LDM.W @SP+, {R0,R1} -4202: F9 F7 B4 95 MOV:G.W R5, @(-H'084C,R1) -4206: AC 09 ADD:Q.W #2, R4 -4208: 12 03 STM.W {R0,R1}, @-SP -420A: 18 BF FE JSR @loc_BFFE -420D: 02 03 LDM.W @SP+, {R0,R1} -420F: F9 F7 B6 95 MOV:G.W R5, @(-H'084A,R1) -4213: 01 B8 BF SCB/F R0, loc_41D5 -4216: 19 RTS +41D5: A8 81 MOV:G.W R0, R1 ; cycles=3 +41D7: A1 1A SHLL.B R1 ; cycles=2 +41D9: A1 1A SHLL.B R1 ; cycles=2 +41DB: A1 1A SHLL.B R1 ; cycles=2 +41DD: A8 84 MOV:G.W R0, R4 ; cycles=3 +41DF: A4 10 SWAP.B R4 ; cycles=3 +41E1: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41E3: 18 BF FE JSR @loc_BFFE ; cycles=14 +41E6: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41E8: F9 F7 B0 95 MOV:G.W R5, @(-H'0850,R1) ; cycles=7 +41EC: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41EE: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41F0: 18 BF FE JSR @loc_BFFE ; cycles=13 +41F3: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41F5: F9 F7 B2 95 MOV:G.W R5, @(-H'084E,R1) ; cycles=6 +41F9: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41FB: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41FD: 18 BF FE JSR @loc_BFFE ; cycles=14 +4200: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +4202: F9 F7 B4 95 MOV:G.W R5, @(-H'084C,R1) ; cycles=7 +4206: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4208: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +420A: 18 BF FE JSR @loc_BFFE ; cycles=13 +420D: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +420F: F9 F7 B6 95 MOV:G.W R5, @(-H'084A,R1) ; cycles=6 +4213: 01 B8 BF SCB/F R0, loc_41D5 ; cycles=3/4/9 false/-1/t +4216: 19 RTS ; cycles=12 loc_4217: -4217: 15 F7 98 13 CLR.B @H'F798 ; refs H'F798 in on_chip_ram -421B: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs H'F731 in on_chip_ram -421F: 15 FE 82 D2 BCLR.B #2, @P1DR ; clear bit 2 of P1DR -4223: 1D F7 00 07 24 24 MOV:G.W #H'2424, @H'F700 ; refs H'F700 in on_chip_ram -4229: 1D F7 02 07 24 24 MOV:G.W #H'2424, @H'F702 ; refs H'F702 in on_chip_ram -422F: 1D F7 04 07 24 24 MOV:G.W #H'2424, @H'F704 ; refs H'F704 in on_chip_ram -4235: 1D F7 06 07 24 24 MOV:G.W #H'2424, @H'F706 ; refs H'F706 in on_chip_ram -423B: 15 F7 08 06 7F MOV:G.B #H'7F, @H'F708 ; refs H'F708 in on_chip_ram -4240: 15 F7 09 06 24 MOV:G.B #H'24, @H'F709 ; refs H'F709 in on_chip_ram -4245: 1D F7 0A 07 24 24 MOV:G.W #H'2424, @H'F70A ; refs H'F70A in on_chip_ram -424B: 15 F7 10 13 CLR.B @H'F710 ; refs H'F710 in on_chip_ram -424F: 15 F7 11 13 CLR.B @H'F711 ; refs H'F711 in on_chip_ram -4253: 15 F7 12 13 CLR.B @H'F712 ; refs H'F712 in on_chip_ram -4257: 15 F7 13 13 CLR.B @H'F713 ; refs H'F713 in on_chip_ram -425B: 15 F7 14 13 CLR.B @H'F714 ; refs H'F714 in on_chip_ram -425F: 15 F7 15 13 CLR.B @H'F715 ; refs H'F715 in on_chip_ram -4263: 15 F7 16 13 CLR.B @H'F716 ; refs H'F716 in on_chip_ram -4267: 15 F7 17 13 CLR.B @H'F717 ; refs H'F717 in on_chip_ram -426B: 15 F7 18 06 FF MOV:G.B #H'FF, @H'F718 ; refs H'F718 in on_chip_ram -4270: 15 F7 19 06 FF MOV:G.B #H'FF, @H'F719 ; refs H'F719 in on_chip_ram -4275: 15 F7 1A 06 FF MOV:G.B #H'FF, @H'F71A ; refs H'F71A in on_chip_ram -427A: 15 F7 1B 06 FF MOV:G.B #H'FF, @H'F71B ; refs H'F71B in on_chip_ram -427F: 15 F7 1C 06 FF MOV:G.B #H'FF, @H'F71C ; refs H'F71C in on_chip_ram -4284: 15 F7 1D 06 FF MOV:G.B #H'FF, @H'F71D ; refs H'F71D in on_chip_ram -4289: 15 F7 1E 06 FF MOV:G.B #H'FF, @H'F71E ; refs H'F71E in on_chip_ram -428E: 15 F7 1F 06 FF MOV:G.B #H'FF, @H'F71F ; refs H'F71F in on_chip_ram -4293: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs H'FAF0 in on_chip_ram -4299: 1D FA F2 07 4F 4E MOV:G.W #H'4F4E, @H'FAF2 ; refs H'FAF2 in on_chip_ram -429F: 1D FA F4 07 4E 45 MOV:G.W #H'4E45, @H'FAF4 ; refs H'FAF4 in on_chip_ram -42A5: 1D FA F6 07 43 54 MOV:G.W #H'4354, @H'FAF6 ; refs H'FAF6 in on_chip_ram -42AB: 1D FA F8 07 3A 4E MOV:G.W #H'3A4E, @H'FAF8 ; refs H'FAF8 in on_chip_ram -42B1: 1D FA FA 07 4F 54 MOV:G.W #H'4F54, @H'FAFA ; refs H'FAFA in on_chip_ram -42B7: 1D FA FC 07 20 41 MOV:G.W #H'2041, @H'FAFC ; refs H'FAFC in on_chip_ram -42BD: 1D FA FE 07 43 54 MOV:G.W #H'4354, @H'FAFE ; refs H'FAFE in on_chip_ram -42C3: 5D 00 00 MOV:I.W #H'0000, R5 -42C6: 1E FC 03 BSR loc_3ECC -42C9: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs H'FAF0 in on_chip_ram -42CF: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs H'FAF2 in on_chip_ram -42D5: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs H'FAF4 in on_chip_ram -42DB: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs H'FAF6 in on_chip_ram -42E1: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs H'FAF8 in on_chip_ram -42E7: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs H'FAFA in on_chip_ram -42ED: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs H'FAFC in on_chip_ram -42F3: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs H'FAFE in on_chip_ram -42F9: 5D 00 01 MOV:I.W #H'0001, R5 -42FC: 1E FB CD BSR loc_3ECC -42FF: 5D 00 02 MOV:I.W #H'0002, R5 -4302: 1E FB C7 BSR loc_3ECC -4305: 5D 00 03 MOV:I.W #H'0003, R5 -4308: 1E FB C1 BSR loc_3ECC -430B: 19 RTS +4217: 15 F7 98 13 CLR.B @H'F798 ; refs H'F798 in on_chip_ram; cycles=8 +421B: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs H'F731 in on_chip_ram; cycles=8 +421F: 15 FE 82 D2 BCLR.B #2, @P1DR ; clear bit 2 of P1DR; cycles=8 +4223: 1D F7 00 07 24 24 MOV:G.W #H'2424, @H'F700 ; refs H'F700 in on_chip_ram; cycles=9 +4229: 1D F7 02 07 24 24 MOV:G.W #H'2424, @H'F702 ; refs H'F702 in on_chip_ram; cycles=9 +422F: 1D F7 04 07 24 24 MOV:G.W #H'2424, @H'F704 ; refs H'F704 in on_chip_ram; cycles=9 +4235: 1D F7 06 07 24 24 MOV:G.W #H'2424, @H'F706 ; refs H'F706 in on_chip_ram; cycles=9 +423B: 15 F7 08 06 7F MOV:G.B #H'7F, @H'F708 ; refs H'F708 in on_chip_ram; cycles=9 +4240: 15 F7 09 06 24 MOV:G.B #H'24, @H'F709 ; refs H'F709 in on_chip_ram; cycles=9 +4245: 1D F7 0A 07 24 24 MOV:G.W #H'2424, @H'F70A ; refs H'F70A in on_chip_ram; cycles=9 +424B: 15 F7 10 13 CLR.B @H'F710 ; refs H'F710 in on_chip_ram; cycles=8 +424F: 15 F7 11 13 CLR.B @H'F711 ; refs H'F711 in on_chip_ram; cycles=8 +4253: 15 F7 12 13 CLR.B @H'F712 ; refs H'F712 in on_chip_ram; cycles=8 +4257: 15 F7 13 13 CLR.B @H'F713 ; refs H'F713 in on_chip_ram; cycles=8 +425B: 15 F7 14 13 CLR.B @H'F714 ; refs H'F714 in on_chip_ram; cycles=8 +425F: 15 F7 15 13 CLR.B @H'F715 ; refs H'F715 in on_chip_ram; cycles=8 +4263: 15 F7 16 13 CLR.B @H'F716 ; refs H'F716 in on_chip_ram; cycles=8 +4267: 15 F7 17 13 CLR.B @H'F717 ; refs H'F717 in on_chip_ram; cycles=8 +426B: 15 F7 18 06 FF MOV:G.B #H'FF, @H'F718 ; refs H'F718 in on_chip_ram; cycles=9 +4270: 15 F7 19 06 FF MOV:G.B #H'FF, @H'F719 ; refs H'F719 in on_chip_ram; cycles=9 +4275: 15 F7 1A 06 FF MOV:G.B #H'FF, @H'F71A ; refs H'F71A in on_chip_ram; cycles=9 +427A: 15 F7 1B 06 FF MOV:G.B #H'FF, @H'F71B ; refs H'F71B in on_chip_ram; cycles=9 +427F: 15 F7 1C 06 FF MOV:G.B #H'FF, @H'F71C ; refs H'F71C in on_chip_ram; cycles=9 +4284: 15 F7 1D 06 FF MOV:G.B #H'FF, @H'F71D ; refs H'F71D in on_chip_ram; cycles=9 +4289: 15 F7 1E 06 FF MOV:G.B #H'FF, @H'F71E ; refs H'F71E in on_chip_ram; cycles=9 +428E: 15 F7 1F 06 FF MOV:G.B #H'FF, @H'F71F ; refs H'F71F in on_chip_ram; cycles=9 +4293: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs H'FAF0 in on_chip_ram; cycles=9 +4299: 1D FA F2 07 4F 4E MOV:G.W #H'4F4E, @H'FAF2 ; refs H'FAF2 in on_chip_ram; cycles=9 +429F: 1D FA F4 07 4E 45 MOV:G.W #H'4E45, @H'FAF4 ; refs H'FAF4 in on_chip_ram; cycles=9 +42A5: 1D FA F6 07 43 54 MOV:G.W #H'4354, @H'FAF6 ; refs H'FAF6 in on_chip_ram; cycles=9 +42AB: 1D FA F8 07 3A 4E MOV:G.W #H'3A4E, @H'FAF8 ; refs H'FAF8 in on_chip_ram; cycles=9 +42B1: 1D FA FA 07 4F 54 MOV:G.W #H'4F54, @H'FAFA ; refs H'FAFA in on_chip_ram; cycles=9 +42B7: 1D FA FC 07 20 41 MOV:G.W #H'2041, @H'FAFC ; refs H'FAFC in on_chip_ram; cycles=9 +42BD: 1D FA FE 07 43 54 MOV:G.W #H'4354, @H'FAFE ; refs H'FAFE in on_chip_ram; cycles=9 +42C3: 5D 00 00 MOV:I.W #H'0000, R5 ; cycles=3 +42C6: 1E FC 03 BSR loc_3ECC ; cycles=13 +42C9: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs H'FAF0 in on_chip_ram; cycles=9 +42CF: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs H'FAF2 in on_chip_ram; cycles=9 +42D5: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs H'FAF4 in on_chip_ram; cycles=9 +42DB: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs H'FAF6 in on_chip_ram; cycles=9 +42E1: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs H'FAF8 in on_chip_ram; cycles=9 +42E7: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs H'FAFA in on_chip_ram; cycles=9 +42ED: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs H'FAFC in on_chip_ram; cycles=9 +42F3: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs H'FAFE in on_chip_ram; cycles=9 +42F9: 5D 00 01 MOV:I.W #H'0001, R5 ; cycles=3 +42FC: 1E FB CD BSR loc_3ECC ; cycles=13 +42FF: 5D 00 02 MOV:I.W #H'0002, R5 ; cycles=3 +4302: 1E FB C7 BSR loc_3ECC ; cycles=13 +4305: 5D 00 03 MOV:I.W #H'0003, R5 ; cycles=3 +4308: 1E FB C1 BSR loc_3ECC ; cycles=13 +430B: 19 RTS ; cycles=13 loc_430C: -430C: 15 FE 8B D0 BCLR.B #0, @P6DR ; clear bit 0 of P6DR -4310: 15 F5 55 06 AA MOV:G.B #H'AA, @H'F555 ; refs H'F555 in program_or_external -4315: 15 F4 AA 06 55 MOV:G.B #H'55, @H'F4AA ; refs H'F4AA in program_or_external -431A: 15 F5 55 06 CC MOV:G.B #H'CC, @H'F555 ; refs H'F555 in program_or_external -431F: 15 FE 8B C0 BSET.B #0, @P6DR ; set bit 0 of P6DR -4323: 19 RTS +430C: 15 FE 8B D0 BCLR.B #0, @P6DR ; clear bit 0 of P6DR; cycles=9 +4310: 15 F5 55 06 AA MOV:G.B #H'AA, @H'F555 ; refs H'F555 in program_or_external; cycles=9 +4315: 15 F4 AA 06 55 MOV:G.B #H'55, @H'F4AA ; refs H'F4AA in program_or_external; cycles=9 +431A: 15 F5 55 06 CC MOV:G.B #H'CC, @H'F555 ; refs H'F555 in program_or_external; cycles=9 +431F: 15 FE 8B C0 BSET.B #0, @P6DR ; set bit 0 of P6DR; cycles=8 +4323: 19 RTS ; cycles=13 loc_4324: -4324: 5C 00 38 MOV:I.W #H'0038, R4 -4327: 5D 00 04 MOV:I.W #H'0004, R5 -432A: 1E FB 9F BSR loc_3ECC -432D: 5C 00 01 MOV:I.W #H'0001, R4 -4330: 5D 00 04 MOV:I.W #H'0004, R5 -4333: 1E FB 96 BSR loc_3ECC -4336: 5C 00 0E MOV:I.W #H'000E, R4 -4339: 5D 00 04 MOV:I.W #H'0004, R5 -433C: 1E FB 8D BSR loc_3ECC -433F: 5C 00 06 MOV:I.W #H'0006, R4 -4342: 5D 00 04 MOV:I.W #H'0004, R5 -4345: 1E FB 84 BSR loc_3ECC -4348: 1E CD 83 BSR loc_10CE -434B: 19 RTS +4324: 5C 00 38 MOV:I.W #H'0038, R4 ; cycles=3 +4327: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +432A: 1E FB 9F BSR loc_3ECC ; cycles=13 +432D: 5C 00 01 MOV:I.W #H'0001, R4 ; cycles=3 +4330: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +4333: 1E FB 96 BSR loc_3ECC ; cycles=14 +4336: 5C 00 0E MOV:I.W #H'000E, R4 ; cycles=3 +4339: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +433C: 1E FB 8D BSR loc_3ECC ; cycles=13 +433F: 5C 00 06 MOV:I.W #H'0006, R4 ; cycles=3 +4342: 5D 00 04 MOV:I.W #H'0004, R5 ; cycles=3 +4345: 1E FB 84 BSR loc_3ECC ; cycles=14 +4348: 1E CD 83 BSR loc_10CE ; cycles=13 +434B: 19 RTS ; cycles=13 loc_434C: -434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70 -4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44 -4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66 -435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00 -4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50 -4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40 -436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR -436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR -4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR -4376: 15 FE E8 C6 BSET.B #6, @ADCSR ; set ADIE (bit 6) of ADCSR -437A: 15 FE FD C4 BSET.B #4, @SYSCR2 ; set IRQ3E (bit 4) of SYSCR2 -437E: 15 FE FD C5 BSET.B #5, @SYSCR2 ; set IRQ4E (bit 5) of SYSCR2 -4382: 15 FE 8E F6 BTST.B #6, @P7DR ; refs P7DR in register_field -4386: 27 06 BEQ loc_438E -4388: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096) +434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70; cycles=9 +4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44; cycles=9 +4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66; cycles=9 +435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00; cycles=9 +4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50; cycles=9 +4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40; cycles=9 +436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR; cycles=9 +436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR; cycles=9 +4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR; cycles=9 +4376: 15 FE E8 C6 BSET.B #6, @ADCSR ; set ADIE (bit 6) of ADCSR; cycles=9 +437A: 15 FE FD C4 BSET.B #4, @SYSCR2 ; set IRQ3E (bit 4) of SYSCR2; cycles=9 +437E: 15 FE FD C5 BSET.B #5, @SYSCR2 ; set IRQ4E (bit 5) of SYSCR2; cycles=9 +4382: 15 FE 8E F6 BTST.B #6, @P7DR ; refs P7DR in register_field; cycles=7 +4386: 27 06 BEQ loc_438E ; cycles=3/7 nt/t +4388: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 loc_438E: -438E: 0C 03 00 88 LDC.W #H'0300, SR -4392: 19 RTS +438E: 0C 03 00 88 LDC.W #H'0300, SR ; cycles=6 +4392: 19 RTS ; cycles=12 vec_nmi_4393: -4393: 0A RTE +4393: 0A RTE ; cycles=14 loc_4394: -4394: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs H'F731 in on_chip_ram -4399: 32 00 86 BHI loc_4422 -439C: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -43A0: 36 00 7F BNE loc_4422 -43A3: 1D F7 36 83 MOV:G.W @H'F736, R3 ; refs H'F736 in on_chip_ram -43A7: 37 00 78 BEQ loc_4422 -43AA: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs H'F69E in on_chip_ram -43AE: 1D F6 BE 34 SUB.W @H'F6BE, R4 ; refs H'F6BE in on_chip_ram -43B2: AB DF BCLR.W #15, R3 -43B4: 26 19 BNE loc_43CF -43B6: AB DE BCLR.W #14, R3 -43B8: 26 21 BNE loc_43DB -43BA: AB DD BCLR.W #13, R3 -43BC: 26 29 BNE loc_43E7 -43BE: AB DC BCLR.W #12, R3 -43C0: 26 31 BNE loc_43F3 -43C2: AB DB BCLR.W #11, R3 -43C4: 26 39 BNE loc_43FF -43C6: AB DA BCLR.W #10, R3 -43C8: 26 43 BNE loc_440D -43CA: 1E D5 D5 BSR loc_19A2 -43CD: 20 53 BRA loc_4422 +4394: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs H'F731 in on_chip_ram; cycles=7 +4399: 32 00 86 BHI loc_4422 ; cycles=3/8 nt/t +439C: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=7 +43A0: 36 00 7F BNE loc_4422 ; cycles=3/7 nt/t +43A3: 1D F7 36 83 MOV:G.W @H'F736, R3 ; refs H'F736 in on_chip_ram; cycles=6 +43A7: 37 00 78 BEQ loc_4422 ; cycles=3/8 nt/t +43AA: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs H'F69E in on_chip_ram; cycles=7 +43AE: 1D F6 BE 34 SUB.W @H'F6BE, R4 ; refs H'F6BE in on_chip_ram; cycles=7 +43B2: AB DF BCLR.W #15, R3 ; cycles=3 +43B4: 26 19 BNE loc_43CF ; cycles=3/7 nt/t +43B6: AB DE BCLR.W #14, R3 ; cycles=3 +43B8: 26 21 BNE loc_43DB ; cycles=3/7 nt/t +43BA: AB DD BCLR.W #13, R3 ; cycles=3 +43BC: 26 29 BNE loc_43E7 ; cycles=3/7 nt/t +43BE: AB DC BCLR.W #12, R3 ; cycles=3 +43C0: 26 31 BNE loc_43F3 ; cycles=3/7 nt/t +43C2: AB DB BCLR.W #11, R3 ; cycles=3 +43C4: 26 39 BNE loc_43FF ; cycles=3/7 nt/t +43C6: AB DA BCLR.W #10, R3 ; cycles=3 +43C8: 26 43 BNE loc_440D ; cycles=3/7 nt/t +43CA: 1E D5 D5 BSR loc_19A2 ; cycles=13 +43CD: 20 53 BRA loc_4422 ; cycles=8 loc_43CF: -43CF: 0E 5E BSR loc_442F -43D1: 4C 00 02 CMP:I #H'0002, R4 -43D4: 27 03 BEQ loc_43D9 -43D6: 1E D6 5C BSR loc_1A35 +43CF: 0E 5E BSR loc_442F ; cycles=14 +43D1: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43D4: 27 03 BEQ loc_43D9 ; cycles=3/7 nt/t +43D6: 1E D6 5C BSR loc_1A35 ; cycles=13 loc_43D9: -43D9: 20 47 BRA loc_4422 +43D9: 20 47 BRA loc_4422 ; cycles=8 loc_43DB: -43DB: 0E 52 BSR loc_442F -43DD: 4C 00 02 CMP:I #H'0002, R4 -43E0: 27 03 BEQ loc_43E5 -43E2: 1E D6 B7 BSR loc_1A9C +43DB: 0E 52 BSR loc_442F ; cycles=14 +43DD: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43E0: 27 03 BEQ loc_43E5 ; cycles=3/7 nt/t +43E2: 1E D6 B7 BSR loc_1A9C ; cycles=13 loc_43E5: -43E5: 20 3B BRA loc_4422 +43E5: 20 3B BRA loc_4422 ; cycles=8 loc_43E7: -43E7: 0E 46 BSR loc_442F -43E9: 4C 00 02 CMP:I #H'0002, R4 -43EC: 27 03 BEQ loc_43F1 -43EE: 1E D6 F3 BSR loc_1AE4 +43E7: 0E 46 BSR loc_442F ; cycles=14 +43E9: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43EC: 27 03 BEQ loc_43F1 ; cycles=3/7 nt/t +43EE: 1E D6 F3 BSR loc_1AE4 ; cycles=13 loc_43F1: -43F1: 20 2F BRA loc_4422 +43F1: 20 2F BRA loc_4422 ; cycles=8 loc_43F3: -43F3: 0E 3A BSR loc_442F -43F5: 4C 00 02 CMP:I #H'0002, R4 -43F8: 27 03 BEQ loc_43FD -43FA: 1E D7 0E BSR loc_1B0B +43F3: 0E 3A BSR loc_442F ; cycles=14 +43F5: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43F8: 27 03 BEQ loc_43FD ; cycles=3/7 nt/t +43FA: 1E D7 0E BSR loc_1B0B ; cycles=13 loc_43FD: -43FD: 20 23 BRA loc_4422 +43FD: 20 23 BRA loc_4422 ; cycles=8 loc_43FF: -43FF: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs H'F770 in on_chip_ram -4404: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram -4408: 1E 04 EF BSR loc_48FA -440B: 20 15 BRA loc_4422 +43FF: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs H'F770 in on_chip_ram; cycles=9 +4404: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram; cycles=7 +4408: 1E 04 EF BSR loc_48FA ; cycles=13 +440B: 20 15 BRA loc_4422 ; cycles=8 loc_440D: -440D: 0E 20 BSR loc_442F -440F: 4C 00 02 CMP:I #H'0002, R4 -4412: 27 0C BEQ loc_4420 -4414: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs H'F770 in on_chip_ram -4419: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram -441D: 1E 04 DA BSR loc_48FA +440D: 0E 20 BSR loc_442F ; cycles=14 +440F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4412: 27 0C BEQ loc_4420 ; cycles=3/7 nt/t +4414: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs H'F770 in on_chip_ram; cycles=9 +4419: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram; cycles=6 +441D: 1E 04 DA BSR loc_48FA ; cycles=14 loc_4420: -4420: 20 00 BRA loc_4422 +4420: 20 00 BRA loc_4422 ; cycles=7 loc_4422: -4422: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs H'F69E in on_chip_ram -4426: 1D F6 BE 94 MOV:G.W R4, @H'F6BE ; refs H'F6BE in on_chip_ram -442A: 15 FB 02 13 CLR.B @H'FB02 ; refs H'FB02 in on_chip_ram -442E: 19 RTS +4422: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs H'F69E in on_chip_ram; cycles=7 +4426: 1D F6 BE 94 MOV:G.W R4, @H'F6BE ; refs H'F6BE in on_chip_ram; cycles=7 +442A: 15 FB 02 13 CLR.B @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=9 +442E: 19 RTS ; cycles=12 loc_442F: -442F: 15 F6 F7 24 ADD:G.B @H'F6F7, R4 ; refs H'F6F7 in on_chip_ram -4433: 44 88 CMP:E #H'88, R4 -4435: 24 0D BCC loc_4444 -4437: 44 78 CMP:E #H'78, R4 -4439: 23 13 BLS loc_444E -443B: 15 F6 F7 94 MOV:G.B R4, @H'F6F7 ; refs H'F6F7 in on_chip_ram -443F: 5C 00 02 MOV:I.W #H'0002, R4 -4442: 20 12 BRA loc_4456 +442F: 15 F6 F7 24 ADD:G.B @H'F6F7, R4 ; refs H'F6F7 in on_chip_ram; cycles=6 +4433: 44 88 CMP:E #H'88, R4 ; cycles=2 +4435: 24 0D BCC loc_4444 ; cycles=3/8 nt/t +4437: 44 78 CMP:E #H'78, R4 ; cycles=2 +4439: 23 13 BLS loc_444E ; cycles=3/8 nt/t +443B: 15 F6 F7 94 MOV:G.B R4, @H'F6F7 ; refs H'F6F7 in on_chip_ram; cycles=6 +443F: 5C 00 02 MOV:I.W #H'0002, R4 ; cycles=3 +4442: 20 12 BRA loc_4456 ; cycles=7 loc_4444: -4444: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs H'F6F7 in on_chip_ram -4449: 5C 00 00 MOV:I.W #H'0000, R4 -444C: 20 08 BRA loc_4456 +4444: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs H'F6F7 in on_chip_ram; cycles=9 +4449: 5C 00 00 MOV:I.W #H'0000, R4 ; cycles=3 +444C: 20 08 BRA loc_4456 ; cycles=7 loc_444E: -444E: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs H'F6F7 in on_chip_ram -4453: 5C 00 01 MOV:I.W #H'0001, R4 +444E: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs H'F6F7 in on_chip_ram; cycles=9 +4453: 5C 00 01 MOV:I.W #H'0001, R4 ; cycles=3 loc_4456: -4456: 19 RTS +4456: 19 RTS ; cycles=12 loc_4457: -4457: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs H'F731 in on_chip_ram -445C: 32 00 86 BHI loc_44E5 -445F: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -4463: 36 00 7F BNE loc_44E5 -4466: 1D F7 38 83 MOV:G.W @H'F738, R3 ; refs H'F738 in on_chip_ram -446A: 37 00 78 BEQ loc_44E5 -446D: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs H'F69C in on_chip_ram -4471: 1D F6 BC 34 SUB.W @H'F6BC, R4 ; refs H'F6BC in on_chip_ram -4475: AB DF BCLR.W #15, R3 -4477: 26 19 BNE loc_4492 -4479: AB DE BCLR.W #14, R3 -447B: 26 21 BNE loc_449E -447D: AB DD BCLR.W #13, R3 -447F: 26 29 BNE loc_44AA -4481: AB DC BCLR.W #12, R3 -4483: 26 31 BNE loc_44B6 -4485: AB DB BCLR.W #11, R3 -4487: 26 39 BNE loc_44C2 -4489: AB DA BCLR.W #10, R3 -448B: 26 43 BNE loc_44D0 -448D: 1E D5 12 BSR loc_19A2 -4490: 20 53 BRA loc_44E5 +4457: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs H'F731 in on_chip_ram; cycles=6 +445C: 32 00 86 BHI loc_44E5 ; cycles=3/7 nt/t +445F: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=6 +4463: 36 00 7F BNE loc_44E5 ; cycles=3/8 nt/t +4466: 1D F7 38 83 MOV:G.W @H'F738, R3 ; refs H'F738 in on_chip_ram; cycles=7 +446A: 37 00 78 BEQ loc_44E5 ; cycles=3/7 nt/t +446D: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs H'F69C in on_chip_ram; cycles=6 +4471: 1D F6 BC 34 SUB.W @H'F6BC, R4 ; refs H'F6BC in on_chip_ram; cycles=6 +4475: AB DF BCLR.W #15, R3 ; cycles=3 +4477: 26 19 BNE loc_4492 ; cycles=3/8 nt/t +4479: AB DE BCLR.W #14, R3 ; cycles=3 +447B: 26 21 BNE loc_449E ; cycles=3/8 nt/t +447D: AB DD BCLR.W #13, R3 ; cycles=3 +447F: 26 29 BNE loc_44AA ; cycles=3/8 nt/t +4481: AB DC BCLR.W #12, R3 ; cycles=3 +4483: 26 31 BNE loc_44B6 ; cycles=3/8 nt/t +4485: AB DB BCLR.W #11, R3 ; cycles=3 +4487: 26 39 BNE loc_44C2 ; cycles=3/8 nt/t +4489: AB DA BCLR.W #10, R3 ; cycles=3 +448B: 26 43 BNE loc_44D0 ; cycles=3/8 nt/t +448D: 1E D5 12 BSR loc_19A2 ; cycles=14 +4490: 20 53 BRA loc_44E5 ; cycles=7 loc_4492: -4492: 0E 5E BSR loc_44F2 -4494: 4C 00 02 CMP:I #H'0002, R4 -4497: 27 03 BEQ loc_449C -4499: 1E D5 99 BSR loc_1A35 +4492: 0E 5E BSR loc_44F2 ; cycles=13 +4494: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4497: 27 03 BEQ loc_449C ; cycles=3/8 nt/t +4499: 1E D5 99 BSR loc_1A35 ; cycles=14 loc_449C: -449C: 20 47 BRA loc_44E5 +449C: 20 47 BRA loc_44E5 ; cycles=7 loc_449E: -449E: 0E 52 BSR loc_44F2 -44A0: 4C 00 02 CMP:I #H'0002, R4 -44A3: 27 03 BEQ loc_44A8 -44A5: 1E D5 F4 BSR loc_1A9C +449E: 0E 52 BSR loc_44F2 ; cycles=13 +44A0: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44A3: 27 03 BEQ loc_44A8 ; cycles=3/8 nt/t +44A5: 1E D5 F4 BSR loc_1A9C ; cycles=14 loc_44A8: -44A8: 20 3B BRA loc_44E5 +44A8: 20 3B BRA loc_44E5 ; cycles=7 loc_44AA: -44AA: 0E 46 BSR loc_44F2 -44AC: 4C 00 02 CMP:I #H'0002, R4 -44AF: 27 03 BEQ loc_44B4 -44B1: 1E D6 30 BSR loc_1AE4 +44AA: 0E 46 BSR loc_44F2 ; cycles=13 +44AC: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44AF: 27 03 BEQ loc_44B4 ; cycles=3/8 nt/t +44B1: 1E D6 30 BSR loc_1AE4 ; cycles=14 loc_44B4: -44B4: 20 2F BRA loc_44E5 +44B4: 20 2F BRA loc_44E5 ; cycles=7 loc_44B6: -44B6: 0E 3A BSR loc_44F2 -44B8: 4C 00 02 CMP:I #H'0002, R4 -44BB: 27 03 BEQ loc_44C0 -44BD: 1E D6 4B BSR loc_1B0B +44B6: 0E 3A BSR loc_44F2 ; cycles=13 +44B8: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44BB: 27 03 BEQ loc_44C0 ; cycles=3/8 nt/t +44BD: 1E D6 4B BSR loc_1B0B ; cycles=14 loc_44C0: -44C0: 20 23 BRA loc_44E5 +44C0: 20 23 BRA loc_44E5 ; cycles=7 loc_44C2: -44C2: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs H'F770 in on_chip_ram -44C7: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram -44CB: 1E 04 2C BSR loc_48FA -44CE: 20 15 BRA loc_44E5 +44C2: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs H'F770 in on_chip_ram; cycles=9 +44C7: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram; cycles=6 +44CB: 1E 04 2C BSR loc_48FA ; cycles=14 +44CE: 20 15 BRA loc_44E5 ; cycles=7 loc_44D0: -44D0: 0E 20 BSR loc_44F2 -44D2: 4C 00 02 CMP:I #H'0002, R4 -44D5: 27 0C BEQ loc_44E3 -44D7: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs H'F770 in on_chip_ram -44DC: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram -44E0: 1E 04 17 BSR loc_48FA +44D0: 0E 20 BSR loc_44F2 ; cycles=13 +44D2: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44D5: 27 0C BEQ loc_44E3 ; cycles=3/8 nt/t +44D7: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs H'F770 in on_chip_ram; cycles=9 +44DC: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram; cycles=7 +44E0: 1E 04 17 BSR loc_48FA ; cycles=13 loc_44E3: -44E3: 20 00 BRA loc_44E5 +44E3: 20 00 BRA loc_44E5 ; cycles=8 loc_44E5: -44E5: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs H'F69C in on_chip_ram -44E9: 1D F6 BC 94 MOV:G.W R4, @H'F6BC ; refs H'F6BC in on_chip_ram -44ED: 15 FB 02 13 CLR.B @H'FB02 ; refs H'FB02 in on_chip_ram -44F1: 19 RTS +44E5: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs H'F69C in on_chip_ram; cycles=6 +44E9: 1D F6 BC 94 MOV:G.W R4, @H'F6BC ; refs H'F6BC in on_chip_ram; cycles=6 +44ED: 15 FB 02 13 CLR.B @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=8 +44F1: 19 RTS ; cycles=13 loc_44F2: -44F2: 15 F6 F8 24 ADD:G.B @H'F6F8, R4 ; refs H'F6F8 in on_chip_ram -44F6: 44 88 CMP:E #H'88, R4 -44F8: 24 0D BCC loc_4507 -44FA: 44 78 CMP:E #H'78, R4 -44FC: 23 13 BLS loc_4511 -44FE: 15 F6 F8 94 MOV:G.B R4, @H'F6F8 ; refs H'F6F8 in on_chip_ram -4502: 5C 00 02 MOV:I.W #H'0002, R4 -4505: 20 12 BRA loc_4519 +44F2: 15 F6 F8 24 ADD:G.B @H'F6F8, R4 ; refs H'F6F8 in on_chip_ram; cycles=7 +44F6: 44 88 CMP:E #H'88, R4 ; cycles=2 +44F8: 24 0D BCC loc_4507 ; cycles=3/7 nt/t +44FA: 44 78 CMP:E #H'78, R4 ; cycles=2 +44FC: 23 13 BLS loc_4511 ; cycles=3/7 nt/t +44FE: 15 F6 F8 94 MOV:G.B R4, @H'F6F8 ; refs H'F6F8 in on_chip_ram; cycles=7 +4502: 5C 00 02 MOV:I.W #H'0002, R4 ; cycles=3 +4505: 20 12 BRA loc_4519 ; cycles=8 loc_4507: -4507: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs H'F6F8 in on_chip_ram -450C: 5C 00 00 MOV:I.W #H'0000, R4 -450F: 20 08 BRA loc_4519 +4507: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs H'F6F8 in on_chip_ram; cycles=9 +450C: 5C 00 00 MOV:I.W #H'0000, R4 ; cycles=3 +450F: 20 08 BRA loc_4519 ; cycles=8 loc_4511: -4511: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs H'F6F8 in on_chip_ram -4516: 5C 00 01 MOV:I.W #H'0001, R4 +4511: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs H'F6F8 in on_chip_ram; cycles=9 +4516: 5C 00 01 MOV:I.W #H'0001, R4 ; cycles=3 loc_4519: -4519: 19 RTS +4519: 19 RTS ; cycles=13 loc_451A: -451A: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs H'F731 in on_chip_ram -451F: 32 00 86 BHI loc_45A8 -4522: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -4526: 36 00 7F BNE loc_45A8 -4529: 1D F7 3A 83 MOV:G.W @H'F73A, R3 ; refs H'F73A in on_chip_ram -452D: 37 00 78 BEQ loc_45A8 -4530: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs H'F69A in on_chip_ram -4534: 1D F6 BA 34 SUB.W @H'F6BA, R4 ; refs H'F6BA in on_chip_ram -4538: AB DF BCLR.W #15, R3 -453A: 26 19 BNE loc_4555 -453C: AB DE BCLR.W #14, R3 -453E: 26 21 BNE loc_4561 -4540: AB DD BCLR.W #13, R3 -4542: 26 29 BNE loc_456D -4544: AB DC BCLR.W #12, R3 -4546: 26 31 BNE loc_4579 -4548: AB DB BCLR.W #11, R3 -454A: 26 39 BNE loc_4585 -454C: AB DA BCLR.W #10, R3 -454E: 26 43 BNE loc_4593 -4550: 1E D4 4F BSR loc_19A2 -4553: 20 53 BRA loc_45A8 +451A: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs H'F731 in on_chip_ram; cycles=7 +451F: 32 00 86 BHI loc_45A8 ; cycles=3/8 nt/t +4522: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=7 +4526: 36 00 7F BNE loc_45A8 ; cycles=3/7 nt/t +4529: 1D F7 3A 83 MOV:G.W @H'F73A, R3 ; refs H'F73A in on_chip_ram; cycles=6 +452D: 37 00 78 BEQ loc_45A8 ; cycles=3/8 nt/t +4530: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs H'F69A in on_chip_ram; cycles=7 +4534: 1D F6 BA 34 SUB.W @H'F6BA, R4 ; refs H'F6BA in on_chip_ram; cycles=7 +4538: AB DF BCLR.W #15, R3 ; cycles=3 +453A: 26 19 BNE loc_4555 ; cycles=3/7 nt/t +453C: AB DE BCLR.W #14, R3 ; cycles=3 +453E: 26 21 BNE loc_4561 ; cycles=3/7 nt/t +4540: AB DD BCLR.W #13, R3 ; cycles=3 +4542: 26 29 BNE loc_456D ; cycles=3/7 nt/t +4544: AB DC BCLR.W #12, R3 ; cycles=3 +4546: 26 31 BNE loc_4579 ; cycles=3/7 nt/t +4548: AB DB BCLR.W #11, R3 ; cycles=3 +454A: 26 39 BNE loc_4585 ; cycles=3/7 nt/t +454C: AB DA BCLR.W #10, R3 ; cycles=3 +454E: 26 43 BNE loc_4593 ; cycles=3/7 nt/t +4550: 1E D4 4F BSR loc_19A2 ; cycles=13 +4553: 20 53 BRA loc_45A8 ; cycles=8 loc_4555: -4555: 0E 5E BSR loc_45B5 -4557: 4C 00 02 CMP:I #H'0002, R4 -455A: 27 03 BEQ loc_455F -455C: 1E D4 D6 BSR loc_1A35 +4555: 0E 5E BSR loc_45B5 ; cycles=14 +4557: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +455A: 27 03 BEQ loc_455F ; cycles=3/7 nt/t +455C: 1E D4 D6 BSR loc_1A35 ; cycles=13 loc_455F: -455F: 20 47 BRA loc_45A8 +455F: 20 47 BRA loc_45A8 ; cycles=8 loc_4561: -4561: 0E 52 BSR loc_45B5 -4563: 4C 00 02 CMP:I #H'0002, R4 -4566: 27 03 BEQ loc_456B -4568: 1E D5 31 BSR loc_1A9C +4561: 0E 52 BSR loc_45B5 ; cycles=14 +4563: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4566: 27 03 BEQ loc_456B ; cycles=3/7 nt/t +4568: 1E D5 31 BSR loc_1A9C ; cycles=13 loc_456B: -456B: 20 3B BRA loc_45A8 +456B: 20 3B BRA loc_45A8 ; cycles=8 loc_456D: -456D: 0E 46 BSR loc_45B5 -456F: 4C 00 02 CMP:I #H'0002, R4 -4572: 27 03 BEQ loc_4577 -4574: 1E D5 6D BSR loc_1AE4 +456D: 0E 46 BSR loc_45B5 ; cycles=14 +456F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4572: 27 03 BEQ loc_4577 ; cycles=3/7 nt/t +4574: 1E D5 6D BSR loc_1AE4 ; cycles=13 loc_4577: -4577: 20 2F BRA loc_45A8 +4577: 20 2F BRA loc_45A8 ; cycles=8 loc_4579: -4579: 0E 3A BSR loc_45B5 -457B: 4C 00 02 CMP:I #H'0002, R4 -457E: 27 03 BEQ loc_4583 -4580: 1E D5 88 BSR loc_1B0B +4579: 0E 3A BSR loc_45B5 ; cycles=14 +457B: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +457E: 27 03 BEQ loc_4583 ; cycles=3/7 nt/t +4580: 1E D5 88 BSR loc_1B0B ; cycles=13 loc_4583: -4583: 20 23 BRA loc_45A8 +4583: 20 23 BRA loc_45A8 ; cycles=8 loc_4585: -4585: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs H'F770 in on_chip_ram -458A: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram -458E: 1E 03 69 BSR loc_48FA -4591: 20 15 BRA loc_45A8 +4585: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs H'F770 in on_chip_ram; cycles=9 +458A: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram; cycles=7 +458E: 1E 03 69 BSR loc_48FA ; cycles=13 +4591: 20 15 BRA loc_45A8 ; cycles=8 loc_4593: -4593: 0E 20 BSR loc_45B5 -4595: 4C 00 02 CMP:I #H'0002, R4 -4598: 27 0C BEQ loc_45A6 -459A: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs H'F770 in on_chip_ram -459F: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram -45A3: 1E 03 54 BSR loc_48FA +4593: 0E 20 BSR loc_45B5 ; cycles=14 +4595: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4598: 27 0C BEQ loc_45A6 ; cycles=3/7 nt/t +459A: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs H'F770 in on_chip_ram; cycles=9 +459F: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs H'F772 in on_chip_ram; cycles=6 +45A3: 1E 03 54 BSR loc_48FA ; cycles=14 loc_45A6: -45A6: 20 00 BRA loc_45A8 +45A6: 20 00 BRA loc_45A8 ; cycles=7 loc_45A8: -45A8: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs H'F69A in on_chip_ram -45AC: 1D F6 BA 94 MOV:G.W R4, @H'F6BA ; refs H'F6BA in on_chip_ram -45B0: 15 FB 02 13 CLR.B @H'FB02 ; refs H'FB02 in on_chip_ram -45B4: 19 RTS +45A8: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs H'F69A in on_chip_ram; cycles=7 +45AC: 1D F6 BA 94 MOV:G.W R4, @H'F6BA ; refs H'F6BA in on_chip_ram; cycles=7 +45B0: 15 FB 02 13 CLR.B @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=9 +45B4: 19 RTS ; cycles=12 loc_45B5: -45B5: 15 F6 F9 24 ADD:G.B @H'F6F9, R4 ; refs H'F6F9 in on_chip_ram -45B9: 44 88 CMP:E #H'88, R4 -45BB: 24 0D BCC loc_45CA -45BD: 44 78 CMP:E #H'78, R4 -45BF: 23 13 BLS loc_45D4 -45C1: 15 F6 F9 94 MOV:G.B R4, @H'F6F9 ; refs H'F6F9 in on_chip_ram -45C5: 5C 00 02 MOV:I.W #H'0002, R4 -45C8: 20 12 BRA loc_45DC +45B5: 15 F6 F9 24 ADD:G.B @H'F6F9, R4 ; refs H'F6F9 in on_chip_ram; cycles=6 +45B9: 44 88 CMP:E #H'88, R4 ; cycles=2 +45BB: 24 0D BCC loc_45CA ; cycles=3/8 nt/t +45BD: 44 78 CMP:E #H'78, R4 ; cycles=2 +45BF: 23 13 BLS loc_45D4 ; cycles=3/8 nt/t +45C1: 15 F6 F9 94 MOV:G.B R4, @H'F6F9 ; refs H'F6F9 in on_chip_ram; cycles=6 +45C5: 5C 00 02 MOV:I.W #H'0002, R4 ; cycles=3 +45C8: 20 12 BRA loc_45DC ; cycles=7 loc_45CA: -45CA: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs H'F6F9 in on_chip_ram -45CF: 5C 00 00 MOV:I.W #H'0000, R4 -45D2: 20 08 BRA loc_45DC +45CA: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs H'F6F9 in on_chip_ram; cycles=9 +45CF: 5C 00 00 MOV:I.W #H'0000, R4 ; cycles=3 +45D2: 20 08 BRA loc_45DC ; cycles=7 loc_45D4: -45D4: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs H'F6F9 in on_chip_ram -45D9: 5C 00 01 MOV:I.W #H'0001, R4 +45D4: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs H'F6F9 in on_chip_ram; cycles=9 +45D9: 5C 00 01 MOV:I.W #H'0001, R4 ; cycles=3 loc_45DC: -45DC: 19 RTS +45DC: 19 RTS ; cycles=12 loc_48EF: -48EF: 1D F7 34 80 MOV:G.W @H'F734, R0 ; refs H'F734 in on_chip_ram -48F3: 1D F7 32 90 MOV:G.W R0, @H'F732 ; refs H'F732 in on_chip_ram -48F7: 0E 01 BSR loc_48FA -48F9: 19 RTS +48EF: 1D F7 34 80 MOV:G.W @H'F734, R0 ; refs H'F734 in on_chip_ram; cycles=6 +48F3: 1D F7 32 90 MOV:G.W R0, @H'F732 ; refs H'F732 in on_chip_ram; cycles=6 +48F7: 0E 01 BSR loc_48FA ; cycles=14 +48F9: 19 RTS ; cycles=13 loc_48FA: -48FA: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -48FE: 26 29 BNE loc_4929 -4900: 15 F7 32 04 1A CMP:G.B #H'1A, @H'F732 ; refs H'F732 in on_chip_ram -4905: 27 22 BEQ loc_4929 -4907: 1D F7 32 05 19 00 CMP:G.W #H'1900, @H'F732 ; refs H'F732 in on_chip_ram -490D: 27 1A BEQ loc_4929 -490F: 1D E1 EC FD BTST.W #13, @H'E1EC ; refs H'E1EC in program_or_external -4913: 27 14 BEQ loc_4929 -4915: 1D E1 EC 80 MOV:G.W @H'E1EC, R0 ; refs H'E1EC in program_or_external -4919: 0C 9F FF 50 AND.W #H'9FFF, R0 -491D: 1D E9 EC 90 MOV:G.W R0, @H'E9EC ; refs H'E9EC in program_or_external -4921: 52 80 MOV:E.B #H'80, R2 -4923: 5B 00 F6 MOV:I.W #H'00F6, R3 -4926: 1E F5 2B BSR loc_3E54 +48FA: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=7 +48FE: 26 29 BNE loc_4929 ; cycles=3/7 nt/t +4900: 15 F7 32 04 1A CMP:G.B #H'1A, @H'F732 ; refs H'F732 in on_chip_ram; cycles=7 +4905: 27 22 BEQ loc_4929 ; cycles=3/8 nt/t +4907: 1D F7 32 05 19 00 CMP:G.W #H'1900, @H'F732 ; refs H'F732 in on_chip_ram; cycles=6 +490D: 27 1A BEQ loc_4929 ; cycles=3/8 nt/t +490F: 1D E1 EC FD BTST.W #13, @H'E1EC ; refs H'E1EC in program_or_external; cycles=6 +4913: 27 14 BEQ loc_4929 ; cycles=3/8 nt/t +4915: 1D E1 EC 80 MOV:G.W @H'E1EC, R0 ; refs H'E1EC in program_or_external; cycles=6 +4919: 0C 9F FF 50 AND.W #H'9FFF, R0 ; cycles=4 +491D: 1D E9 EC 90 MOV:G.W R0, @H'E9EC ; refs H'E9EC in program_or_external; cycles=6 +4921: 52 80 MOV:E.B #H'80, R2 ; cycles=2 +4923: 5B 00 F6 MOV:I.W #H'00F6, R3 ; cycles=3 +4926: 1E F5 2B BSR loc_3E54 ; cycles=13 loc_4929: -4929: 15 F7 6E F6 BTST.B #6, @H'F76E ; refs H'F76E in on_chip_ram -492D: 26 0E BNE loc_493D -492F: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs H'F732 in on_chip_ram -4933: A0 12 EXTU.B R0 -4935: A0 1A SHLL.B R0 -4937: F8 49 3E 80 MOV:G.W @(H'493E,R0), R0 -493B: 11 D8 JSR @R0 +4929: 15 F7 6E F6 BTST.B #6, @H'F76E ; refs H'F76E in on_chip_ram; cycles=6 +492D: 26 0E BNE loc_493D ; cycles=3/8 nt/t +492F: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs H'F732 in on_chip_ram; cycles=6 +4933: A0 12 EXTU.B R0 ; cycles=3 +4935: A0 1A SHLL.B R0 ; cycles=2 +4937: F8 49 3E 80 MOV:G.W @(H'493E,R0), R0 ; cycles=6 +493B: 11 D8 JSR @R0 ; cycles=14 loc_493D: -493D: 19 RTS +493D: 19 RTS ; cycles=13 loc_6206: -6206: 0C 01 FF 55 AND.W #H'01FF, R5 -620A: 4D 00 7F CMP:I #H'007F, R5 -620D: 23 07 BLS loc_6216 -620F: 4D 01 7F CMP:I #H'017F, R5 -6212: 23 04 BLS loc_6218 -6214: 20 0C BRA loc_6222 +6206: 0C 01 FF 55 AND.W #H'01FF, R5 ; cycles=4 +620A: 4D 00 7F CMP:I #H'007F, R5 ; cycles=3 +620D: 23 07 BLS loc_6216 ; cycles=3/8 nt/t +620F: 4D 01 7F CMP:I #H'017F, R5 ; cycles=3 +6212: 23 04 BLS loc_6218 ; cycles=3/7 nt/t +6214: 20 0C BRA loc_6222 ; cycles=7 loc_6216: -6216: 20 12 BRA loc_622A +6216: 20 12 BRA loc_622A ; cycles=7 loc_6218: -6218: 0C 00 80 35 SUB.W #H'0080, R5 -621C: 0C 01 00 25 ADD:G.W #H'0100, R5 -6220: 20 08 BRA loc_622A +6218: 0C 00 80 35 SUB.W #H'0080, R5 ; cycles=4 +621C: 0C 01 00 25 ADD:G.W #H'0100, R5 ; cycles=4 +6220: 20 08 BRA loc_622A ; cycles=7 loc_6222: -6222: 0C 01 80 35 SUB.W #H'0180, R5 -6226: 0C 02 00 25 ADD:G.W #H'0200, R5 +6222: 0C 01 80 35 SUB.W #H'0180, R5 ; cycles=4 +6226: 0C 02 00 25 ADD:G.W #H'0200, R5 ; cycles=4 loc_622A: -622A: 19 RTS +622A: 19 RTS ; cycles=12 loc_622B: -622B: AD 84 MOV:G.W R5, R4 -622D: A5 12 EXTU.B R5 -622F: A4 10 SWAP.B R4 -6231: 04 07 54 AND.B #H'07, R4 -6234: 44 00 CMP:E #H'00, R4 -6236: 27 0C BEQ loc_6244 -6238: 44 01 CMP:E #H'01, R4 -623A: 27 11 BEQ loc_624D -623C: 44 02 CMP:E #H'02, R4 -623E: 27 16 BEQ loc_6256 -6240: 44 03 CMP:E #H'03, R4 -6242: 27 1B BEQ loc_625F +622B: AD 84 MOV:G.W R5, R4 ; cycles=3 +622D: A5 12 EXTU.B R5 ; cycles=3 +622F: A4 10 SWAP.B R4 ; cycles=3 +6231: 04 07 54 AND.B #H'07, R4 ; cycles=3 +6234: 44 00 CMP:E #H'00, R4 ; cycles=2 +6236: 27 0C BEQ loc_6244 ; cycles=3/7 nt/t +6238: 44 01 CMP:E #H'01, R4 ; cycles=2 +623A: 27 11 BEQ loc_624D ; cycles=3/7 nt/t +623C: 44 02 CMP:E #H'02, R4 ; cycles=2 +623E: 27 16 BEQ loc_6256 ; cycles=3/7 nt/t +6240: 44 03 CMP:E #H'03, R4 ; cycles=2 +6242: 27 1B BEQ loc_625F ; cycles=3/7 nt/t loc_6244: -6244: 45 7F CMP:E #H'7F, R5 -6246: 22 17 BHI loc_625F -6248: 5C 00 00 MOV:I.W #H'0000, R4 -624B: 20 17 BRA loc_6264 +6244: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6246: 22 17 BHI loc_625F ; cycles=3/7 nt/t +6248: 5C 00 00 MOV:I.W #H'0000, R4 ; cycles=3 +624B: 20 17 BRA loc_6264 ; cycles=8 loc_624D: -624D: 45 FF CMP:E #H'FF, R5 -624F: 22 0E BHI loc_625F -6251: 5C 00 80 MOV:I.W #H'0080, R4 -6254: 20 0E BRA loc_6264 +624D: 45 FF CMP:E #H'FF, R5 ; cycles=2 +624F: 22 0E BHI loc_625F ; cycles=3/8 nt/t +6251: 5C 00 80 MOV:I.W #H'0080, R4 ; cycles=3 +6254: 20 0E BRA loc_6264 ; cycles=7 loc_6256: -6256: 45 7F CMP:E #H'7F, R5 -6258: 22 05 BHI loc_625F -625A: 5C 01 80 MOV:I.W #H'0180, R4 -625D: 20 05 BRA loc_6264 +6256: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6258: 22 05 BHI loc_625F ; cycles=3/7 nt/t +625A: 5C 01 80 MOV:I.W #H'0180, R4 ; cycles=3 +625D: 20 05 BRA loc_6264 ; cycles=8 loc_625F: -625F: AC 13 CLR.W R4 -6261: 5D 01 FF MOV:I.W #H'01FF, R5 +625F: AC 13 CLR.W R4 ; cycles=3 +6261: 5D 01 FF MOV:I.W #H'01FF, R5 ; cycles=3 loc_6264: -6264: AC 25 ADD:G.W R4, R5 -6266: 19 RTS +6264: AC 25 ADD:G.W R4, R5 ; cycles=3 +6266: 19 RTS ; cycles=12 loc_BA26: -BA26: 15 F9 C0 16 TST.B @H'F9C0 ; refs H'F9C0 in on_chip_ram -BA2A: 26 FA BNE loc_BA26 -BA2C: 15 F9 C0 06 64 MOV:G.B #H'64, @H'F9C0 ; refs H'F9C0 in on_chip_ram -BA31: 15 F9 C4 06 07 MOV:G.B #H'07, @H'F9C4 ; refs H'F9C4 in on_chip_ram -BA36: 1D F8 50 80 MOV:G.W @H'F850, R0 ; refs H'F850 in on_chip_ram -BA3A: 1D F8 58 90 MOV:G.W R0, @H'F858 ; refs H'F858 in on_chip_ram -BA3E: 1D F8 52 80 MOV:G.W @H'F852, R0 ; refs H'F852 in on_chip_ram -BA42: 1D F8 5A 90 MOV:G.W R0, @H'F85A ; refs H'F85A in on_chip_ram -BA46: 15 F8 54 80 MOV:G.B @H'F854, R0 ; refs H'F854 in on_chip_ram -BA4A: 15 F8 5C 90 MOV:G.B R0, @H'F85C ; refs H'F85C in on_chip_ram -BA4E: 50 5A MOV:E.B #H'5A, R0 -BA50: 15 F8 58 60 XOR.B @H'F858, R0 ; refs H'F858 in on_chip_ram -BA54: 15 F8 59 60 XOR.B @H'F859, R0 ; refs H'F859 in on_chip_ram -BA58: 15 F8 5A 60 XOR.B @H'F85A, R0 ; refs H'F85A in on_chip_ram -BA5C: 15 F8 5B 60 XOR.B @H'F85B, R0 ; refs H'F85B in on_chip_ram -BA60: 15 F8 5C 60 XOR.B @H'F85C, R0 ; refs H'F85C in on_chip_ram -BA64: 15 F8 5D 90 MOV:G.B R0, @H'F85D ; refs H'F85D in on_chip_ram +BA26: 15 F9 C0 16 TST.B @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=7 +BA2A: 26 FA BNE loc_BA26 ; cycles=3/7 nt/t +BA2C: 15 F9 C0 06 64 MOV:G.B #H'64, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 +BA31: 15 F9 C4 06 07 MOV:G.B #H'07, @H'F9C4 ; refs H'F9C4 in on_chip_ram; cycles=9 +BA36: 1D F8 50 80 MOV:G.W @H'F850, R0 ; refs H'F850 in on_chip_ram; cycles=7 +BA3A: 1D F8 58 90 MOV:G.W R0, @H'F858 ; refs H'F858 in on_chip_ram; cycles=7 +BA3E: 1D F8 52 80 MOV:G.W @H'F852, R0 ; refs H'F852 in on_chip_ram; cycles=7 +BA42: 1D F8 5A 90 MOV:G.W R0, @H'F85A ; refs H'F85A in on_chip_ram; cycles=7 +BA46: 15 F8 54 80 MOV:G.B @H'F854, R0 ; refs H'F854 in on_chip_ram; cycles=7 +BA4A: 15 F8 5C 90 MOV:G.B R0, @H'F85C ; refs H'F85C in on_chip_ram; cycles=7 +BA4E: 50 5A MOV:E.B #H'5A, R0 ; cycles=2 +BA50: 15 F8 58 60 XOR.B @H'F858, R0 ; refs H'F858 in on_chip_ram; cycles=7 +BA54: 15 F8 59 60 XOR.B @H'F859, R0 ; refs H'F859 in on_chip_ram; cycles=7 +BA58: 15 F8 5A 60 XOR.B @H'F85A, R0 ; refs H'F85A in on_chip_ram; cycles=7 +BA5C: 15 F8 5B 60 XOR.B @H'F85B, R0 ; refs H'F85B in on_chip_ram; cycles=7 +BA60: 15 F8 5C 60 XOR.B @H'F85C, R0 ; refs H'F85C in on_chip_ram; cycles=7 +BA64: 15 F8 5D 90 MOV:G.B R0, @H'F85D ; refs H'F85D in on_chip_ram; cycles=7 loc_BA68: -BA68: 15 FE DC F7 BTST.B #7, @SCI1_SSR ; refs SCI1_SSR in register_field -BA6C: 27 FA BEQ loc_BA68 -BA6E: 15 F8 58 80 MOV:G.B @H'F858, R0 ; refs H'F858 in on_chip_ram -BA72: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR -BA76: 15 F9 C2 06 01 MOV:G.B #H'01, @H'F9C2 ; refs H'F9C2 in on_chip_ram -BA7B: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR -BA7F: 15 FE DA C7 BSET.B #7, @SCI1_SCR ; set TIE (bit 7) of SCI1_SCR -BA83: 19 RTS +BA68: 15 FE DC F7 BTST.B #7, @SCI1_SSR ; refs SCI1_SSR in register_field; cycles=7 +BA6C: 27 FA BEQ loc_BA68 ; cycles=3/7 nt/t +BA6E: 15 F8 58 80 MOV:G.B @H'F858, R0 ; refs H'F858 in on_chip_ram; cycles=7 +BA72: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; cycles=7 +BA76: 15 F9 C2 06 01 MOV:G.B #H'01, @H'F9C2 ; refs H'F9C2 in on_chip_ram; cycles=9 +BA7B: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; cycles=8 +BA7F: 15 FE DA C7 BSET.B #7, @SCI1_SCR ; set TIE (bit 7) of SCI1_SCR; cycles=8 +BA83: 19 RTS ; cycles=13 vec_sci1_txi_BA84: -BA84: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BA88: 27 1F BEQ loc_BAA9 -BA8A: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram -BA8E: 27 19 BEQ loc_BAA9 -BA90: 15 F9 C3 16 TST.B @H'F9C3 ; refs H'F9C3 in on_chip_ram -BA94: 27 13 BEQ loc_BAA9 -BA96: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BA9A: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram -BA9E: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR -BAA2: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs H'F9C0 in on_chip_ram -BAA7: 20 48 BRA loc_BAF1 +BA84: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=7 +BA88: 27 1F BEQ loc_BAA9 ; cycles=3/7 nt/t +BA8A: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram; cycles=7 +BA8E: 27 19 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA90: 15 F9 C3 16 TST.B @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=7 +BA94: 27 13 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA96: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=9 +BA9A: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=9 +BA9E: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; cycles=9 +BAA2: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 +BAA7: 20 48 BRA loc_BAF1 ; cycles=8 loc_BAA9: -BAA9: BF 90 MOV:G.W R0, @-R7 -BAAB: 15 F9 C2 80 MOV:G.B @H'F9C2, R0 ; refs H'F9C2 in on_chip_ram -BAAF: A0 12 EXTU.B R0 -BAB1: F0 F8 58 80 MOV:G.B @(-H'07A8,R0), R0 -BAB5: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR -BAB9: CF 80 MOV:G.W @R7+, R0 -BABB: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR -BABF: 15 F9 C2 08 ADD:Q.B #1, @H'F9C2 ; refs H'F9C2 in on_chip_ram -BAC3: 15 F9 C2 04 06 CMP:G.B #H'06, @H'F9C2 ; refs H'F9C2 in on_chip_ram -BAC8: 26 27 BNE loc_BAF1 -BACA: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR -BACE: 15 F7 95 F6 BTST.B #6, @H'F795 ; refs H'F795 in on_chip_ram -BAD2: 26 14 BNE loc_BAE8 -BAD4: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram -BAD8: 26 07 BNE loc_BAE1 -BADA: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs H'F9C0 in on_chip_ram -BADF: 20 0C BRA loc_BAED +BAA9: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +BAAB: 15 F9 C2 80 MOV:G.B @H'F9C2, R0 ; refs H'F9C2 in on_chip_ram; cycles=6 +BAAF: A0 12 EXTU.B R0 ; cycles=3 +BAB1: F0 F8 58 80 MOV:G.B @(-H'07A8,R0), R0 ; cycles=6 +BAB5: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; cycles=6 +BAB9: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +BABB: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; cycles=8 +BABF: 15 F9 C2 08 ADD:Q.B #1, @H'F9C2 ; refs H'F9C2 in on_chip_ram; cycles=8 +BAC3: 15 F9 C2 04 06 CMP:G.B #H'06, @H'F9C2 ; refs H'F9C2 in on_chip_ram; cycles=6 +BAC8: 26 27 BNE loc_BAF1 ; cycles=3/7 nt/t +BACA: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; cycles=9 +BACE: 15 F7 95 F6 BTST.B #6, @H'F795 ; refs H'F795 in on_chip_ram; cycles=7 +BAD2: 26 14 BNE loc_BAE8 ; cycles=3/7 nt/t +BAD4: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs H'F791 in on_chip_ram; cycles=7 +BAD8: 26 07 BNE loc_BAE1 ; cycles=3/7 nt/t +BADA: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 +BADF: 20 0C BRA loc_BAED ; cycles=8 loc_BAE1: -BAE1: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs H'F9C0 in on_chip_ram -BAE6: 20 05 BRA loc_BAED +BAE1: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 +BAE6: 20 05 BRA loc_BAED ; cycles=7 loc_BAE8: -BAE8: 15 F9 C0 06 F0 MOV:G.B #H'F0, @H'F9C0 ; refs H'F9C0 in on_chip_ram +BAE8: 15 F9 C0 06 F0 MOV:G.B #H'F0, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 loc_BAED: -BAED: 15 F9 C1 13 CLR.B @H'F9C1 ; refs H'F9C1 in on_chip_ram +BAED: 15 F9 C1 13 CLR.B @H'F9C1 ; refs H'F9C1 in on_chip_ram; cycles=8 loc_BAF1: -BAF1: 0A RTE +BAF1: 0A RTE ; cycles=14 loc_BAF2: -BAF2: 15 F9 B5 81 MOV:G.B @H'F9B5, R1 ; refs H'F9B5 in on_chip_ram -BAF6: A1 12 EXTU.B R1 -BAF8: 15 F9 B0 71 CMP:G.B @H'F9B0, R1 ; refs H'F9B0 in on_chip_ram -BAFC: 26 02 BNE loc_BB00 -BAFE: 20 56 BRA loc_BB56 +BAF2: 15 F9 B5 81 MOV:G.B @H'F9B5, R1 ; refs H'F9B5 in on_chip_ram; cycles=7 +BAF6: A1 12 EXTU.B R1 ; cycles=3 +BAF8: 15 F9 B0 71 CMP:G.B @H'F9B0, R1 ; refs H'F9B0 in on_chip_ram; cycles=7 +BAFC: 26 02 BNE loc_BB00 ; cycles=3/7 nt/t +BAFE: 20 56 BRA loc_BB56 ; cycles=7 loc_BB00: -BB00: 15 FA A2 C3 BSET.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BB04: A9 80 MOV:G.W R1, R0 -BB06: A8 1A SHLL.W R0 -BB08: F8 F8 70 80 MOV:G.W @(-H'0790,R0), R0 -BB0C: A8 85 MOV:G.W R0, R5 -BB0E: 1E A6 F5 BSR loc_6206 -BB11: A8 81 MOV:G.W R0, R1 -BB13: A1 10 SWAP.B R1 -BB15: A1 1B SHLR.B R1 -BB17: A1 82 MOV:G.B R1, R2 -BB19: 04 07 51 AND.B #H'07, R1 -BB1C: 15 F8 50 91 MOV:G.B R1, @H'F850 ; refs H'F850 in on_chip_ram -BB20: 15 F8 52 95 MOV:G.B R5, @H'F852 ; refs H'F852 in on_chip_ram -BB24: A5 10 SWAP.B R5 -BB26: 04 78 52 AND.B #H'78, R2 -BB29: A2 45 OR.B R2, R5 -BB2B: 15 F8 51 95 MOV:G.B R5, @H'F851 ; refs H'F851 in on_chip_ram -BB2F: 0C 01 FF 50 AND.W #H'01FF, R0 -BB33: A8 1A SHLL.W R0 -BB35: F8 E8 00 84 MOV:G.W @(-H'1800,R0), R4 -BB39: 15 F8 54 94 MOV:G.B R4, @H'F854 ; refs H'F854 in on_chip_ram -BB3D: A4 10 SWAP.B R4 -BB3F: 15 F8 53 94 MOV:G.B R4, @H'F853 ; refs H'F853 in on_chip_ram -BB43: 1E FE E0 BSR loc_BA26 -BB46: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs H'F9C6 in on_chip_ram -BB4C: 15 F9 C8 06 14 MOV:G.B #H'14, @H'F9C8 ; refs H'F9C8 in on_chip_ram -BB51: 15 FA A3 06 80 MOV:G.B #H'80, @H'FAA3 ; refs H'FAA3 in on_chip_ram +BB00: 15 FA A2 C3 BSET.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=9 +BB04: A9 80 MOV:G.W R1, R0 ; cycles=3 +BB06: A8 1A SHLL.W R0 ; cycles=3 +BB08: F8 F8 70 80 MOV:G.W @(-H'0790,R0), R0 ; cycles=7 +BB0C: A8 85 MOV:G.W R0, R5 ; cycles=3 +BB0E: 1E A6 F5 BSR loc_6206 ; cycles=13 +BB11: A8 81 MOV:G.W R0, R1 ; cycles=3 +BB13: A1 10 SWAP.B R1 ; cycles=3 +BB15: A1 1B SHLR.B R1 ; cycles=2 +BB17: A1 82 MOV:G.B R1, R2 ; cycles=2 +BB19: 04 07 51 AND.B #H'07, R1 ; cycles=3 +BB1C: 15 F8 50 91 MOV:G.B R1, @H'F850 ; refs H'F850 in on_chip_ram; cycles=7 +BB20: 15 F8 52 95 MOV:G.B R5, @H'F852 ; refs H'F852 in on_chip_ram; cycles=7 +BB24: A5 10 SWAP.B R5 ; cycles=3 +BB26: 04 78 52 AND.B #H'78, R2 ; cycles=3 +BB29: A2 45 OR.B R2, R5 ; cycles=2 +BB2B: 15 F8 51 95 MOV:G.B R5, @H'F851 ; refs H'F851 in on_chip_ram; cycles=6 +BB2F: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +BB33: A8 1A SHLL.W R0 ; cycles=3 +BB35: F8 E8 00 84 MOV:G.W @(-H'1800,R0), R4 ; cycles=6 +BB39: 15 F8 54 94 MOV:G.B R4, @H'F854 ; refs H'F854 in on_chip_ram; cycles=6 +BB3D: A4 10 SWAP.B R4 ; cycles=3 +BB3F: 15 F8 53 94 MOV:G.B R4, @H'F853 ; refs H'F853 in on_chip_ram; cycles=6 +BB43: 1E FE E0 BSR loc_BA26 ; cycles=14 +BB46: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs H'F9C6 in on_chip_ram; cycles=11 +BB4C: 15 F9 C8 06 14 MOV:G.B #H'14, @H'F9C8 ; refs H'F9C8 in on_chip_ram; cycles=9 +BB51: 15 FA A3 06 80 MOV:G.B #H'80, @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=9 loc_BB56: -BB56: 19 RTS +BB56: 19 RTS ; cycles=12 vec_sci1_eri_BB57: -BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; refs H'FAA4 in on_chip_ram -BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR -BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR -BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR +BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; refs H'FAA4 in on_chip_ram; cycles=8 +BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; cycles=8 +BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; cycles=8 +BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; cycles=8 vec_sci1_rxi_BB67: -BB67: 12 03 STM.W {R0,R1}, @-SP -BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR -BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; refs SCI1_RDR in register_field -BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs H'F9C1 in on_chip_ram -BB75: 26 06 BNE loc_BB7D -BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs H'F9C3 in on_chip_ram -BB7B: 20 0D BRA loc_BB8A +BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; cycles=8 +BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; refs SCI1_RDR in register_field; cycles=6 +BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs H'F9C1 in on_chip_ram; cycles=6 +BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t +BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=8 +BB7B: 20 0D BRA loc_BB8A ; cycles=8 loc_BB7D: -BB7D: 15 F9 C3 04 05 CMP:G.B #H'05, @H'F9C3 ; refs H'F9C3 in on_chip_ram -BB82: 23 06 BLS loc_BB8A -BB84: 15 FA A4 13 CLR.B @H'FAA4 ; refs H'FAA4 in on_chip_ram -BB88: 20 19 BRA loc_BBA3 +BB7D: 15 F9 C3 04 05 CMP:G.B #H'05, @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=6 +BB82: 23 06 BLS loc_BB8A ; cycles=3/7 nt/t +BB84: 15 FA A4 13 CLR.B @H'FAA4 ; refs H'FAA4 in on_chip_ram; cycles=9 +BB88: 20 19 BRA loc_BBA3 ; cycles=7 loc_BB8A: -BB8A: 15 F9 C3 81 MOV:G.B @H'F9C3, R1 ; refs H'F9C3 in on_chip_ram -BB8E: A1 12 EXTU.B R1 -BB90: F1 F8 68 90 MOV:G.B R0, @(-H'0798,R1) -BB94: A1 08 ADD:Q.B #1, R1 -BB96: 15 F9 C3 91 MOV:G.B R1, @H'F9C3 ; refs H'F9C3 in on_chip_ram -BB9A: 41 06 CMP:E #H'06, R1 -BB9C: 26 05 BNE loc_BBA3 -BB9E: 15 F9 C5 06 14 MOV:G.B #H'14, @H'F9C5 ; refs H'F9C5 in on_chip_ram +BB8A: 15 F9 C3 81 MOV:G.B @H'F9C3, R1 ; refs H'F9C3 in on_chip_ram; cycles=7 +BB8E: A1 12 EXTU.B R1 ; cycles=3 +BB90: F1 F8 68 90 MOV:G.B R0, @(-H'0798,R1) ; cycles=7 +BB94: A1 08 ADD:Q.B #1, R1 ; cycles=4 +BB96: 15 F9 C3 91 MOV:G.B R1, @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=7 +BB9A: 41 06 CMP:E #H'06, R1 ; cycles=2 +BB9C: 26 05 BNE loc_BBA3 ; cycles=3/7 nt/t +BB9E: 15 F9 C5 06 14 MOV:G.B #H'14, @H'F9C5 ; refs H'F9C5 in on_chip_ram; cycles=9 loc_BBA3: -BBA3: 15 F9 C1 06 05 MOV:G.B #H'05, @H'F9C1 ; refs H'F9C1 in on_chip_ram -BBA8: 02 03 LDM.W @SP+, {R0,R1} -BBAA: 0A RTE +BBA3: 15 F9 C1 06 05 MOV:G.B #H'05, @H'F9C1 ; refs H'F9C1 in on_chip_ram; cycles=9 +BBA8: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +BBAA: 0A RTE ; cycles=13 loc_BBAB: -BBAB: 15 F9 C3 04 06 CMP:G.B #H'06, @H'F9C3 ; refs H'F9C3 in on_chip_ram -BBB0: 36 02 BC BNE loc_BE6F -BBB3: 1D F8 68 80 MOV:G.W @H'F868, R0 ; refs H'F868 in on_chip_ram -BBB7: 1D F8 60 90 MOV:G.W R0, @H'F860 ; refs H'F860 in on_chip_ram -BBBB: 1D F8 6A 80 MOV:G.W @H'F86A, R0 ; refs H'F86A in on_chip_ram -BBBF: 1D F8 62 90 MOV:G.W R0, @H'F862 ; refs H'F862 in on_chip_ram -BBC3: 1D F8 6C 80 MOV:G.W @H'F86C, R0 ; refs H'F86C in on_chip_ram -BBC7: 1D F8 64 90 MOV:G.W R0, @H'F864 ; refs H'F864 in on_chip_ram -BBCB: 15 F9 C3 13 CLR.B @H'F9C3 ; refs H'F9C3 in on_chip_ram -BBCF: 15 FA A4 F7 BTST.B #7, @H'FAA4 ; refs H'FAA4 in on_chip_ram -BBD3: 36 02 53 BNE loc_BE29 -BBD6: 50 5A MOV:E.B #H'5A, R0 -BBD8: 15 F8 60 60 XOR.B @H'F860, R0 ; refs H'F860 in on_chip_ram -BBDC: 15 F8 61 60 XOR.B @H'F861, R0 ; refs H'F861 in on_chip_ram -BBE0: 15 F8 62 60 XOR.B @H'F862, R0 ; refs H'F862 in on_chip_ram -BBE4: 15 F8 63 60 XOR.B @H'F863, R0 ; refs H'F863 in on_chip_ram -BBE8: 15 F8 64 60 XOR.B @H'F864, R0 ; refs H'F864 in on_chip_ram -BBEC: 15 F8 65 70 CMP:G.B @H'F865, R0 ; refs H'F865 in on_chip_ram -BBF0: 36 02 36 BNE loc_BE29 -BBF3: 15 FA A6 13 CLR.B @H'FAA6 ; refs H'FAA6 in on_chip_ram -BBF7: 15 F8 61 85 MOV:G.B @H'F861, R5 ; refs H'F861 in on_chip_ram -BBFB: A5 10 SWAP.B R5 -BBFD: 15 F8 62 85 MOV:G.B @H'F862, R5 ; refs H'F862 in on_chip_ram -BC01: 1E A6 27 BSR loc_622B -BC04: AD 84 MOV:G.W R5, R4 -BC06: AC 1A SHLL.W R4 -BC08: 15 F8 60 80 MOV:G.B @H'F860, R0 ; refs H'F860 in on_chip_ram -BC0C: 04 07 50 AND.B #H'07, R0 -BC0F: 15 FA A2 16 TST.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BC13: 26 25 BNE loc_BC3A +BBAB: 15 F9 C3 04 06 CMP:G.B #H'06, @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=6 +BBB0: 36 02 BC BNE loc_BE6F ; cycles=3/7 nt/t +BBB3: 1D F8 68 80 MOV:G.W @H'F868, R0 ; refs H'F868 in on_chip_ram; cycles=6 +BBB7: 1D F8 60 90 MOV:G.W R0, @H'F860 ; refs H'F860 in on_chip_ram; cycles=6 +BBBB: 1D F8 6A 80 MOV:G.W @H'F86A, R0 ; refs H'F86A in on_chip_ram; cycles=6 +BBBF: 1D F8 62 90 MOV:G.W R0, @H'F862 ; refs H'F862 in on_chip_ram; cycles=6 +BBC3: 1D F8 6C 80 MOV:G.W @H'F86C, R0 ; refs H'F86C in on_chip_ram; cycles=6 +BBC7: 1D F8 64 90 MOV:G.W R0, @H'F864 ; refs H'F864 in on_chip_ram; cycles=6 +BBCB: 15 F9 C3 13 CLR.B @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=8 +BBCF: 15 FA A4 F7 BTST.B #7, @H'FAA4 ; refs H'FAA4 in on_chip_ram; cycles=6 +BBD3: 36 02 53 BNE loc_BE29 ; cycles=3/8 nt/t +BBD6: 50 5A MOV:E.B #H'5A, R0 ; cycles=2 +BBD8: 15 F8 60 60 XOR.B @H'F860, R0 ; refs H'F860 in on_chip_ram; cycles=7 +BBDC: 15 F8 61 60 XOR.B @H'F861, R0 ; refs H'F861 in on_chip_ram; cycles=7 +BBE0: 15 F8 62 60 XOR.B @H'F862, R0 ; refs H'F862 in on_chip_ram; cycles=7 +BBE4: 15 F8 63 60 XOR.B @H'F863, R0 ; refs H'F863 in on_chip_ram; cycles=7 +BBE8: 15 F8 64 60 XOR.B @H'F864, R0 ; refs H'F864 in on_chip_ram; cycles=7 +BBEC: 15 F8 65 70 CMP:G.B @H'F865, R0 ; refs H'F865 in on_chip_ram; cycles=7 +BBF0: 36 02 36 BNE loc_BE29 ; cycles=3/7 nt/t +BBF3: 15 FA A6 13 CLR.B @H'FAA6 ; refs H'FAA6 in on_chip_ram; cycles=8 +BBF7: 15 F8 61 85 MOV:G.B @H'F861, R5 ; refs H'F861 in on_chip_ram; cycles=6 +BBFB: A5 10 SWAP.B R5 ; cycles=3 +BBFD: 15 F8 62 85 MOV:G.B @H'F862, R5 ; refs H'F862 in on_chip_ram; cycles=6 +BC01: 1E A6 27 BSR loc_622B ; cycles=14 +BC04: AD 84 MOV:G.W R5, R4 ; cycles=3 +BC06: AC 1A SHLL.W R4 ; cycles=3 +BC08: 15 F8 60 80 MOV:G.B @H'F860, R0 ; refs H'F860 in on_chip_ram; cycles=7 +BC0C: 04 07 50 AND.B #H'07, R0 ; cycles=3 +BC0F: 15 FA A2 16 TST.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=6 +BC13: 26 25 BNE loc_BC3A ; cycles=3/8 nt/t loc_BC15: -BC15: 15 FA A2 C7 BSET.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BC19: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs H'F861 in on_chip_ram -BC1D: 36 00 EB BNE loc_BD0B -BC20: 40 00 CMP:E #H'00, R0 -BC22: 27 45 BEQ loc_BC69 -BC24: 40 01 CMP:E #H'01, R0 -BC26: 37 00 AE BEQ loc_BCD7 -BC29: 40 02 CMP:E #H'02, R0 -BC2B: 37 00 D6 BEQ loc_BD04 -BC2E: 40 07 CMP:E #H'07, R0 -BC30: 37 01 D2 BEQ loc_BE05 -BC33: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BC37: 30 02 35 BRA loc_BE6F +BC15: 15 FA A2 C7 BSET.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BC19: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs H'F861 in on_chip_ram; cycles=6 +BC1D: 36 00 EB BNE loc_BD0B ; cycles=3/8 nt/t +BC20: 40 00 CMP:E #H'00, R0 ; cycles=2 +BC22: 27 45 BEQ loc_BC69 ; cycles=3/7 nt/t +BC24: 40 01 CMP:E #H'01, R0 ; cycles=2 +BC26: 37 00 AE BEQ loc_BCD7 ; cycles=3/7 nt/t +BC29: 40 02 CMP:E #H'02, R0 ; cycles=2 +BC2B: 37 00 D6 BEQ loc_BD04 ; cycles=3/8 nt/t +BC2E: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC30: 37 01 D2 BEQ loc_BE05 ; cycles=3/7 nt/t +BC33: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BC37: 30 02 35 BRA loc_BE6F ; cycles=8 loc_BC3A: -BC3A: A0 F2 BTST.B #2, R0 -BC3C: 27 1E BEQ loc_BC5C -BC3E: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs H'F861 in on_chip_ram -BC42: 36 01 E2 BNE loc_BE27 -BC45: 40 04 CMP:E #H'04, R0 -BC47: 37 00 C4 BEQ loc_BD0E -BC4A: 40 05 CMP:E #H'05, R0 -BC4C: 37 01 31 BEQ loc_BD80 -BC4F: 40 06 CMP:E #H'06, R0 -BC51: 37 01 87 BEQ loc_BDDB -BC54: 40 07 CMP:E #H'07, R0 -BC56: 37 01 AC BEQ loc_BE05 -BC59: 30 02 13 BRA loc_BE6F +BC3A: A0 F2 BTST.B #2, R0 ; cycles=2 +BC3C: 27 1E BEQ loc_BC5C ; cycles=3/7 nt/t +BC3E: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs H'F861 in on_chip_ram; cycles=7 +BC42: 36 01 E2 BNE loc_BE27 ; cycles=3/7 nt/t +BC45: 40 04 CMP:E #H'04, R0 ; cycles=2 +BC47: 37 00 C4 BEQ loc_BD0E ; cycles=3/8 nt/t +BC4A: 40 05 CMP:E #H'05, R0 ; cycles=2 +BC4C: 37 01 31 BEQ loc_BD80 ; cycles=3/7 nt/t +BC4F: 40 06 CMP:E #H'06, R0 ; cycles=2 +BC51: 37 01 87 BEQ loc_BDDB ; cycles=3/8 nt/t +BC54: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC56: 37 01 AC BEQ loc_BE05 ; cycles=3/7 nt/t +BC59: 30 02 13 BRA loc_BE6F ; cycles=8 loc_BC5C: -BC5C: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BC60: 37 02 0C BEQ loc_BE6F -BC63: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram -BC67: 20 AC BRA loc_BC15 +BC5C: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=9 +BC60: 37 02 0C BEQ loc_BE6F ; cycles=3/7 nt/t +BC63: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=8 +BC67: 20 AC BRA loc_BC15 ; cycles=8 loc_BC69: -BC69: AD 16 TST.W R5 -BC6B: 26 1E BNE loc_BC8B -BC6D: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram -BC71: A0 10 SWAP.B R0 -BC73: 50 80 MOV:E.B #H'80, R0 -BC75: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) -BC79: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) -BC7D: 15 F8 64 06 80 MOV:G.B #H'80, @H'F864 ; refs H'F864 in on_chip_ram -BC82: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) -BC86: 1E 01 E7 BSR loc_BE70 -BC89: 20 25 BRA loc_BCB0 +BC69: AD 16 TST.W R5 ; cycles=3 +BC6B: 26 1E BNE loc_BC8B ; cycles=3/8 nt/t +BC6D: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram; cycles=6 +BC71: A0 10 SWAP.B R0 ; cycles=3 +BC73: 50 80 MOV:E.B #H'80, R0 ; cycles=2 +BC75: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC79: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC7D: 15 F8 64 06 80 MOV:G.B #H'80, @H'F864 ; refs H'F864 in on_chip_ram; cycles=9 +BC82: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BC86: 1E 01 E7 BSR loc_BE70 ; cycles=13 +BC89: 20 25 BRA loc_BCB0 ; cycles=8 loc_BC8B: -BC8B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram -BC8F: A0 10 SWAP.B R0 -BC91: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram -BC95: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) -BC99: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) -BC9D: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) -BCA1: FC C5 64 81 MOV:G.W @(-H'3A9C,R4), R1 -BCA5: A1 12 EXTU.B R1 -BCA7: 27 04 BEQ loc_BCAD -BCA9: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) +BC8B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram; cycles=6 +BC8F: A0 10 SWAP.B R0 ; cycles=3 +BC91: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram; cycles=6 +BC95: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC99: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC9D: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BCA1: FC C5 64 81 MOV:G.W @(-H'3A9C,R4), R1 ; cycles=6 +BCA5: A1 12 EXTU.B R1 ; cycles=3 +BCA7: 27 04 BEQ loc_BCAD ; cycles=3/8 nt/t +BCA9: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 loc_BCAD: -BCAD: 1E 01 C0 BSR loc_BE70 +BCAD: 1E 01 C0 BSR loc_BE70 ; cycles=14 loc_BCB0: -BCB0: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs H'F850 in on_chip_ram -BCB5: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs H'F861 in on_chip_ram -BCB9: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram -BCBD: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs H'F862 in on_chip_ram -BCC1: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs H'F852 in on_chip_ram -BCC5: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram -BCC9: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs H'F854 in on_chip_ram -BCCD: 1E FD 56 BSR loc_BA26 -BCD0: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BCD4: 30 01 98 BRA loc_BE6F +BCB0: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs H'F850 in on_chip_ram; cycles=9 +BCB5: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs H'F861 in on_chip_ram; cycles=6 +BCB9: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram; cycles=6 +BCBD: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs H'F862 in on_chip_ram; cycles=6 +BCC1: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs H'F852 in on_chip_ram; cycles=6 +BCC5: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram; cycles=6 +BCC9: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs H'F854 in on_chip_ram; cycles=6 +BCCD: 1E FD 56 BSR loc_BA26 ; cycles=14 +BCD0: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=9 +BCD4: 30 01 98 BRA loc_BE6F ; cycles=7 loc_BCD7: -BCD7: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs H'F850 in on_chip_ram -BCDC: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs H'F861 in on_chip_ram -BCE0: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram -BCE4: 15 F8 62 80 MOV:G.B @H'F862, R0 ; refs H'F862 in on_chip_ram -BCE8: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram -BCEC: FC E0 00 80 MOV:G.W @(-H'2000,R4), R0 -BCF0: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs H'F854 in on_chip_ram -BCF4: A0 10 SWAP.B R0 -BCF6: 15 F8 53 90 MOV:G.B R0, @H'F853 ; refs H'F853 in on_chip_ram -BCFA: 1E FD 29 BSR loc_BA26 -BCFD: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BD01: 30 01 6B BRA loc_BE6F +BCD7: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs H'F850 in on_chip_ram; cycles=9 +BCDC: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs H'F861 in on_chip_ram; cycles=7 +BCE0: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram; cycles=7 +BCE4: 15 F8 62 80 MOV:G.B @H'F862, R0 ; refs H'F862 in on_chip_ram; cycles=7 +BCE8: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram; cycles=7 +BCEC: FC E0 00 80 MOV:G.W @(-H'2000,R4), R0 ; cycles=7 +BCF0: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs H'F854 in on_chip_ram; cycles=7 +BCF4: A0 10 SWAP.B R0 ; cycles=3 +BCF6: 15 F8 53 90 MOV:G.B R0, @H'F853 ; refs H'F853 in on_chip_ram; cycles=7 +BCFA: 1E FD 29 BSR loc_BA26 ; cycles=13 +BCFD: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BD01: 30 01 6B BRA loc_BE6F ; cycles=8 loc_BD04: -BD04: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BD08: 30 01 64 BRA loc_BE6F +BD04: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=9 +BD08: 30 01 64 BRA loc_BE6F ; cycles=7 loc_BD0B: -BD0B: 30 01 61 BRA loc_BE6F +BD0B: 30 01 61 BRA loc_BE6F ; cycles=8 loc_BD0E: -BD0E: AD 16 TST.W R5 -BD10: 26 19 BNE loc_BD2B -BD12: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram -BD16: A0 10 SWAP.B R0 -BD18: 50 80 MOV:E.B #H'80, R0 -BD1A: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) -BD1E: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) -BD22: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) -BD26: 1E 01 47 BSR loc_BE70 -BD29: 20 3C BRA loc_BD67 +BD0E: AD 16 TST.W R5 ; cycles=3 +BD10: 26 19 BNE loc_BD2B ; cycles=3/7 nt/t +BD12: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram; cycles=7 +BD16: A0 10 SWAP.B R0 ; cycles=3 +BD18: 50 80 MOV:E.B #H'80, R0 ; cycles=2 +BD1A: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=7 +BD1E: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=7 +BD22: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BD26: 1E 01 47 BSR loc_BE70 ; cycles=13 +BD29: 20 3C BRA loc_BD67 ; cycles=8 loc_BD2B: -BD2B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram -BD2F: A0 10 SWAP.B R0 -BD31: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram -BD35: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) -BD39: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) -BD3D: F4 C5 65 81 MOV:G.B @(-H'3A9B,R4), R1 -BD41: A1 12 EXTU.B R1 -BD43: 27 1F BEQ loc_BD64 -BD45: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) -BD49: 15 F7 6E F7 BTST.B #7, @H'F76E ; refs H'F76E in on_chip_ram -BD4D: 27 15 BEQ loc_BD64 -BD4F: 12 31 STM.W {R0,R4,R5}, @-SP -BD51: 15 F7 6E 84 MOV:G.B @H'F76E, R4 ; refs H'F76E in on_chip_ram -BD55: A4 10 SWAP.B R4 -BD57: A1 84 MOV:G.B R1, R4 -BD59: 0C 0F FE 54 AND.W #H'0FFE, R4 -BD5D: A8 85 MOV:G.W R0, R5 -BD5F: 1E 02 7E BSR loc_BFE0 -BD62: 02 31 LDM.W @SP+, {R0,R4,R5} +BD2B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram; cycles=6 +BD2F: A0 10 SWAP.B R0 ; cycles=3 +BD31: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram; cycles=6 +BD35: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BD39: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BD3D: F4 C5 65 81 MOV:G.B @(-H'3A9B,R4), R1 ; cycles=6 +BD41: A1 12 EXTU.B R1 ; cycles=3 +BD43: 27 1F BEQ loc_BD64 ; cycles=3/8 nt/t +BD45: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 +BD49: 15 F7 6E F7 BTST.B #7, @H'F76E ; refs H'F76E in on_chip_ram; cycles=6 +BD4D: 27 15 BEQ loc_BD64 ; cycles=3/8 nt/t +BD4F: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +BD51: 15 F7 6E 84 MOV:G.B @H'F76E, R4 ; refs H'F76E in on_chip_ram; cycles=6 +BD55: A4 10 SWAP.B R4 ; cycles=3 +BD57: A1 84 MOV:G.B R1, R4 ; cycles=2 +BD59: 0C 0F FE 54 AND.W #H'0FFE, R4 ; cycles=4 +BD5D: A8 85 MOV:G.W R0, R5 ; cycles=3 +BD5F: 1E 02 7E BSR loc_BFE0 ; cycles=14 +BD62: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 loc_BD64: -BD64: 1E 01 09 BSR loc_BE70 +BD64: 1E 01 09 BSR loc_BE70 ; cycles=13 loc_BD67: -BD67: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BD6B: 27 08 BEQ loc_BD75 -BD6D: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs H'F9B5 in on_chip_ram -BD71: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs H'F9B5 in on_chip_ram +BD67: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=6 +BD6B: 27 08 BEQ loc_BD75 ; cycles=3/8 nt/t +BD6D: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=8 +BD71: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=8 loc_BD75: -BD75: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram -BD79: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BD7D: 30 00 EF BRA loc_BE6F +BD75: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=8 +BD79: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BD7D: 30 00 EF BRA loc_BE6F ; cycles=8 loc_BD80: -BD80: 4D 00 6C CMP:I #H'006C, R5 -BD83: 27 3A BEQ loc_BDBF -BD85: 4D 00 6D CMP:I #H'006D, R5 -BD88: 27 35 BEQ loc_BDBF -BD8A: 4D 00 6E CMP:I #H'006E, R5 -BD8D: 27 30 BEQ loc_BDBF -BD8F: 4D 00 6E CMP:I #H'006E, R5 -BD92: 27 2B BEQ loc_BDBF -BD94: 15 F7 31 F7 BTST.B #7, @H'F731 ; refs H'F731 in on_chip_ram -BD98: 27 28 BEQ loc_BDC2 -BD9A: 4D 00 6B CMP:I #H'006B, R5 -BD9D: 27 16 BEQ loc_BDB5 -BD9F: 4D 00 96 CMP:I #H'0096, R5 -BDA2: 27 11 BEQ loc_BDB5 -BDA4: 4D 00 97 CMP:I #H'0097, R5 -BDA7: 27 0C BEQ loc_BDB5 -BDA9: 4D 00 C6 CMP:I #H'00C6, R5 -BDAC: 27 07 BEQ loc_BDB5 -BDAE: 4D 00 F8 CMP:I #H'00F8, R5 -BDB1: 27 02 BEQ loc_BDB5 -BDB3: 20 0D BRA loc_BDC2 +BD80: 4D 00 6C CMP:I #H'006C, R5 ; cycles=3 +BD83: 27 3A BEQ loc_BDBF ; cycles=3/8 nt/t +BD85: 4D 00 6D CMP:I #H'006D, R5 ; cycles=3 +BD88: 27 35 BEQ loc_BDBF ; cycles=3/7 nt/t +BD8A: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD8D: 27 30 BEQ loc_BDBF ; cycles=3/8 nt/t +BD8F: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD92: 27 2B BEQ loc_BDBF ; cycles=3/7 nt/t +BD94: 15 F7 31 F7 BTST.B #7, @H'F731 ; refs H'F731 in on_chip_ram; cycles=7 +BD98: 27 28 BEQ loc_BDC2 ; cycles=3/7 nt/t +BD9A: 4D 00 6B CMP:I #H'006B, R5 ; cycles=3 +BD9D: 27 16 BEQ loc_BDB5 ; cycles=3/8 nt/t +BD9F: 4D 00 96 CMP:I #H'0096, R5 ; cycles=3 +BDA2: 27 11 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDA4: 4D 00 97 CMP:I #H'0097, R5 ; cycles=3 +BDA7: 27 0C BEQ loc_BDB5 ; cycles=3/8 nt/t +BDA9: 4D 00 C6 CMP:I #H'00C6, R5 ; cycles=3 +BDAC: 27 07 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDAE: 4D 00 F8 CMP:I #H'00F8, R5 ; cycles=3 +BDB1: 27 02 BEQ loc_BDB5 ; cycles=3/8 nt/t +BDB3: 20 0D BRA loc_BDC2 ; cycles=8 loc_BDB5: -BDB5: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs H'F731 in on_chip_ram -BDB9: 15 F7 90 D7 BCLR.B #7, @H'F790 ; refs H'F790 in on_chip_ram -BDBD: 20 03 BRA loc_BDC2 +BDB5: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs H'F731 in on_chip_ram; cycles=8 +BDB9: 15 F7 90 D7 BCLR.B #7, @H'F790 ; refs H'F790 in on_chip_ram; cycles=8 +BDBD: 20 03 BRA loc_BDC2 ; cycles=8 loc_BDBF: -BDBF: 1E 00 AE BSR loc_BE70 +BDBF: 1E 00 AE BSR loc_BE70 ; cycles=14 loc_BDC2: -BDC2: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BDC6: 27 08 BEQ loc_BDD0 -BDC8: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs H'F9B5 in on_chip_ram -BDCC: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs H'F9B5 in on_chip_ram +BDC2: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=7 +BDC6: 27 08 BEQ loc_BDD0 ; cycles=3/7 nt/t +BDC8: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=9 +BDCC: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=9 loc_BDD0: -BDD0: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram -BDD4: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BDD8: 30 00 94 BRA loc_BE6F +BDD0: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=9 +BDD4: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=9 +BDD8: 30 00 94 BRA loc_BE6F ; cycles=7 loc_BDDB: -BDDB: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram -BDDF: A0 10 SWAP.B R0 -BDE1: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram -BDE5: FC E4 00 90 MOV:G.W R0, @(-H'1C00,R4) -BDE9: F5 EC 00 C6 BSET.B #6, @(-H'1400,R5) -BDED: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram -BDF1: 27 08 BEQ loc_BDFB -BDF3: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs H'F9B5 in on_chip_ram -BDF7: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs H'F9B5 in on_chip_ram +BDDB: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs H'F863 in on_chip_ram; cycles=6 +BDDF: A0 10 SWAP.B R0 ; cycles=3 +BDE1: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram; cycles=6 +BDE5: FC E4 00 90 MOV:G.W R0, @(-H'1C00,R4) ; cycles=6 +BDE9: F5 EC 00 C6 BSET.B #6, @(-H'1400,R5) ; cycles=8 +BDED: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=6 +BDF1: 27 08 BEQ loc_BDFB ; cycles=3/8 nt/t +BDF3: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=8 +BDF7: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs H'F9B5 in on_chip_ram; cycles=8 loc_BDFB: -BDFB: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram -BDFF: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BE03: 20 6A BRA loc_BE6F +BDFB: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=8 +BDFF: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BE03: 20 6A BRA loc_BE6F ; cycles=8 loc_BE05: -BE05: 1D F8 58 80 MOV:G.W @H'F858, R0 ; refs H'F858 in on_chip_ram -BE09: 1D F8 50 90 MOV:G.W R0, @H'F850 ; refs H'F850 in on_chip_ram -BE0D: 1D F8 5A 80 MOV:G.W @H'F85A, R0 ; refs H'F85A in on_chip_ram -BE11: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs H'F852 in on_chip_ram -BE15: 1D F8 5C 80 MOV:G.W @H'F85C, R0 ; refs H'F85C in on_chip_ram -BE19: 1D F8 54 90 MOV:G.W R0, @H'F854 ; refs H'F854 in on_chip_ram -BE1D: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs H'F9C0 in on_chip_ram -BE22: 1E FC 01 BSR loc_BA26 -BE25: 20 48 BRA loc_BE6F +BE05: 1D F8 58 80 MOV:G.W @H'F858, R0 ; refs H'F858 in on_chip_ram; cycles=6 +BE09: 1D F8 50 90 MOV:G.W R0, @H'F850 ; refs H'F850 in on_chip_ram; cycles=6 +BE0D: 1D F8 5A 80 MOV:G.W @H'F85A, R0 ; refs H'F85A in on_chip_ram; cycles=6 +BE11: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs H'F852 in on_chip_ram; cycles=6 +BE15: 1D F8 5C 80 MOV:G.W @H'F85C, R0 ; refs H'F85C in on_chip_ram; cycles=6 +BE19: 1D F8 54 90 MOV:G.W R0, @H'F854 ; refs H'F854 in on_chip_ram; cycles=6 +BE1D: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 +BE22: 1E FC 01 BSR loc_BA26 ; cycles=13 +BE25: 20 48 BRA loc_BE6F ; cycles=8 loc_BE27: -BE27: 20 46 BRA loc_BE6F +BE27: 20 46 BRA loc_BE6F ; cycles=8 loc_BE29: -BE29: 15 FA A4 D7 BCLR.B #7, @H'FAA4 ; refs H'FAA4 in on_chip_ram -BE2D: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram -BE31: 27 3A BEQ loc_BE6D -BE33: 15 FA A6 08 ADD:Q.B #1, @H'FAA6 ; refs H'FAA6 in on_chip_ram -BE37: 15 FA A6 04 02 CMP:G.B #H'02, @H'FAA6 ; refs H'FAA6 in on_chip_ram -BE3C: 25 0F BCS loc_BE4D -BE3E: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs H'F9C0 in on_chip_ram -BE43: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram -BE47: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BE4B: 20 20 BRA loc_BE6D +BE29: 15 FA A4 D7 BCLR.B #7, @H'FAA4 ; refs H'FAA4 in on_chip_ram; cycles=8 +BE2D: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs H'FAA5 in on_chip_ram; cycles=6 +BE31: 27 3A BEQ loc_BE6D ; cycles=3/8 nt/t +BE33: 15 FA A6 08 ADD:Q.B #1, @H'FAA6 ; refs H'FAA6 in on_chip_ram; cycles=8 +BE37: 15 FA A6 04 02 CMP:G.B #H'02, @H'FAA6 ; refs H'FAA6 in on_chip_ram; cycles=6 +BE3C: 25 0F BCS loc_BE4D ; cycles=3/7 nt/t +BE3E: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 +BE43: 15 FA A3 13 CLR.B @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=8 +BE47: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BE4B: 20 20 BRA loc_BE6D ; cycles=8 loc_BE4D: -BE4D: 15 F8 50 06 07 MOV:G.B #H'07, @H'F850 ; refs H'F850 in on_chip_ram -BE52: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs H'F861 in on_chip_ram -BE56: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram -BE5A: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs H'F862 in on_chip_ram -BE5E: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs H'F852 in on_chip_ram -BE62: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram -BE66: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs H'F854 in on_chip_ram -BE6A: 1E FB B9 BSR loc_BA26 +BE4D: 15 F8 50 06 07 MOV:G.B #H'07, @H'F850 ; refs H'F850 in on_chip_ram; cycles=9 +BE52: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs H'F861 in on_chip_ram; cycles=7 +BE56: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs H'F851 in on_chip_ram; cycles=7 +BE5A: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs H'F862 in on_chip_ram; cycles=7 +BE5E: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs H'F852 in on_chip_ram; cycles=7 +BE62: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs H'F864 in on_chip_ram; cycles=7 +BE66: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs H'F854 in on_chip_ram; cycles=7 +BE6A: 1E FB B9 BSR loc_BA26 ; cycles=13 loc_BE6D: -BE6D: 20 00 BRA loc_BE6F +BE6D: 20 00 BRA loc_BE6F ; cycles=8 loc_BE6F: -BE6F: 19 RTS +BE6F: 19 RTS ; cycles=13 loc_BE70: -BE70: 15 F9 B9 83 MOV:G.B @H'F9B9, R3 ; refs H'F9B9 in on_chip_ram -BE74: A3 12 EXTU.B R3 -BE76: AB 1A SHLL.W R3 -BE78: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs H'F9B4 in on_chip_ram -BE7C: A1 12 EXTU.B R1 -BE7E: A9 1A SHLL.W R1 +BE70: 15 F9 B9 83 MOV:G.B @H'F9B9, R3 ; refs H'F9B9 in on_chip_ram; cycles=7 +BE74: A3 12 EXTU.B R3 ; cycles=3 +BE76: AB 1A SHLL.W R3 ; cycles=3 +BE78: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs H'F9B4 in on_chip_ram; cycles=7 +BE7C: A1 12 EXTU.B R1 ; cycles=3 +BE7E: A9 1A SHLL.W R1 ; cycles=3 loc_BE80: -BE80: A3 71 CMP:G.B R3, R1 -BE82: 27 0D BEQ loc_BE91 -BE84: FB F9 70 75 CMP:G.W @(-H'0690,R3), R5 -BE88: 27 13 BEQ loc_BE9D -BE8A: A3 09 ADD:Q.B #2, R3 -BE8C: 04 3F 53 AND.B #H'3F, R3 -BE8F: 20 EF BRA loc_BE80 +BE80: A3 71 CMP:G.B R3, R1 ; cycles=2 +BE82: 27 0D BEQ loc_BE91 ; cycles=3/7 nt/t +BE84: FB F9 70 75 CMP:G.W @(-H'0690,R3), R5 ; cycles=7 +BE88: 27 13 BEQ loc_BE9D ; cycles=3/7 nt/t +BE8A: A3 09 ADD:Q.B #2, R3 ; cycles=4 +BE8C: 04 3F 53 AND.B #H'3F, R3 ; cycles=3 +BE8F: 20 EF BRA loc_BE80 ; cycles=8 loc_BE91: -BE91: F9 F9 70 95 MOV:G.W R5, @(-H'0690,R1) -BE95: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs H'F9B4 in on_chip_ram -BE99: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs H'F9B4 in on_chip_ram +BE91: F9 F9 70 95 MOV:G.W R5, @(-H'0690,R1) ; cycles=6 +BE95: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs H'F9B4 in on_chip_ram; cycles=8 +BE99: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs H'F9B4 in on_chip_ram; cycles=8 loc_BE9D: -BE9D: 19 RTS +BE9D: 19 RTS ; cycles=13 loc_BE9E: -BE9E: 15 FA A5 80 MOV:G.B @H'FAA5, R0 ; refs H'FAA5 in on_chip_ram -BEA2: 04 80 50 AND.B #H'80, R0 -BEA5: 15 FA A3 50 AND.B @H'FAA3, R0 ; refs H'FAA3 in on_chip_ram -BEA9: 15 FA A3 90 MOV:G.B R0, @H'FAA3 ; refs H'FAA3 in on_chip_ram -BEAD: 26 06 BNE loc_BEB5 -BEAF: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram -BEB3: 20 33 BRA loc_BEE8 +BE9E: 15 FA A5 80 MOV:G.B @H'FAA5, R0 ; refs H'FAA5 in on_chip_ram; cycles=7 +BEA2: 04 80 50 AND.B #H'80, R0 ; cycles=3 +BEA5: 15 FA A3 50 AND.B @H'FAA3, R0 ; refs H'FAA3 in on_chip_ram; cycles=6 +BEA9: 15 FA A3 90 MOV:G.B R0, @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=6 +BEAD: 26 06 BNE loc_BEB5 ; cycles=3/8 nt/t +BEAF: 15 FA A2 13 CLR.B @H'FAA2 ; refs H'FAA2 in on_chip_ram; cycles=8 +BEB3: 20 33 BRA loc_BEE8 ; cycles=8 loc_BEB5: -BEB5: 1D F9 C6 16 TST.W @H'F9C6 ; refs H'F9C6 in on_chip_ram -BEB9: 26 2D BNE loc_BEE8 -BEBB: 15 F9 C8 16 TST.B @H'F9C8 ; refs H'F9C8 in on_chip_ram -BEBF: 27 23 BEQ loc_BEE4 -BEC1: 15 F9 C8 0C ADD:Q.B #-1, @H'F9C8 ; refs H'F9C8 in on_chip_ram -BEC5: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs H'F9C6 in on_chip_ram -BECB: 15 FA A3 F7 BTST.B #7, @H'FAA3 ; refs H'FAA3 in on_chip_ram -BECF: 27 17 BEQ loc_BEE8 -BED1: 15 F9 C3 13 CLR.B @H'F9C3 ; refs H'F9C3 in on_chip_ram -BED5: 1E FB 4E BSR loc_BA26 -BED8: 20 0E BRA loc_BEE8 +BEB5: 1D F9 C6 16 TST.W @H'F9C6 ; refs H'F9C6 in on_chip_ram; cycles=6 +BEB9: 26 2D BNE loc_BEE8 ; cycles=3/8 nt/t +BEBB: 15 F9 C8 16 TST.B @H'F9C8 ; refs H'F9C8 in on_chip_ram; cycles=6 +BEBF: 27 23 BEQ loc_BEE4 ; cycles=3/8 nt/t +BEC1: 15 F9 C8 0C ADD:Q.B #-1, @H'F9C8 ; refs H'F9C8 in on_chip_ram; cycles=8 +BEC5: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs H'F9C6 in on_chip_ram; cycles=9 +BECB: 15 FA A3 F7 BTST.B #7, @H'FAA3 ; refs H'FAA3 in on_chip_ram; cycles=6 +BECF: 27 17 BEQ loc_BEE8 ; cycles=3/8 nt/t +BED1: 15 F9 C3 13 CLR.B @H'F9C3 ; refs H'F9C3 in on_chip_ram; cycles=8 +BED5: 1E FB 4E BSR loc_BA26 ; cycles=14 +BED8: 20 0E BRA loc_BEE8 ; cycles=7 loc_BEE4: -BEE4: 15 F9 C5 13 CLR.B @H'F9C5 ; refs H'F9C5 in on_chip_ram +BEE4: 15 F9 C5 13 CLR.B @H'F9C5 ; refs H'F9C5 in on_chip_ram; cycles=9 loc_BEE8: -BEE8: 19 RTS +BEE8: 19 RTS ; cycles=12 vec_frt1_ocia_BEEA: -BEEA: 15 FE 91 D5 BCLR.B #5, @FRT1_TCSR ; clear OCFA (bit 5) of FRT1_TCSR -BEEE: 15 F9 C0 16 TST.B @H'F9C0 ; refs H'F9C0 in on_chip_ram -BEF2: 27 04 BEQ loc_BEF8 -BEF4: 15 F9 C0 0C ADD:Q.B #-1, @H'F9C0 ; refs H'F9C0 in on_chip_ram +BEEA: 15 FE 91 D5 BCLR.B #5, @FRT1_TCSR ; clear OCFA (bit 5) of FRT1_TCSR; cycles=9 +BEEE: 15 F9 C0 16 TST.B @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=7 +BEF2: 27 04 BEQ loc_BEF8 ; cycles=3/7 nt/t +BEF4: 15 F9 C0 0C ADD:Q.B #-1, @H'F9C0 ; refs H'F9C0 in on_chip_ram; cycles=9 loc_BEF8: -BEF8: 15 F9 C1 16 TST.B @H'F9C1 ; refs H'F9C1 in on_chip_ram -BEFC: 27 04 BEQ loc_BF02 -BEFE: 15 F9 C1 0C ADD:Q.B #-1, @H'F9C1 ; refs H'F9C1 in on_chip_ram +BEF8: 15 F9 C1 16 TST.B @H'F9C1 ; refs H'F9C1 in on_chip_ram; cycles=7 +BEFC: 27 04 BEQ loc_BF02 ; cycles=3/7 nt/t +BEFE: 15 F9 C1 0C ADD:Q.B #-1, @H'F9C1 ; refs H'F9C1 in on_chip_ram; cycles=9 loc_BF02: -BF02: 1D F9 C6 16 TST.W @H'F9C6 ; refs H'F9C6 in on_chip_ram -BF06: 27 04 BEQ loc_BF0C -BF08: 1D F9 C6 0C ADD:Q.W #-1, @H'F9C6 ; refs H'F9C6 in on_chip_ram +BF02: 1D F9 C6 16 TST.W @H'F9C6 ; refs H'F9C6 in on_chip_ram; cycles=7 +BF06: 27 04 BEQ loc_BF0C ; cycles=3/7 nt/t +BF08: 1D F9 C6 0C ADD:Q.W #-1, @H'F9C6 ; refs H'F9C6 in on_chip_ram; cycles=9 loc_BF0C: -BF0C: 15 F6 F6 F7 BTST.B #7, @H'F6F6 ; refs H'F6F6 in on_chip_ram -BF10: 27 10 BEQ loc_BF22 -BF12: 1D F6 F4 16 TST.W @H'F6F4 ; refs H'F6F4 in on_chip_ram -BF16: 26 06 BNE loc_BF1E -BF18: 15 F6 F6 C5 BSET.B #5, @H'F6F6 ; refs H'F6F6 in on_chip_ram -BF1C: 20 04 BRA loc_BF22 +BF0C: 15 F6 F6 F7 BTST.B #7, @H'F6F6 ; refs H'F6F6 in on_chip_ram; cycles=7 +BF10: 27 10 BEQ loc_BF22 ; cycles=3/7 nt/t +BF12: 1D F6 F4 16 TST.W @H'F6F4 ; refs H'F6F4 in on_chip_ram; cycles=7 +BF16: 26 06 BNE loc_BF1E ; cycles=3/7 nt/t +BF18: 15 F6 F6 C5 BSET.B #5, @H'F6F6 ; refs H'F6F6 in on_chip_ram; cycles=9 +BF1C: 20 04 BRA loc_BF22 ; cycles=7 loc_BF1E: -BF1E: 1D F6 F4 0C ADD:Q.W #-1, @H'F6F4 ; refs H'F6F4 in on_chip_ram +BF1E: 1D F6 F4 0C ADD:Q.W #-1, @H'F6F4 ; refs H'F6F4 in on_chip_ram; cycles=9 loc_BF22: -BF22: 0A RTE +BF22: 0A RTE ; cycles=13 vec_frt2_ocia_BF23: -BF23: 15 FE A1 D5 BCLR.B #5, @FRT2_TCSR ; clear OCFA (bit 5) of FRT2_TCSR -BF27: 15 F9 C4 16 TST.B @H'F9C4 ; refs H'F9C4 in on_chip_ram -BF2B: 27 04 BEQ loc_BF31 -BF2D: 15 F9 C4 0C ADD:Q.B #-1, @H'F9C4 ; refs H'F9C4 in on_chip_ram +BF23: 15 FE A1 D5 BCLR.B #5, @FRT2_TCSR ; clear OCFA (bit 5) of FRT2_TCSR; cycles=8 +BF27: 15 F9 C4 16 TST.B @H'F9C4 ; refs H'F9C4 in on_chip_ram; cycles=6 +BF2B: 27 04 BEQ loc_BF31 ; cycles=3/8 nt/t +BF2D: 15 F9 C4 0C ADD:Q.B #-1, @H'F9C4 ; refs H'F9C4 in on_chip_ram; cycles=8 loc_BF31: -BF31: 15 F9 C5 16 TST.B @H'F9C5 ; refs H'F9C5 in on_chip_ram -BF35: 27 04 BEQ loc_BF3B -BF37: 15 F9 C5 0C ADD:Q.B #-1, @H'F9C5 ; refs H'F9C5 in on_chip_ram +BF31: 15 F9 C5 16 TST.B @H'F9C5 ; refs H'F9C5 in on_chip_ram; cycles=6 +BF35: 27 04 BEQ loc_BF3B ; cycles=3/8 nt/t +BF37: 15 F9 C5 0C ADD:Q.B #-1, @H'F9C5 ; refs H'F9C5 in on_chip_ram; cycles=8 loc_BF3B: -BF3B: 15 F7 24 16 TST.B @H'F724 ; refs H'F724 in on_chip_ram -BF3F: 27 06 BEQ loc_BF47 -BF41: 15 F7 24 0C ADD:Q.B #-1, @H'F724 ; refs H'F724 in on_chip_ram -BF45: 20 09 BRA loc_BF50 +BF3B: 15 F7 24 16 TST.B @H'F724 ; refs H'F724 in on_chip_ram; cycles=6 +BF3F: 27 06 BEQ loc_BF47 ; cycles=3/8 nt/t +BF41: 15 F7 24 0C ADD:Q.B #-1, @H'F724 ; refs H'F724 in on_chip_ram; cycles=8 +BF45: 20 09 BRA loc_BF50 ; cycles=8 loc_BF47: -BF47: 15 F7 24 06 03 MOV:G.B #H'03, @H'F724 ; refs H'F724 in on_chip_ram -BF4C: 15 F7 23 15 NOT.B @H'F723 ; refs H'F723 in on_chip_ram +BF47: 15 F7 24 06 03 MOV:G.B #H'03, @H'F724 ; refs H'F724 in on_chip_ram; cycles=9 +BF4C: 15 F7 23 15 NOT.B @H'F723 ; refs H'F723 in on_chip_ram; cycles=9 loc_BF50: -BF50: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -BF54: 27 17 BEQ loc_BF6D -BF56: 15 FB 02 16 TST.B @H'FB02 ; refs H'FB02 in on_chip_ram -BF5A: 27 06 BEQ loc_BF62 -BF5C: 15 FB 02 0C ADD:Q.B #-1, @H'FB02 ; refs H'FB02 in on_chip_ram -BF60: 20 0B BRA loc_BF6D +BF50: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=7 +BF54: 27 17 BEQ loc_BF6D ; cycles=3/7 nt/t +BF56: 15 FB 02 16 TST.B @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=7 +BF5A: 27 06 BEQ loc_BF62 ; cycles=3/7 nt/t +BF5C: 15 FB 02 0C ADD:Q.B #-1, @H'FB02 ; refs H'FB02 in on_chip_ram; cycles=9 +BF60: 20 0B BRA loc_BF6D ; cycles=7 loc_BF62: -BF62: 15 FB 03 D7 BCLR.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram -BF66: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP -BF68: 1E 89 84 BSR loc_48EF -BF6B: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} +BF62: 15 FB 03 D7 BCLR.B #7, @H'FB03 ; refs H'FB03 in on_chip_ram; cycles=9 +BF66: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +BF68: 1E 89 84 BSR loc_48EF ; cycles=13 +BF6B: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 loc_BF6D: -BF6D: 15 F7 6C 16 TST.B @H'F76C ; refs H'F76C in on_chip_ram -BF71: 27 04 BEQ loc_BF77 -BF73: 15 F7 6C 0C ADD:Q.B #-1, @H'F76C ; refs H'F76C in on_chip_ram +BF6D: 15 F7 6C 16 TST.B @H'F76C ; refs H'F76C in on_chip_ram; cycles=6 +BF71: 27 04 BEQ loc_BF77 ; cycles=3/8 nt/t +BF73: 15 F7 6C 0C ADD:Q.B #-1, @H'F76C ; refs H'F76C in on_chip_ram; cycles=8 loc_BF77: -BF77: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram -BF7B: 27 04 BEQ loc_BF81 -BF7D: 15 F8 40 0C ADD:Q.B #-1, @H'F840 ; refs H'F840 in on_chip_ram +BF77: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram; cycles=6 +BF7B: 27 04 BEQ loc_BF81 ; cycles=3/8 nt/t +BF7D: 15 F8 40 0C ADD:Q.B #-1, @H'F840 ; refs H'F840 in on_chip_ram; cycles=8 loc_BF81: -BF81: 15 F7 26 16 TST.B @H'F726 ; refs H'F726 in on_chip_ram -BF85: 27 1C BEQ loc_BFA3 -BF87: 15 F7 26 0C ADD:Q.B #-1, @H'F726 ; refs H'F726 in on_chip_ram -BF8B: 26 16 BNE loc_BFA3 -BF8D: 15 F7 13 D6 BCLR.B #6, @H'F713 ; refs H'F713 in on_chip_ram -BF91: 26 10 BNE loc_BFA3 -BF93: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs H'F711 in on_chip_ram -BF97: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs H'F711 in on_chip_ram -BF9B: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs H'F711 in on_chip_ram -BF9F: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs H'F711 in on_chip_ram +BF81: 15 F7 26 16 TST.B @H'F726 ; refs H'F726 in on_chip_ram; cycles=6 +BF85: 27 1C BEQ loc_BFA3 ; cycles=3/8 nt/t +BF87: 15 F7 26 0C ADD:Q.B #-1, @H'F726 ; refs H'F726 in on_chip_ram; cycles=8 +BF8B: 26 16 BNE loc_BFA3 ; cycles=3/8 nt/t +BF8D: 15 F7 13 D6 BCLR.B #6, @H'F713 ; refs H'F713 in on_chip_ram; cycles=8 +BF91: 26 10 BNE loc_BFA3 ; cycles=3/8 nt/t +BF93: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs H'F711 in on_chip_ram; cycles=8 +BF97: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs H'F711 in on_chip_ram; cycles=8 +BF9B: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs H'F711 in on_chip_ram; cycles=8 +BF9F: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs H'F711 in on_chip_ram; cycles=8 loc_BFA3: -BFA3: 15 F7 97 16 TST.B @H'F797 ; refs H'F797 in on_chip_ram -BFA7: 27 0A BEQ loc_BFB3 -BFA9: 15 F7 97 0C ADD:Q.B #-1, @H'F797 ; refs H'F797 in on_chip_ram -BFAD: 26 04 BNE loc_BFB3 -BFAF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs H'F731 in on_chip_ram +BFA3: 15 F7 97 16 TST.B @H'F797 ; refs H'F797 in on_chip_ram; cycles=6 +BFA7: 27 0A BEQ loc_BFB3 ; cycles=3/8 nt/t +BFA9: 15 F7 97 0C ADD:Q.B #-1, @H'F797 ; refs H'F797 in on_chip_ram; cycles=8 +BFAD: 26 04 BNE loc_BFB3 ; cycles=3/8 nt/t +BFAF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs H'F731 in on_chip_ram; cycles=8 loc_BFB3: -BFB3: 15 F7 98 16 TST.B @H'F798 ; refs H'F798 in on_chip_ram -BFB7: 27 0A BEQ loc_BFC3 -BFB9: 15 F7 98 0C ADD:Q.B #-1, @H'F798 ; refs H'F798 in on_chip_ram -BFBD: 26 04 BNE loc_BFC3 -BFBF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs H'F731 in on_chip_ram +BFB3: 15 F7 98 16 TST.B @H'F798 ; refs H'F798 in on_chip_ram; cycles=6 +BFB7: 27 0A BEQ loc_BFC3 ; cycles=3/8 nt/t +BFB9: 15 F7 98 0C ADD:Q.B #-1, @H'F798 ; refs H'F798 in on_chip_ram; cycles=8 +BFBD: 26 04 BNE loc_BFC3 ; cycles=3/8 nt/t +BFBF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs H'F731 in on_chip_ram; cycles=8 loc_BFC3: -BFC3: 0A RTE +BFC3: 0A RTE ; cycles=14 vec_interval_timer_BFC4: -BFC4: 15 FE EC F7 BTST.B #7, @WDT_TCSR_R ; refs WDT_TCSR_R in register_field -BFC8: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096) -BFCE: 15 F7 94 08 ADD:Q.B #1, @H'F794 ; refs H'F794 in on_chip_ram -BFD2: 15 F7 94 04 0A CMP:G.B #H'0A, @H'F794 ; refs H'F794 in on_chip_ram -BFD7: 26 06 BNE loc_BFDF -BFD9: 1D FE EC 07 A5 7F MOV:G.W #H'A57F, @WDT_TCSR_R ; WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096) +BFC4: 15 FE EC F7 BTST.B #7, @WDT_TCSR_R ; refs WDT_TCSR_R in register_field; cycles=7 +BFC8: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 +BFCE: 15 F7 94 08 ADD:Q.B #1, @H'F794 ; refs H'F794 in on_chip_ram; cycles=9 +BFD2: 15 F7 94 04 0A CMP:G.B #H'0A, @H'F794 ; refs H'F794 in on_chip_ram; cycles=7 +BFD7: 26 06 BNE loc_BFDF ; cycles=3/8 nt/t +BFD9: 1D FE EC 07 A5 7F MOV:G.W #H'A57F, @WDT_TCSR_R ; WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096); cycles=9 loc_BFDF: -BFDF: 0A RTE +BFDF: 0A RTE ; cycles=14 loc_BFE0: -BFE0: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs H'F840 in on_chip_ram +BFE0: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs H'F840 in on_chip_ram; cycles=9 loc_BFE5: -BFE5: AD 82 MOV:G.W R5, R2 -BFE7: 0E 27 BSR loc_C010 -BFE9: 0E 4E BSR loc_C039 -BFEB: AA 75 CMP:G.W R2, R5 -BFED: 27 0E BEQ loc_BFFD -BFEF: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram -BFF3: 27 04 BEQ loc_BFF9 -BFF5: AA 85 MOV:G.W R2, R5 -BFF7: 20 EC BRA loc_BFE5 +BFE5: AD 82 MOV:G.W R5, R2 ; cycles=3 +BFE7: 0E 27 BSR loc_C010 ; cycles=14 +BFE9: 0E 4E BSR loc_C039 ; cycles=14 +BFEB: AA 75 CMP:G.W R2, R5 ; cycles=3 +BFED: 27 0E BEQ loc_BFFD ; cycles=3/8 nt/t +BFEF: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram; cycles=6 +BFF3: 27 04 BEQ loc_BFF9 ; cycles=3/8 nt/t +BFF5: AA 85 MOV:G.W R2, R5 ; cycles=3 +BFF7: 20 EC BRA loc_BFE5 ; cycles=8 loc_BFF9: -BFF9: 15 F8 41 C7 BSET.B #7, @H'F841 ; refs H'F841 in on_chip_ram +BFF9: 15 F8 41 C7 BSET.B #7, @H'F841 ; refs H'F841 in on_chip_ram; cycles=8 loc_BFFD: -BFFD: 19 RTS +BFFD: 19 RTS ; cycles=13 loc_BFFE: -BFFE: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs H'F840 in on_chip_ram -C003: 0E 34 BSR loc_C039 -C005: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram -C009: 26 04 BNE loc_C00F -C00B: 15 F8 41 C6 BSET.B #6, @H'F841 ; refs H'F841 in on_chip_ram +BFFE: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs H'F840 in on_chip_ram; cycles=9 +C003: 0E 34 BSR loc_C039 ; cycles=14 +C005: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram; cycles=6 +C009: 26 04 BNE loc_C00F ; cycles=3/8 nt/t +C00B: 15 F8 41 C6 BSET.B #6, @H'F841 ; refs H'F841 in on_chip_ram; cycles=8 loc_C00F: -C00F: 19 RTS +C00F: 19 RTS ; cycles=13 loc_C010: -C010: 0E 58 BSR loc_C06A +C010: 0E 58 BSR loc_C06A ; cycles=13 loc_C012: -C012: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram -C016: 27 20 BEQ loc_C038 -C018: 1E 01 06 BSR loc_C121 -C01B: A3 80 MOV:G.B R3, R0 -C01D: 0E 6C BSR loc_C08B -C01F: 27 F1 BEQ loc_C012 -C021: A4 80 MOV:G.B R4, R0 -C023: 0E 66 BSR loc_C08B -C025: 27 EB BEQ loc_C012 -C027: AD 80 MOV:G.W R5, R0 -C029: A0 10 SWAP.B R0 -C02B: 0E 5E BSR loc_C08B -C02D: 27 E3 BEQ loc_C012 -C02F: A5 80 MOV:G.B R5, R0 -C031: 0E 58 BSR loc_C08B -C033: 27 DD BEQ loc_C012 -C035: 1E 01 0A BSR loc_C142 +C012: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram; cycles=7 +C016: 27 20 BEQ loc_C038 ; cycles=3/7 nt/t +C018: 1E 01 06 BSR loc_C121 ; cycles=13 +C01B: A3 80 MOV:G.B R3, R0 ; cycles=2 +C01D: 0E 6C BSR loc_C08B ; cycles=14 +C01F: 27 F1 BEQ loc_C012 ; cycles=3/8 nt/t +C021: A4 80 MOV:G.B R4, R0 ; cycles=2 +C023: 0E 66 BSR loc_C08B ; cycles=14 +C025: 27 EB BEQ loc_C012 ; cycles=3/8 nt/t +C027: AD 80 MOV:G.W R5, R0 ; cycles=3 +C029: A0 10 SWAP.B R0 ; cycles=3 +C02B: 0E 5E BSR loc_C08B ; cycles=14 +C02D: 27 E3 BEQ loc_C012 ; cycles=3/8 nt/t +C02F: A5 80 MOV:G.B R5, R0 ; cycles=2 +C031: 0E 58 BSR loc_C08B ; cycles=14 +C033: 27 DD BEQ loc_C012 ; cycles=3/8 nt/t +C035: 1E 01 0A BSR loc_C142 ; cycles=14 loc_C038: -C038: 19 RTS +C038: 19 RTS ; cycles=12 loc_C039: -C039: 0E 2F BSR loc_C06A +C039: 0E 2F BSR loc_C06A ; cycles=14 loc_C03B: -C03B: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram -C03F: 27 28 BEQ loc_C069 -C041: 1E 00 DD BSR loc_C121 -C044: A3 80 MOV:G.B R3, R0 -C046: 0E 43 BSR loc_C08B -C048: 27 F1 BEQ loc_C03B -C04A: A4 80 MOV:G.B R4, R0 -C04C: 0E 3D BSR loc_C08B -C04E: 27 EB BEQ loc_C03B -C050: 1E 00 CE BSR loc_C121 -C053: A3 80 MOV:G.B R3, R0 -C055: A0 C0 BSET.B #0, R0 -C057: 0E 32 BSR loc_C08B -C059: 27 E0 BEQ loc_C03B -C05B: 1E 00 7D BSR loc_C0DB -C05E: A5 10 SWAP.B R5 -C060: 1E 00 A9 BSR loc_C10C -C063: 1E 00 75 BSR loc_C0DB -C066: 1E 00 D9 BSR loc_C142 +C03B: 15 F8 40 16 TST.B @H'F840 ; refs H'F840 in on_chip_ram; cycles=6 +C03F: 27 28 BEQ loc_C069 ; cycles=3/8 nt/t +C041: 1E 00 DD BSR loc_C121 ; cycles=14 +C044: A3 80 MOV:G.B R3, R0 ; cycles=2 +C046: 0E 43 BSR loc_C08B ; cycles=13 +C048: 27 F1 BEQ loc_C03B ; cycles=3/7 nt/t +C04A: A4 80 MOV:G.B R4, R0 ; cycles=2 +C04C: 0E 3D BSR loc_C08B ; cycles=13 +C04E: 27 EB BEQ loc_C03B ; cycles=3/7 nt/t +C050: 1E 00 CE BSR loc_C121 ; cycles=13 +C053: A3 80 MOV:G.B R3, R0 ; cycles=2 +C055: A0 C0 BSET.B #0, R0 ; cycles=2 +C057: 0E 32 BSR loc_C08B ; cycles=14 +C059: 27 E0 BEQ loc_C03B ; cycles=3/8 nt/t +C05B: 1E 00 7D BSR loc_C0DB ; cycles=14 +C05E: A5 10 SWAP.B R5 ; cycles=3 +C060: 1E 00 A9 BSR loc_C10C ; cycles=13 +C063: 1E 00 75 BSR loc_C0DB ; cycles=14 +C066: 1E 00 D9 BSR loc_C142 ; cycles=13 loc_C069: -C069: 19 RTS +C069: 19 RTS ; cycles=13 loc_C06A: -C06A: 0C 0F FF 54 AND.W #H'0FFF, R4 -C06E: 4C 08 00 CMP:I #H'0800, R4 -C071: 24 0B BCC loc_C07E -C073: AC 83 MOV:G.W R4, R3 -C075: A3 10 SWAP.B R3 -C077: A3 1A SHLL.B R3 -C079: 04 A0 43 OR.B #H'A0, R3 -C07C: 20 0C BRA loc_C08A +C06A: 0C 0F FF 54 AND.W #H'0FFF, R4 ; cycles=4 +C06E: 4C 08 00 CMP:I #H'0800, R4 ; cycles=3 +C071: 24 0B BCC loc_C07E ; cycles=3/8 nt/t +C073: AC 83 MOV:G.W R4, R3 ; cycles=3 +C075: A3 10 SWAP.B R3 ; cycles=3 +C077: A3 1A SHLL.B R3 ; cycles=2 +C079: 04 A0 43 OR.B #H'A0, R3 ; cycles=3 +C07C: 20 0C BRA loc_C08A ; cycles=7 loc_C07E: -C07E: AC 83 MOV:G.W R4, R3 -C080: A3 10 SWAP.B R3 -C082: A3 1A SHLL.B R3 -C084: 04 0E 53 AND.B #H'0E, R3 -C087: 04 E0 43 OR.B #H'E0, R3 +C07E: AC 83 MOV:G.W R4, R3 ; cycles=3 +C080: A3 10 SWAP.B R3 ; cycles=3 +C082: A3 1A SHLL.B R3 ; cycles=2 +C084: 04 0E 53 AND.B #H'0E, R3 ; cycles=3 +C087: 04 E0 43 OR.B #H'E0, R3 ; cycles=3 loc_C08A: -C08A: 19 RTS +C08A: 19 RTS ; cycles=12 loc_C08B: -C08B: 59 00 07 MOV:I.W #H'0007, R1 +C08B: 59 00 07 MOV:I.W #H'0007, R1 ; cycles=3 loc_C08E: -C08E: A0 1A SHLL.B R0 -C090: 24 06 BCC loc_C098 -C092: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR -C096: 20 04 BRA loc_C09C +C08E: A0 1A SHLL.B R0 ; cycles=2 +C090: 24 06 BCC loc_C098 ; cycles=3/7 nt/t +C092: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C096: 20 04 BRA loc_C09C ; cycles=7 loc_C098: -C098: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR +C098: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 loc_C09C: -C09C: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0A0: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0A4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0A8: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C0AC: 01 B9 DF SCB/F R1, loc_C08E -C0AF: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13 -C0B4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0B8: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0BC: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field -C0C0: 27 0D BEQ loc_C0CF -C0C2: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C0C6: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93 -C0CB: 50 00 MOV:E.B #H'00, R0 -C0CD: 20 0B BRA loc_C0DA +C09C: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A0: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A8: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0AC: 01 B9 DF SCB/F R1, loc_C08E ; cycles=3/4/8 false/-1/t +C0AF: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0B4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0B8: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0BC: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=7 +C0C0: 27 0D BEQ loc_C0CF ; cycles=3/7 nt/t +C0C2: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0C6: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0CB: 50 00 MOV:E.B #H'00, R0 ; cycles=2 +C0CD: 20 0B BRA loc_C0DA ; cycles=8 loc_C0CF: -C0CF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C0D3: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93 -C0D8: 50 01 MOV:E.B #H'01, R0 +C0CF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0D3: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0D8: 50 01 MOV:E.B #H'01, R0 ; cycles=2 loc_C0DA: -C0DA: 19 RTS +C0DA: 19 RTS ; cycles=12 loc_C0DB: -C0DB: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13 -C0E0: 59 00 07 MOV:I.W #H'0007, R1 +C0DB: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0E0: 59 00 07 MOV:I.W #H'0007, R1 ; cycles=3 loc_C0E3: -C0E3: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0E7: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C0EB: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field -C0EF: 27 04 BEQ loc_C0F5 -C0F1: A5 49 BSET.B R1, R5 -C0F3: 20 02 BRA loc_C0F7 +C0E3: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0E7: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0EB: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=6 +C0EF: 27 04 BEQ loc_C0F5 ; cycles=3/8 nt/t +C0F1: A5 49 BSET.B R1, R5 ; cycles=2 +C0F3: 20 02 BRA loc_C0F7 ; cycles=8 loc_C0F5: -C0F5: A5 59 BCLR.B R1, R5 +C0F5: A5 59 BCLR.B R1, R5 ; cycles=2 loc_C0F7: -C0F7: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C0FB: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C0FF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C103: 01 B9 DD SCB/F R1, loc_C0E3 -C106: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93 -C10B: 19 RTS +C0F7: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FB: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C103: 01 B9 DD SCB/F R1, loc_C0E3 ; cycles=3/4/9 false/-1/t +C106: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C10B: 19 RTS ; cycles=13 loc_C10C: -C10C: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR -C110: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C114: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C118: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C11C: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C120: 19 RTS +C10C: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C110: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C114: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C118: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C11C: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C120: 19 RTS ; cycles=12 loc_C121: -C121: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR -C125: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C129: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C12D: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C131: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR -C135: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C139: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C13D: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C141: 19 RTS +C121: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=8 +C125: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C129: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C12D: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C131: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=8 +C135: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C139: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C13D: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C141: 19 RTS ; cycles=13 loc_C142: -C142: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR -C146: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C14A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C14E: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C152: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR -C156: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C15A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR -C15E: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR -C162: 19 RTS +C142: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C146: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14E: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C152: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C156: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15E: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C162: 19 RTS ; cycles=12 diff --git a/build/rom_decompiled.json b/build/rom_decompiled.json index 9ca8a95..b753aba 100644 --- a/build/rom_decompiled.json +++ b/build/rom_decompiled.json @@ -4700,6 +4700,11 @@ "operands": "#H'FE80, R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -4713,6 +4718,12 @@ "operands": "#H'0700, SR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -4726,6 +4737,13 @@ "operands": "#H'FF, @P1DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65152, @@ -4746,6 +4764,13 @@ "operands": "#H'00, @P1DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65154, @@ -4766,6 +4791,13 @@ "operands": "#H'F9, @P6DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65161, @@ -4786,6 +4818,13 @@ "operands": "#H'F1, @P6DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65163, @@ -4806,6 +4845,13 @@ "operands": "#H'00, @P7DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65164, @@ -4826,6 +4872,13 @@ "operands": "#H'00, @P7DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -4846,6 +4899,13 @@ "operands": "#H'93, @P9DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65278, @@ -4866,6 +4926,13 @@ "operands": "#H'00, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -4886,6 +4953,13 @@ "operands": "#H'87, @SYSCR1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65276, @@ -4906,6 +4980,13 @@ "operands": "#H'84, @SYSCR2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65277, @@ -4926,6 +5007,13 @@ "operands": "#H'02, @FRT1_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65168, @@ -4946,6 +5034,13 @@ "operands": "#H'01, @FRT1_TCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65169, @@ -4966,6 +5061,12 @@ "operands": "#H'00, @FRT1_FRC_H", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65170, @@ -4986,6 +5087,13 @@ "operands": "#H'009C, @FRT1_OCRA_L", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65172, @@ -5006,6 +5114,13 @@ "operands": "#H'02, @FRT2_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65184, @@ -5026,6 +5141,13 @@ "operands": "#H'01, @FRT2_TCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65185, @@ -5046,6 +5168,13 @@ "operands": "#H'00, @FRT2_FRC_H", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65186, @@ -5066,6 +5195,12 @@ "operands": "#H'7A12, @FRT2_OCRA_H", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65188, @@ -5086,6 +5221,13 @@ "operands": "#H'00, @FRT3_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65200, @@ -5106,6 +5248,13 @@ "operands": "#H'00, @FRT3_TCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65201, @@ -5126,6 +5275,13 @@ "operands": "#H'00, @TMR_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65232, @@ -5146,6 +5302,13 @@ "operands": "#H'10, @TMR_TCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65233, @@ -5166,6 +5329,13 @@ "operands": "#H'38, @PWM1_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65216, @@ -5186,6 +5356,13 @@ "operands": "#H'FF, @PWM1_DTR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65217, @@ -5206,6 +5383,13 @@ "operands": "#H'38, @PWM2_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65220, @@ -5226,6 +5410,13 @@ "operands": "#H'FF, @PWM2_DTR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65221, @@ -5246,6 +5437,13 @@ "operands": "#H'3B, @PWM3_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65224, @@ -5266,6 +5464,13 @@ "operands": "#H'7D, @PWM3_DTR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65225, @@ -5286,6 +5491,13 @@ "operands": "#H'24, @SCI1_SMR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65240, @@ -5306,6 +5518,13 @@ "operands": "#H'3C, @SCI1_SCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65242, @@ -5326,6 +5545,13 @@ "operands": "#H'07, @SCI1_BRR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65241, @@ -5346,6 +5572,13 @@ "operands": "#H'24, @SCI2_SMR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65264, @@ -5366,6 +5599,13 @@ "operands": "#H'0C, @SCI2_SCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65266, @@ -5386,6 +5626,13 @@ "operands": "#H'07, @SCI2_BRR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65265, @@ -5406,6 +5653,13 @@ "operands": "#H'19, @ADCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65256, @@ -5426,6 +5680,13 @@ "operands": "#H'7F, @H'FEE9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65257, @@ -5446,6 +5707,13 @@ "operands": "#H'F0, @WCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65296, @@ -5466,6 +5734,13 @@ "operands": "#H'FF, @RAMCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65297, @@ -5486,6 +5761,12 @@ "operands": "#7, @P1DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65154, @@ -5508,6 +5789,15 @@ "targets": [ 16246 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5521,6 +5811,11 @@ "operands": "#H'0040, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5534,6 +5829,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5549,6 +5849,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5562,6 +5870,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5575,6 +5888,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5590,6 +5908,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5603,6 +5930,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5616,6 +5948,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5631,6 +5968,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5644,6 +5989,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5657,6 +6007,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5672,6 +6027,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5685,6 +6049,11 @@ "operands": "#H'0207, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5698,6 +6067,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5713,6 +6087,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5726,6 +6108,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5739,6 +6126,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5754,6 +6146,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5767,6 +6168,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5780,6 +6186,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5795,6 +6206,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5808,6 +6227,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5821,6 +6245,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5836,6 +6265,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5849,6 +6287,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5862,6 +6305,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5877,6 +6325,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5890,6 +6346,11 @@ "operands": "#H'0048, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5903,6 +6364,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5918,6 +6384,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5931,6 +6406,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5944,6 +6424,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5959,6 +6444,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5972,6 +6465,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -5985,6 +6483,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6000,6 +6503,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6013,6 +6525,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6026,6 +6543,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6041,6 +6563,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6054,6 +6584,11 @@ "operands": "#H'021B, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6067,6 +6602,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6082,6 +6622,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6095,6 +6644,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6108,6 +6662,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6123,6 +6682,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6136,6 +6703,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6149,6 +6721,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6164,6 +6741,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6177,6 +6763,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6190,6 +6781,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6205,6 +6801,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6218,6 +6822,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6231,6 +6840,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6246,6 +6860,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6259,6 +6882,11 @@ "operands": "#H'0050, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6272,6 +6900,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6287,6 +6920,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6300,6 +6941,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6313,6 +6959,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6328,6 +6979,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6341,6 +7001,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6354,6 +7019,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6369,6 +7039,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6382,6 +7060,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6395,6 +7078,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6410,6 +7098,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6423,6 +7120,11 @@ "operands": "#H'021C, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6436,6 +7138,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6451,6 +7158,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6464,6 +7179,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6477,6 +7197,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6492,6 +7217,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6505,6 +7239,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6518,6 +7257,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6533,6 +7277,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6546,6 +7298,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6559,6 +7316,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6574,6 +7336,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6587,6 +7358,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6600,6 +7376,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6615,6 +7396,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6628,6 +7417,11 @@ "operands": "#H'0058, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6641,6 +7435,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6656,6 +7455,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6669,6 +7477,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6682,6 +7495,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6697,6 +7515,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6710,6 +7536,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6723,6 +7554,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6738,6 +7574,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6751,6 +7596,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6764,6 +7614,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6779,6 +7634,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6792,6 +7655,11 @@ "operands": "#H'0207, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6805,6 +7673,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6820,6 +7693,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6833,6 +7715,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6846,6 +7733,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6861,6 +7753,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6874,6 +7774,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6887,6 +7792,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6902,6 +7812,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6915,6 +7834,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6928,6 +7852,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6943,6 +7872,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6956,6 +7893,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6969,6 +7911,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6984,6 +7931,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -6997,6 +7953,11 @@ "operands": "#H'0060, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7010,6 +7971,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7025,6 +7991,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7038,6 +8012,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7051,6 +8030,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7066,6 +8050,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7079,6 +8072,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7092,6 +8090,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7107,6 +8110,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7120,6 +8131,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7133,6 +8149,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7148,6 +8169,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7161,6 +8191,11 @@ "operands": "#H'021B, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7174,6 +8209,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7189,6 +8229,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7202,6 +8250,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7215,6 +8268,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7230,6 +8288,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7243,6 +8310,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7256,6 +8328,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7271,6 +8348,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7284,6 +8369,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7297,6 +8387,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7312,6 +8407,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7325,6 +8429,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7338,6 +8447,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7353,6 +8467,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7366,6 +8488,11 @@ "operands": "#H'0068, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7379,6 +8506,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7394,6 +8526,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7407,6 +8548,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7420,6 +8566,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7435,6 +8586,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7448,6 +8607,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7461,6 +8625,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7476,6 +8645,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7489,6 +8667,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7502,6 +8685,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7517,6 +8705,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7530,6 +8726,11 @@ "operands": "#H'021C, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7543,6 +8744,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7558,6 +8764,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7571,6 +8786,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7584,6 +8804,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7599,6 +8824,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7612,6 +8845,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7625,6 +8863,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7640,6 +8883,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7653,6 +8905,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7666,6 +8923,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7681,6 +8943,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7694,6 +8964,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7707,6 +8982,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7722,6 +9002,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7735,6 +9024,11 @@ "operands": "#H'0070, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7748,6 +9042,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7763,6 +9062,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7776,6 +9083,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7789,6 +9101,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7804,6 +9121,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7817,6 +9143,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7830,6 +9161,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7845,6 +9181,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7858,6 +9202,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7871,6 +9220,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7886,6 +9240,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7899,6 +9262,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7912,6 +9280,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7927,6 +9300,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7940,6 +9321,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7953,6 +9339,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7968,6 +9359,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7981,6 +9381,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -7994,6 +9399,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8009,6 +9419,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8022,6 +9440,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8035,6 +9458,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8050,6 +9478,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8063,6 +9500,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8076,6 +9518,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8091,6 +9538,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8104,6 +9559,11 @@ "operands": "#H'0078, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8117,6 +9577,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8132,6 +9597,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8145,6 +9619,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8158,6 +9637,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8173,6 +9657,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8186,6 +9678,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8199,6 +9696,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8214,6 +9716,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8227,6 +9738,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8240,6 +9756,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8255,6 +9776,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8268,6 +9797,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8281,6 +9815,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8296,6 +9835,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8309,6 +9857,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8322,6 +9875,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8337,6 +9895,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8350,6 +9916,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8363,6 +9934,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8378,6 +9954,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8391,6 +9976,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8404,6 +9994,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8419,6 +10014,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8432,6 +10035,11 @@ "operands": "#H'0204, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8445,6 +10053,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8460,6 +10073,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8473,6 +10095,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8488,6 +10118,14 @@ "targets": [ 9808 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8501,6 +10139,12 @@ "operands": "#7, @H'F689", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63113, @@ -8523,6 +10167,14 @@ "targets": [ 5625 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8536,6 +10188,12 @@ "operands": "@H'F68E, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63118, @@ -8556,6 +10214,12 @@ "operands": "R1, @H'E902", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 59650, @@ -8576,6 +10240,11 @@ "operands": "#H'80, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8589,6 +10258,11 @@ "operands": "#H'0081, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8604,6 +10278,14 @@ "targets": [ 15956 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8617,6 +10299,12 @@ "operands": "@H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8639,6 +10327,14 @@ "targets": [ 5693 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8652,6 +10348,12 @@ "operands": "#7, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8674,6 +10376,14 @@ "targets": [ 5640 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8689,6 +10399,15 @@ "targets": [ 17300 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8702,6 +10421,13 @@ "operands": "#6, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8724,6 +10450,13 @@ "targets": [ 5649 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8739,6 +10472,14 @@ "targets": [ 17495 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8752,6 +10493,12 @@ "operands": "#5, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8774,6 +10521,14 @@ "targets": [ 5658 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8789,6 +10544,15 @@ "targets": [ 17690 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8802,6 +10566,13 @@ "operands": "#4, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8822,6 +10593,13 @@ "operands": "#3, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8844,6 +10622,13 @@ "targets": [ 5671 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8859,6 +10644,14 @@ "targets": [ 5893 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8872,6 +10665,12 @@ "operands": "#2, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8894,6 +10693,14 @@ "targets": [ 5680 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8909,6 +10716,15 @@ "targets": [ 5965 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8922,6 +10738,13 @@ "operands": "#1, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8944,6 +10767,13 @@ "targets": [ 5689 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8959,6 +10789,14 @@ "targets": [ 6037 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -8972,6 +10810,12 @@ "operands": "#0, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -8992,6 +10836,12 @@ "operands": "@H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9014,6 +10864,14 @@ "targets": [ 5766 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9027,6 +10885,12 @@ "operands": "#7, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9049,6 +10913,14 @@ "targets": [ 5708 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9064,6 +10936,15 @@ "targets": [ 6089 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9077,6 +10958,13 @@ "operands": "#6, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9099,6 +10987,13 @@ "targets": [ 5717 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9114,6 +11009,14 @@ "targets": [ 6139 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9127,6 +11030,12 @@ "operands": "#5, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9149,6 +11058,14 @@ "targets": [ 5726 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9164,6 +11081,15 @@ "targets": [ 6189 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9177,6 +11103,13 @@ "operands": "#4, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9199,6 +11132,13 @@ "targets": [ 5735 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9214,6 +11154,14 @@ "targets": [ 6289 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9227,6 +11175,12 @@ "operands": "#3, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9249,6 +11203,14 @@ "targets": [ 5744 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9264,6 +11226,15 @@ "targets": [ 6375 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9277,6 +11248,13 @@ "operands": "#2, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9299,6 +11277,13 @@ "targets": [ 5753 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9314,6 +11299,14 @@ "targets": [ 6474 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9327,6 +11320,12 @@ "operands": "#1, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9349,6 +11348,14 @@ "targets": [ 5762 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9364,6 +11371,15 @@ "targets": [ 6521 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9377,6 +11393,13 @@ "operands": "#0, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -9397,6 +11420,13 @@ "operands": "@H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9419,6 +11449,13 @@ "targets": [ 5844 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9432,6 +11469,13 @@ "operands": "#7, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9454,6 +11498,13 @@ "targets": [ 5781 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9469,6 +11520,14 @@ "targets": [ 6957 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9482,6 +11541,12 @@ "operands": "#6, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9504,6 +11569,14 @@ "targets": [ 5790 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9519,6 +11592,15 @@ "targets": [ 6980 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9532,6 +11614,13 @@ "operands": "#5, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9554,6 +11643,13 @@ "targets": [ 5799 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9569,6 +11665,14 @@ "targets": [ 7003 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9582,6 +11686,12 @@ "operands": "#4, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9604,6 +11714,14 @@ "targets": [ 5808 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9619,6 +11737,15 @@ "targets": [ 7072 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9632,6 +11759,13 @@ "operands": "#3, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9654,6 +11788,13 @@ "targets": [ 5817 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9669,6 +11810,14 @@ "targets": [ 7094 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9682,6 +11831,12 @@ "operands": "#2, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9704,6 +11859,14 @@ "targets": [ 5826 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9719,6 +11882,15 @@ "targets": [ 7116 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9732,6 +11904,13 @@ "operands": "#1, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9754,6 +11933,13 @@ "targets": [ 5835 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9769,6 +11955,14 @@ "targets": [ 7026 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9782,6 +11976,12 @@ "operands": "#0, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -9804,6 +12004,14 @@ "targets": [ 5844 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9819,6 +12027,15 @@ "targets": [ 7049 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9832,6 +12049,13 @@ "operands": "@H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -9854,6 +12078,13 @@ "targets": [ 5892 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9867,6 +12098,13 @@ "operands": "#7, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -9887,6 +12125,13 @@ "operands": "#6, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -9907,6 +12152,13 @@ "operands": "#5, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -9927,6 +12179,13 @@ "operands": "#4, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -9949,6 +12208,13 @@ "targets": [ 5871 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9964,6 +12230,14 @@ "targets": [ 7138 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -9977,6 +12251,12 @@ "operands": "#3, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -9999,6 +12279,14 @@ "targets": [ 5880 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10014,6 +12302,15 @@ "targets": [ 7160 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10027,6 +12324,13 @@ "operands": "#2, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -10047,6 +12351,13 @@ "operands": "#1, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -10067,6 +12378,13 @@ "operands": "#0, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -10087,6 +12405,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10100,6 +12426,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -10122,6 +12454,13 @@ "targets": [ 5956 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10135,6 +12474,13 @@ "operands": "#15, @H'E14E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57678, @@ -10157,6 +12503,13 @@ "targets": [ 5942 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10170,6 +12523,13 @@ "operands": "#6, @H'F730", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63280, @@ -10192,6 +12552,13 @@ "targets": [ 5942 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10205,6 +12572,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -10227,6 +12601,13 @@ "targets": [ 5926 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10240,6 +12621,13 @@ "operands": "@H'F732, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -10260,6 +12648,13 @@ "operands": "R1, @H'F734", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63284, @@ -10280,6 +12675,13 @@ "operands": "#H'1C07, @H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -10300,6 +12702,13 @@ "operands": "#H'14, @H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -10322,6 +12731,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10337,6 +12755,14 @@ "targets": [ 5956 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10350,6 +12776,13 @@ "operands": "@H'F696, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63126, @@ -10370,6 +12803,13 @@ "operands": "@H'F6B6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63158, @@ -10390,6 +12830,11 @@ "operands": "#H'00A9, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10405,6 +12850,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10418,6 +12872,13 @@ "operands": "@H'F696, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63126, @@ -10438,6 +12899,13 @@ "operands": "R4, @H'F6B6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63158, @@ -10458,6 +12926,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10471,6 +12947,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -10493,6 +12975,13 @@ "targets": [ 6028 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10506,6 +12995,13 @@ "operands": "#7, @H'F730", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63280, @@ -10528,6 +13024,13 @@ "targets": [ 6028 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10541,6 +13044,13 @@ "operands": "#13, @H'E16E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57710, @@ -10563,6 +13073,13 @@ "targets": [ 6014 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10576,6 +13093,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -10598,6 +13122,13 @@ "targets": [ 5998 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10611,6 +13142,13 @@ "operands": "@H'F732, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -10631,6 +13169,13 @@ "operands": "R1, @H'F734", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63284, @@ -10651,6 +13196,13 @@ "operands": "#H'1C06, @H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -10671,6 +13223,13 @@ "operands": "#H'14, @H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -10693,6 +13252,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10708,6 +13276,14 @@ "targets": [ 6028 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10721,6 +13297,13 @@ "operands": "@H'F694, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63124, @@ -10741,6 +13324,13 @@ "operands": "@H'F6B4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63156, @@ -10761,6 +13351,11 @@ "operands": "#H'00C5, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10776,6 +13371,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10789,6 +13393,13 @@ "operands": "@H'F694, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63124, @@ -10809,6 +13420,13 @@ "operands": "R4, @H'F6B4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63156, @@ -10829,6 +13447,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10842,6 +13468,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -10864,6 +13496,13 @@ "targets": [ 6080 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10877,6 +13516,13 @@ "operands": "#13, @H'E172", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57714, @@ -10899,6 +13545,13 @@ "targets": [ 6055 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10914,6 +13567,14 @@ "targets": [ 8487 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10929,6 +13590,15 @@ "targets": [ 6080 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10942,6 +13612,12 @@ "operands": "#15, @H'E220", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57888, @@ -10964,6 +13640,14 @@ "targets": [ 6066 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10979,6 +13663,15 @@ "targets": [ 8487 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -10994,6 +13687,14 @@ "targets": [ 6080 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11007,6 +13708,13 @@ "operands": "@H'F692, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63122, @@ -11027,6 +13735,13 @@ "operands": "@H'F6B2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63154, @@ -11047,6 +13762,11 @@ "operands": "#H'00BC, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11062,6 +13782,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11075,6 +13804,13 @@ "operands": "@H'F692, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63122, @@ -11095,6 +13831,13 @@ "operands": "R4, @H'F6B2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63154, @@ -11115,6 +13858,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11128,6 +13879,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -11150,6 +13907,13 @@ "targets": [ 6130 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11163,6 +13927,13 @@ "operands": "#12, @H'E126", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57638, @@ -11185,6 +13956,13 @@ "targets": [ 6130 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11198,6 +13976,13 @@ "operands": "@H'F6AE, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63150, @@ -11218,6 +14003,13 @@ "operands": "@H'F6CE, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63182, @@ -11238,6 +14030,11 @@ "operands": "#H'00A3, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11251,6 +14048,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -11273,6 +14076,14 @@ "targets": [ 6127 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11286,6 +14097,12 @@ "operands": "#3, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -11308,6 +14125,14 @@ "targets": [ 6127 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11321,6 +14146,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11336,6 +14167,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11349,6 +14189,13 @@ "operands": "@H'F6AE, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63150, @@ -11369,6 +14216,13 @@ "operands": "R4, @H'F6CE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63182, @@ -11389,6 +14243,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11402,6 +14264,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -11424,6 +14292,13 @@ "targets": [ 6180 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11437,6 +14312,13 @@ "operands": "#12, @H'E126", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57638, @@ -11459,6 +14341,13 @@ "targets": [ 6180 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11472,6 +14361,13 @@ "operands": "@H'F6AC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63148, @@ -11492,6 +14388,13 @@ "operands": "@H'F6CC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63180, @@ -11512,6 +14415,11 @@ "operands": "#H'00A4, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11525,6 +14433,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -11547,6 +14461,14 @@ "targets": [ 6177 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11560,6 +14482,12 @@ "operands": "#3, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -11582,6 +14510,14 @@ "targets": [ 6177 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11595,6 +14531,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11610,6 +14552,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11623,6 +14574,13 @@ "operands": "@H'F6AC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63148, @@ -11643,6 +14601,13 @@ "operands": "R4, @H'F6CC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63180, @@ -11663,6 +14628,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11676,6 +14649,12 @@ "operands": "#2, @H'F717", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63255, @@ -11698,6 +14677,14 @@ "targets": [ 6245 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11711,6 +14698,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -11733,6 +14726,13 @@ "targets": [ 6236 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11746,6 +14746,13 @@ "operands": "#5, @H'E126", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57638, @@ -11768,6 +14775,13 @@ "targets": [ 6236 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11781,6 +14795,13 @@ "operands": "@H'F6AA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63146, @@ -11801,6 +14822,13 @@ "operands": "@H'F6CA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63178, @@ -11821,6 +14849,11 @@ "operands": "#H'00A5, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11834,6 +14867,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -11856,6 +14895,14 @@ "targets": [ 6233 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11869,6 +14916,12 @@ "operands": "#2, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -11891,6 +14944,14 @@ "targets": [ 6233 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11904,6 +14965,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11919,6 +14986,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11932,6 +15008,13 @@ "operands": "@H'F6AA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63146, @@ -11952,6 +15035,13 @@ "operands": "R4, @H'F6CA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63178, @@ -11972,6 +15062,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -11985,6 +15083,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -12007,6 +15111,13 @@ "targets": [ 6280 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12020,6 +15131,13 @@ "operands": "@H'F6AA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63146, @@ -12040,6 +15158,13 @@ "operands": "@H'F6CA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63178, @@ -12060,6 +15185,11 @@ "operands": "#H'00D8, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12073,6 +15203,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -12095,6 +15231,14 @@ "targets": [ 6277 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12108,6 +15252,12 @@ "operands": "#1, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -12130,6 +15280,14 @@ "targets": [ 6277 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12143,6 +15301,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12158,6 +15322,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12171,6 +15344,13 @@ "operands": "@H'F6AA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63146, @@ -12191,6 +15371,13 @@ "operands": "R4, @H'F6CA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63178, @@ -12211,6 +15398,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12224,6 +15419,12 @@ "operands": "#2, @H'F717", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63255, @@ -12246,6 +15447,14 @@ "targets": [ 6331 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12259,6 +15468,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -12281,6 +15496,13 @@ "targets": [ 6322 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12294,6 +15516,13 @@ "operands": "#5, @H'E126", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57638, @@ -12316,6 +15545,13 @@ "targets": [ 6322 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12329,6 +15565,13 @@ "operands": "@H'F6A8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63144, @@ -12349,6 +15592,13 @@ "operands": "@H'F6C8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63176, @@ -12369,6 +15619,11 @@ "operands": "#H'0080, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12384,6 +15639,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12397,6 +15661,13 @@ "operands": "@H'F6A8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63144, @@ -12417,6 +15688,13 @@ "operands": "R4, @H'F6C8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63176, @@ -12437,6 +15715,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12450,6 +15736,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -12472,6 +15764,13 @@ "targets": [ 6366 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12485,6 +15784,13 @@ "operands": "@H'F6A8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63144, @@ -12505,6 +15811,13 @@ "operands": "@H'F6C8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63176, @@ -12525,6 +15838,11 @@ "operands": "#H'00D9, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12538,6 +15856,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -12560,6 +15884,14 @@ "targets": [ 6363 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12573,6 +15905,12 @@ "operands": "#1, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -12595,6 +15933,14 @@ "targets": [ 6363 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12608,6 +15954,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12623,6 +15975,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12636,6 +15997,13 @@ "operands": "@H'F6A8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63144, @@ -12656,6 +16024,13 @@ "operands": "R4, @H'F6C8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63176, @@ -12676,6 +16051,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12689,6 +16072,12 @@ "operands": "#2, @H'F717", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63255, @@ -12711,6 +16100,14 @@ "targets": [ 6431 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12724,6 +16121,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -12746,6 +16149,13 @@ "targets": [ 6422 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12759,6 +16169,13 @@ "operands": "#5, @H'E126", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57638, @@ -12781,6 +16198,13 @@ "targets": [ 6422 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12794,6 +16218,13 @@ "operands": "@H'F6A6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63142, @@ -12814,6 +16245,13 @@ "operands": "@H'F6C6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63174, @@ -12834,6 +16272,11 @@ "operands": "#H'00A6, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12847,6 +16290,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -12869,6 +16318,14 @@ "targets": [ 6419 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12882,6 +16339,12 @@ "operands": "#2, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -12904,6 +16367,14 @@ "targets": [ 6419 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12917,6 +16388,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12932,6 +16409,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12945,6 +16431,13 @@ "operands": "@H'F6A6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63142, @@ -12965,6 +16458,13 @@ "operands": "R4, @H'F6C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63174, @@ -12985,6 +16485,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -12998,6 +16506,12 @@ "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -13020,6 +16534,13 @@ "targets": [ 6465 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13033,6 +16554,13 @@ "operands": "@H'F6A6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63142, @@ -13053,6 +16581,13 @@ "operands": "@H'F6C6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63174, @@ -13073,6 +16608,11 @@ "operands": "#H'00DA, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13086,6 +16626,12 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -13108,6 +16654,14 @@ "targets": [ 6463 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13121,6 +16675,12 @@ "operands": "#1, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -13143,6 +16703,14 @@ "targets": [ 6463 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13156,6 +16724,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13171,6 +16745,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13184,6 +16767,12 @@ "operands": "@H'F6A6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63142, @@ -13204,6 +16793,12 @@ "operands": "R4, @H'F6C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63174, @@ -13224,6 +16819,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13237,6 +16841,13 @@ "operands": "#H'03, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -13259,6 +16870,14 @@ "targets": [ 6512 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13272,6 +16891,12 @@ "operands": "@H'F6A4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63140, @@ -13292,6 +16917,12 @@ "operands": "@H'F6C4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63172, @@ -13312,6 +16943,12 @@ "operands": "#4, @P7DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -13334,6 +16971,14 @@ "targets": [ 6495 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13347,6 +16992,11 @@ "operands": "#H'0080, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13360,6 +17010,13 @@ "operands": "#5, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -13382,6 +17039,13 @@ "targets": [ 6506 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13395,6 +17059,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13410,6 +17080,14 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13423,6 +17101,13 @@ "operands": "#7, @H'F76D", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63341, @@ -13443,6 +17128,13 @@ "operands": "@H'F6A4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63140, @@ -13463,6 +17155,13 @@ "operands": "R4, @H'F6C4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63172, @@ -13483,6 +17182,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13496,6 +17203,12 @@ "operands": "#H'03, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -13518,6 +17231,13 @@ "targets": [ 6553 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13531,6 +17251,13 @@ "operands": "@H'F6A2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63138, @@ -13551,6 +17278,13 @@ "operands": "@H'F6C2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63170, @@ -13571,6 +17305,13 @@ "operands": "@H'F68C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 26, + "base_cycles": 25, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63116, @@ -13591,6 +17332,11 @@ "operands": "#H'0081, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13604,6 +17350,12 @@ "operands": "#5, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -13626,6 +17378,14 @@ "targets": [ 6551 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13639,6 +17399,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13654,6 +17420,15 @@ "targets": [ 6619 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13667,6 +17442,12 @@ "operands": "@H'F6A2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63138, @@ -13687,6 +17468,12 @@ "operands": "R4, @H'F6C2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63170, @@ -13707,6 +17494,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13720,6 +17516,12 @@ "operands": "R3, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13733,6 +17535,12 @@ "operands": "#H'01FF, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13746,6 +17554,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13759,6 +17573,13 @@ "operands": "@(-H'1C00,R3), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13772,6 +17593,11 @@ "operands": "#H'FC00, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13787,6 +17613,14 @@ "targets": [ 6582 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13800,6 +17634,11 @@ "operands": "#H'FE00, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13813,6 +17652,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13826,6 +17671,12 @@ "operands": "#1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13839,6 +17690,11 @@ "operands": "#H'000F, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13854,6 +17710,14 @@ "targets": [ 6611 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13867,6 +17731,11 @@ "operands": "#H'FFF0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13882,6 +17751,13 @@ "targets": [ 6611 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13895,6 +17771,11 @@ "operands": "#H'8000, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13910,6 +17791,14 @@ "targets": [ 6606 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13923,6 +17812,11 @@ "operands": "#H'001A, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13938,6 +17832,14 @@ "targets": [ 6615 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13951,6 +17853,11 @@ "operands": "#H'FF1C, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13966,6 +17873,15 @@ "targets": [ 6615 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13979,6 +17895,12 @@ "operands": "@(H'1A25,R4), R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -13992,6 +17914,12 @@ "operands": "R4, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 25, + "base_cycles": 25, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14007,6 +17935,15 @@ "targets": [ 6627 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14020,6 +17957,12 @@ "operands": "R3, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14033,6 +17976,12 @@ "operands": "#H'01FF, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14046,6 +17995,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14059,6 +18014,12 @@ "operands": "@(-H'2000,R3), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14072,6 +18033,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14085,6 +18052,12 @@ "operands": "R1, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14100,6 +18073,14 @@ "targets": [ 6649 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14113,6 +18094,12 @@ "operands": "R0, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14126,6 +18113,11 @@ "operands": "#H'8000, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14141,6 +18133,13 @@ "targets": [ 6659 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14154,6 +18153,11 @@ "operands": "#H'0000, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14169,6 +18173,15 @@ "targets": [ 6659 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14182,6 +18195,12 @@ "operands": "R2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14195,6 +18214,11 @@ "operands": "#H'8000, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14210,6 +18234,13 @@ "targets": [ 6659 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14223,6 +18254,11 @@ "operands": "#H'FFFF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14236,6 +18272,12 @@ "operands": "@(-H'2000,R3), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14251,6 +18293,14 @@ "targets": [ 6676 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14264,6 +18314,12 @@ "operands": "R1, @(-H'1800,R3)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14277,6 +18333,11 @@ "operands": "#H'80, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14290,6 +18351,12 @@ "operands": "R5, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14305,6 +18372,15 @@ "targets": [ 15956 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14318,6 +18394,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14331,6 +18415,12 @@ "operands": "R3, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14344,6 +18434,12 @@ "operands": "#H'01FF, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14357,6 +18453,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14370,6 +18472,12 @@ "operands": "@(-H'2000,R3), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14385,6 +18493,14 @@ "targets": [ 6781 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14400,6 +18516,15 @@ "targets": [ 6797 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14413,6 +18538,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14428,6 +18559,14 @@ "targets": [ 6745 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14441,6 +18580,12 @@ "operands": "R0, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14454,6 +18599,12 @@ "operands": "@(-H'1C00,R3), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14467,6 +18618,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14482,6 +18639,14 @@ "targets": [ 6761 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14495,6 +18660,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14510,6 +18681,14 @@ "targets": [ 6731 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14525,6 +18704,15 @@ "targets": [ 6763 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14538,6 +18726,12 @@ "operands": "R0, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14551,6 +18745,12 @@ "operands": "@(-H'1C00,R3), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14564,6 +18764,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14579,6 +18785,14 @@ "targets": [ 6761 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14592,6 +18806,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14607,6 +18827,14 @@ "targets": [ 6747 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14622,6 +18850,15 @@ "targets": [ 6763 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14635,6 +18872,12 @@ "operands": "R2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14648,6 +18891,12 @@ "operands": "@(-H'2000,R3), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14663,6 +18912,14 @@ "targets": [ 6780 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14676,6 +18933,12 @@ "operands": "R0, @(-H'1800,R3)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14689,6 +18952,11 @@ "operands": "#H'80, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14702,6 +18970,12 @@ "operands": "R5, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14717,6 +18991,15 @@ "targets": [ 15956 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14730,6 +19013,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14743,6 +19034,12 @@ "operands": "#15, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14756,6 +19053,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14769,6 +19072,12 @@ "operands": "@(-H'1C00,R3), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14784,6 +19093,14 @@ "targets": [ 6795 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14797,6 +19114,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14812,6 +19135,15 @@ "targets": [ 6783 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14827,6 +19159,15 @@ "targets": [ 6725 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14840,6 +19181,11 @@ "operands": "#H'000F, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14853,6 +19199,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14868,6 +19220,13 @@ "targets": [ 6807 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14883,6 +19242,14 @@ "targets": [ 6800 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14896,6 +19263,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14909,6 +19282,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14922,6 +19301,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14935,6 +19323,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14950,6 +19344,13 @@ "targets": [ 6866 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14963,6 +19364,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -14976,6 +19383,13 @@ "operands": "@H'F733, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63283, @@ -14996,6 +19410,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15009,6 +19429,12 @@ "operands": "#H'0F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15022,6 +19448,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15037,6 +19469,14 @@ "targets": [ 6844 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15050,6 +19490,12 @@ "operands": "#-1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15063,6 +19509,12 @@ "operands": "#H'0F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15076,6 +19528,13 @@ "operands": "R0, @(-H'1C00,R3)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15091,6 +19550,13 @@ "targets": [ 6831 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15106,6 +19572,14 @@ "targets": [ 6855 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15119,6 +19593,12 @@ "operands": "#1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15132,6 +19612,12 @@ "operands": "#H'0F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15145,6 +19631,12 @@ "operands": "R0, @(-H'1C00,R3)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15160,6 +19652,14 @@ "targets": [ 6844 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15173,6 +19673,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15186,6 +19692,12 @@ "operands": "#H'0F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15199,6 +19711,13 @@ "operands": "R0, @H'F733", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63283, @@ -15221,6 +19740,14 @@ "targets": [ 6880 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15234,6 +19761,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15249,6 +19782,13 @@ "targets": [ 6876 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15262,6 +19802,13 @@ "operands": "#1, @H'F733", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63283, @@ -15284,6 +19831,14 @@ "targets": [ 6880 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15297,6 +19852,13 @@ "operands": "#-1, @H'F733", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63283, @@ -15319,6 +19881,14 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15332,6 +19902,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15345,6 +19924,13 @@ "operands": "@H'F75B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63323, @@ -15365,6 +19951,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15378,6 +19970,13 @@ "operands": "@(-H'08A3,R0), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15391,6 +19990,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15406,6 +20011,13 @@ "targets": [ 6908 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15419,6 +20031,12 @@ "operands": "#1, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15432,6 +20050,11 @@ "operands": "#H'2E, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15447,6 +20070,13 @@ "targets": [ 6915 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15460,6 +20090,11 @@ "operands": "#H'00, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15475,6 +20110,14 @@ "targets": [ 6915 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15488,6 +20131,12 @@ "operands": "#H'01, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15503,6 +20152,14 @@ "targets": [ 6915 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15516,6 +20173,11 @@ "operands": "#H'2E, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15529,6 +20191,12 @@ "operands": "R1, @(-H'08A3,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15544,6 +20212,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15557,6 +20234,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15570,6 +20255,12 @@ "operands": "@H'F75B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63323, @@ -15590,6 +20281,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15605,6 +20302,14 @@ "targets": [ 6941 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15618,6 +20323,12 @@ "operands": "#1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15631,6 +20342,11 @@ "operands": "#H'08, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15646,6 +20362,14 @@ "targets": [ 6949 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15659,6 +20383,11 @@ "operands": "#H'08, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15674,6 +20403,15 @@ "targets": [ 6949 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15687,6 +20425,12 @@ "operands": "#-1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15700,6 +20444,11 @@ "operands": "#H'01, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15715,6 +20464,14 @@ "targets": [ 6949 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15728,6 +20485,11 @@ "operands": "#H'01, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15741,6 +20503,12 @@ "operands": "R0, @H'F75B", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63323, @@ -15763,6 +20531,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15776,6 +20553,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15789,6 +20574,12 @@ "operands": "@H'F6D7, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63191, @@ -15809,6 +20600,12 @@ "operands": "@H'F6E7, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63207, @@ -15829,6 +20626,11 @@ "operands": "#H'007E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15844,6 +20646,14 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15857,6 +20667,12 @@ "operands": "@H'F6D7, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63191, @@ -15877,6 +20693,12 @@ "operands": "R4, @H'F6E7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63207, @@ -15897,6 +20719,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15910,6 +20741,13 @@ "operands": "@H'F6D6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63190, @@ -15930,6 +20768,13 @@ "operands": "@H'F6E6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63206, @@ -15950,6 +20795,11 @@ "operands": "#H'006E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15965,6 +20815,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -15978,6 +20837,13 @@ "operands": "@H'F6D6, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63190, @@ -15998,6 +20864,13 @@ "operands": "R4, @H'F6E6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63206, @@ -16018,6 +20891,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16031,6 +20912,12 @@ "operands": "@H'F6D5, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63189, @@ -16051,6 +20938,12 @@ "operands": "@H'F6E5, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63205, @@ -16071,6 +20964,11 @@ "operands": "#H'005E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16086,6 +20984,14 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16099,6 +21005,12 @@ "operands": "@H'F6D5, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63189, @@ -16119,6 +21031,12 @@ "operands": "R4, @H'F6E5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63205, @@ -16139,6 +21057,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16152,6 +21079,13 @@ "operands": "@H'F6D1, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63185, @@ -16172,6 +21106,13 @@ "operands": "@H'F6E1, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63201, @@ -16192,6 +21133,11 @@ "operands": "#H'001E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16207,6 +21153,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16220,6 +21175,13 @@ "operands": "@H'F6D1, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63185, @@ -16240,6 +21202,13 @@ "operands": "R4, @H'F6E1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63201, @@ -16260,6 +21229,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16273,6 +21250,12 @@ "operands": "@H'F6D0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63184, @@ -16293,6 +21276,12 @@ "operands": "@H'F6E0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63200, @@ -16313,6 +21302,11 @@ "operands": "#H'000E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16328,6 +21322,14 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16341,6 +21343,12 @@ "operands": "@H'F6D0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63184, @@ -16361,6 +21369,12 @@ "operands": "R4, @H'F6E0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63200, @@ -16381,6 +21395,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16394,6 +21417,13 @@ "operands": "@H'F6D4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63188, @@ -16414,6 +21444,13 @@ "operands": "@H'F6E4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63204, @@ -16434,6 +21471,11 @@ "operands": "#H'004E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16449,6 +21491,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16462,6 +21513,12 @@ "operands": "@H'F6D4, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63188, @@ -16482,6 +21539,12 @@ "operands": "R4, @H'F6E4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63204, @@ -16502,6 +21565,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16515,6 +21587,13 @@ "operands": "@H'F6D3, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63187, @@ -16535,6 +21614,13 @@ "operands": "@H'F6E3, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63203, @@ -16555,6 +21641,11 @@ "operands": "#H'003E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16570,6 +21661,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16583,6 +21683,12 @@ "operands": "@H'F6D3, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63187, @@ -16603,6 +21709,12 @@ "operands": "R4, @H'F6E3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63203, @@ -16623,6 +21735,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16636,6 +21757,13 @@ "operands": "@H'F6D2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63186, @@ -16656,6 +21784,13 @@ "operands": "@H'F6E2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63202, @@ -16676,6 +21811,11 @@ "operands": "#H'002E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16691,6 +21831,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16704,6 +21853,12 @@ "operands": "@H'F6D2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63186, @@ -16724,6 +21879,12 @@ "operands": "R4, @H'F6E2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63202, @@ -16744,6 +21905,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16757,6 +21927,13 @@ "operands": "@H'F6DC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63196, @@ -16777,6 +21954,13 @@ "operands": "@H'F6EC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63212, @@ -16797,6 +21981,11 @@ "operands": "#H'00CE, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16812,6 +22001,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16825,6 +22023,12 @@ "operands": "@H'F6DC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63196, @@ -16845,6 +22049,12 @@ "operands": "R4, @H'F6EC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63212, @@ -16865,6 +22075,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16878,6 +22097,13 @@ "operands": "@H'F6DB, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63195, @@ -16898,6 +22124,13 @@ "operands": "@H'F6EB, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63211, @@ -16918,6 +22151,11 @@ "operands": "#H'00BE, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16933,6 +22171,15 @@ "targets": [ 7182 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16946,6 +22193,12 @@ "operands": "@H'F6DB, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63195, @@ -16966,6 +22219,12 @@ "operands": "R4, @H'F6EB", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63211, @@ -16986,6 +22245,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -16999,6 +22267,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17014,6 +22288,13 @@ "targets": [ 7196 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17027,6 +22308,13 @@ "operands": "@(H'2706,R5), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17040,6 +22328,12 @@ "operands": "{R4,R5}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17053,6 +22347,14 @@ "operands": "@R0", "kind": "call", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17066,6 +22368,12 @@ "operands": "@SP+, {R4,R5}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17079,6 +22387,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17094,6 +22408,13 @@ "targets": [ 7204 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17107,6 +22428,12 @@ "operands": "#-2, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17122,6 +22449,14 @@ "targets": [ 7182 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17135,6 +22470,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17148,6 +22491,12 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -17170,6 +22519,14 @@ "targets": [ 8501 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17183,6 +22540,12 @@ "operands": "@H'F732, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -17203,6 +22566,12 @@ "operands": "R1, @H'F734", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63284, @@ -17223,6 +22592,12 @@ "operands": "#H'1C03, @H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -17243,6 +22618,13 @@ "operands": "#H'14, @H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -17265,6 +22647,14 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17278,6 +22668,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17291,6 +22690,13 @@ "operands": "#5, @H'F6F6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63222, @@ -17313,6 +22719,13 @@ "targets": [ 9919 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17326,6 +22739,12 @@ "operands": "@H'E124, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57636, @@ -17346,6 +22765,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17359,6 +22784,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17372,6 +22803,12 @@ "operands": "#6, @H'F6F6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63222, @@ -17394,6 +22831,14 @@ "targets": [ 9837 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17407,6 +22852,12 @@ "operands": "#1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17422,6 +22873,14 @@ "targets": [ 9859 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17435,6 +22894,11 @@ "operands": "#H'FF, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17450,6 +22914,15 @@ "targets": [ 9859 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17463,6 +22936,12 @@ "operands": "#-1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17476,6 +22955,12 @@ "operands": "#13, @H'E004", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57348, @@ -17498,6 +22983,14 @@ "targets": [ 9853 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17511,6 +23004,11 @@ "operands": "#H'49, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17526,6 +23024,14 @@ "targets": [ 9859 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17539,6 +23045,11 @@ "operands": "#H'49, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17554,6 +23065,15 @@ "targets": [ 9859 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17567,6 +23087,11 @@ "operands": "#H'16, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17582,6 +23107,14 @@ "targets": [ 9859 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17595,6 +23128,11 @@ "operands": "#H'16, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17608,6 +23146,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17621,6 +23165,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17634,6 +23184,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17647,6 +23203,12 @@ "operands": "#15, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17660,6 +23222,12 @@ "operands": "@H'E124, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57636, @@ -17682,6 +23250,14 @@ "targets": [ 9919 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17695,6 +23271,12 @@ "operands": "R0, @H'E924", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 59684, @@ -17715,6 +23297,11 @@ "operands": "#H'80, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17728,6 +23315,11 @@ "operands": "#H'0092, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17741,6 +23333,13 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -17763,6 +23362,13 @@ "targets": [ 9896 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17776,6 +23382,13 @@ "operands": "#4, @H'F404", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62468, @@ -17798,6 +23411,13 @@ "targets": [ 9896 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17811,6 +23431,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17826,6 +23452,14 @@ "targets": [ 15956 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17839,6 +23473,12 @@ "operands": "#0, @H'F6F6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63222, @@ -17861,6 +23501,14 @@ "targets": [ 9913 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17874,6 +23522,12 @@ "operands": "#H'07D0, @H'F6F4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63220, @@ -17896,6 +23550,15 @@ "targets": [ 9919 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17909,6 +23572,12 @@ "operands": "#H'00C8, @H'F6F4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63220, @@ -17929,6 +23598,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17942,6 +23620,13 @@ "operands": "@H'F9B9, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63929, @@ -17962,6 +23647,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -17975,6 +23666,13 @@ "operands": "@H'F9B4, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -17997,6 +23695,13 @@ "targets": [ 10261 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18012,6 +23717,14 @@ "targets": [ 11430 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18025,6 +23738,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18038,6 +23757,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18051,6 +23776,12 @@ "operands": "@(-H'0690,R0), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18064,6 +23795,12 @@ "operands": "#1, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18077,6 +23814,12 @@ "operands": "#H'1F, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18090,6 +23833,13 @@ "operands": "R1, @H'F9B9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63929, @@ -18110,6 +23860,12 @@ "operands": "#H'01FF, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18123,6 +23879,12 @@ "operands": "R0, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18138,6 +23900,14 @@ "targets": [ 25094 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18151,6 +23921,12 @@ "operands": "R0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18164,6 +23940,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18177,6 +23959,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18192,6 +23980,14 @@ "targets": [ 10399 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18205,6 +24001,12 @@ "operands": "@H'F736, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63286, @@ -18225,6 +24027,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18238,6 +24046,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18253,6 +24067,14 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18266,6 +24088,13 @@ "operands": "@H'F738, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63288, @@ -18286,6 +24115,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18299,6 +24134,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18314,6 +24155,13 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18327,6 +24175,12 @@ "operands": "@H'F73A, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63290, @@ -18347,6 +24201,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18360,6 +24220,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18375,6 +24241,14 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18388,6 +24262,13 @@ "operands": "@H'F73C, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63292, @@ -18408,6 +24289,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18421,6 +24308,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18436,6 +24329,13 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18449,6 +24349,12 @@ "operands": "@H'F73E, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63294, @@ -18469,6 +24375,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18482,6 +24394,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18497,6 +24415,14 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18510,6 +24436,13 @@ "operands": "@H'F740, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63296, @@ -18530,6 +24463,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18543,6 +24482,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18558,6 +24503,13 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18571,6 +24523,12 @@ "operands": "@H'F742, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63298, @@ -18591,6 +24549,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18604,6 +24568,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18619,6 +24589,14 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18632,6 +24610,13 @@ "operands": "@H'F754, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63316, @@ -18652,6 +24637,12 @@ "operands": "#H'01FF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18665,6 +24656,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18680,6 +24677,13 @@ "targets": [ 11435 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18693,6 +24697,12 @@ "operands": "@(H'28A6,R4), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18706,6 +24716,13 @@ "operands": "@R1", "kind": "jump", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18719,6 +24736,13 @@ "operands": "#7, @H'F769", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63337, @@ -18739,6 +24763,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18752,6 +24784,12 @@ "operands": "{R0,R4,R5}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 15, + "note": "6+3n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18767,6 +24805,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18780,6 +24827,12 @@ "operands": "@SP+, {R0,R4,R5}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 18, + "note": "6+4n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18793,6 +24846,13 @@ "operands": "#7, @H'F769", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63337, @@ -18815,6 +24875,14 @@ "targets": [ 10399 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18828,6 +24896,11 @@ "operands": "#H'0007, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18841,6 +24914,12 @@ "operands": "R0, @P7DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -18863,6 +24942,14 @@ "targets": [ 14659 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18876,6 +24963,12 @@ "operands": "@(-H'0980,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18889,6 +24982,12 @@ "operands": "#0, @(-H'0980,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18904,6 +25003,15 @@ "targets": [ 14663 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18917,6 +25025,12 @@ "operands": "@(-H'0980,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18930,6 +25044,12 @@ "operands": "#H'FF, @(-H'0980,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18945,6 +25065,13 @@ "targets": [ 14676 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18958,6 +25085,13 @@ "operands": "R0, @H'F688", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63112, @@ -18980,6 +25114,14 @@ "targets": [ 14687 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -18993,6 +25135,13 @@ "operands": "#H'00, @(-H'0980,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19008,6 +25157,14 @@ "targets": [ 14687 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19021,6 +25178,12 @@ "operands": "R0, @H'F688", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63112, @@ -19043,6 +25206,14 @@ "targets": [ 14643 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19056,6 +25227,13 @@ "operands": "#1, @H'F722", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63266, @@ -19076,6 +25254,13 @@ "operands": "#H'3C, @H'F722", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63266, @@ -19098,6 +25283,14 @@ "targets": [ 14716 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19111,6 +25304,12 @@ "operands": "#H'78, @H'F722", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63266, @@ -19133,6 +25332,13 @@ "targets": [ 14719 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19146,6 +25352,13 @@ "operands": "#H'B4, @H'F722", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63266, @@ -19168,6 +25381,14 @@ "targets": [ 14723 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19181,6 +25402,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19196,6 +25426,14 @@ "targets": [ 14741 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19209,6 +25447,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19224,6 +25470,15 @@ "targets": [ 14894 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19237,6 +25492,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19252,6 +25515,15 @@ "targets": [ 14730 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19265,6 +25537,12 @@ "operands": "@H'F722", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63266, @@ -19285,6 +25563,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19298,6 +25585,13 @@ "operands": "#7, @ADCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65256, @@ -19320,6 +25614,13 @@ "targets": [ 14740 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19333,6 +25634,13 @@ "operands": "#5, @ADCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65256, @@ -19353,6 +25661,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19366,6 +25682,12 @@ "operands": "@H'F720", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63264, @@ -19388,6 +25710,14 @@ "targets": [ 14893 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19401,6 +25731,13 @@ "operands": "#H'A0, @H'F101", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61697, @@ -19421,6 +25758,12 @@ "operands": "#1, @H'F100", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61696, @@ -19443,6 +25786,14 @@ "targets": [ 14893 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -19456,6 +25807,13 @@ "operands": "@H'F71B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63259, @@ -19476,6 +25834,13 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -19496,6 +25861,13 @@ "operands": "@H'F713, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63251, @@ -19516,6 +25888,13 @@ "operands": "R0, @H'F102", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61698, @@ -19536,6 +25915,13 @@ "operands": "@H'F71A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63258, @@ -19556,6 +25942,13 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -19576,6 +25969,13 @@ "operands": "@H'F712, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63250, @@ -19596,6 +25996,13 @@ "operands": "R0, @H'F103", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61699, @@ -19616,6 +26023,13 @@ "operands": "@H'F719, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63257, @@ -19636,6 +26050,13 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -19656,6 +26077,13 @@ "operands": "@H'F711, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63249, @@ -19676,6 +26104,13 @@ "operands": "R0, @H'F104", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61700, @@ -19696,6 +26131,13 @@ "operands": "@H'F718, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63256, @@ -19716,6 +26158,13 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -19736,6 +26185,13 @@ "operands": "@H'F710, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63248, @@ -19756,6 +26212,13 @@ "operands": "R0, @H'F105", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61701, @@ -19776,6 +26239,13 @@ "operands": "@H'F702, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63234, @@ -19796,6 +26266,13 @@ "operands": "R0, @H'F109", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61705, @@ -19816,6 +26293,13 @@ "operands": "@H'F703, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63235, @@ -19836,6 +26320,13 @@ "operands": "R0, @H'F10A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61706, @@ -19856,6 +26347,13 @@ "operands": "@H'F704, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63236, @@ -19876,6 +26374,13 @@ "operands": "R0, @H'F10B", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61707, @@ -19896,6 +26401,13 @@ "operands": "@H'F705, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63237, @@ -19916,6 +26428,13 @@ "operands": "R0, @H'F10C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61708, @@ -19936,6 +26455,13 @@ "operands": "@H'F700, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63232, @@ -19956,6 +26482,13 @@ "operands": "R0, @H'F10D", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61709, @@ -19976,6 +26509,13 @@ "operands": "@H'F701, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63233, @@ -19996,6 +26536,13 @@ "operands": "R0, @H'F10E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61710, @@ -20016,6 +26563,13 @@ "operands": "@P7DR, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -20036,6 +26590,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20049,6 +26609,12 @@ "operands": "#H'03, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20062,6 +26628,12 @@ "operands": "#H'A0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20075,6 +26647,13 @@ "operands": "R0, @H'F10F", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61711, @@ -20095,6 +26674,13 @@ "operands": "#H'03, @H'F720", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63264, @@ -20115,6 +26701,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20128,6 +26723,13 @@ "operands": "@H'F721", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63265, @@ -20150,6 +26752,13 @@ "targets": [ 15046 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20163,6 +26772,13 @@ "operands": "#H'A0, @H'F001", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61441, @@ -20183,6 +26799,13 @@ "operands": "#1, @H'F000", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61440, @@ -20205,6 +26828,13 @@ "targets": [ 15046 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20218,6 +26848,12 @@ "operands": "@H'F71F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63263, @@ -20238,6 +26874,12 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -20258,6 +26900,12 @@ "operands": "@H'F717, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63255, @@ -20278,6 +26926,12 @@ "operands": "R0, @H'F002", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61442, @@ -20298,6 +26952,12 @@ "operands": "@H'F71E, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63262, @@ -20318,6 +26978,12 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -20338,6 +27004,12 @@ "operands": "@H'F716, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63254, @@ -20358,6 +27030,12 @@ "operands": "R0, @H'F003", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61443, @@ -20378,6 +27056,12 @@ "operands": "@H'F71D, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63261, @@ -20398,6 +27082,12 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -20418,6 +27108,12 @@ "operands": "@H'F715, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63253, @@ -20438,6 +27134,12 @@ "operands": "R0, @H'F004", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61444, @@ -20458,6 +27160,12 @@ "operands": "@H'F71C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63260, @@ -20478,6 +27186,12 @@ "operands": "@H'F723, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -20498,6 +27212,12 @@ "operands": "@H'F714, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63252, @@ -20518,6 +27238,12 @@ "operands": "R0, @H'F005", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61445, @@ -20538,6 +27264,12 @@ "operands": "@H'F708, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63240, @@ -20558,6 +27290,12 @@ "operands": "R0, @H'F009", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61449, @@ -20578,6 +27316,12 @@ "operands": "@H'F709, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63241, @@ -20598,6 +27342,12 @@ "operands": "R0, @H'F00A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61450, @@ -20618,6 +27368,12 @@ "operands": "@H'F70A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63242, @@ -20638,6 +27394,12 @@ "operands": "R0, @H'F00B", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61451, @@ -20658,6 +27420,12 @@ "operands": "@H'F70B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63243, @@ -20678,6 +27446,12 @@ "operands": "R0, @H'F00C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61452, @@ -20698,6 +27472,12 @@ "operands": "@H'F706, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63238, @@ -20718,6 +27498,12 @@ "operands": "R0, @H'F00D", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61453, @@ -20738,6 +27524,12 @@ "operands": "@H'F707, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63239, @@ -20758,6 +27550,12 @@ "operands": "R0, @H'F00E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61454, @@ -20778,6 +27576,12 @@ "operands": "@P7DR, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -20798,6 +27602,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20811,6 +27621,12 @@ "operands": "#H'03, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20824,6 +27640,12 @@ "operands": "#H'A0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20837,6 +27659,12 @@ "operands": "R0, @H'F00F", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61455, @@ -20857,6 +27685,13 @@ "operands": "#H'03, @H'F721", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63265, @@ -20877,6 +27712,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20890,6 +27733,12 @@ "operands": "R0, @-R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20903,6 +27752,12 @@ "operands": "#1, @H'F100", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61696, @@ -20925,6 +27780,14 @@ "targets": [ 15405 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20938,6 +27801,13 @@ "operands": "@H'F10F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61711, @@ -20958,6 +27828,11 @@ "operands": "#H'A9, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20973,6 +27848,13 @@ "targets": [ 15072 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -20986,6 +27868,11 @@ "operands": "#H'A8, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21001,6 +27888,13 @@ "targets": [ 15202 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21016,6 +27910,15 @@ "targets": [ 15405 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21029,6 +27932,13 @@ "operands": "@H'F6F0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21049,6 +27959,12 @@ "operands": "#H'C0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21062,6 +27978,12 @@ "operands": "R0, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21082,6 +28004,12 @@ "operands": "@H'F10C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61708, @@ -21102,6 +28030,12 @@ "operands": "@H'F69A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63130, @@ -21124,6 +28058,14 @@ "targets": [ 15101 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21137,6 +28079,12 @@ "operands": "#5, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21157,6 +28105,12 @@ "operands": "R0, @H'F69A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63130, @@ -21177,6 +28131,12 @@ "operands": "@H'F10A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61706, @@ -21197,6 +28157,12 @@ "operands": "@H'F698, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63128, @@ -21219,6 +28185,14 @@ "targets": [ 15119 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21232,6 +28206,12 @@ "operands": "#4, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21252,6 +28232,12 @@ "operands": "R0, @H'F698", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63128, @@ -21272,6 +28258,12 @@ "operands": "@H'F108, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61704, @@ -21292,6 +28284,12 @@ "operands": "@H'F696, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63126, @@ -21314,6 +28312,14 @@ "targets": [ 15137 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21327,6 +28333,12 @@ "operands": "#3, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21347,6 +28359,12 @@ "operands": "R0, @H'F696", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63126, @@ -21367,6 +28385,12 @@ "operands": "@H'F106, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61702, @@ -21387,6 +28411,12 @@ "operands": "@H'F694, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63124, @@ -21409,6 +28439,14 @@ "targets": [ 15155 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21422,6 +28460,12 @@ "operands": "#2, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21442,6 +28486,12 @@ "operands": "R0, @H'F694", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63124, @@ -21462,6 +28512,12 @@ "operands": "@H'F104, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61700, @@ -21482,6 +28538,12 @@ "operands": "@H'F692, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63122, @@ -21504,6 +28566,14 @@ "targets": [ 15173 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21517,6 +28587,12 @@ "operands": "#1, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21537,6 +28613,12 @@ "operands": "R0, @H'F692", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63122, @@ -21557,6 +28639,12 @@ "operands": "@H'F102, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61698, @@ -21577,6 +28665,12 @@ "operands": "@H'F690, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63120, @@ -21599,6 +28693,14 @@ "targets": [ 15191 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21612,6 +28714,12 @@ "operands": "#0, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21632,6 +28740,12 @@ "operands": "R0, @H'F690", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63120, @@ -21652,6 +28766,12 @@ "operands": "@H'F101, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61697, @@ -21672,6 +28792,12 @@ "operands": "#0, @H'F720", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63264, @@ -21694,6 +28820,15 @@ "targets": [ 15405 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21707,6 +28842,13 @@ "operands": "@H'F6F0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21727,6 +28869,12 @@ "operands": "#H'3F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21740,6 +28888,12 @@ "operands": "R0, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21760,6 +28914,12 @@ "operands": "@H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -21780,6 +28940,12 @@ "operands": "@H'F10C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61708, @@ -21800,6 +28966,12 @@ "operands": "@H'F69E, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63134, @@ -21822,6 +28994,14 @@ "targets": [ 15235 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21835,6 +29015,12 @@ "operands": "#7, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21855,6 +29041,12 @@ "operands": "R0, @H'F69E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63134, @@ -21875,6 +29067,12 @@ "operands": "@H'F10A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61706, @@ -21895,6 +29093,12 @@ "operands": "@H'F69C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63132, @@ -21917,6 +29121,14 @@ "targets": [ 15253 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -21930,6 +29142,12 @@ "operands": "#6, @H'F6F0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63216, @@ -21950,6 +29168,12 @@ "operands": "R0, @H'F69C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63132, @@ -21970,6 +29194,12 @@ "operands": "@H'F109, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61705, @@ -21990,6 +29220,12 @@ "operands": "@H'F6D0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63184, @@ -22012,6 +29248,14 @@ "targets": [ 15271 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22025,6 +29269,12 @@ "operands": "#0, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22045,6 +29295,12 @@ "operands": "R0, @H'F6D0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63184, @@ -22065,6 +29321,12 @@ "operands": "@H'F108, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61704, @@ -22085,6 +29347,12 @@ "operands": "@H'F6D1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63185, @@ -22107,6 +29375,14 @@ "targets": [ 15289 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22120,6 +29396,12 @@ "operands": "#1, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22140,6 +29422,12 @@ "operands": "R0, @H'F6D1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63185, @@ -22160,6 +29448,12 @@ "operands": "@H'F107, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61703, @@ -22180,6 +29474,12 @@ "operands": "@H'F6D2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63186, @@ -22202,6 +29502,14 @@ "targets": [ 15307 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22215,6 +29523,12 @@ "operands": "#2, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22235,6 +29549,12 @@ "operands": "R0, @H'F6D2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63186, @@ -22255,6 +29575,12 @@ "operands": "@H'F106, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61702, @@ -22275,6 +29601,12 @@ "operands": "@H'F6D3, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63187, @@ -22297,6 +29629,14 @@ "targets": [ 15325 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22310,6 +29650,12 @@ "operands": "#3, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22330,6 +29676,12 @@ "operands": "R0, @H'F6D3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63187, @@ -22350,6 +29702,12 @@ "operands": "@H'F105, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61701, @@ -22370,6 +29728,12 @@ "operands": "@H'F6D4, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63188, @@ -22392,6 +29756,14 @@ "targets": [ 15343 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22405,6 +29777,12 @@ "operands": "#4, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22425,6 +29803,12 @@ "operands": "R0, @H'F6D4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63188, @@ -22445,6 +29829,12 @@ "operands": "@H'F104, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61700, @@ -22465,6 +29855,12 @@ "operands": "@H'F6D5, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63189, @@ -22487,6 +29883,14 @@ "targets": [ 15361 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22500,6 +29904,12 @@ "operands": "#5, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22520,6 +29930,12 @@ "operands": "R0, @H'F6D5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63189, @@ -22540,6 +29956,12 @@ "operands": "@H'F103, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61699, @@ -22560,6 +29982,12 @@ "operands": "@H'F6D6, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63190, @@ -22582,6 +30010,14 @@ "targets": [ 15379 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22595,6 +30031,12 @@ "operands": "#6, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22615,6 +30057,12 @@ "operands": "R0, @H'F6D6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63190, @@ -22635,6 +30083,12 @@ "operands": "@H'F102, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61698, @@ -22655,6 +30109,12 @@ "operands": "@H'F6D7, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63191, @@ -22677,6 +30137,14 @@ "targets": [ 15397 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22690,6 +30158,12 @@ "operands": "#7, @H'F6F2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63218, @@ -22710,6 +30184,12 @@ "operands": "R0, @H'F6D7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63191, @@ -22730,6 +30210,12 @@ "operands": "@H'F101, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61697, @@ -22750,6 +30236,12 @@ "operands": "#1, @H'F720", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63264, @@ -22770,6 +30262,13 @@ "operands": "@R7+, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22783,6 +30282,13 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22796,6 +30302,13 @@ "operands": "R0, @-R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22809,6 +30322,13 @@ "operands": "#1, @H'F000", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61440, @@ -22831,6 +30351,13 @@ "targets": [ 15766 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22844,6 +30371,12 @@ "operands": "@H'F00F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61455, @@ -22864,6 +30397,11 @@ "operands": "#H'A9, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22879,6 +30417,14 @@ "targets": [ 15433 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22892,6 +30438,11 @@ "operands": "#H'A8, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22907,6 +30458,14 @@ "targets": [ 15563 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22922,6 +30481,14 @@ "targets": [ 15766 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22935,6 +30502,12 @@ "operands": "@H'F6F1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -22955,6 +30528,12 @@ "operands": "#H'C0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -22968,6 +30547,13 @@ "operands": "R0, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -22988,6 +30574,13 @@ "operands": "@H'F00C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61452, @@ -23008,6 +30601,13 @@ "operands": "@H'F6AA, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63146, @@ -23030,6 +30630,13 @@ "targets": [ 15462 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23043,6 +30650,13 @@ "operands": "#5, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23063,6 +30677,13 @@ "operands": "R0, @H'F6AA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63146, @@ -23083,6 +30704,13 @@ "operands": "@H'F00A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61450, @@ -23103,6 +30731,13 @@ "operands": "@H'F6A8, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63144, @@ -23125,6 +30760,13 @@ "targets": [ 15480 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23138,6 +30780,13 @@ "operands": "#4, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23158,6 +30807,13 @@ "operands": "R0, @H'F6A8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63144, @@ -23178,6 +30834,13 @@ "operands": "@H'F008, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61448, @@ -23198,6 +30861,13 @@ "operands": "@H'F6A6, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63142, @@ -23220,6 +30890,13 @@ "targets": [ 15498 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23233,6 +30910,13 @@ "operands": "#3, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23253,6 +30937,13 @@ "operands": "R0, @H'F6A6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63142, @@ -23273,6 +30964,13 @@ "operands": "@H'F006, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61446, @@ -23293,6 +30991,13 @@ "operands": "@H'F6A4, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63140, @@ -23315,6 +31020,13 @@ "targets": [ 15516 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23328,6 +31040,13 @@ "operands": "#2, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23348,6 +31067,13 @@ "operands": "R0, @H'F6A4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63140, @@ -23368,6 +31094,13 @@ "operands": "@H'F004, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61444, @@ -23388,6 +31121,13 @@ "operands": "@H'F6A2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63138, @@ -23410,6 +31150,13 @@ "targets": [ 15534 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23423,6 +31170,13 @@ "operands": "#1, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23443,6 +31197,13 @@ "operands": "R0, @H'F6A2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63138, @@ -23463,6 +31224,13 @@ "operands": "@H'F002, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61442, @@ -23483,6 +31251,13 @@ "operands": "@H'F6A0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63136, @@ -23505,6 +31280,13 @@ "targets": [ 15552 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23518,6 +31300,13 @@ "operands": "#0, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23538,6 +31327,13 @@ "operands": "R0, @H'F6A0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63136, @@ -23558,6 +31354,13 @@ "operands": "@H'F001, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61441, @@ -23578,6 +31381,13 @@ "operands": "#0, @H'F721", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63265, @@ -23600,6 +31410,14 @@ "targets": [ 15766 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23613,6 +31431,12 @@ "operands": "@H'F6F1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23633,6 +31457,12 @@ "operands": "#H'3F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23646,6 +31476,13 @@ "operands": "R0, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23666,6 +31503,13 @@ "operands": "@H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -23686,6 +31530,13 @@ "operands": "@H'F00C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61452, @@ -23706,6 +31557,13 @@ "operands": "@H'F6AE, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63150, @@ -23728,6 +31586,13 @@ "targets": [ 15596 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23741,6 +31606,13 @@ "operands": "#7, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23761,6 +31633,13 @@ "operands": "R0, @H'F6AE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63150, @@ -23781,6 +31660,13 @@ "operands": "@H'F00A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61450, @@ -23801,6 +31687,13 @@ "operands": "@H'F6AC, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63148, @@ -23823,6 +31716,13 @@ "targets": [ 15614 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23836,6 +31736,13 @@ "operands": "#6, @H'F6F1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63217, @@ -23856,6 +31763,13 @@ "operands": "R0, @H'F6AC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63148, @@ -23876,6 +31790,13 @@ "operands": "@H'F009, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61449, @@ -23896,6 +31817,13 @@ "operands": "@H'F6D8, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63192, @@ -23918,6 +31846,13 @@ "targets": [ 15632 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -23931,6 +31866,13 @@ "operands": "#0, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -23951,6 +31893,13 @@ "operands": "R0, @H'F6D8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63192, @@ -23971,6 +31920,13 @@ "operands": "@H'F008, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61448, @@ -23991,6 +31947,13 @@ "operands": "@H'F6D9, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63193, @@ -24013,6 +31976,13 @@ "targets": [ 15650 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24026,6 +31996,13 @@ "operands": "#1, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24046,6 +32023,13 @@ "operands": "R0, @H'F6D9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63193, @@ -24066,6 +32050,13 @@ "operands": "@H'F007, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61447, @@ -24086,6 +32077,13 @@ "operands": "@H'F6DA, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63194, @@ -24108,6 +32106,13 @@ "targets": [ 15668 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24121,6 +32126,13 @@ "operands": "#2, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24141,6 +32153,13 @@ "operands": "R0, @H'F6DA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63194, @@ -24161,6 +32180,13 @@ "operands": "@H'F006, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61446, @@ -24181,6 +32207,13 @@ "operands": "@H'F6DB, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63195, @@ -24203,6 +32236,13 @@ "targets": [ 15686 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24216,6 +32256,13 @@ "operands": "#3, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24236,6 +32283,13 @@ "operands": "R0, @H'F6DB", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63195, @@ -24256,6 +32310,13 @@ "operands": "@H'F005, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61445, @@ -24276,6 +32337,13 @@ "operands": "@H'F6DC, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63196, @@ -24298,6 +32366,13 @@ "targets": [ 15704 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24311,6 +32386,13 @@ "operands": "#4, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24331,6 +32413,13 @@ "operands": "R0, @H'F6DC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63196, @@ -24351,6 +32440,13 @@ "operands": "@H'F004, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61444, @@ -24371,6 +32467,13 @@ "operands": "@H'F6DD, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63197, @@ -24393,6 +32496,13 @@ "targets": [ 15722 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24406,6 +32516,13 @@ "operands": "#5, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24426,6 +32543,13 @@ "operands": "R0, @H'F6DD", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63197, @@ -24446,6 +32570,13 @@ "operands": "@H'F003, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61443, @@ -24466,6 +32597,13 @@ "operands": "@H'F6DE, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63198, @@ -24488,6 +32626,13 @@ "targets": [ 15740 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24501,6 +32646,13 @@ "operands": "#6, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24521,6 +32673,13 @@ "operands": "R0, @H'F6DE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63198, @@ -24541,6 +32700,13 @@ "operands": "@H'F002, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61442, @@ -24561,6 +32727,13 @@ "operands": "@H'F6DF, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63199, @@ -24583,6 +32756,13 @@ "targets": [ 15758 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24596,6 +32776,13 @@ "operands": "#7, @H'F6F3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63219, @@ -24616,6 +32803,13 @@ "operands": "R0, @H'F6DF", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63199, @@ -24636,6 +32830,13 @@ "operands": "@H'F001, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61441, @@ -24656,6 +32857,13 @@ "operands": "#1, @H'F721", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63265, @@ -24676,6 +32884,12 @@ "operands": "@R7+, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24689,6 +32903,12 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24702,6 +32922,12 @@ "operands": "#5, @ADCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65256, @@ -24722,6 +32948,12 @@ "operands": "{R0,R1,R2,R3,R4,R5}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 24, + "note": "6+3n, n=6", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24735,6 +32967,12 @@ "operands": "@H'F68A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63114, @@ -24755,6 +32993,12 @@ "operands": "#H'14, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24768,6 +33012,13 @@ "operands": "@ADDRA_H, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65248, @@ -24788,6 +33039,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24801,6 +33058,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24814,6 +33077,13 @@ "operands": "@(-H'304A,R1), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24827,6 +33097,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24840,6 +33116,12 @@ "operands": "#H'15, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 23, + "base_cycles": 23, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24853,6 +33135,12 @@ "operands": "@H'F68A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63114, @@ -24875,6 +33163,14 @@ "targets": [ 15880 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24888,6 +33184,12 @@ "operands": "@H'F68A, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63114, @@ -24908,6 +33210,12 @@ "operands": "R0, @H'F68A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63114, @@ -24928,6 +33236,12 @@ "operands": "#H'03, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -24950,6 +33264,13 @@ "targets": [ 15880 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24963,6 +33284,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24976,6 +33303,12 @@ "operands": "R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -24989,6 +33322,12 @@ "operands": "#H'0101, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 25, + "base_cycles": 25, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25002,6 +33341,12 @@ "operands": "#H'0101, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 25, + "base_cycles": 25, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25015,6 +33360,12 @@ "operands": "R3, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25028,6 +33379,13 @@ "operands": "@H'E102, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57602, @@ -25048,6 +33406,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25061,6 +33425,12 @@ "operands": "R1, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25076,6 +33446,13 @@ "targets": [ 15856 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25089,6 +33466,12 @@ "operands": "R0, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25102,6 +33485,11 @@ "operands": "#H'8000, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25117,6 +33505,14 @@ "targets": [ 15866 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25130,6 +33526,11 @@ "operands": "#H'0000, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25145,6 +33546,14 @@ "targets": [ 15866 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25158,6 +33567,12 @@ "operands": "R2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25171,6 +33586,11 @@ "operands": "#H'8000, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25186,6 +33606,14 @@ "targets": [ 15866 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25199,6 +33627,11 @@ "operands": "#H'FFFF, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25212,6 +33645,13 @@ "operands": "@H'E102, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57602, @@ -25234,6 +33674,13 @@ "targets": [ 15880 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25247,6 +33694,13 @@ "operands": "R1, @H'F68E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63118, @@ -25267,6 +33721,13 @@ "operands": "#7, @H'F689", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63113, @@ -25287,6 +33748,13 @@ "operands": "@H'F68B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63115, @@ -25307,6 +33775,12 @@ "operands": "#H'14, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25320,6 +33794,12 @@ "operands": "@ADDRB_H, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65250, @@ -25340,6 +33820,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25353,6 +33839,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25366,6 +33858,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25379,6 +33877,12 @@ "operands": "#H'15, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 23, + "base_cycles": 23, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25392,6 +33896,13 @@ "operands": "@H'F68C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63116, @@ -25414,6 +33925,13 @@ "targets": [ 15912 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25427,6 +33945,13 @@ "operands": "@H'F68B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63115, @@ -25449,6 +33974,13 @@ "targets": [ 15949 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25462,6 +33994,13 @@ "operands": "R0, @H'F68B", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63115, @@ -25482,6 +34021,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25495,6 +34040,12 @@ "operands": "R0, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25508,6 +34059,12 @@ "operands": "R3, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 18, + "base_cycles": 18, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25521,6 +34078,12 @@ "operands": "R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25534,6 +34097,12 @@ "operands": "#H'00C8, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 29, + "base_cycles": 29, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25547,6 +34116,12 @@ "operands": "#H'04, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25560,6 +34135,12 @@ "operands": "#H'00AB, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25573,6 +34154,12 @@ "operands": "R3, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25586,6 +34173,12 @@ "operands": "#4, @P7DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -25608,6 +34201,14 @@ "targets": [ 15945 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25621,6 +34222,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25634,6 +34241,12 @@ "operands": "R0, @H'F68C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63116, @@ -25654,6 +34267,12 @@ "operands": "@SP+, {R0,R1,R2,R3,R4,R5}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 30, + "note": "6+4n, n=6", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25667,6 +34286,12 @@ "operands": "#7, @ADCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65256, @@ -25687,6 +34312,13 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25700,6 +34332,12 @@ "operands": "#7, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25715,6 +34353,13 @@ "targets": [ 16026 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25728,6 +34373,13 @@ "operands": "@H'F9B5, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -25748,6 +34400,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25761,6 +34419,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25774,6 +34438,13 @@ "operands": "@H'F9B0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -25794,6 +34465,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25807,6 +34484,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25820,6 +34503,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25835,6 +34524,13 @@ "targets": [ 15990 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25848,6 +34544,13 @@ "operands": "@(-H'0790,R0), R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25863,6 +34566,13 @@ "targets": [ 16026 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25876,6 +34586,12 @@ "operands": "#2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25891,6 +34607,14 @@ "targets": [ 15976 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25904,6 +34628,13 @@ "operands": "R3, @(-H'0790,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25917,6 +34648,13 @@ "operands": "#1, @H'F9B0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -25937,6 +34675,13 @@ "operands": "#7, @H'F9B0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -25957,6 +34702,13 @@ "operands": "@H'F9B0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -25977,6 +34729,12 @@ "operands": "#1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -25990,6 +34748,12 @@ "operands": "#H'7F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26003,6 +34767,12 @@ "operands": "@H'F9B5, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -26025,6 +34795,14 @@ "targets": [ 16026 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26038,6 +34816,12 @@ "operands": "{R2,R3}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26053,6 +34837,15 @@ "targets": [ 16339 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26066,6 +34859,12 @@ "operands": "@SP+, {R2,R3}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26081,6 +34880,14 @@ "targets": [ 16002 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26094,6 +34901,12 @@ "operands": "#6, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26109,6 +34922,13 @@ "targets": [ 16075 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26122,6 +34942,13 @@ "operands": "@H'F9B9, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63929, @@ -26142,6 +34969,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26155,6 +34988,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26168,6 +35007,13 @@ "operands": "@H'F9B4, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -26188,6 +35034,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26201,6 +35053,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26214,6 +35072,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26229,6 +35093,13 @@ "targets": [ 16063 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26242,6 +35113,13 @@ "operands": "@(-H'0690,R0), R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26257,6 +35135,13 @@ "targets": [ 16075 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26270,6 +35155,12 @@ "operands": "#2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26283,6 +35174,12 @@ "operands": "#H'3F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26298,6 +35195,15 @@ "targets": [ 16046 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26311,6 +35217,12 @@ "operands": "R3, @(-H'0690,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26324,6 +35236,12 @@ "operands": "#1, @H'F9B4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -26344,6 +35262,12 @@ "operands": "#5, @H'F9B4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -26364,6 +35288,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26377,6 +35310,12 @@ "operands": "{R0,R1,R2,R3,R4}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 21, + "note": "6+3n, n=5", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26390,6 +35329,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26403,6 +35348,11 @@ "operands": "#H'03, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26418,6 +35368,13 @@ "targets": [ 16089 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26433,6 +35390,14 @@ "targets": [ 16192 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26448,6 +35413,15 @@ "targets": [ 16165 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26461,6 +35435,12 @@ "operands": "R5, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26474,6 +35454,11 @@ "operands": "#H'00, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26489,6 +35474,14 @@ "targets": [ 16105 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26502,6 +35495,11 @@ "operands": "#H'01, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26517,6 +35515,14 @@ "targets": [ 16110 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26530,6 +35536,11 @@ "operands": "#H'02, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26545,6 +35556,14 @@ "targets": [ 16115 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26560,6 +35579,15 @@ "targets": [ 16120 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26573,6 +35601,11 @@ "operands": "#H'0080, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26588,6 +35621,14 @@ "targets": [ 16123 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26601,6 +35642,11 @@ "operands": "#H'00C0, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26616,6 +35662,15 @@ "targets": [ 16123 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26629,6 +35684,11 @@ "operands": "#H'0090, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26644,6 +35704,14 @@ "targets": [ 16123 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26657,6 +35725,11 @@ "operands": "#H'00D0, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26670,6 +35743,12 @@ "operands": "#H'10, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26683,6 +35762,12 @@ "operands": "#H'FAB0, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26696,6 +35781,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26709,6 +35800,13 @@ "operands": "@(-H'0510,R1), R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26722,6 +35820,13 @@ "operands": "@R3, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26737,6 +35842,13 @@ "targets": [ 16144 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26750,6 +35862,13 @@ "operands": "R2, @R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26765,6 +35884,14 @@ "targets": [ 16168 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26778,6 +35905,12 @@ "operands": "#1, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26791,6 +35924,12 @@ "operands": "#1, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26804,6 +35943,11 @@ "operands": "#H'10, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26819,6 +35963,13 @@ "targets": [ 16154 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26834,6 +35985,14 @@ "targets": [ 16132 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26847,6 +36006,13 @@ "operands": "#H'00E0, @H'FB00", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64256, @@ -26867,6 +36033,11 @@ "operands": "#H'00E0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26882,6 +36053,15 @@ "targets": [ 16192 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26895,6 +36075,12 @@ "operands": "@SP+, {R0,R1,R2,R3,R4}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 26, + "note": "6+4n, n=5", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26908,6 +36094,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26921,6 +36116,12 @@ "operands": "R5, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26934,6 +36135,12 @@ "operands": "R1, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26947,6 +36154,13 @@ "operands": "@H'FB00, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64256, @@ -26969,6 +36183,13 @@ "targets": [ 16184 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -26982,6 +36203,13 @@ "operands": "R4, @H'FB00", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64256, @@ -27004,6 +36232,14 @@ "targets": [ 16192 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27017,6 +36253,11 @@ "operands": "#H'0200, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27030,6 +36271,12 @@ "operands": "R2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27045,6 +36292,15 @@ "targets": [ 16192 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27058,6 +36314,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27071,6 +36336,13 @@ "operands": "SR, @-R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 7, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27084,6 +36356,12 @@ "operands": "#H'00FF, SR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27097,6 +36375,12 @@ "operands": "#H'0600, SR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27110,6 +36394,12 @@ "operands": "@H'F200, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61952, @@ -27130,6 +36420,12 @@ "operands": "#7, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27145,6 +36441,14 @@ "targets": [ 16202 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27158,6 +36462,12 @@ "operands": "#8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27173,6 +36483,14 @@ "targets": [ 16237 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27186,6 +36504,12 @@ "operands": "#9, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27201,6 +36525,14 @@ "targets": [ 16226 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27214,6 +36546,12 @@ "operands": "R4, @H'F200", "kind": "normal", "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61952, @@ -27236,6 +36574,14 @@ "targets": [ 16242 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27249,6 +36595,12 @@ "operands": "R4, @H'F201", "kind": "normal", "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61953, @@ -27269,6 +36621,12 @@ "operands": "#1, @H'FB00", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64256, @@ -27291,6 +36649,15 @@ "targets": [ 16242 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27304,6 +36671,12 @@ "operands": "@H'F201, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 61953, @@ -27324,6 +36697,12 @@ "operands": "@R7+, SR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27337,6 +36716,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27350,6 +36737,11 @@ "operands": "#H'2710, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27363,6 +36755,11 @@ "operands": "#H'C350, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27376,6 +36773,13 @@ "operands": "#7, @P1DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65154, @@ -27398,6 +36802,14 @@ "targets": [ 16252 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27411,6 +36823,12 @@ "operands": "#7, @P1DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65154, @@ -27433,6 +36851,14 @@ "targets": [ 16259 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27446,6 +36872,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27459,6 +36891,13 @@ "operands": "@(-H'2000,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27472,6 +36911,13 @@ "operands": "@(-H'1800,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27485,6 +36931,13 @@ "operands": "@(-H'0980,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27498,6 +36951,12 @@ "operands": "#2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27511,6 +36970,11 @@ "operands": "#H'0800, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27526,6 +36990,14 @@ "targets": [ 16268 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27541,6 +37013,15 @@ "targets": [ 17164 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27556,6 +37037,14 @@ "targets": [ 17188 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27571,6 +37060,15 @@ "targets": [ 16534 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27586,6 +37084,14 @@ "targets": [ 16571 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27601,6 +37107,15 @@ "targets": [ 16919 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27616,6 +37131,14 @@ "targets": [ 17228 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27629,6 +37152,12 @@ "operands": "#H'5A00, @WDT_TCSR_R", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65260, @@ -27649,6 +37178,12 @@ "operands": "@H'F794", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63380, @@ -27671,6 +37206,15 @@ "targets": [ 16339 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27686,6 +37230,15 @@ "targets": [ 48043 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27701,6 +37254,14 @@ "targets": [ 16367 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27716,6 +37277,14 @@ "targets": [ 16454 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27731,6 +37300,15 @@ "targets": [ 48798 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27746,6 +37324,14 @@ "targets": [ 10246 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27761,6 +37347,15 @@ "targets": [ 14640 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27776,6 +37371,14 @@ "targets": [ 5600 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27791,6 +37394,15 @@ "targets": [ 16305 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27804,6 +37416,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -27826,6 +37444,14 @@ "targets": [ 16366 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27839,6 +37465,12 @@ "operands": "#7, @H'FAA5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -27861,6 +37493,14 @@ "targets": [ 16357 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27874,6 +37514,12 @@ "operands": "@H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -27896,6 +37542,14 @@ "targets": [ 16366 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27909,6 +37563,12 @@ "operands": "@H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -27931,6 +37591,14 @@ "targets": [ 16366 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27946,6 +37614,15 @@ "targets": [ 47858 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27959,6 +37636,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -27972,6 +37657,12 @@ "operands": "@H'F9C5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63941, @@ -27994,6 +37685,14 @@ "targets": [ 16391 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28007,6 +37706,12 @@ "operands": "@H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -28027,6 +37732,12 @@ "operands": "@H'F9B0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -28047,6 +37758,12 @@ "operands": "#7, @H'FAA5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -28069,6 +37786,14 @@ "targets": [ 16395 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28084,6 +37809,15 @@ "targets": [ 16396 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28099,6 +37833,15 @@ "targets": [ 16395 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28112,6 +37855,12 @@ "operands": "#7, @H'FAA5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -28132,6 +37881,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28145,6 +37903,13 @@ "operands": "@H'F730", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63280, @@ -28165,6 +37930,13 @@ "operands": "@H'F756", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63318, @@ -28185,6 +37957,13 @@ "operands": "@H'F757", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63319, @@ -28205,6 +37984,13 @@ "operands": "@H'F758", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63320, @@ -28225,6 +38011,13 @@ "operands": "@H'F759", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63321, @@ -28245,6 +38038,13 @@ "operands": "@H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -28265,6 +38065,13 @@ "operands": "@H'F75C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63324, @@ -28285,6 +38092,13 @@ "operands": "@H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -28305,6 +38119,13 @@ "operands": "@H'E046", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57414, @@ -28325,6 +38146,13 @@ "operands": "@H'F76A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63338, @@ -28345,6 +38173,13 @@ "operands": "@H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -28365,6 +38200,13 @@ "operands": "@H'F795", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63381, @@ -28385,6 +38227,13 @@ "operands": "@H'F76E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63342, @@ -28407,6 +38256,14 @@ "targets": [ 16501 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28422,6 +38279,14 @@ "targets": [ 16919 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28435,6 +38300,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28448,6 +38322,13 @@ "operands": "@H'F9C4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63940, @@ -28470,6 +38351,13 @@ "targets": [ 16472 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28483,6 +38371,13 @@ "operands": "#7, @H'FAA5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -28505,6 +38400,13 @@ "targets": [ 16473 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28518,6 +38420,13 @@ "operands": "@H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -28540,6 +38449,13 @@ "targets": [ 16473 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28553,6 +38469,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28566,6 +38490,12 @@ "operands": "@H'F9B0, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -28586,6 +38516,12 @@ "operands": "R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28599,6 +38535,12 @@ "operands": "@H'F9B5, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -28621,6 +38563,14 @@ "targets": [ 16500 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28634,6 +38584,12 @@ "operands": "R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28647,6 +38603,13 @@ "operands": "#H'00, @(-H'0790,R2)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28660,6 +38623,13 @@ "operands": "#1, @H'F9B0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -28680,6 +38650,13 @@ "operands": "#7, @H'F9B0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -28700,6 +38677,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28713,6 +38698,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28726,6 +38717,12 @@ "operands": "@(-H'2000,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28739,6 +38736,12 @@ "operands": "@(-H'1C00,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28752,6 +38755,12 @@ "operands": "@(-H'1800,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28765,6 +38774,11 @@ "operands": "#H'0200, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28780,6 +38794,13 @@ "targets": [ 16524 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28793,6 +38814,13 @@ "operands": "@(-H'1400,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28806,6 +38834,12 @@ "operands": "#2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28819,6 +38853,11 @@ "operands": "#H'0400, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28834,6 +38873,14 @@ "targets": [ 16503 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28849,6 +38896,15 @@ "targets": [ 16534 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28862,6 +38918,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -28875,6 +38940,13 @@ "operands": "#H'0080, @H'E000", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57344, @@ -28895,6 +38967,13 @@ "operands": "#H'8000, @H'E006", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57350, @@ -28915,6 +38994,13 @@ "operands": "#H'FFFF, @H'E080", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57472, @@ -28935,6 +39021,13 @@ "operands": "#H'0080, @H'E800", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 59392, @@ -28955,6 +39048,13 @@ "operands": "#H'8000, @H'E806", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 59398, @@ -28975,6 +39075,13 @@ "operands": "#H'FFFF, @H'E880", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 59520, @@ -28995,6 +39102,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29008,6 +39123,11 @@ "operands": "#H'0040, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29021,6 +39141,12 @@ "operands": "#H'FFFF, @(-H'0792,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29034,6 +39160,12 @@ "operands": "#H'FFFF, @(-H'0752,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29047,6 +39179,12 @@ "operands": "#H'FFFF, @(-H'0712,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29060,6 +39198,12 @@ "operands": "#H'FFFF, @(-H'06D2,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29073,6 +39217,12 @@ "operands": "#H'FFFF, @(-H'0692,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29086,6 +39236,12 @@ "operands": "#-2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29101,6 +39257,13 @@ "targets": [ 16574 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29114,6 +39277,13 @@ "operands": "#H'14, @H'F9C4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63940, @@ -29134,6 +39304,13 @@ "operands": "#H'80, @H'F6F7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63223, @@ -29154,6 +39331,13 @@ "operands": "#H'80, @H'F6F8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63224, @@ -29174,6 +39358,13 @@ "operands": "#H'80, @H'F6F9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63225, @@ -29194,6 +39385,13 @@ "operands": "#7, @P7DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -29216,6 +39414,13 @@ "targets": [ 16643 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29229,6 +39434,13 @@ "operands": "#H'6B6F, @H'F402", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62466, @@ -29251,6 +39463,13 @@ "targets": [ 16816 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29264,6 +39483,11 @@ "operands": "#H'0100, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29277,6 +39501,12 @@ "operands": "#-2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29290,6 +39520,13 @@ "operands": "@(-H'369C,R0), R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29303,6 +39540,13 @@ "operands": "R5, @(-H'0C00,R0)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29316,6 +39560,13 @@ "operands": "R0, @-R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29329,6 +39580,12 @@ "operands": "R0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29344,6 +39601,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29357,6 +39622,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29372,6 +39643,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29385,6 +39665,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29400,6 +39686,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29413,6 +39707,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29428,6 +39728,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29441,6 +39750,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29456,6 +39771,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29469,6 +39792,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29484,6 +39813,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29497,6 +39835,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29512,6 +39856,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29525,6 +39877,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29540,6 +39898,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29553,6 +39920,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29568,6 +39941,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29581,6 +39962,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29596,6 +39983,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29609,6 +40005,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29624,6 +40026,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29637,6 +40047,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29652,6 +40068,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29665,6 +40090,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29680,6 +40111,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29693,6 +40132,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29708,6 +40153,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29721,6 +40175,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29736,6 +40196,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29749,6 +40217,12 @@ "operands": "#H'0100, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29764,6 +40238,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29777,6 +40260,12 @@ "operands": "@R7+, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29792,6 +40281,13 @@ "targets": [ 16646 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29805,6 +40301,11 @@ "operands": "#H'000F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29818,6 +40319,12 @@ "operands": "R0, @-R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29831,6 +40338,12 @@ "operands": "R0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29844,6 +40357,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29857,6 +40376,11 @@ "operands": "#H'2020, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29872,6 +40396,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29885,6 +40417,12 @@ "operands": "#2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29898,6 +40436,11 @@ "operands": "#H'2020, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29913,6 +40456,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29926,6 +40477,12 @@ "operands": "#2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29939,6 +40496,11 @@ "operands": "#H'2020, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29954,6 +40516,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29967,6 +40537,12 @@ "operands": "#2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29980,6 +40556,11 @@ "operands": "#H'2020, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -29995,6 +40576,14 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30008,6 +40597,13 @@ "operands": "@R7+, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30023,6 +40619,14 @@ "targets": [ 16775 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30038,6 +40642,14 @@ "targets": [ 16850 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30051,6 +40663,11 @@ "operands": "#H'000F, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30064,6 +40681,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30077,6 +40700,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30090,6 +40719,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30103,6 +40738,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30116,6 +40757,12 @@ "operands": "R0, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30129,6 +40776,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30142,6 +40795,12 @@ "operands": "{R0,R1}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30157,6 +40816,15 @@ "targets": [ 49150 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30170,6 +40838,12 @@ "operands": "@SP+, {R0,R1}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30183,6 +40857,13 @@ "operands": "R5, @(-H'0850,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30196,6 +40877,12 @@ "operands": "#2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30209,6 +40896,12 @@ "operands": "{R0,R1}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30224,6 +40917,14 @@ "targets": [ 49150 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30237,6 +40938,12 @@ "operands": "@SP+, {R0,R1}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30250,6 +40957,12 @@ "operands": "R5, @(-H'084E,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30263,6 +40976,12 @@ "operands": "#2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30276,6 +40995,12 @@ "operands": "{R0,R1}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30291,6 +41016,15 @@ "targets": [ 49150 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30304,6 +41038,12 @@ "operands": "@SP+, {R0,R1}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30317,6 +41057,13 @@ "operands": "R5, @(-H'084C,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30330,6 +41077,12 @@ "operands": "#2, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30343,6 +41096,12 @@ "operands": "{R0,R1}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30358,6 +41117,14 @@ "targets": [ 49150 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30371,6 +41138,12 @@ "operands": "@SP+, {R0,R1}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30384,6 +41157,12 @@ "operands": "R5, @(-H'084A,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30399,6 +41178,14 @@ "targets": [ 16853 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30412,6 +41199,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -30425,6 +41220,12 @@ "operands": "@H'F798", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63384, @@ -30445,6 +41246,12 @@ "operands": "#7, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -30465,6 +41272,12 @@ "operands": "#2, @P1DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65154, @@ -30485,6 +41298,12 @@ "operands": "#H'2424, @H'F700", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63232, @@ -30505,6 +41324,12 @@ "operands": "#H'2424, @H'F702", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63234, @@ -30525,6 +41350,12 @@ "operands": "#H'2424, @H'F704", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63236, @@ -30545,6 +41376,12 @@ "operands": "#H'2424, @H'F706", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63238, @@ -30565,6 +41402,13 @@ "operands": "#H'7F, @H'F708", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63240, @@ -30585,6 +41429,13 @@ "operands": "#H'24, @H'F709", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63241, @@ -30605,6 +41456,12 @@ "operands": "#H'2424, @H'F70A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63242, @@ -30625,6 +41482,12 @@ "operands": "@H'F710", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63248, @@ -30645,6 +41508,12 @@ "operands": "@H'F711", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63249, @@ -30665,6 +41534,12 @@ "operands": "@H'F712", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63250, @@ -30685,6 +41560,12 @@ "operands": "@H'F713", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63251, @@ -30705,6 +41586,12 @@ "operands": "@H'F714", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63252, @@ -30725,6 +41612,12 @@ "operands": "@H'F715", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63253, @@ -30745,6 +41638,12 @@ "operands": "@H'F716", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63254, @@ -30765,6 +41664,12 @@ "operands": "@H'F717", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63255, @@ -30785,6 +41690,13 @@ "operands": "#H'FF, @H'F718", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63256, @@ -30805,6 +41717,13 @@ "operands": "#H'FF, @H'F719", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63257, @@ -30825,6 +41744,13 @@ "operands": "#H'FF, @H'F71A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63258, @@ -30845,6 +41771,13 @@ "operands": "#H'FF, @H'F71B", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63259, @@ -30865,6 +41798,13 @@ "operands": "#H'FF, @H'F71C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63260, @@ -30885,6 +41825,13 @@ "operands": "#H'FF, @H'F71D", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63261, @@ -30905,6 +41852,13 @@ "operands": "#H'FF, @H'F71E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63262, @@ -30925,6 +41879,13 @@ "operands": "#H'FF, @H'F71F", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63263, @@ -30945,6 +41906,12 @@ "operands": "#H'2043, @H'FAF0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64240, @@ -30965,6 +41932,12 @@ "operands": "#H'4F4E, @H'FAF2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64242, @@ -30985,6 +41958,12 @@ "operands": "#H'4E45, @H'FAF4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64244, @@ -31005,6 +41984,12 @@ "operands": "#H'4354, @H'FAF6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64246, @@ -31025,6 +42010,12 @@ "operands": "#H'3A4E, @H'FAF8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64248, @@ -31045,6 +42036,12 @@ "operands": "#H'4F54, @H'FAFA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64250, @@ -31065,6 +42062,12 @@ "operands": "#H'2041, @H'FAFC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64252, @@ -31085,6 +42088,12 @@ "operands": "#H'4354, @H'FAFE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64254, @@ -31105,6 +42114,11 @@ "operands": "#H'0000, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31120,6 +42134,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31133,6 +42155,12 @@ "operands": "#H'2020, @H'FAF0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64240, @@ -31153,6 +42181,12 @@ "operands": "#H'2020, @H'FAF2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64242, @@ -31173,6 +42207,12 @@ "operands": "#H'2020, @H'FAF4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64244, @@ -31193,6 +42233,12 @@ "operands": "#H'2020, @H'FAF6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64246, @@ -31213,6 +42259,12 @@ "operands": "#H'2020, @H'FAF8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64248, @@ -31233,6 +42285,12 @@ "operands": "#H'2020, @H'FAFA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64250, @@ -31253,6 +42311,12 @@ "operands": "#H'2020, @H'FAFC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64252, @@ -31273,6 +42337,12 @@ "operands": "#H'2020, @H'FAFE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64254, @@ -31293,6 +42363,11 @@ "operands": "#H'0001, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31308,6 +42383,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31321,6 +42404,11 @@ "operands": "#H'0002, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31336,6 +42424,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31349,6 +42445,11 @@ "operands": "#H'0003, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31364,6 +42465,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31377,6 +42486,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31390,6 +42508,13 @@ "operands": "#0, @P6DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65163, @@ -31410,6 +42535,13 @@ "operands": "#H'AA, @H'F555", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62805, @@ -31430,6 +42562,13 @@ "operands": "#H'55, @H'F4AA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62634, @@ -31450,6 +42589,13 @@ "operands": "#H'CC, @H'F555", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 62805, @@ -31470,6 +42616,12 @@ "operands": "#0, @P6DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65163, @@ -31490,6 +42642,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31503,6 +42664,11 @@ "operands": "#H'0038, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31516,6 +42682,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31531,6 +42702,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31544,6 +42723,11 @@ "operands": "#H'0001, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31557,6 +42741,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31572,6 +42761,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31585,6 +42783,11 @@ "operands": "#H'000E, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31598,6 +42801,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31613,6 +42821,14 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31626,6 +42842,11 @@ "operands": "#H'0006, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31639,6 +42860,11 @@ "operands": "#H'0004, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31654,6 +42880,15 @@ "targets": [ 16076 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31669,6 +42904,14 @@ "targets": [ 4302 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31682,6 +42925,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31695,6 +42947,13 @@ "operands": "#H'70, @IPRA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65280, @@ -31715,6 +42974,13 @@ "operands": "#H'44, @IPRB", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65281, @@ -31735,6 +43001,13 @@ "operands": "#H'66, @IPRC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65282, @@ -31755,6 +43028,13 @@ "operands": "#H'00, @IPRD", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65283, @@ -31775,6 +43055,13 @@ "operands": "#H'50, @IPRE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65284, @@ -31795,6 +43082,13 @@ "operands": "#H'40, @IPRF", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65285, @@ -31815,6 +43109,13 @@ "operands": "#6, @SCI1_SCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65242, @@ -31835,6 +43136,13 @@ "operands": "#5, @FRT1_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65168, @@ -31855,6 +43163,13 @@ "operands": "#5, @FRT2_TCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65184, @@ -31875,6 +43190,13 @@ "operands": "#6, @ADCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65256, @@ -31895,6 +43217,13 @@ "operands": "#4, @SYSCR2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65277, @@ -31915,6 +43244,13 @@ "operands": "#5, @SYSCR2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65277, @@ -31935,6 +43271,13 @@ "operands": "#6, @P7DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65166, @@ -31957,6 +43300,13 @@ "targets": [ 17294 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -31970,6 +43320,13 @@ "operands": "#H'A53F, @WDT_TCSR_R", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65260, @@ -31990,6 +43347,12 @@ "operands": "#H'0300, SR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32003,6 +43366,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32016,6 +43387,13 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32029,6 +43407,13 @@ "operands": "#H'01, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -32051,6 +43436,14 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32064,6 +43457,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -32086,6 +43486,13 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32099,6 +43506,12 @@ "operands": "@H'F736, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63286, @@ -32121,6 +43534,14 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32134,6 +43555,13 @@ "operands": "@H'F69E, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63134, @@ -32154,6 +43582,13 @@ "operands": "@H'F6BE, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63166, @@ -32174,6 +43609,12 @@ "operands": "#15, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32189,6 +43630,13 @@ "targets": [ 17359 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32202,6 +43650,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32217,6 +43671,13 @@ "targets": [ 17371 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32230,6 +43691,12 @@ "operands": "#13, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32245,6 +43712,13 @@ "targets": [ 17383 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32258,6 +43732,12 @@ "operands": "#12, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32273,6 +43753,13 @@ "targets": [ 17395 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32286,6 +43773,12 @@ "operands": "#11, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32301,6 +43794,13 @@ "targets": [ 17407 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32314,6 +43814,12 @@ "operands": "#10, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32329,6 +43835,13 @@ "targets": [ 17421 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32344,6 +43857,14 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32359,6 +43880,15 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32374,6 +43904,15 @@ "targets": [ 17455 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32387,6 +43926,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32402,6 +43946,13 @@ "targets": [ 17369 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32417,6 +43968,14 @@ "targets": [ 6709 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32432,6 +43991,15 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32447,6 +44015,15 @@ "targets": [ 17455 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32460,6 +44037,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32475,6 +44057,13 @@ "targets": [ 17381 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32490,6 +44079,14 @@ "targets": [ 6812 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32505,6 +44102,15 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32520,6 +44126,15 @@ "targets": [ 17455 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32533,6 +44148,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32548,6 +44168,13 @@ "targets": [ 17393 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32563,6 +44190,14 @@ "targets": [ 6884 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32578,6 +44213,15 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32593,6 +44237,15 @@ "targets": [ 17455 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32606,6 +44259,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32621,6 +44279,13 @@ "targets": [ 17405 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32636,6 +44301,14 @@ "targets": [ 6923 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32651,6 +44324,15 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32664,6 +44346,13 @@ "operands": "#H'80, @H'F770", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63344, @@ -32684,6 +44373,13 @@ "operands": "R4, @H'F772", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63346, @@ -32706,6 +44402,14 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32721,6 +44425,15 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32736,6 +44449,15 @@ "targets": [ 17455 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32749,6 +44471,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32764,6 +44491,13 @@ "targets": [ 17440 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32777,6 +44511,13 @@ "operands": "#H'80, @H'F770", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63344, @@ -32797,6 +44538,12 @@ "operands": "R4, @H'F772", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63346, @@ -32819,6 +44566,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32834,6 +44590,14 @@ "targets": [ 17442 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32847,6 +44611,13 @@ "operands": "@H'F69E, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63134, @@ -32867,6 +44638,13 @@ "operands": "R4, @H'F6BE", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63166, @@ -32887,6 +44665,13 @@ "operands": "@H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -32907,6 +44692,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32920,6 +44713,12 @@ "operands": "@H'F6F7, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63223, @@ -32940,6 +44739,11 @@ "operands": "#H'88, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32955,6 +44759,14 @@ "targets": [ 17476 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32968,6 +44780,11 @@ "operands": "#H'78, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32983,6 +44800,14 @@ "targets": [ 17486 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -32996,6 +44821,12 @@ "operands": "R4, @H'F6F7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63223, @@ -33016,6 +44847,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33031,6 +44867,14 @@ "targets": [ 17494 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33044,6 +44888,13 @@ "operands": "#H'80, @H'F6F7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63223, @@ -33064,6 +44915,11 @@ "operands": "#H'0000, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33079,6 +44935,14 @@ "targets": [ 17494 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33092,6 +44956,13 @@ "operands": "#H'80, @H'F6F7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63223, @@ -33112,6 +44983,11 @@ "operands": "#H'0001, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33125,6 +45001,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33138,6 +45022,12 @@ "operands": "#H'01, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -33160,6 +45050,13 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33173,6 +45070,12 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -33195,6 +45098,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33208,6 +45119,13 @@ "operands": "@H'F738, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63288, @@ -33230,6 +45148,13 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33243,6 +45168,12 @@ "operands": "@H'F69C, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63132, @@ -33263,6 +45194,12 @@ "operands": "@H'F6BC, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63164, @@ -33283,6 +45220,12 @@ "operands": "#15, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33298,6 +45241,14 @@ "targets": [ 17554 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33311,6 +45262,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33326,6 +45283,14 @@ "targets": [ 17566 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33339,6 +45304,12 @@ "operands": "#13, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33354,6 +45325,14 @@ "targets": [ 17578 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33367,6 +45346,12 @@ "operands": "#12, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33382,6 +45367,14 @@ "targets": [ 17590 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33395,6 +45388,12 @@ "operands": "#11, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33410,6 +45409,14 @@ "targets": [ 17602 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33423,6 +45430,12 @@ "operands": "#10, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33438,6 +45451,14 @@ "targets": [ 17616 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33453,6 +45474,15 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33468,6 +45498,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33483,6 +45521,14 @@ "targets": [ 17650 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33496,6 +45542,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33511,6 +45562,14 @@ "targets": [ 17564 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33526,6 +45585,15 @@ "targets": [ 6709 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33541,6 +45609,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33556,6 +45632,14 @@ "targets": [ 17650 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33569,6 +45653,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33584,6 +45673,14 @@ "targets": [ 17576 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33599,6 +45696,15 @@ "targets": [ 6812 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33614,6 +45720,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33629,6 +45743,14 @@ "targets": [ 17650 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33642,6 +45764,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33657,6 +45784,14 @@ "targets": [ 17588 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33672,6 +45807,15 @@ "targets": [ 6884 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33687,6 +45831,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33702,6 +45854,14 @@ "targets": [ 17650 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33715,6 +45875,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33730,6 +45895,14 @@ "targets": [ 17600 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33745,6 +45918,15 @@ "targets": [ 6923 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33760,6 +45942,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33773,6 +45963,13 @@ "operands": "#H'40, @H'F770", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63344, @@ -33793,6 +45990,12 @@ "operands": "R4, @H'F772", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63346, @@ -33815,6 +46018,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33830,6 +46042,14 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33845,6 +46065,14 @@ "targets": [ 17650 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33858,6 +46086,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33873,6 +46106,14 @@ "targets": [ 17635 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33886,6 +46127,13 @@ "operands": "#H'40, @H'F770", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63344, @@ -33906,6 +46154,13 @@ "operands": "R4, @H'F772", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63346, @@ -33928,6 +46183,14 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33943,6 +46206,15 @@ "targets": [ 17637 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -33956,6 +46228,12 @@ "operands": "@H'F69C, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63132, @@ -33976,6 +46254,12 @@ "operands": "R4, @H'F6BC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63164, @@ -33996,6 +46280,12 @@ "operands": "@H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -34016,6 +46306,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34029,6 +46328,13 @@ "operands": "@H'F6F8, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63224, @@ -34049,6 +46355,11 @@ "operands": "#H'88, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34064,6 +46375,13 @@ "targets": [ 17671 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34077,6 +46395,11 @@ "operands": "#H'78, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34092,6 +46415,13 @@ "targets": [ 17681 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34105,6 +46435,13 @@ "operands": "R4, @H'F6F8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63224, @@ -34125,6 +46462,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34140,6 +46482,15 @@ "targets": [ 17689 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34153,6 +46504,13 @@ "operands": "#H'80, @H'F6F8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63224, @@ -34173,6 +46531,11 @@ "operands": "#H'0000, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34188,6 +46551,15 @@ "targets": [ 17689 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34201,6 +46573,13 @@ "operands": "#H'80, @H'F6F8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63224, @@ -34221,6 +46600,11 @@ "operands": "#H'0001, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34234,6 +46618,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34247,6 +46640,13 @@ "operands": "#H'01, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -34269,6 +46669,14 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34282,6 +46690,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -34304,6 +46719,13 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34317,6 +46739,12 @@ "operands": "@H'F73A, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63290, @@ -34339,6 +46767,14 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34352,6 +46788,13 @@ "operands": "@H'F69A, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63130, @@ -34372,6 +46815,13 @@ "operands": "@H'F6BA, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63162, @@ -34392,6 +46842,12 @@ "operands": "#15, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34407,6 +46863,13 @@ "targets": [ 17749 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34420,6 +46883,12 @@ "operands": "#14, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34435,6 +46904,13 @@ "targets": [ 17761 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34448,6 +46924,12 @@ "operands": "#13, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34463,6 +46945,13 @@ "targets": [ 17773 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34476,6 +46965,12 @@ "operands": "#12, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34491,6 +46986,13 @@ "targets": [ 17785 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34504,6 +47006,12 @@ "operands": "#11, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34519,6 +47027,13 @@ "targets": [ 17797 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34532,6 +47047,12 @@ "operands": "#10, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34547,6 +47068,13 @@ "targets": [ 17811 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34562,6 +47090,14 @@ "targets": [ 6562 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34577,6 +47113,15 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34592,6 +47137,15 @@ "targets": [ 17845 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34605,6 +47159,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34620,6 +47179,13 @@ "targets": [ 17759 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34635,6 +47201,14 @@ "targets": [ 6709 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34650,6 +47224,15 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34665,6 +47248,15 @@ "targets": [ 17845 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34678,6 +47270,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34693,6 +47290,13 @@ "targets": [ 17771 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34708,6 +47312,14 @@ "targets": [ 6812 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34723,6 +47335,15 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34738,6 +47359,15 @@ "targets": [ 17845 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34751,6 +47381,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34766,6 +47401,13 @@ "targets": [ 17783 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34781,6 +47423,14 @@ "targets": [ 6884 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34796,6 +47446,15 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34811,6 +47470,15 @@ "targets": [ 17845 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34824,6 +47492,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34839,6 +47512,13 @@ "targets": [ 17795 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34854,6 +47534,14 @@ "targets": [ 6923 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34869,6 +47557,15 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34882,6 +47579,13 @@ "operands": "#H'20, @H'F770", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63344, @@ -34902,6 +47606,13 @@ "operands": "R4, @H'F772", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63346, @@ -34924,6 +47635,14 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34939,6 +47658,15 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34954,6 +47682,15 @@ "targets": [ 17845 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34967,6 +47704,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34982,6 +47724,13 @@ "targets": [ 17830 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -34995,6 +47744,13 @@ "operands": "#H'20, @H'F770", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63344, @@ -35015,6 +47771,12 @@ "operands": "R4, @H'F772", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63346, @@ -35037,6 +47799,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35052,6 +47823,14 @@ "targets": [ 17832 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35065,6 +47844,13 @@ "operands": "@H'F69A, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63130, @@ -35085,6 +47871,13 @@ "operands": "R4, @H'F6BA", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63162, @@ -35105,6 +47898,13 @@ "operands": "@H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -35125,6 +47925,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35138,6 +47946,12 @@ "operands": "@H'F6F9, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63225, @@ -35158,6 +47972,11 @@ "operands": "#H'88, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35173,6 +47992,14 @@ "targets": [ 17866 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35186,6 +48013,11 @@ "operands": "#H'78, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35201,6 +48033,14 @@ "targets": [ 17876 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35214,6 +48054,12 @@ "operands": "R4, @H'F6F9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63225, @@ -35234,6 +48080,11 @@ "operands": "#H'0002, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35249,6 +48100,14 @@ "targets": [ 17884 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35262,6 +48121,13 @@ "operands": "#H'80, @H'F6F9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63225, @@ -35282,6 +48148,11 @@ "operands": "#H'0000, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35297,6 +48168,14 @@ "targets": [ 17884 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35310,6 +48189,13 @@ "operands": "#H'80, @H'F6F9", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63225, @@ -35330,6 +48216,11 @@ "operands": "#H'0001, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35343,6 +48234,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35356,6 +48255,12 @@ "operands": "@H'F734, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63284, @@ -35376,6 +48281,12 @@ "operands": "R0, @H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -35398,6 +48309,15 @@ "targets": [ 18682 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35411,6 +48331,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35424,6 +48353,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -35446,6 +48382,13 @@ "targets": [ 18729 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35459,6 +48402,13 @@ "operands": "#H'1A, @H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -35481,6 +48431,14 @@ "targets": [ 18729 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35494,6 +48452,12 @@ "operands": "#H'1900, @H'F732", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -35516,6 +48480,14 @@ "targets": [ 18729 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35529,6 +48501,12 @@ "operands": "#13, @H'E1EC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57836, @@ -35551,6 +48529,14 @@ "targets": [ 18729 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35564,6 +48550,12 @@ "operands": "@H'E1EC, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 57836, @@ -35584,6 +48576,12 @@ "operands": "#H'9FFF, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35597,6 +48595,12 @@ "operands": "R0, @H'E9EC", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 59884, @@ -35617,6 +48621,11 @@ "operands": "#H'80, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35630,6 +48639,11 @@ "operands": "#H'00F6, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35645,6 +48659,14 @@ "targets": [ 15956 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35658,6 +48680,12 @@ "operands": "#6, @H'F76E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63342, @@ -35680,6 +48708,14 @@ "targets": [ 18749 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35693,6 +48729,12 @@ "operands": "@H'F732, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63282, @@ -35713,6 +48755,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35726,6 +48774,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35739,6 +48793,12 @@ "operands": "@(H'493E,R0), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35752,6 +48812,15 @@ "operands": "@R0", "kind": "call", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35765,6 +48834,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35778,6 +48856,12 @@ "operands": "#H'01FF, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35791,6 +48875,11 @@ "operands": "#H'007F, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35806,6 +48895,14 @@ "targets": [ 25110 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35819,6 +48916,11 @@ "operands": "#H'017F, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35834,6 +48936,13 @@ "targets": [ 25112 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35849,6 +48958,14 @@ "targets": [ 25122 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35864,6 +48981,14 @@ "targets": [ 25130 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35877,6 +49002,12 @@ "operands": "#H'0080, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35890,6 +49021,12 @@ "operands": "#H'0100, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35905,6 +49042,14 @@ "targets": [ 25130 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35918,6 +49063,12 @@ "operands": "#H'0180, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35931,6 +49082,12 @@ "operands": "#H'0200, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35944,6 +49101,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35957,6 +49122,12 @@ "operands": "R5, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35970,6 +49141,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35983,6 +49160,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -35996,6 +49179,12 @@ "operands": "#H'07, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36009,6 +49198,11 @@ "operands": "#H'00, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36024,6 +49218,13 @@ "targets": [ 25156 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36037,6 +49238,11 @@ "operands": "#H'01, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36052,6 +49258,13 @@ "targets": [ 25165 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36065,6 +49278,11 @@ "operands": "#H'02, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36080,6 +49298,13 @@ "targets": [ 25174 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36093,6 +49318,11 @@ "operands": "#H'03, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36108,6 +49338,13 @@ "targets": [ 25183 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36121,6 +49358,11 @@ "operands": "#H'7F, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36136,6 +49378,13 @@ "targets": [ 25183 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36149,6 +49398,11 @@ "operands": "#H'0000, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36164,6 +49418,15 @@ "targets": [ 25188 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36177,6 +49440,11 @@ "operands": "#H'FF, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36192,6 +49460,14 @@ "targets": [ 25183 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36205,6 +49481,11 @@ "operands": "#H'0080, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36220,6 +49501,14 @@ "targets": [ 25188 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36233,6 +49522,11 @@ "operands": "#H'7F, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36248,6 +49542,13 @@ "targets": [ 25183 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36261,6 +49562,11 @@ "operands": "#H'0180, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36276,6 +49582,15 @@ "targets": [ 25188 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36289,6 +49604,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36302,6 +49623,11 @@ "operands": "#H'01FF, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36315,6 +49641,12 @@ "operands": "R4, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36328,6 +49660,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36341,6 +49681,13 @@ "operands": "@H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -36363,6 +49710,13 @@ "targets": [ 47654 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36376,6 +49730,13 @@ "operands": "#H'64, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -36396,6 +49757,13 @@ "operands": "#H'07, @H'F9C4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63940, @@ -36416,6 +49784,13 @@ "operands": "@H'F850, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63568, @@ -36436,6 +49811,13 @@ "operands": "R0, @H'F858", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63576, @@ -36456,6 +49838,13 @@ "operands": "@H'F852, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63570, @@ -36476,6 +49865,13 @@ "operands": "R0, @H'F85A", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63578, @@ -36496,6 +49892,13 @@ "operands": "@H'F854, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63572, @@ -36516,6 +49919,13 @@ "operands": "R0, @H'F85C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63580, @@ -36536,6 +49946,11 @@ "operands": "#H'5A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36549,6 +49964,13 @@ "operands": "@H'F858, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63576, @@ -36569,6 +49991,13 @@ "operands": "@H'F859, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63577, @@ -36589,6 +50018,13 @@ "operands": "@H'F85A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63578, @@ -36609,6 +50045,13 @@ "operands": "@H'F85B, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63579, @@ -36629,6 +50072,13 @@ "operands": "@H'F85C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63580, @@ -36649,6 +50099,13 @@ "operands": "R0, @H'F85D", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63581, @@ -36669,6 +50126,13 @@ "operands": "#7, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -36691,6 +50155,13 @@ "targets": [ 47720 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36704,6 +50175,13 @@ "operands": "@H'F858, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63576, @@ -36724,6 +50202,13 @@ "operands": "R0, @SCI1_TDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65243, @@ -36744,6 +50229,13 @@ "operands": "#H'01, @H'F9C2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63938, @@ -36764,6 +50256,12 @@ "operands": "#7, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -36784,6 +50282,12 @@ "operands": "#7, @SCI1_SCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65242, @@ -36804,6 +50308,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36817,6 +50330,13 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -36839,6 +50359,13 @@ "targets": [ 47785 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36852,6 +50379,13 @@ "operands": "#7, @H'FAA5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -36874,6 +50408,13 @@ "targets": [ 47785 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36887,6 +50428,13 @@ "operands": "@H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -36909,6 +50457,13 @@ "targets": [ 47785 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -36922,6 +50477,13 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -36942,6 +50504,13 @@ "operands": "@H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -36962,6 +50531,13 @@ "operands": "#7, @SCI1_SCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65242, @@ -36982,6 +50558,13 @@ "operands": "#H'1F, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -37004,6 +50587,15 @@ "targets": [ 47857 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37017,6 +50609,12 @@ "operands": "R0, @-R7", "kind": "normal", "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37030,6 +50628,12 @@ "operands": "@H'F9C2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63938, @@ -37050,6 +50654,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37063,6 +50673,12 @@ "operands": "@(-H'07A8,R0), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37076,6 +50692,12 @@ "operands": "R0, @SCI1_TDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65243, @@ -37096,6 +50718,13 @@ "operands": "@R7+, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37109,6 +50738,12 @@ "operands": "#7, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -37129,6 +50764,12 @@ "operands": "#1, @H'F9C2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63938, @@ -37149,6 +50790,12 @@ "operands": "#H'06, @H'F9C2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63938, @@ -37171,6 +50818,13 @@ "targets": [ 47857 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37184,6 +50838,13 @@ "operands": "#7, @SCI1_SCR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65242, @@ -37204,6 +50865,13 @@ "operands": "#6, @H'F795", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63381, @@ -37226,6 +50894,13 @@ "targets": [ 47848 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37239,6 +50914,13 @@ "operands": "#7, @H'F791", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63377, @@ -37261,6 +50943,13 @@ "targets": [ 47841 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37274,6 +50963,13 @@ "operands": "#H'09, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -37296,6 +50992,15 @@ "targets": [ 47853 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37309,6 +51014,13 @@ "operands": "#H'09, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -37331,6 +51043,14 @@ "targets": [ 47853 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37344,6 +51064,13 @@ "operands": "#H'F0, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -37364,6 +51091,12 @@ "operands": "@H'F9C1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63937, @@ -37384,6 +51117,13 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37397,6 +51137,13 @@ "operands": "@H'F9B5, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -37417,6 +51164,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37430,6 +51183,13 @@ "operands": "@H'F9B0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63920, @@ -37452,6 +51212,13 @@ "targets": [ 47872 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37467,6 +51234,14 @@ "targets": [ 47958 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37480,6 +51255,13 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -37500,6 +51282,12 @@ "operands": "R1, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37513,6 +51301,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37526,6 +51320,13 @@ "operands": "@(-H'0790,R0), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37539,6 +51340,12 @@ "operands": "R0, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37554,6 +51361,14 @@ "targets": [ 25094 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37567,6 +51382,12 @@ "operands": "R0, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37580,6 +51401,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37593,6 +51420,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37606,6 +51439,12 @@ "operands": "R1, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37619,6 +51458,12 @@ "operands": "#H'07, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37632,6 +51477,13 @@ "operands": "R1, @H'F850", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63568, @@ -37652,6 +51504,13 @@ "operands": "R5, @H'F852", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63570, @@ -37672,6 +51531,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37685,6 +51550,12 @@ "operands": "#H'78, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37698,6 +51569,12 @@ "operands": "R2, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37711,6 +51588,12 @@ "operands": "R5, @H'F851", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63569, @@ -37731,6 +51614,12 @@ "operands": "#H'01FF, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37744,6 +51633,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37757,6 +51652,12 @@ "operands": "@(-H'1800,R0), R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37770,6 +51671,12 @@ "operands": "R4, @H'F854", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63572, @@ -37790,6 +51697,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37803,6 +51716,12 @@ "operands": "R4, @H'F853", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63571, @@ -37825,6 +51744,15 @@ "targets": [ 47654 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37838,6 +51766,13 @@ "operands": "#H'01F4, @H'F9C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63942, @@ -37858,6 +51793,13 @@ "operands": "#H'14, @H'F9C8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63944, @@ -37878,6 +51820,13 @@ "operands": "#H'80, @H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -37898,6 +51847,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -37911,6 +51868,12 @@ "operands": "#7, @H'FAA4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64164, @@ -37931,6 +51894,12 @@ "operands": "#5, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -37951,6 +51920,12 @@ "operands": "#4, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -37971,6 +51946,12 @@ "operands": "#3, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -37991,6 +51972,12 @@ "operands": "{R0,R1}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38004,6 +51991,12 @@ "operands": "#6, @SCI1_SSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65244, @@ -38024,6 +52017,12 @@ "operands": "@SCI1_RDR, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65245, @@ -38044,6 +52043,12 @@ "operands": "@H'F9C1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63937, @@ -38066,6 +52071,14 @@ "targets": [ 47997 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38079,6 +52092,12 @@ "operands": "@H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -38101,6 +52120,15 @@ "targets": [ 48010 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38114,6 +52142,12 @@ "operands": "#H'05, @H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -38136,6 +52170,13 @@ "targets": [ 48010 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38149,6 +52190,13 @@ "operands": "@H'FAA4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64164, @@ -38171,6 +52219,14 @@ "targets": [ 48035 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38184,6 +52240,13 @@ "operands": "@H'F9C3, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -38204,6 +52267,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38217,6 +52286,13 @@ "operands": "R0, @(-H'0798,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38230,6 +52306,12 @@ "operands": "#1, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38243,6 +52325,13 @@ "operands": "R1, @H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -38263,6 +52352,11 @@ "operands": "#H'06, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38278,6 +52372,13 @@ "targets": [ 48035 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38291,6 +52392,13 @@ "operands": "#H'14, @H'F9C5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63941, @@ -38311,6 +52419,13 @@ "operands": "#H'05, @H'F9C1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63937, @@ -38331,6 +52446,12 @@ "operands": "@SP+, {R0,R1}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38344,6 +52465,12 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38357,6 +52484,12 @@ "operands": "#H'06, @H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -38379,6 +52512,13 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38392,6 +52532,12 @@ "operands": "@H'F868, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63592, @@ -38412,6 +52558,12 @@ "operands": "R0, @H'F860", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63584, @@ -38432,6 +52584,12 @@ "operands": "@H'F86A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63594, @@ -38452,6 +52610,12 @@ "operands": "R0, @H'F862", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63586, @@ -38472,6 +52636,12 @@ "operands": "@H'F86C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63596, @@ -38492,6 +52662,12 @@ "operands": "R0, @H'F864", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -38512,6 +52688,12 @@ "operands": "@H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -38532,6 +52714,12 @@ "operands": "#7, @H'FAA4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64164, @@ -38554,6 +52742,14 @@ "targets": [ 48681 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38567,6 +52763,11 @@ "operands": "#H'5A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38580,6 +52781,13 @@ "operands": "@H'F860, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63584, @@ -38600,6 +52808,13 @@ "operands": "@H'F861, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -38620,6 +52835,13 @@ "operands": "@H'F862, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63586, @@ -38640,6 +52862,13 @@ "operands": "@H'F863, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63587, @@ -38660,6 +52889,13 @@ "operands": "@H'F864, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -38680,6 +52916,13 @@ "operands": "@H'F865, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63589, @@ -38702,6 +52945,13 @@ "targets": [ 48681 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38715,6 +52965,12 @@ "operands": "@H'FAA6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64166, @@ -38735,6 +52991,12 @@ "operands": "@H'F861, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -38755,6 +53017,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38768,6 +53036,12 @@ "operands": "@H'F862, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63586, @@ -38790,6 +53064,15 @@ "targets": [ 25131 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38803,6 +53086,12 @@ "operands": "R5, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38816,6 +53105,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38829,6 +53124,13 @@ "operands": "@H'F860, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63584, @@ -38849,6 +53151,12 @@ "operands": "#H'07, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38862,6 +53170,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -38884,6 +53198,14 @@ "targets": [ 48186 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38897,6 +53219,12 @@ "operands": "#7, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -38917,6 +53245,12 @@ "operands": "#7, @H'F861", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -38939,6 +53273,14 @@ "targets": [ 48395 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38952,6 +53294,11 @@ "operands": "#H'00, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38967,6 +53314,13 @@ "targets": [ 48233 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38980,6 +53334,11 @@ "operands": "#H'01, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -38995,6 +53354,13 @@ "targets": [ 48343 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39008,6 +53374,11 @@ "operands": "#H'02, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39023,6 +53394,14 @@ "targets": [ 48388 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39036,6 +53415,11 @@ "operands": "#H'07, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39051,6 +53435,13 @@ "targets": [ 48645 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39064,6 +53455,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -39086,6 +53483,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39099,6 +53505,12 @@ "operands": "#2, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39114,6 +53526,13 @@ "targets": [ 48220 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39127,6 +53546,13 @@ "operands": "#7, @H'F861", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -39149,6 +53575,13 @@ "targets": [ 48679 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39162,6 +53595,11 @@ "operands": "#H'04, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39177,6 +53615,14 @@ "targets": [ 48398 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39190,6 +53636,11 @@ "operands": "#H'05, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39205,6 +53656,13 @@ "targets": [ 48512 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39218,6 +53676,11 @@ "operands": "#H'06, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39233,6 +53696,14 @@ "targets": [ 48603 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39246,6 +53717,11 @@ "operands": "#H'07, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39261,6 +53737,13 @@ "targets": [ 48645 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39276,6 +53759,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39289,6 +53781,13 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -39311,6 +53810,13 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39324,6 +53830,12 @@ "operands": "@H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -39346,6 +53858,15 @@ "targets": [ 48149 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39359,6 +53880,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39374,6 +53901,14 @@ "targets": [ 48267 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39387,6 +53922,12 @@ "operands": "@H'F863, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63587, @@ -39407,6 +53948,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39420,6 +53967,11 @@ "operands": "#H'80, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39433,6 +53985,12 @@ "operands": "R0, @(-H'2000,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39446,6 +54004,12 @@ "operands": "R0, @(-H'1800,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39459,6 +54023,13 @@ "operands": "#H'80, @H'F864", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -39479,6 +54050,13 @@ "operands": "#7, @(-H'1400,R5)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39494,6 +54072,14 @@ "targets": [ 48752 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39509,6 +54095,15 @@ "targets": [ 48304 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39522,6 +54117,12 @@ "operands": "@H'F863, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63587, @@ -39542,6 +54143,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39555,6 +54162,12 @@ "operands": "@H'F864, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -39575,6 +54188,12 @@ "operands": "R0, @(-H'2000,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39588,6 +54207,12 @@ "operands": "R0, @(-H'1800,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39601,6 +54226,12 @@ "operands": "#7, @(-H'1400,R5)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39614,6 +54245,12 @@ "operands": "@(-H'3A9C,R4), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39627,6 +54264,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39642,6 +54285,14 @@ "targets": [ 48301 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39655,6 +54306,12 @@ "operands": "R0, @(-H'0C00,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39670,6 +54327,15 @@ "targets": [ 48752 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39683,6 +54349,13 @@ "operands": "#H'04, @H'F850", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63568, @@ -39703,6 +54376,12 @@ "operands": "@H'F861, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -39723,6 +54402,12 @@ "operands": "R0, @H'F851", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63569, @@ -39743,6 +54428,12 @@ "operands": "@H'F862, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63586, @@ -39763,6 +54454,12 @@ "operands": "R0, @H'F852", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63570, @@ -39783,6 +54480,12 @@ "operands": "@H'F864, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -39803,6 +54506,12 @@ "operands": "R0, @H'F854", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63572, @@ -39825,6 +54534,15 @@ "targets": [ 47654 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39838,6 +54556,13 @@ "operands": "#7, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -39860,6 +54585,14 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39873,6 +54606,13 @@ "operands": "#H'04, @H'F850", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63568, @@ -39893,6 +54633,13 @@ "operands": "@H'F861, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -39913,6 +54660,13 @@ "operands": "R0, @H'F851", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63569, @@ -39933,6 +54687,13 @@ "operands": "@H'F862, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63586, @@ -39953,6 +54714,13 @@ "operands": "R0, @H'F851", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63569, @@ -39973,6 +54741,13 @@ "operands": "@(-H'2000,R4), R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -39986,6 +54761,13 @@ "operands": "R0, @H'F854", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63572, @@ -40006,6 +54788,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40019,6 +54807,13 @@ "operands": "R0, @H'F853", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63571, @@ -40041,6 +54836,14 @@ "targets": [ 47654 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40054,6 +54857,12 @@ "operands": "#7, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -40076,6 +54885,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40089,6 +54907,13 @@ "operands": "#7, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -40111,6 +54936,14 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40126,6 +54959,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40139,6 +54981,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40154,6 +55002,13 @@ "targets": [ 48427 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40167,6 +55022,13 @@ "operands": "@H'F863, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63587, @@ -40187,6 +55049,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40200,6 +55068,11 @@ "operands": "#H'80, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40213,6 +55086,13 @@ "operands": "R0, @(-H'2000,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40226,6 +55106,13 @@ "operands": "R0, @(-H'1800,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40239,6 +55126,13 @@ "operands": "#7, @(-H'1400,R5)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40254,6 +55148,14 @@ "targets": [ 48752 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40269,6 +55171,15 @@ "targets": [ 48487 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40282,6 +55193,12 @@ "operands": "@H'F863, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63587, @@ -40302,6 +55219,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40315,6 +55238,12 @@ "operands": "@H'F864, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -40335,6 +55264,12 @@ "operands": "R0, @(-H'2000,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40348,6 +55283,12 @@ "operands": "#7, @(-H'1400,R5)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40361,6 +55302,12 @@ "operands": "@(-H'3A9B,R4), R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40374,6 +55321,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40389,6 +55342,14 @@ "targets": [ 48484 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40402,6 +55363,12 @@ "operands": "R0, @(-H'0C00,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40415,6 +55382,12 @@ "operands": "#7, @H'F76E", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63342, @@ -40437,6 +55410,14 @@ "targets": [ 48484 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40450,6 +55431,12 @@ "operands": "{R0,R4,R5}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 15, + "note": "6+3n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40463,6 +55450,12 @@ "operands": "@H'F76E, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63342, @@ -40483,6 +55476,12 @@ "operands": "R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40496,6 +55495,12 @@ "operands": "R1, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40509,6 +55514,12 @@ "operands": "#H'0FFE, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40522,6 +55533,12 @@ "operands": "R0, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40537,6 +55554,15 @@ "targets": [ 49120 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40550,6 +55576,12 @@ "operands": "@SP+, {R0,R4,R5}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 18, + "note": "6+4n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40565,6 +55597,14 @@ "targets": [ 48752 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40578,6 +55618,12 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -40600,6 +55646,14 @@ "targets": [ 48501 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40613,6 +55667,12 @@ "operands": "#1, @H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -40633,6 +55693,12 @@ "operands": "#7, @H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -40653,6 +55719,12 @@ "operands": "@H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -40673,6 +55745,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -40695,6 +55773,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40708,6 +55795,11 @@ "operands": "#H'006C, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40723,6 +55815,14 @@ "targets": [ 48575 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40736,6 +55836,11 @@ "operands": "#H'006D, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40751,6 +55856,13 @@ "targets": [ 48575 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40764,6 +55876,11 @@ "operands": "#H'006E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40779,6 +55896,14 @@ "targets": [ 48575 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40792,6 +55917,11 @@ "operands": "#H'006E, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40807,6 +55937,13 @@ "targets": [ 48575 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40820,6 +55957,13 @@ "operands": "#7, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -40842,6 +55986,13 @@ "targets": [ 48578 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40855,6 +56006,11 @@ "operands": "#H'006B, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40870,6 +56026,14 @@ "targets": [ 48565 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40883,6 +56047,11 @@ "operands": "#H'0096, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40898,6 +56067,13 @@ "targets": [ 48565 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40911,6 +56087,11 @@ "operands": "#H'0097, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40926,6 +56107,14 @@ "targets": [ 48565 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40939,6 +56128,11 @@ "operands": "#H'00C6, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40954,6 +56148,13 @@ "targets": [ 48565 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40967,6 +56168,11 @@ "operands": "#H'00F8, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40982,6 +56188,14 @@ "targets": [ 48565 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -40997,6 +56211,15 @@ "targets": [ 48578 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41010,6 +56233,12 @@ "operands": "#7, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -41030,6 +56259,12 @@ "operands": "#7, @H'F790", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63376, @@ -41052,6 +56287,15 @@ "targets": [ 48578 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41067,6 +56311,15 @@ "targets": [ 48752 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41080,6 +56333,13 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -41102,6 +56362,13 @@ "targets": [ 48592 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41115,6 +56382,13 @@ "operands": "#1, @H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -41135,6 +56409,13 @@ "operands": "#7, @H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -41155,6 +56436,13 @@ "operands": "@H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -41175,6 +56463,13 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -41197,6 +56492,14 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41210,6 +56513,12 @@ "operands": "@H'F863, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63587, @@ -41230,6 +56539,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41243,6 +56558,12 @@ "operands": "@H'F864, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -41263,6 +56584,12 @@ "operands": "R0, @(-H'1C00,R4)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41276,6 +56603,12 @@ "operands": "#6, @(-H'1400,R5)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41289,6 +56622,12 @@ "operands": "#3, @H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -41311,6 +56650,14 @@ "targets": [ 48635 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41324,6 +56671,12 @@ "operands": "#1, @H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -41344,6 +56697,12 @@ "operands": "#7, @H'F9B5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63925, @@ -41364,6 +56723,12 @@ "operands": "@H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -41384,6 +56749,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -41406,6 +56777,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41419,6 +56799,12 @@ "operands": "@H'F858, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63576, @@ -41439,6 +56825,12 @@ "operands": "R0, @H'F850", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63568, @@ -41459,6 +56851,12 @@ "operands": "@H'F85A, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63578, @@ -41479,6 +56877,12 @@ "operands": "R0, @H'F852", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63570, @@ -41499,6 +56903,12 @@ "operands": "@H'F85C, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63580, @@ -41519,6 +56929,12 @@ "operands": "R0, @H'F854", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63572, @@ -41539,6 +56955,13 @@ "operands": "#H'1F, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -41561,6 +56984,14 @@ "targets": [ 47654 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41576,6 +57007,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41591,6 +57031,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41604,6 +57053,12 @@ "operands": "#7, @H'FAA4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64164, @@ -41624,6 +57079,12 @@ "operands": "#7, @H'FAA5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -41646,6 +57107,14 @@ "targets": [ 48749 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41659,6 +57128,12 @@ "operands": "#1, @H'FAA6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64166, @@ -41679,6 +57154,12 @@ "operands": "#H'02, @H'FAA6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64166, @@ -41701,6 +57182,13 @@ "targets": [ 48717 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41714,6 +57202,13 @@ "operands": "#H'1F, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -41734,6 +57229,12 @@ "operands": "@H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -41754,6 +57255,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -41776,6 +57283,15 @@ "targets": [ 48749 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41789,6 +57305,13 @@ "operands": "#H'07, @H'F850", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63568, @@ -41809,6 +57332,13 @@ "operands": "@H'F861, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63585, @@ -41829,6 +57359,13 @@ "operands": "R0, @H'F851", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63569, @@ -41849,6 +57386,13 @@ "operands": "@H'F862, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63586, @@ -41869,6 +57413,13 @@ "operands": "R0, @H'F852", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63570, @@ -41889,6 +57440,13 @@ "operands": "@H'F864, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63588, @@ -41909,6 +57467,13 @@ "operands": "R0, @H'F854", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63572, @@ -41931,6 +57496,14 @@ "targets": [ 47654 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41946,6 +57519,15 @@ "targets": [ 48751 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41959,6 +57541,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -41972,6 +57563,13 @@ "operands": "@H'F9B9, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63929, @@ -41992,6 +57590,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42005,6 +57609,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42018,6 +57628,13 @@ "operands": "@H'F9B4, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -42038,6 +57655,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42051,6 +57674,12 @@ "operands": "R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42064,6 +57693,12 @@ "operands": "R3, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42079,6 +57714,13 @@ "targets": [ 48785 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42092,6 +57734,13 @@ "operands": "@(-H'0690,R3), R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42107,6 +57756,13 @@ "targets": [ 48797 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42120,6 +57776,12 @@ "operands": "#2, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42133,6 +57795,12 @@ "operands": "#H'3F, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42148,6 +57816,15 @@ "targets": [ 48768 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42161,6 +57838,12 @@ "operands": "R5, @(-H'0690,R1)", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42174,6 +57857,12 @@ "operands": "#1, @H'F9B4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -42194,6 +57883,12 @@ "operands": "#5, @H'F9B4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63924, @@ -42214,6 +57909,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42227,6 +57931,13 @@ "operands": "@H'FAA5, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64165, @@ -42247,6 +57958,12 @@ "operands": "#H'80, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42260,6 +57977,12 @@ "operands": "@H'FAA3, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -42280,6 +58003,12 @@ "operands": "R0, @H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -42302,6 +58031,14 @@ "targets": [ 48821 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42315,6 +58052,12 @@ "operands": "@H'FAA2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64162, @@ -42337,6 +58080,15 @@ "targets": [ 48872 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42350,6 +58102,12 @@ "operands": "@H'F9C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63942, @@ -42372,6 +58130,14 @@ "targets": [ 48872 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42385,6 +58151,12 @@ "operands": "@H'F9C8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63944, @@ -42407,6 +58179,14 @@ "targets": [ 48868 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42420,6 +58200,12 @@ "operands": "#-1, @H'F9C8", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63944, @@ -42440,6 +58226,12 @@ "operands": "#H'01F4, @H'F9C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63942, @@ -42460,6 +58252,12 @@ "operands": "#7, @H'FAA3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64163, @@ -42482,6 +58280,14 @@ "targets": [ 48872 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42495,6 +58301,12 @@ "operands": "@H'F9C3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63939, @@ -42517,6 +58329,15 @@ "targets": [ 47654 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42532,6 +58353,14 @@ "targets": [ 48872 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42545,6 +58374,13 @@ "operands": "@H'F9C5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63941, @@ -42565,6 +58401,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42578,6 +58422,13 @@ "operands": "#5, @FRT1_TCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65169, @@ -42598,6 +58449,13 @@ "operands": "@H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -42620,6 +58478,13 @@ "targets": [ 48888 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42633,6 +58498,13 @@ "operands": "#-1, @H'F9C0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63936, @@ -42653,6 +58525,13 @@ "operands": "@H'F9C1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63937, @@ -42675,6 +58554,13 @@ "targets": [ 48898 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42688,6 +58574,13 @@ "operands": "#-1, @H'F9C1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63937, @@ -42708,6 +58601,13 @@ "operands": "@H'F9C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63942, @@ -42730,6 +58630,13 @@ "targets": [ 48908 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42743,6 +58650,13 @@ "operands": "#-1, @H'F9C6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63942, @@ -42763,6 +58677,13 @@ "operands": "#7, @H'F6F6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63222, @@ -42785,6 +58706,13 @@ "targets": [ 48930 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42798,6 +58726,13 @@ "operands": "@H'F6F4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63220, @@ -42820,6 +58755,13 @@ "targets": [ 48926 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42833,6 +58775,13 @@ "operands": "#5, @H'F6F6", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63222, @@ -42855,6 +58804,14 @@ "targets": [ 48930 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42868,6 +58825,13 @@ "operands": "#-1, @H'F6F4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63220, @@ -42888,6 +58852,12 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42901,6 +58871,12 @@ "operands": "#5, @FRT2_TCSR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65185, @@ -42921,6 +58897,12 @@ "operands": "@H'F9C4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63940, @@ -42943,6 +58925,14 @@ "targets": [ 48945 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -42956,6 +58946,12 @@ "operands": "#-1, @H'F9C4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63940, @@ -42976,6 +58972,12 @@ "operands": "@H'F9C5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63941, @@ -42998,6 +59000,14 @@ "targets": [ 48955 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43011,6 +59021,12 @@ "operands": "#-1, @H'F9C5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63941, @@ -43031,6 +59047,12 @@ "operands": "@H'F724", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63268, @@ -43053,6 +59075,14 @@ "targets": [ 48967 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43066,6 +59096,12 @@ "operands": "#-1, @H'F724", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63268, @@ -43088,6 +59124,15 @@ "targets": [ 48976 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43101,6 +59146,13 @@ "operands": "#H'03, @H'F724", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63268, @@ -43121,6 +59173,13 @@ "operands": "@H'F723", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63267, @@ -43141,6 +59200,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -43163,6 +59229,13 @@ "targets": [ 49005 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43176,6 +59249,13 @@ "operands": "@H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -43198,6 +59278,13 @@ "targets": [ 48994 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43211,6 +59298,13 @@ "operands": "#-1, @H'FB02", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64258, @@ -43233,6 +59327,14 @@ "targets": [ 49005 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43246,6 +59348,13 @@ "operands": "#7, @H'FB03", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 64259, @@ -43266,6 +59375,12 @@ "operands": "{R0,R1,R2,R3,R4,R5}, @-SP", "kind": "normal", "targets": [], + "cycles": { + "cycles": 24, + "note": "6+3n, n=6", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43281,6 +59396,14 @@ "targets": [ 18671 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43294,6 +59417,12 @@ "operands": "@SP+, {R0,R1,R2,R3,R4,R5}", "kind": "normal", "targets": [], + "cycles": { + "cycles": 30, + "note": "6+4n, n=6", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43307,6 +59436,12 @@ "operands": "@H'F76C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63340, @@ -43329,6 +59464,14 @@ "targets": [ 49015 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43342,6 +59485,12 @@ "operands": "#-1, @H'F76C", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63340, @@ -43362,6 +59511,12 @@ "operands": "@H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -43384,6 +59539,14 @@ "targets": [ 49025 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43397,6 +59560,12 @@ "operands": "#-1, @H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -43417,6 +59586,12 @@ "operands": "@H'F726", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63270, @@ -43439,6 +59614,14 @@ "targets": [ 49059 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43452,6 +59635,12 @@ "operands": "#-1, @H'F726", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63270, @@ -43474,6 +59663,14 @@ "targets": [ 49059 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43487,6 +59684,12 @@ "operands": "#6, @H'F713", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63251, @@ -43509,6 +59712,14 @@ "targets": [ 49059 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43522,6 +59733,12 @@ "operands": "#7, @H'F711", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63249, @@ -43542,6 +59759,12 @@ "operands": "#6, @H'F711", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63249, @@ -43562,6 +59785,12 @@ "operands": "#5, @H'F711", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63249, @@ -43582,6 +59811,12 @@ "operands": "#4, @H'F711", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63249, @@ -43602,6 +59837,12 @@ "operands": "@H'F797", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63383, @@ -43624,6 +59865,14 @@ "targets": [ 49075 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43637,6 +59886,12 @@ "operands": "#-1, @H'F797", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63383, @@ -43659,6 +59914,14 @@ "targets": [ 49075 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43672,6 +59935,12 @@ "operands": "#7, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -43692,6 +59961,12 @@ "operands": "@H'F798", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63384, @@ -43714,6 +59989,14 @@ "targets": [ 49091 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43727,6 +60010,12 @@ "operands": "#-1, @H'F798", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63384, @@ -43749,6 +60038,14 @@ "targets": [ 49091 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43762,6 +60059,12 @@ "operands": "#7, @H'F731", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63281, @@ -43782,6 +60085,13 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43795,6 +60105,13 @@ "operands": "#7, @WDT_TCSR_R", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65260, @@ -43815,6 +60132,13 @@ "operands": "#H'A53F, @WDT_TCSR_R", "kind": "normal", "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65260, @@ -43835,6 +60159,13 @@ "operands": "#1, @H'F794", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63380, @@ -43855,6 +60186,13 @@ "operands": "#H'0A, @H'F794", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63380, @@ -43877,6 +60215,14 @@ "targets": [ 49119 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43890,6 +60236,12 @@ "operands": "#H'A57F, @WDT_TCSR_R", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65260, @@ -43910,6 +60262,13 @@ "operands": "", "kind": "rte", "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43923,6 +60282,13 @@ "operands": "#H'0A, @H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -43943,6 +60309,12 @@ "operands": "R5, R2", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43958,6 +60330,15 @@ "targets": [ 49168 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43973,6 +60354,15 @@ "targets": [ 49209 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -43986,6 +60376,12 @@ "operands": "R2, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44001,6 +60397,14 @@ "targets": [ 49149 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44014,6 +60418,12 @@ "operands": "@H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -44036,6 +60446,14 @@ "targets": [ 49145 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44049,6 +60467,12 @@ "operands": "R2, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44064,6 +60488,15 @@ "targets": [ 49125 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44077,6 +60510,12 @@ "operands": "#7, @H'F841", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63553, @@ -44097,6 +60536,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44110,6 +60558,13 @@ "operands": "#H'0A, @H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -44132,6 +60587,15 @@ "targets": [ 49209 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44145,6 +60609,12 @@ "operands": "@H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -44167,6 +60637,14 @@ "targets": [ 49167 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44180,6 +60658,12 @@ "operands": "#6, @H'F841", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63553, @@ -44200,6 +60684,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44215,6 +60708,14 @@ "targets": [ 49258 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44228,6 +60729,13 @@ "operands": "@H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -44250,6 +60758,13 @@ "targets": [ 49208 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44265,6 +60780,14 @@ "targets": [ 49441 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44278,6 +60801,12 @@ "operands": "R3, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44293,6 +60822,15 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44308,6 +60846,14 @@ "targets": [ 49170 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44321,6 +60867,12 @@ "operands": "R4, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44336,6 +60888,15 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44351,6 +60912,14 @@ "targets": [ 49170 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44364,6 +60933,12 @@ "operands": "R5, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44377,6 +60952,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44392,6 +60973,15 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44407,6 +60997,14 @@ "targets": [ 49170 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44420,6 +61018,12 @@ "operands": "R5, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44435,6 +61039,15 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44450,6 +61063,14 @@ "targets": [ 49170 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44465,6 +61086,15 @@ "targets": [ 49474 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44478,6 +61108,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44493,6 +61131,15 @@ "targets": [ 49258 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44506,6 +61153,12 @@ "operands": "@H'F840", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 63552, @@ -44528,6 +61181,14 @@ "targets": [ 49257 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44543,6 +61204,15 @@ "targets": [ 49441 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44556,6 +61226,12 @@ "operands": "R3, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44571,6 +61247,14 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44586,6 +61270,13 @@ "targets": [ 49211 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44599,6 +61290,12 @@ "operands": "R4, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44614,6 +61311,14 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44629,6 +61334,13 @@ "targets": [ 49211 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44644,6 +61356,14 @@ "targets": [ 49441 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44657,6 +61377,12 @@ "operands": "R3, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44670,6 +61396,12 @@ "operands": "#0, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44685,6 +61417,15 @@ "targets": [ 49291 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44700,6 +61441,14 @@ "targets": [ 49211 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44715,6 +61464,15 @@ "targets": [ 49371 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44728,6 +61486,12 @@ "operands": "R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44743,6 +61507,14 @@ "targets": [ 49420 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44758,6 +61530,15 @@ "targets": [ 49371 ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44773,6 +61554,14 @@ "targets": [ 49474 ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44786,6 +61575,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44799,6 +61597,12 @@ "operands": "#H'0FFF, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44812,6 +61616,11 @@ "operands": "#H'0800, R4", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44827,6 +61636,14 @@ "targets": [ 49278 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44840,6 +61657,12 @@ "operands": "R4, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44853,6 +61676,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44866,6 +61695,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44879,6 +61714,12 @@ "operands": "#H'A0, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44894,6 +61735,14 @@ "targets": [ 49290 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44907,6 +61756,12 @@ "operands": "R4, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44920,6 +61775,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44933,6 +61794,12 @@ "operands": "R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44946,6 +61813,12 @@ "operands": "#H'0E, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44959,6 +61832,12 @@ "operands": "#H'E0, R3", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44972,6 +61851,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44985,6 +61872,11 @@ "operands": "#H'0007, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -44998,6 +61890,12 @@ "operands": "R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45013,6 +61911,13 @@ "targets": [ 49304 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45026,6 +61931,13 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45048,6 +61960,14 @@ "targets": [ 49308 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45061,6 +61981,13 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45081,6 +62008,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45101,6 +62035,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45121,6 +62062,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45141,6 +62089,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45163,6 +62118,14 @@ "targets": [ 49294 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45176,6 +62139,13 @@ "operands": "#H'13, @P9DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65278, @@ -45196,6 +62166,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45216,6 +62193,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45236,6 +62220,13 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45258,6 +62249,13 @@ "targets": [ 49359 ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45271,6 +62269,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45291,6 +62296,13 @@ "operands": "#H'93, @P9DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65278, @@ -45311,6 +62323,11 @@ "operands": "#H'00, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45326,6 +62343,15 @@ "targets": [ 49370 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45339,6 +62365,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45359,6 +62391,13 @@ "operands": "#H'93, @P9DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65278, @@ -45379,6 +62418,11 @@ "operands": "#H'01, R0", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45392,6 +62436,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45405,6 +62457,13 @@ "operands": "#H'13, @P9DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65278, @@ -45425,6 +62484,11 @@ "operands": "#H'0007, R1", "kind": "normal", "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45438,6 +62502,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45458,6 +62528,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45478,6 +62554,12 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45500,6 +62582,14 @@ "targets": [ 49397 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45513,6 +62603,12 @@ "operands": "R1, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45528,6 +62624,15 @@ "targets": [ 49399 ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45541,6 +62646,12 @@ "operands": "R1, R5", "kind": "normal", "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45554,6 +62665,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45574,6 +62691,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45594,6 +62717,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45616,6 +62745,14 @@ "targets": [ 49379 ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45629,6 +62766,13 @@ "operands": "#H'93, @P9DDR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65278, @@ -45649,6 +62793,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45662,6 +62815,13 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45682,6 +62842,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45702,6 +62869,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45722,6 +62896,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45742,6 +62923,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45762,6 +62950,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45775,6 +62971,12 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45795,6 +62997,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45815,6 +63023,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45835,6 +63049,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45855,6 +63075,12 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45875,6 +63101,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45895,6 +63127,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45915,6 +63153,12 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45935,6 +63179,15 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true @@ -45948,6 +63201,13 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45968,6 +63228,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -45988,6 +63255,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -46008,6 +63282,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -46028,6 +63309,13 @@ "operands": "#7, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -46048,6 +63336,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -46068,6 +63363,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -46088,6 +63390,13 @@ "operands": "#1, @P9DR", "kind": "normal", "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [ { "address": 65279, @@ -46108,6 +63417,14 @@ "operands": "", "kind": "return", "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, "references": [], "comment": "", "valid": true diff --git a/h8536/cli.py b/h8536/cli.py index b72505d..a25b385 100644 --- a/h8536/cli.py +++ b/h8536/cli.py @@ -4,6 +4,7 @@ import argparse from pathlib import Path from .analysis import build_call_graph, collect_labels, linear_sweep, trace +from .cycles import annotate_cycles from .data_analysis import analyze_unreached_data from .decoder import H8536Decoder from .formatting import parse_int @@ -31,6 +32,7 @@ def main() -> int: parser.add_argument("--entry", type=parse_int, action="append", default=[], help="extra entry point to trace") parser.add_argument("--br", type=parse_int, default=None, help="optional BR value for @aa:8 short absolute operands") parser.add_argument("--linear", action="store_true", help="linear-sweep the selected range instead of tracing from vectors") + parser.add_argument("--cycles", action="store_true", help="append Appendix A cycle estimates to assembly comments") parser.add_argument("--callgraph-dot", type=Path, default=None, help="optional Graphviz DOT call graph output") args = parser.parse_args() @@ -60,6 +62,7 @@ def main() -> int: else: instructions = trace(decoder, starts, args.start, end) labels.update(collect_labels(instructions.values(), vectors)) + annotate_cycles(instructions, args.mode) data_candidates = analyze_unreached_data(rom, instructions, args.start, end) call_graph = build_call_graph(instructions, vectors, labels) @@ -75,6 +78,7 @@ def main() -> int: traced=not args.linear, dtc_vectors=dtc_vectors, data_candidates=data_candidates, + show_cycles=args.cycles, ), encoding="utf-8", ) diff --git a/h8536/cycles.py b/h8536/cycles.py new file mode 100644 index 0000000..89ec3cf --- /dev/null +++ b/h8536/cycles.py @@ -0,0 +1,376 @@ +from __future__ import annotations + +from .decoder import is_ea_byte +from .model import Instruction + + +CYCLE_SOURCE = "manual Appendix A.4, tables A-7/A-8" +CYCLE_ASSUMPTION = "on-chip instruction fetch/operand access, no external wait states" + + +def annotate_cycles(instructions: dict[int, Instruction], mode: str) -> None: + for instruction in instructions.values(): + instruction.cycles = estimate_cycles(instruction, mode) + + +def cycle_comment(cycles: dict[str, object] | None) -> str: + if not cycles: + return "" + if "cycles" in cycles: + return f"cycles={cycles['cycles']}" + if "cycles_min" in cycles and "cycles_max" in cycles: + return f"cycles={cycles['cycles_min']}-{cycles['cycles_max']}" + if "not_taken" in cycles and "taken" in cycles: + return f"cycles={cycles['not_taken']}/{cycles['taken']} nt/t" + if "trap_not_taken" in cycles: + return f"cycles={cycles['trap_not_taken']}/{cycles['trap_taken']} no-trap/trap" + if "false" in cycles: + return f"cycles={cycles['false']}/{cycles['count_minus_1']}/{cycles['taken']} false/-1/t" + return "" + + +def estimate_cycles(instruction: Instruction, mode: str) -> dict[str, object] | None: + if not instruction.valid: + return None + + if instruction.raw and is_ea_byte(instruction.raw[0]): + base = _estimate_general_cycles(instruction, mode) + else: + base = _estimate_direct_cycles(instruction, mode) + if base is None: + return None + + base.setdefault("source", CYCLE_SOURCE) + base.setdefault("assumption", CYCLE_ASSUMPTION) + return base + + +def _info( + cycles: int, + base_cycles: int | None = None, + adjustment: int = 0, + stack_adjustment: int = 0, + note: str | None = None, +) -> dict[str, object]: + info: dict[str, object] = {"cycles": cycles} + if base_cycles is not None: + info["base_cycles"] = base_cycles + if adjustment: + info["alignment_adjustment"] = adjustment + if stack_adjustment: + info["stack_adjustment"] = stack_adjustment + if note: + info["note"] = note + return info + + +def _branch_info(not_taken: int, taken: int, instruction: Instruction) -> dict[str, object]: + adjusted_taken = taken + _branch_adjust(instruction.address) + info: dict[str, object] = { + "not_taken": not_taken, + "taken": adjusted_taken, + "base_taken": taken, + } + if adjusted_taken != taken: + info["alignment_adjustment_taken"] = adjusted_taken - taken + return info + + +def _mode_min_max(mode: str, minimum: int, maximum: int) -> int: + return maximum if mode == "max" else minimum + + +def _branch_adjust(address: int) -> int: + # Table A-8(a): branch/system transfer adjustment is 0 at even starts, 1 at odd starts. + return address & 1 + + +def _ea_mode(raw: bytes) -> tuple[str, str] | None: + if not raw: + return None + b = raw[0] + if 0xA0 <= b <= 0xAF: + return "reg", "W" if b & 0x08 else "B" + if 0xB0 <= b <= 0xBF: + return "predec", "W" if b & 0x08 else "B" + if 0xC0 <= b <= 0xCF: + return "postinc", "W" if b & 0x08 else "B" + if 0xD0 <= b <= 0xDF: + return "indirect", "W" if b & 0x08 else "B" + if 0xE0 <= b <= 0xEF: + return "disp8", "W" if b & 0x08 else "B" + if 0xF0 <= b <= 0xFF: + return "disp16", "W" if b & 0x08 else "B" + if b == 0x04: + return "imm", "B" + if b == 0x0C: + return "imm", "W" + if b == 0x05: + return "abs8", "B" + if b == 0x0D: + return "abs8", "W" + if b == 0x15: + return "abs16", "B" + if b == 0x1D: + return "abs16", "W" + return None + + +def _a8_adjust(address: int, ea_mode: str, size: str, mov_imm_to_ea: bool = False) -> int: + # Table A-8(b), simplified for decoded modes used by this tool. + if mov_imm_to_ea: + if size == "B": + return 1 + even = { + "reg": 2, + "predec": 0, + "postinc": 2, + "indirect": 2, + "disp8": 2, + "disp16": 0, + "abs8": 2, + "abs16": 2, + } + odd = { + "reg": 0, + "predec": 2, + "postinc": 0, + "indirect": 0, + "disp8": 0, + "disp16": 2, + "abs8": 0, + "abs16": 0, + } + return (odd if address & 1 else even).get(ea_mode, 0) + + even_default = { + "reg": 0, + "predec": 1, + "postinc": 0, + "indirect": 1, + "disp8": 1, + "disp16": 1, + "abs8": 0, + "abs16": 1, + "imm": 0, + } + odd_default = { + "reg": 0, + "predec": 0, + "postinc": 1, + "indirect": 0, + "disp8": 0, + "disp16": 0, + "abs8": 1, + "abs16": 0, + "imm": 0, + } + return (odd_default if address & 1 else even_default).get(ea_mode, 0) + + +def _memory_read_base(ea_mode: str, size: str) -> int: + if ea_mode == "reg": + return 2 if size == "B" else 3 + if ea_mode == "imm": + return 3 if size == "B" else 4 + if ea_mode in {"disp8", "disp16", "abs16"}: + return 6 + return 5 + + +def _memory_write_base(ea_mode: str, size: str) -> int: + if ea_mode == "reg": + return 2 if size == "B" else 3 + if ea_mode in {"disp8", "disp16", "abs16"}: + return 6 + return 5 + + +def _read_modify_write_base(ea_mode: str, size: str) -> int: + if ea_mode == "reg": + return 2 if size == "B" else 3 + if ea_mode in {"disp8", "disp16", "abs16"}: + return 8 + return 7 + + +def _imm_to_ea_base(ea_mode: str, size: str) -> int: + if ea_mode == "reg": + return 2 if size == "B" else 3 + if ea_mode in {"disp8", "disp16", "abs16"}: + return 8 if size == "B" else 9 + return 7 if size == "B" else 8 + + +def _estimate_general_cycles(instruction: Instruction, mode: str) -> dict[str, object] | None: + parsed = _ea_mode(instruction.raw) + if parsed is None or len(instruction.raw) < 2: + return None + ea_mode, ea_size = parsed + mnemonic = instruction.mnemonic + op = instruction.raw[1 + (1 if ea_mode in {"imm", "abs8"} else 2 if ea_mode == "abs16" else 0)] + if ea_mode in {"disp8"}: + op = instruction.raw[2] + elif ea_mode == "disp16": + op = instruction.raw[3] + + mov_imm_to_ea = mnemonic.startswith("MOV:G") and instruction.operands.startswith("#") + adjustment = _a8_adjust(instruction.address, ea_mode, ea_size, mov_imm_to_ea) + + if mnemonic.startswith(("ADD:G", "ADDS", "SUB", "SUBS", "ADDX", "SUBX", "AND.", "OR.", "XOR.", "CMP:G")): + base = _memory_read_base(ea_mode, ea_size) + elif mnemonic.startswith("MOV:G"): + base = _imm_to_ea_base(ea_mode, ea_size) if mov_imm_to_ea else _memory_write_base(ea_mode, ea_size) + elif mnemonic.startswith(("BTST", "TST")): + base = _memory_read_base(ea_mode, ea_size) + elif mnemonic.startswith(("BSET", "BCLR", "BNOT", "CLR", "NEG", "NOT", "SHAL", "SHAR", "SHLL", "SHLR", "ROTL", "ROTR", "ROTXL", "ROTXR", "TAS")): + base = _read_modify_write_base(ea_mode, ea_size) + elif mnemonic.startswith("ADD:Q"): + base = 4 if ea_mode == "reg" else _read_modify_write_base(ea_mode, ea_size) + elif mnemonic.startswith("MULXU.B"): + base = 18 if ea_mode == "reg" else 19 + elif mnemonic.startswith("MULXU.W"): + base = 25 + elif mnemonic.startswith("DIVXU.B"): + base = 21 if ea_mode == "reg" else 23 + elif mnemonic.startswith("DIVXU.W"): + base = 28 if ea_mode == "reg" else 29 + elif mnemonic.startswith(("LDC.B", "STC.B")): + base = 4 if ea_mode in {"reg", "imm"} else 6 if ea_mode in {"abs8", "indirect", "predec", "postinc"} else 7 + elif mnemonic.startswith(("LDC.W", "STC.W")): + base = 6 if ea_mode in {"reg", "imm"} else 7 if ea_mode in {"abs8", "indirect", "predec", "postinc"} else 8 + elif mnemonic.startswith(("ORC", "ANDC", "XORC")): + base = 4 + adjustment = 0 + elif mnemonic.startswith(("EXTS", "EXTU", "SWAP")): + base = 3 + adjustment = 0 + elif mnemonic.startswith(("MOVFPE", "MOVTPE")): + cycles = _mode_min_max(mode, 13, 20) + return _info(cycles, note="E-clock peripheral transfer") + else: + return None + + return _info(base + adjustment, base, adjustment) + + +def _estimate_direct_cycles(instruction: Instruction, mode: str) -> dict[str, object] | None: + raw = instruction.raw + mnemonic = instruction.mnemonic + if not raw: + return None + op = raw[0] + + if mnemonic.startswith("B") and 0x20 <= op <= 0x3F: + info = _branch_info(3, 7, instruction) + if mnemonic == "BRA": + info["cycles"] = info["taken"] + elif mnemonic == "BRN": + info["cycles"] = info["not_taken"] + return info + if mnemonic.startswith("SCB/"): + taken = 8 + _branch_adjust(instruction.address) + return { + "false": 3, + "count_minus_1": 4, + "taken": taken, + "base_taken": 8, + } + if mnemonic == "BSR": + base = 9 + adjust = _branch_adjust(instruction.address) + stack = 4 + return _info(base + stack + adjust, base, adjust, stack, "PC word push to stack") + if mnemonic == "JMP": + if op == 0x10: + base = 7 + elif len(raw) >= 2 and raw[0] == 0x11 and 0xD0 <= raw[1] <= 0xD7: + base = 6 + elif len(raw) >= 2 and raw[0] == 0x11 and 0xE0 <= raw[1] <= 0xE7: + base = 7 + elif len(raw) >= 2 and raw[0] == 0x11 and 0xF0 <= raw[1] <= 0xF7: + base = 8 + else: + return None + adjust = _branch_adjust(instruction.address) + return _info(base + adjust, base, adjust) + if mnemonic == "JSR": + if op == 0x18: + base = 9 + elif len(raw) >= 2 and raw[0] == 0x11 and 0xD8 <= raw[1] <= 0xDF: + base = 9 + elif len(raw) >= 2 and raw[0] == 0x11 and 0xE8 <= raw[1] <= 0xEF: + base = 9 + elif len(raw) >= 2 and raw[0] == 0x11 and 0xF8 <= raw[1] <= 0xFF: + base = 10 + else: + return None + adjust = _branch_adjust(instruction.address) + stack = 4 + return _info(base + stack + adjust, base, adjust, stack, "PC word push to stack") + if mnemonic == "PJMP": + base = 9 if op == 0x13 else 8 + adjust = _branch_adjust(instruction.address) + return _info(base + adjust, base, adjust) + if mnemonic == "PJSR": + base = 15 if op == 0x03 else 13 + adjust = _branch_adjust(instruction.address) + stack = 6 if mode == "max" else 4 + return _info(base + stack + adjust, base, adjust, stack, "return address push to stack") + if mnemonic == "TRAPA": + return _info(_mode_min_max(mode, 17, 22)) + if mnemonic == "TRAP/VS": + return { + "trap_not_taken": 3, + "trap_taken": _mode_min_max(mode, 18, 23) + _branch_adjust(instruction.address), + "base_trap_taken": _mode_min_max(mode, 18, 23), + } + if mnemonic == "RTE": + base = _mode_min_max(mode, 13, 15) + adjust = _branch_adjust(instruction.address) + return _info(base + adjust, base, adjust) + if mnemonic == "RTS": + base = 8 + adjust = _branch_adjust(instruction.address) + stack = 4 + return _info(base + stack + adjust, base, adjust, stack, "PC word pop from stack") + if mnemonic == "RTD": + base = 9 + adjust = _branch_adjust(instruction.address) + stack = 4 + return _info(base + stack + adjust, base, adjust, stack, "PC word pop from stack") + if mnemonic == "PRTS": + base = 12 + adjust = _branch_adjust(instruction.address) + stack = 6 if mode == "max" else 4 + return _info(base + stack + adjust, base, adjust, stack, "return address pop from stack") + if mnemonic == "PRTD": + base = 13 + adjust = _branch_adjust(instruction.address) + stack = 6 if mode == "max" else 4 + return _info(base + stack + adjust, base, adjust, stack, "return address pop from stack") + if mnemonic == "UNLK": + return _info(5) + if mnemonic == "LINK": + return _info(6 if len(raw) == 2 else 7) + if mnemonic == "LDM.W": + n = raw[1].bit_count() + cycles = 6 + 4 * n + return _info(cycles, note=f"6+4n, n={n}") + if mnemonic == "STM.W": + n = raw[1].bit_count() + cycles = 6 + 3 * n + return _info(cycles, note=f"6+3n, n={n}") + if mnemonic in {"NOP", "SLEEP"}: + return _info(2) + if mnemonic.startswith("CMP:E"): + return _info(2) + if mnemonic.startswith("CMP:I"): + return _info(3) + if mnemonic.startswith("MOV:E"): + return _info(2) + if mnemonic.startswith("MOV:I"): + return _info(3) + if mnemonic.startswith(("MOV:L", "MOV:S", "MOV:F")): + return _info(5) + return None diff --git a/h8536/model.py b/h8536/model.py index a0ea759..43bb101 100644 --- a/h8536/model.py +++ b/h8536/model.py @@ -28,6 +28,7 @@ class Instruction: references: list[int] = field(default_factory=list) writes_br: bool = False br_value: int | None = None + cycles: dict[str, object] | None = None @property def size(self) -> int: diff --git a/h8536/render.py b/h8536/render.py index cd82f86..67fefa5 100644 --- a/h8536/render.py +++ b/h8536/render.py @@ -3,6 +3,7 @@ from __future__ import annotations import json from pathlib import Path +from .cycles import cycle_comment from .formatting import h16, label_for from .memory import MEMORY_REGIONS, region_for from .model import Instruction @@ -30,6 +31,7 @@ def format_listing( traced: bool, dtc_vectors: dict[int, DtcVectorEntry] | None = None, data_candidates: dict[str, list[dict[str, object]]] | None = None, + show_cycles: bool = False, ) -> str: lines: list[str] = [] lines.append("; H8/536 ROM disassembly") @@ -43,6 +45,8 @@ def format_listing( lines.append("; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC.") lines.append("; - The register field is H'FE80-H'FFFF; names below come from appendix B.") lines.append("; - @aa:8 short absolute operands use BR as the upper address byte.") + if show_cycles: + lines.append("; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states.") lines.append("") lines.append("; Memory Map") for region in MEMORY_REGIONS: @@ -84,7 +88,15 @@ def format_listing( lines.append(f"{labels[address]}:") raw = " ".join(f"{byte:02X}" for byte in ins.raw) padded_raw = raw.ljust(14) - comment_parts = [part for part in (ins.comment, _reference_comment(ins) if not ins.comment else "") if part] + comment_parts = [ + part + for part in ( + ins.comment, + _reference_comment(ins) if not ins.comment else "", + cycle_comment(ins.cycles) if show_cycles else "", + ) + if part + ] comment = f" ; {'; '.join(comment_parts)}" if comment_parts else "" lines.append(f"{address:04X}: {padded_raw} {ins.text}{comment}") lines.append("") @@ -128,6 +140,7 @@ def write_json( "operands": ins.operands, "kind": ins.kind, "targets": ins.targets, + "cycles": ins.cycles, "references": [ { "address": address, diff --git a/tests/test_cycles_manual_examples.py b/tests/test_cycles_manual_examples.py new file mode 100644 index 0000000..15ae969 --- /dev/null +++ b/tests/test_cycles_manual_examples.py @@ -0,0 +1,48 @@ +import unittest + +from h8536.cycles import estimate_cycles +from h8536.decoder import H8536Decoder +from h8536.rom import Rom + + +def decode_at(data: list[int], address: int = 0): + return H8536Decoder(Rom(bytes(data), base=address)).decode(address) + + +class ManualCycleExamplesTest(unittest.TestCase): + def test_add_word_register_indirect_matches_manual_even_and_odd_examples(self): + even = decode_at([0xD8, 0x21], 0x0100) + odd = decode_at([0xD8, 0x21], 0x0101) + + self.assertEqual(even.text, "ADD:G.W @R0, R1") + self.assertEqual(estimate_cycles(even, "min")["cycles"], 6) + self.assertEqual(estimate_cycles(even, "min")["base_cycles"], 5) + self.assertEqual(estimate_cycles(even, "min")["alignment_adjustment"], 1) + + self.assertEqual(odd.text, "ADD:G.W @R0, R1") + self.assertEqual(estimate_cycles(odd, "min")["cycles"], 5) + self.assertEqual(estimate_cycles(odd, "min")["base_cycles"], 5) + + def test_jsr_register_indirect_matches_manual_stack_adjusted_example(self): + even = decode_at([0x11, 0xD8], 0xFC00) + odd = decode_at([0x11, 0xD8], 0xFC01) + + self.assertEqual(even.text, "JSR @R0") + self.assertEqual(estimate_cycles(even, "min")["cycles"], 13) + self.assertEqual(estimate_cycles(even, "min")["base_cycles"], 9) + self.assertEqual(estimate_cycles(even, "min")["stack_adjustment"], 4) + + self.assertEqual(odd.text, "JSR @R0") + self.assertEqual(estimate_cycles(odd, "min")["cycles"], 14) + self.assertEqual(estimate_cycles(odd, "min")["alignment_adjustment"], 1) + + def test_conditional_branch_keeps_taken_and_not_taken_counts(self): + instruction = decode_at([0x26, 0x02], 0x0000) + cycles = estimate_cycles(instruction, "min") + + self.assertEqual(cycles["not_taken"], 3) + self.assertEqual(cycles["taken"], 7) + + +if __name__ == "__main__": + unittest.main()