LCD emulation
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Aiden
@@ -82,9 +82,9 @@ To start the current emulator harness:
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- Handles the E-clock transfer instructions `MOVFPE` and `MOVTPE`.
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- Recognizes likely LCD E-clock access routines at `H'F200`/`H'F201`, including busy-flag polling and data/control writes.
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- Generates a separate C-like pseudocode view from the JSON, preserving labels, calls, branches, register names, inferred symbols, metadata comments, optional cycle notes, and simple structured `if`/`do while` patterns.
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- Provides an early H8/536 emulator harness with ROM/RAM/register memory mapping, reset-vector boot, SCI1 transmit capture, MOV condition-code updates, `SCB/F`, stack/call/return support, indirect `JMP/JSR @Rn` dispatch, scaffolded SCI1 RXI/ERI/TXI and interval/FRT1-OCIA/FRT2-OCIA interrupt scheduling, a P9 bit-banged bus model, and an opt-in P9 transfer fast path.
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- Provides an early H8/536 emulator harness with ROM/RAM/register memory mapping, reset-vector boot, SCI1 transmit capture, MOV condition-code updates, `SCB/F`, stack/call/return support, indirect `JMP/JSR @Rn` dispatch, scaffolded SCI1 RXI/ERI/TXI and interval/FRT1-OCIA/FRT2-OCIA interrupt scheduling, a P9 bit-banged bus model, a 16x4 LCD bus/DDRAM model for `H'F200`/`H'F201`, and an opt-in P9 transfer fast path.
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- Includes an emulator probe that reports hot PCs, recent P9/SCI accesses, serial report queue/gate traces, RAM lifecycle watches, final SCI1/TXI state, and captured P9 byte candidates while running the real ROM.
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- Includes an RX command probe that boots until SCI1 RXI is serviceable, injects host six-byte frames through RDR/RDRF, listens for device TX frames, and reports serial latch/table/LCD-buffer effects.
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- Includes an RX command probe that boots until SCI1 RXI is serviceable, injects host six-byte frames through RDR/RDRF, listens for device TX frames, and reports serial latch/table/LCD-buffer and emulated-LCD effects.
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Current serial observations:
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@@ -94,6 +94,7 @@ Current serial observations:
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- Idle cadence from the reference file: 54 frames, average about 699.9 ms, min 601 ms, max 803 ms.
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- Static/runtime finding: `F9C4` is a candidate idle heartbeat/report countdown. Init loads `H'14`, `loc_BA26` reloads `H'07` after a send, FRT2 OCIA decrements it, and `loc_4046` can enqueue report `H'0000` when it reaches zero and the queue is empty.
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- Runtime-confirmed heartbeat path: `loc_4067` writes `H'0000` into the queue via a zero-extended word move, `loc_BAF2/loc_BB08` dequeue it, `loc_BB1C/loc_BB20/loc_BB2B` stage the TX bytes, and `loc_BA26` emits `00 00 00 00 80 DA`.
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- Emulator LCD finding: the ROM writes the boot/no-active-session message to the LCD bus as ` CONNECT:NOT ACT` on line 0 by the time SCI1 RX is serviceable. Valid and invalid six-byte host frames leave that display active while normal serial replies/heartbeats continue.
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- RX probe finding: the `--preset connect-lcd` sequence reaches the command-`0x04` handler; `04 00 00 80 00 DE` writes table index zero, fills the LCD line buffer with `CONNECT: OK`, and emits `02 00 02 00 00 5A` in the current emulator model.
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- Observed capture labels such as `cam_power_button_candidate` and `call_button_candidate` are deliberately treated as capture overlays, not protocol facts hard-coded in ROM.
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@@ -207,7 +208,7 @@ python h8536_emulator_rx_probe.py --help
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- `--target-frame "00 00 00 00 80 DA"`: compare staged/emitted TX bytes against an expected six-byte frame.
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- `h8536_emulator_rx_probe.py "04 00 00 80 00"`: append the checksum, inject the host frame through SCI1 RX, and summarize responses.
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- `h8536_emulator_rx_probe.py --preset connect-lcd`: replay the current CONNECT LCD activation candidates.
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- Current status: boots from `H'1000`, initializes SCI1, models the first P9 bit-banged handshakes, captures P9 byte candidates, can optionally fast-path known P9 routines, and schedules FRT1/FRT2 OCIA. With the P9 fast path and current timer cadence, the emulator reaches the SCI1 transmit path and emits the observed heartbeat frame `00 00 00 00 80 DA`.
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- Current status: boots from `H'1000`, initializes SCI1, models the first P9 bit-banged handshakes, captures P9 byte candidates, can optionally fast-path known P9 routines, schedules FRT1/FRT2 OCIA, captures the ROM-driven LCD line ` CONNECT:NOT ACT`, and emits the observed heartbeat frame `00 00 00 00 80 DA`.
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## Code Layout
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@@ -238,7 +239,7 @@ python h8536_emulator_rx_probe.py --help
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- `h8536/report_source_trace.py`: direct `loc_3E54` report enqueue source tracer.
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- `h8536/table_xrefs.py`: table/index xrefs and LCD correlation report generation.
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- `h8536/consistency.py`: decompiler/pseudocode semantic consistency checks.
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- `h8536/emulator/`: early H8/536 emulator package split into CPU state, memory map, SCI1 TX capture, P9 bus model, runner, probe, CLI, and peripheral scaffolding.
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- `h8536/emulator/`: early H8/536 emulator package split into CPU state, memory map, SCI1 TX capture, P9 bus model, LCD model, runner, probe, CLI, and peripheral scaffolding.
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- `h8536/emulator/rx_probe.py`: host-frame injection and response/listener probe for SCI1 RX experiments.
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- `h8536/board_profile.py`: Sony RCP-TX7 board-trace annotations, including the MAX202 RS232 path.
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- `h8536/peripheral_access.py`: FRT/A-D TEMP-register access analysis.
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@@ -46,6 +46,7 @@ from .cpu import CPUState
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from .errors import EmulatorError, UnsupportedInstruction
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from .fast_paths import P9FastPath, P9FastPathConfig, P9FastPathEvent
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from .memory import MemoryAccess, MemoryMap, describe_regions
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from .peripherals import LCD
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from .runner import H8536Emulator, RunReport
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from .sci import SCI1, SciTxEvent
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@@ -63,6 +64,7 @@ __all__ = [
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"IPRA",
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"IPRC",
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"IPRE",
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"LCD",
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"MemoryAccess",
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"MemoryMap",
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"ON_CHIP_RAM_END",
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@@ -20,7 +20,7 @@ from .constants import (
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SCI1_SSR,
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SCI1_TDR,
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)
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from .peripherals.lcd import LCD_E_CLOCK_DATA, LCD_E_CLOCK_STATUS
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from .peripherals.lcd import LCD, LCD_E_CLOCK_DATA, LCD_E_CLOCK_STATUS
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from .peripherals.p9_bus import P9Bus
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from .sci import SCI1
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@@ -38,6 +38,7 @@ class MemoryMap:
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def __init__(self, rom_bytes: bytes, sci1: SCI1 | None = None) -> None:
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self.rom = Rom(rom_bytes, base=0)
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self.sci1 = sci1 if sci1 is not None else SCI1()
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self.lcd = LCD()
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self.p9_bus = P9Bus()
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self.ram = bytearray(ON_CHIP_RAM_END - ON_CHIP_RAM_START + 1)
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self.registers = bytearray(REGISTER_FIELD_END - REGISTER_FIELD_START + 1)
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@@ -60,11 +61,9 @@ class MemoryMap:
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value = self.sci1.read(address)
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self._set_register(address, value)
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elif address == LCD_E_CLOCK_STATUS:
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# LCD E-clock/status space. Default to ready/zero so boot can pass
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# busy-flag polling until a fuller external bus model exists.
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value = 0x00
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value = self.lcd.read_status()
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elif address == LCD_E_CLOCK_DATA:
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value = self.external.get(address, 0x00)
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value = self.lcd.read_data()
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elif address in self.external:
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value = self.external[address]
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elif ON_CHIP_RAM_START <= address <= ON_CHIP_RAM_END:
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@@ -94,6 +93,12 @@ class MemoryMap:
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if address in (SCI1_SMR, SCI1_BRR, SCI1_SCR, SCI1_TDR, SCI1_SSR, SCI1_RDR):
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self.sci1.write(address, value)
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self._set_register(address, self.sci1.read(address))
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elif address == LCD_E_CLOCK_STATUS:
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self.lcd.write_command(value)
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self.external[address] = value
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elif address == LCD_E_CLOCK_DATA:
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self.lcd.write_data(value)
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self.external[address] = value
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elif ON_CHIP_RAM_START <= address <= ON_CHIP_RAM_END:
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self.ram[address - ON_CHIP_RAM_START] = value
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elif address == P9DDR:
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@@ -1,11 +1,13 @@
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from __future__ import annotations
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from .lcd import LCD_E_CLOCK_DATA, LCD_E_CLOCK_STATUS
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from .lcd import LCD, LCD_E_CLOCK_DATA, LCD_E_CLOCK_STATUS, LCD_LINE_WIDTH
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from .p9_bus import P9_ACK_BIT, P9_STROBE_BIT, P9Bus, P9StrobeEvent
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__all__ = [
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"LCD_E_CLOCK_DATA",
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"LCD_E_CLOCK_STATUS",
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"LCD",
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"LCD_LINE_WIDTH",
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"P9_ACK_BIT",
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"P9_STROBE_BIT",
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"P9Bus",
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@@ -1,5 +1,69 @@
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from __future__ import annotations
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from dataclasses import dataclass, field
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LCD_E_CLOCK_STATUS = 0xF200
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LCD_E_CLOCK_DATA = 0xF201
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LCD_LINE_WIDTH = 16
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LCD_LINE_STARTS = (0x00, 0x40, 0x10, 0x50)
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LCD_DDRAM_SIZE = 0x80
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@dataclass
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class LCD:
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ddram: bytearray = field(default_factory=lambda: bytearray([0x20] * LCD_DDRAM_SIZE))
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cursor: int = 0
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data_latch: int = 0
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command_latch: int = 0
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def read_status(self) -> int:
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return self.cursor & 0x7F
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def read_data(self) -> int:
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return self.data_latch & 0xFF
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def write_command(self, value: int) -> None:
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value &= 0xFF
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self.command_latch = value
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if value & 0x80:
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self.cursor = value & 0x7F
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elif value == 0x01:
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self.ddram[:] = bytes([0x20]) * LCD_DDRAM_SIZE
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self.cursor = 0
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elif value == 0x02:
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self.cursor = 0
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def write_data(self, value: int) -> None:
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value &= 0xFF
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self.data_latch = value
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if 0 <= self.cursor < LCD_DDRAM_SIZE:
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self.ddram[self.cursor] = value
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self.cursor = (self.cursor + 1) & 0x7F
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def line_text(self, line: int, width: int = LCD_LINE_WIDTH) -> str:
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if not 0 <= line < len(LCD_LINE_STARTS):
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raise ValueError(f"LCD line out of range: {line}")
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start = LCD_LINE_STARTS[line]
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return "".join(_display_char(self.ddram[(start + offset) & 0x7F]) for offset in range(width))
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def display_lines(self, lines: int = 4, width: int = LCD_LINE_WIDTH) -> list[str]:
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return [self.line_text(line, width) for line in range(lines)]
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def display_text(self, lines: int = 4, width: int = LCD_LINE_WIDTH) -> str:
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return " | ".join(self.display_lines(lines, width))
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def _display_char(value: int) -> str:
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return chr(value) if 0x20 <= value <= 0x7E else "."
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__all__ = [
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"LCD",
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"LCD_DDRAM_SIZE",
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"LCD_E_CLOCK_DATA",
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"LCD_E_CLOCK_STATUS",
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"LCD_LINE_STARTS",
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"LCD_LINE_WIDTH",
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]
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@@ -139,6 +139,9 @@ class FrameResult:
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lines.append(" new_tx_frames=" + " | ".join(format_frame(frame) for frame in self.new_tx_frames))
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else:
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lines.append(" new_tx_frames=none")
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lcd_display = self.state_after.get("lcd_display_ascii")
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if isinstance(lcd_display, str):
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lines.append(f" lcd_display={lcd_display!r}")
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state_changes = _state_change_lines(self.state_before, self.state_after)
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if state_changes:
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lines.append(" state_changes:")
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@@ -220,7 +223,8 @@ def run_rx_probe(
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boot_summary = (
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f"boot={boot_reason} steps={boot_steps_used} pc={h16(emulator.cpu.pc)} "
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f"SCR={emulator.sci1.scr:02X} SSR={emulator.sci1.ssr:02X} "
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f"rx_serviceable={int(_rx_ready(emulator))}"
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f"rx_serviceable={int(_rx_ready(emulator))} "
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f"lcd_display={emulator.memory.lcd.display_text(lines=4)!r}"
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)
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results = [
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@@ -380,6 +384,7 @@ def _state_snapshot(emulator: H8536Emulator) -> dict[str, int | str]:
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for address, name in STATE_WORDS.items():
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snapshot[name] = emulator.memory.read16(address)
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snapshot["lcd_line_buffer_ascii"] = _ascii_window(emulator, 0xFAF0, 16)
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snapshot["lcd_display_ascii"] = emulator.memory.lcd.display_text(lines=4, width=16)
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snapshot["tx_frame_staging"] = format_frame(bytes(emulator.memory.read8(0xF850 + offset) for offset in range(6)))
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snapshot["rx_frame_validation"] = format_frame(bytes(emulator.memory.read8(0xF860 + offset) for offset in range(6)))
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return snapshot
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@@ -20,6 +20,29 @@ class EmulatorLcdBusTest(unittest.TestCase):
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self.assertEqual(memory.read8(LCD_E_CLOCK_DATA), 0x41)
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def test_command_sets_ddram_cursor_and_data_updates_display_text(self):
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memory = MemoryMap(b"\x00" * 4)
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memory.write8(LCD_E_CLOCK_STATUS, 0x80)
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for value in b"CONNECT: NOT ACT":
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memory.write8(LCD_E_CLOCK_DATA, value)
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self.assertEqual(memory.lcd.line_text(0), "CONNECT: NOT ACT")
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def test_rom_line_mapping_matches_16x4_lcd_addresses(self):
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memory = MemoryMap(b"\x00" * 4)
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memory.write8(LCD_E_CLOCK_STATUS, 0xC0)
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memory.write8(LCD_E_CLOCK_DATA, ord("1"))
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memory.write8(LCD_E_CLOCK_STATUS, 0x90)
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memory.write8(LCD_E_CLOCK_DATA, ord("2"))
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memory.write8(LCD_E_CLOCK_STATUS, 0xD0)
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memory.write8(LCD_E_CLOCK_DATA, ord("3"))
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self.assertTrue(memory.lcd.line_text(1).startswith("1"))
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self.assertTrue(memory.lcd.line_text(2).startswith("2"))
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self.assertTrue(memory.lcd.line_text(3).startswith("3"))
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if __name__ == "__main__":
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unittest.main()
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