Stage 1 rewrite

docs/PHASE_7_6_SYSTEM_MEMORY_PLAYOUT_BUFFER_DESIGN.md

@@ -4,6 +4,11 @@
 
 In progress.
 
+Follow-up direction:
+
+- Phase 7.6 proved the BGRA8 system-memory path and exposed the need for a larger cadence/scheduler split.
+- Continue the broader rewrite in [PHASE_7_7_RENDER_CADENCE_PLAYOUT_DESIGN.md](/c:/Users/Aiden/Documents/GitHub/video-shader-toys/docs/PHASE_7_7_RENDER_CADENCE_PLAYOUT_DESIGN.md).
+
 Implemented so far:
 
 - BGRA8 `SystemOutputFramePool` with non-GL tests