127 lines
4.6 KiB
Python
127 lines
4.6 KiB
Python
import unittest
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from h8536.pseudocode import PseudocodeOptions, generate_pseudocode, split_operands
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class PseudocodeTest(unittest.TestCase):
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def test_split_operands_keeps_displacement_expression_together(self):
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self.assertEqual(split_operands("@(H'04,R6), R0"), ["@(H'04,R6)", "R0"])
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self.assertEqual(split_operands("{R0,R1}, @-SP"), ["{R0,R1}", "@-SP"])
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def test_generates_c_like_function_from_decompiler_json(self):
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payload = {
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"vectors": [{"address": 0, "name": "reset", "target": 0x0100, "target_label": "vec_reset_0100"}],
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"call_graph": {
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"nodes": [
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{
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"start": 0x0100,
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"end": 0x0110,
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"label": "vec_reset_0100",
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"sources": ["reset"],
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"instruction_count": 5,
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"calls": [0x0200],
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},
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{
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"start": 0x0200,
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"end": 0x0200,
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"label": "loc_0200",
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"sources": [],
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"instruction_count": 1,
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"calls": [],
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},
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],
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"edges": [],
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},
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"instructions": [
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{
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"address": 0x0100,
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"text": "MOV:G.B #H'FF, @P1DDR",
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"mnemonic": "MOV:G.B",
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"operands": "#H'FF, @P1DDR",
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"kind": "normal",
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"targets": [],
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"references": [{"address": 0xFE80, "name": "P1DDR", "region": "register_field"}],
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"comment": "P1DDR = H'FF",
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"peripheral_access": [
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{
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"register": "FRT2_FRC",
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"direction": "write",
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"size": "W",
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"byte": "high",
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},
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],
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},
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{
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"address": 0x0105,
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"text": "MOV:G.B #H'80, @RAMCR",
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"mnemonic": "MOV:G.B",
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"operands": "#H'80, @RAMCR",
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"kind": "normal",
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"targets": [],
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"references": [{"address": 0xFF11, "name": "RAMCR", "region": "register_field"}],
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"comment": "RAMCR = H'80",
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"sci": {
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"inferences": [
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{"comment": "SCI1 async baud 31250 bps"},
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],
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},
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},
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{
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"address": 0x010A,
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"text": "BNE loc_0110",
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"mnemonic": "BNE",
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"operands": "loc_0110",
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"kind": "branch",
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"targets": [0x0110],
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"references": [],
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"comment": "",
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},
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{
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"address": 0x010C,
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"text": "BSR loc_0200",
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"mnemonic": "BSR",
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"operands": "loc_0200",
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"kind": "call",
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"targets": [0x0200],
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"references": [],
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"comment": "",
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},
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{
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"address": 0x0110,
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"text": "RTS",
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"mnemonic": "RTS",
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"operands": "",
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"kind": "return",
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"targets": [],
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"references": [],
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"comment": "",
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},
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{
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"address": 0x0200,
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"text": "RTS",
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"mnemonic": "RTS",
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"operands": "",
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"kind": "return",
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"targets": [],
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"references": [],
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"comment": "",
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},
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],
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}
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text = generate_pseudocode(payload, options=PseudocodeOptions())
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self.assertIn("void vec_reset_0100(void)", text)
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self.assertIn("P1DDR = (uint8_t)(0xFF);", text)
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self.assertIn("RAMCR = (uint8_t)(0x80);", text)
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self.assertIn("SCI1 async baud 31250 bps", text)
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self.assertIn("FRT2_FRC W write high TEMP access", text)
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self.assertIn("if (!Z) goto loc_0110;", text)
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self.assertIn("loc_0200();", text)
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self.assertIn("loc_0110:", text)
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self.assertIn("return;", text)
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if __name__ == "__main__":
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unittest.main()
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