2590 lines
63 KiB
JSON
2590 lines
63 KiB
JSON
{
|
|
"vectors": [
|
|
{
|
|
"address": 0,
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|
"name": "reset",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 4,
|
|
"name": "invalid_instruction",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 6,
|
|
"name": "zero_divide",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
|
|
{
|
|
"address": 8,
|
|
"name": "trap_vs",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 16,
|
|
"name": "address_error",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 18,
|
|
"name": "trace",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 22,
|
|
"name": "nmi",
|
|
"target": 17299,
|
|
"target_label": "vec_nmi_4393"
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|
},
|
|
{
|
|
"address": 32,
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|
"name": "trapa_0",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 34,
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|
"name": "trapa_1",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 36,
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|
"name": "trapa_2",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 38,
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|
"name": "trapa_3",
|
|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 40,
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|
"name": "trapa_4",
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|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 42,
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|
"name": "trapa_5",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 44,
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|
"name": "trapa_6",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 46,
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|
"name": "trapa_7",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 48,
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|
"name": "trapa_8",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 50,
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|
"name": "trapa_9",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
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|
"address": 52,
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|
"name": "trapa_a",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 54,
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|
"name": "trapa_b",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 56,
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|
"name": "trapa_c",
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|
"target": 4096,
|
|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 58,
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|
"name": "trapa_d",
|
|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 60,
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|
"name": "trapa_e",
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"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
|
|
"address": 62,
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|
"name": "trapa_f",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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},
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|
{
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"address": 64,
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"name": "irq0",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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},
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{
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"address": 66,
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"name": "interval_timer",
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|
"target": 49092,
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"target_label": "vec_interval_timer_BFC4"
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},
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{
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|
"address": 72,
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|
"name": "irq1",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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},
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{
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|
"address": 80,
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|
"name": "irq2",
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|
"target": 4096,
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"target_label": "vec_reset_1000"
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},
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{
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"address": 82,
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|
"name": "irq3",
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"target": 15408,
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"target_label": "vec_irq3_3C30"
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},
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{
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"address": 88,
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"name": "irq4",
|
|
"target": 15047,
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"target_label": "vec_irq4_3AC7"
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},
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|
{
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"address": 90,
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|
"name": "irq5",
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|
"target": 4096,
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|
"target_label": "vec_reset_1000"
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|
},
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|
{
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|
"address": 98,
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|
"name": "frt1_ocia",
|
|
"target": 48874,
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|
"target_label": "vec_frt1_ocia_BEEA"
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|
},
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|
{
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"address": 106,
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|
"name": "frt2_ocia",
|
|
"target": 48931,
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|
"target_label": "vec_frt2_ocia_BF23"
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|
},
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|
{
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|
"address": 128,
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|
"name": "sci1_eri",
|
|
"target": 47959,
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|
"target_label": "vec_sci1_eri_BB57"
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},
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|
{
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|
"address": 130,
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|
"name": "sci1_rxi",
|
|
"target": 47975,
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"target_label": "vec_sci1_rxi_BB67"
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},
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{
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"address": 132,
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"name": "sci1_txi",
|
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"target": 47748,
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"target_label": "vec_sci1_txi_BA84"
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},
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|
{
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|
"address": 144,
|
|
"name": "ad_adi",
|
|
"target": 15769,
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"target_label": "vec_ad_adi_3D99"
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}
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],
|
|
"dtc_vectors": [],
|
|
"memory_regions": [
|
|
{
|
|
"name": "exception_vectors",
|
|
"start": 0,
|
|
"end": 159,
|
|
"kind": "vectors",
|
|
"manual": "section 2 address space"
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|
},
|
|
{
|
|
"name": "dtc_vectors",
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|
"start": 160,
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|
"end": 255,
|
|
"kind": "dtc_vectors",
|
|
"manual": "section 2 address space"
|
|
},
|
|
{
|
|
"name": "program_or_external",
|
|
"start": 256,
|
|
"end": 63103,
|
|
"kind": "program",
|
|
"manual": "section 2/17 mode-dependent ROM or external space"
|
|
},
|
|
{
|
|
"name": "on_chip_ram",
|
|
"start": 63104,
|
|
"end": 65151,
|
|
"kind": "ram",
|
|
"manual": "section 16 RAM"
|
|
},
|
|
{
|
|
"name": "register_field",
|
|
"start": 65152,
|
|
"end": 65535,
|
|
"kind": "registers",
|
|
"manual": "appendix B register map"
|
|
}
|
|
],
|
|
"data_candidates": {
|
|
"strings": [],
|
|
"pointer_tables": []
|
|
},
|
|
"call_graph": {
|
|
"nodes": [],
|
|
"edges": []
|
|
},
|
|
"timing_summary": {
|
|
"blocks": [],
|
|
"loops": []
|
|
},
|
|
"sci": {
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|
"clock_hz": 20000000,
|
|
"formulas": {
|
|
"async": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
|
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"sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))"
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|
},
|
|
"manual_references": [
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"Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source",
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"Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source",
|
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"Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator",
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"Manual/0900766b802125d0.md:16303 asynchronous BRR formula",
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|
"Manual/0900766b802125d0.md:16379 synchronous BRR formula",
|
|
"Manual/0900766b802125d0.md:16410 SCI clock source selection tables"
|
|
],
|
|
"channels": {
|
|
"SCI1": {
|
|
"writes": [],
|
|
"configurations": []
|
|
},
|
|
"SCI2": {
|
|
"writes": [],
|
|
"configurations": []
|
|
}
|
|
}
|
|
},
|
|
"sci_protocol": {
|
|
"manual_references": [
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"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
|
|
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
|
|
"Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
|
|
"Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
|
|
"Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
|
|
"Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
|
|
"Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
|
|
"Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
|
|
"Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
|
|
"Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
|
|
"Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
|
|
"Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
|
|
"Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
|
|
],
|
|
"channels": {
|
|
"SCI1": {
|
|
"events": []
|
|
},
|
|
"SCI2": {
|
|
"events": []
|
|
}
|
|
},
|
|
"events": []
|
|
},
|
|
"serial_reconstruction": {
|
|
"kind": "serial_reconstruction",
|
|
"candidates": [],
|
|
"ram_roles": [],
|
|
"evidence": [],
|
|
"required_evidence": {
|
|
"tx": [
|
|
"tx_buffer_region",
|
|
"tx_checksum_seed",
|
|
"checksum_byte",
|
|
"xor_checksum_chain",
|
|
"initial_send_from_buffer_start",
|
|
"tx_index_initialized_to_one",
|
|
"tx_isr_indexed_send",
|
|
"tx_index_increment",
|
|
"tx_index_compare_frame_length"
|
|
],
|
|
"rx": [
|
|
"rx_rdr_read",
|
|
"rx_indexed_store",
|
|
"rx_index_increment_store",
|
|
"rx_isr_compare_frame_length",
|
|
"rx_complete_timer",
|
|
"rx_processor_requires_six_bytes",
|
|
"rx_copy_capture_to_frame_buffer",
|
|
"rx_checksum_seed",
|
|
"rx_xor_checksum_validation"
|
|
]
|
|
}
|
|
},
|
|
"board_profile": {
|
|
"board": "sony_rcp_tx7",
|
|
"name": "Sony RCP-TX7",
|
|
"summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.",
|
|
"manual_references": [
|
|
"Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD",
|
|
"Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD",
|
|
"Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals",
|
|
"Manual/0900766b802125d0.md:11201 P96 is RXD1 input",
|
|
"Manual/0900766b802125d0.md:11202 P95 is TXD1 output",
|
|
"Manual/0900766b802125d0.md:15725 SCI1 RXD input pin",
|
|
"Manual/0900766b802125d0.md:15726 SCI1 TXD output pin",
|
|
"Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR",
|
|
"Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR",
|
|
"Manual/0900766b802125d0.md:15794 RDR receive data register",
|
|
"Manual/0900766b802125d0.md:15823 TDR transmit data register",
|
|
"Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions",
|
|
"Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output",
|
|
"Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input",
|
|
"Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags",
|
|
"Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions",
|
|
"Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94"
|
|
],
|
|
"traces": [
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "TXD",
|
|
"h8_pin": 66,
|
|
"h8_pin_name": "P95/TXD",
|
|
"h8_function": "TXD1",
|
|
"max202_pin": 11,
|
|
"evidence": "MAX202 pin 11 traces to H8 pin 66"
|
|
},
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "RXD",
|
|
"h8_pin": 67,
|
|
"h8_pin_name": "P96/RXD",
|
|
"h8_function": "RXD1",
|
|
"max202_pin": 12,
|
|
"evidence": "MAX202 pin 12 traces to H8 pin 67"
|
|
}
|
|
],
|
|
"channels": {
|
|
"SCI1": {
|
|
"traced_to_max202": true,
|
|
"path": "RS232/MAX202",
|
|
"pins": [
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "TXD",
|
|
"h8_pin": 66,
|
|
"h8_pin_name": "P95/TXD",
|
|
"h8_function": "TXD1",
|
|
"max202_pin": 11,
|
|
"evidence": "MAX202 pin 11 traces to H8 pin 66"
|
|
},
|
|
{
|
|
"channel": "SCI1",
|
|
"signal": "RXD",
|
|
"h8_pin": 67,
|
|
"h8_pin_name": "P96/RXD",
|
|
"h8_function": "RXD1",
|
|
"max202_pin": 12,
|
|
"evidence": "MAX202 pin 12 traces to H8 pin 67"
|
|
}
|
|
],
|
|
"scr": {
|
|
"value": 12,
|
|
"value_hex": "H'0C",
|
|
"tie": false,
|
|
"rie": false,
|
|
"tx_enabled": false,
|
|
"rx_enabled": false
|
|
},
|
|
"accesses": []
|
|
},
|
|
"SCI2": {
|
|
"traced_to_max202": false,
|
|
"path": null,
|
|
"note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.",
|
|
"p9sci2e": false,
|
|
"scr": {
|
|
"value": 12,
|
|
"value_hex": "H'0C",
|
|
"tie": false,
|
|
"rie": false,
|
|
"tx_enabled": false,
|
|
"rx_enabled": false
|
|
},
|
|
"accesses": []
|
|
}
|
|
},
|
|
"instructions": {},
|
|
"state": {
|
|
"SYSCR2": {
|
|
"value": 128,
|
|
"value_hex": "H'80"
|
|
},
|
|
"P9SCI2E": false
|
|
}
|
|
},
|
|
"peripheral_access": {
|
|
"manual_references": [
|
|
"Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access",
|
|
"Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte",
|
|
"Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP",
|
|
"Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP",
|
|
"Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte"
|
|
],
|
|
"warnings": []
|
|
},
|
|
"indirect_flow": {
|
|
"sites": []
|
|
},
|
|
"dataflow": {
|
|
"blocks": [
|
|
{
|
|
"start": 11776,
|
|
"instructions": [
|
|
11776
|
|
],
|
|
"end": 11776,
|
|
"end_exclusive": 11779
|
|
},
|
|
{
|
|
"start": 11779,
|
|
"instructions": [
|
|
11779
|
|
],
|
|
"end": 11779,
|
|
"end_exclusive": 11782
|
|
},
|
|
{
|
|
"start": 11782,
|
|
"instructions": [
|
|
11782,
|
|
11786
|
|
],
|
|
"end": 11786,
|
|
"end_exclusive": 11788
|
|
},
|
|
{
|
|
"start": 11788,
|
|
"instructions": [
|
|
11788,
|
|
11792,
|
|
11796
|
|
],
|
|
"end": 11796,
|
|
"end_exclusive": 11798
|
|
},
|
|
{
|
|
"start": 11798,
|
|
"instructions": [
|
|
11798,
|
|
11802
|
|
],
|
|
"end": 11802,
|
|
"end_exclusive": 11806
|
|
},
|
|
{
|
|
"start": 11806,
|
|
"instructions": [
|
|
11806,
|
|
11810
|
|
],
|
|
"end": 11810,
|
|
"end_exclusive": 11812
|
|
},
|
|
{
|
|
"start": 11812,
|
|
"instructions": [
|
|
11812,
|
|
11816,
|
|
11820
|
|
],
|
|
"end": 11820,
|
|
"end_exclusive": 11822
|
|
},
|
|
{
|
|
"start": 11822,
|
|
"instructions": [
|
|
11822,
|
|
11826
|
|
],
|
|
"end": 11826,
|
|
"end_exclusive": 11830
|
|
},
|
|
{
|
|
"start": 11830,
|
|
"instructions": [
|
|
11830
|
|
],
|
|
"end": 11830,
|
|
"end_exclusive": 11833
|
|
},
|
|
{
|
|
"start": 11833,
|
|
"instructions": [
|
|
11833,
|
|
11837,
|
|
11839
|
|
],
|
|
"end": 11839,
|
|
"end_exclusive": 11841
|
|
},
|
|
{
|
|
"start": 11841,
|
|
"instructions": [
|
|
11841,
|
|
11843
|
|
],
|
|
"end": 11843,
|
|
"end_exclusive": 11845
|
|
},
|
|
{
|
|
"start": 11845,
|
|
"instructions": [
|
|
11845,
|
|
11849,
|
|
11853
|
|
],
|
|
"end": 11853,
|
|
"end_exclusive": 11855
|
|
},
|
|
{
|
|
"start": 11855,
|
|
"instructions": [
|
|
11855,
|
|
11859
|
|
],
|
|
"end": 11859,
|
|
"end_exclusive": 11863
|
|
},
|
|
{
|
|
"start": 11863,
|
|
"instructions": [
|
|
11863
|
|
],
|
|
"end": 11863,
|
|
"end_exclusive": 11866
|
|
},
|
|
{
|
|
"start": 11866,
|
|
"instructions": [
|
|
11866,
|
|
11870,
|
|
11872
|
|
],
|
|
"end": 11872,
|
|
"end_exclusive": 11874
|
|
},
|
|
{
|
|
"start": 11874,
|
|
"instructions": [
|
|
11874,
|
|
11878
|
|
],
|
|
"end": 11878,
|
|
"end_exclusive": 11880
|
|
},
|
|
{
|
|
"start": 11880,
|
|
"instructions": [
|
|
11880
|
|
],
|
|
"end": 11880,
|
|
"end_exclusive": 11884
|
|
},
|
|
{
|
|
"start": 11884,
|
|
"instructions": [
|
|
11884
|
|
],
|
|
"end": 11884,
|
|
"end_exclusive": 11887
|
|
},
|
|
{
|
|
"start": 11887,
|
|
"instructions": [
|
|
11887,
|
|
11891,
|
|
11895
|
|
],
|
|
"end": 11895,
|
|
"end_exclusive": 11897
|
|
},
|
|
{
|
|
"start": 11897,
|
|
"instructions": [
|
|
11897,
|
|
11901,
|
|
11903
|
|
],
|
|
"end": 11903,
|
|
"end_exclusive": 11906
|
|
}
|
|
],
|
|
"registers": [
|
|
"R0",
|
|
"R1",
|
|
"R2",
|
|
"R3",
|
|
"R4",
|
|
"R5",
|
|
"R6",
|
|
"R7"
|
|
],
|
|
"control_registers": [
|
|
"CCR",
|
|
"BR",
|
|
"EP",
|
|
"DP",
|
|
"TP",
|
|
"SR"
|
|
]
|
|
},
|
|
"symbols": {
|
|
"symbols": [
|
|
{
|
|
"address": 57390,
|
|
"name": "mem_E02E",
|
|
"region": "program_or_external",
|
|
"kind": "memory",
|
|
"access_count": 1,
|
|
"read_count": 1,
|
|
"write_count": 0,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 11891,
|
|
"last_access": 11891,
|
|
"accesses": [
|
|
{
|
|
"address": 57390,
|
|
"instruction_address": 11891,
|
|
"instruction": "CMP:G.W @H'E02E, R1",
|
|
"mnemonic": "CMP:G.W",
|
|
"direction": "read",
|
|
"width": "word",
|
|
"operand": "@H'E02E",
|
|
"operand_index": 0
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 57392,
|
|
"name": "mem_E030",
|
|
"region": "program_or_external",
|
|
"kind": "memory",
|
|
"access_count": 1,
|
|
"read_count": 1,
|
|
"write_count": 0,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 11887,
|
|
"last_access": 11887,
|
|
"accesses": [
|
|
{
|
|
"address": 57392,
|
|
"instruction_address": 11887,
|
|
"instruction": "MOV:G.W @H'E030, R1",
|
|
"mnemonic": "MOV:G.W",
|
|
"direction": "read",
|
|
"width": "word",
|
|
"operand": "@H'E030",
|
|
"operand_index": 0
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 59430,
|
|
"name": "mem_E826",
|
|
"region": "program_or_external",
|
|
"kind": "memory",
|
|
"access_count": 2,
|
|
"read_count": 2,
|
|
"write_count": 0,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 11782,
|
|
"last_access": 11806,
|
|
"accesses": [
|
|
{
|
|
"address": 59430,
|
|
"instruction_address": 11782,
|
|
"instruction": "BTST.W #15, @H'E826",
|
|
"mnemonic": "BTST.W",
|
|
"direction": "read",
|
|
"width": "word",
|
|
"operand": "@H'E826",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 59430,
|
|
"instruction_address": 11806,
|
|
"instruction": "BTST.W #14, @H'E826",
|
|
"mnemonic": "BTST.W",
|
|
"direction": "read",
|
|
"width": "word",
|
|
"operand": "@H'E826",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 59438,
|
|
"name": "mem_E82E",
|
|
"region": "program_or_external",
|
|
"kind": "memory",
|
|
"access_count": 1,
|
|
"read_count": 0,
|
|
"write_count": 1,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"word"
|
|
],
|
|
"width": "word",
|
|
"first_access": 11897,
|
|
"last_access": 11897,
|
|
"accesses": [
|
|
{
|
|
"address": 59438,
|
|
"instruction_address": 11897,
|
|
"instruction": "MOV:G.W R1, @H'E82E",
|
|
"mnemonic": "MOV:G.W",
|
|
"direction": "write",
|
|
"width": "word",
|
|
"operand": "@H'E82E",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63249,
|
|
"name": "ram_F711",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 4,
|
|
"read_count": 4,
|
|
"write_count": 4,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 11845,
|
|
"last_access": 11880,
|
|
"accesses": [
|
|
{
|
|
"address": 63249,
|
|
"instruction_address": 11845,
|
|
"instruction": "BCLR.B #0, @H'F711",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F711",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63249,
|
|
"instruction_address": 11855,
|
|
"instruction": "BSET.B #0, @H'F711",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F711",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63249,
|
|
"instruction_address": 11874,
|
|
"instruction": "BCLR.B #1, @H'F711",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F711",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63249,
|
|
"instruction_address": 11880,
|
|
"instruction": "BSET.B #1, @H'F711",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F711",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63251,
|
|
"name": "ram_F713",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 2,
|
|
"read_count": 2,
|
|
"write_count": 2,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 11792,
|
|
"last_access": 11802,
|
|
"accesses": [
|
|
{
|
|
"address": 63251,
|
|
"instruction_address": 11792,
|
|
"instruction": "BSET.B #4, @H'F713",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F713",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63251,
|
|
"instruction_address": 11802,
|
|
"instruction": "BCLR.B #4, @H'F713",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F713",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63254,
|
|
"name": "ram_F716",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 4,
|
|
"read_count": 4,
|
|
"write_count": 4,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 11816,
|
|
"last_access": 11859,
|
|
"accesses": [
|
|
{
|
|
"address": 63254,
|
|
"instruction_address": 11816,
|
|
"instruction": "BSET.B #7, @H'F716",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F716",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63254,
|
|
"instruction_address": 11826,
|
|
"instruction": "BCLR.B #7, @H'F716",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F716",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63254,
|
|
"instruction_address": 11849,
|
|
"instruction": "BCLR.B #5, @H'F716",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F716",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63254,
|
|
"instruction_address": 11859,
|
|
"instruction": "BSET.B #5, @H'F716",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F716",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"address": 63377,
|
|
"name": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram",
|
|
"access_count": 4,
|
|
"read_count": 4,
|
|
"write_count": 4,
|
|
"unknown_count": 0,
|
|
"width_hints": [
|
|
"byte"
|
|
],
|
|
"width": "byte",
|
|
"first_access": 11788,
|
|
"last_access": 11822,
|
|
"accesses": [
|
|
{
|
|
"address": 63377,
|
|
"instruction_address": 11788,
|
|
"instruction": "BSET.B #6, @H'F791",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F791",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63377,
|
|
"instruction_address": 11798,
|
|
"instruction": "BCLR.B #6, @H'F791",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F791",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63377,
|
|
"instruction_address": 11812,
|
|
"instruction": "BSET.B #5, @H'F791",
|
|
"mnemonic": "BSET.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F791",
|
|
"operand_index": 1
|
|
},
|
|
{
|
|
"address": 63377,
|
|
"instruction_address": 11822,
|
|
"instruction": "BCLR.B #5, @H'F791",
|
|
"mnemonic": "BCLR.B",
|
|
"direction": "read_write",
|
|
"width": "byte",
|
|
"operand": "@H'F791",
|
|
"operand_index": 1
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"by_address": {
|
|
"57390": "mem_E02E",
|
|
"57392": "mem_E030",
|
|
"59430": "mem_E826",
|
|
"59438": "mem_E82E",
|
|
"63249": "ram_F711",
|
|
"63251": "ram_F713",
|
|
"63254": "ram_F716",
|
|
"63377": "ram_F791"
|
|
}
|
|
},
|
|
"lcd_text": {
|
|
"strings": [],
|
|
"regions": [],
|
|
"searches": [
|
|
{
|
|
"term": "CONNECT",
|
|
"literal_hits": [],
|
|
"candidate_hits": [],
|
|
"near_matches": [],
|
|
"status": "not_found"
|
|
}
|
|
],
|
|
"notes": [
|
|
"LCD text scan is byte-oriented and conservative; strings may be inline script fields.",
|
|
"Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes."
|
|
]
|
|
},
|
|
"lcd_driver": {
|
|
"addresses": [
|
|
{
|
|
"address": 61952,
|
|
"name": "lcd_status_control",
|
|
"role": "status/control register inferred from busy polling and command writes"
|
|
},
|
|
{
|
|
"address": 61953,
|
|
"name": "lcd_data",
|
|
"role": "data register inferred from paired data reads/writes"
|
|
}
|
|
],
|
|
"accesses": [],
|
|
"polling_loops": [],
|
|
"routines": [],
|
|
"instructions": {}
|
|
},
|
|
"instructions": [
|
|
{
|
|
"address": 11776,
|
|
"address_region": "program_or_external",
|
|
"bytes": "30FEA3",
|
|
"text": "BRA loc_2CA6",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2CA6",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11430
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"cycles": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11776,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11779,
|
|
"address_region": "program_or_external",
|
|
"bytes": "30FEA0",
|
|
"text": "BRA loc_2CA6",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2CA6",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11430
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 8,
|
|
"base_taken": 7,
|
|
"alignment_adjustment_taken": 1,
|
|
"cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11779,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11782,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DE826FF",
|
|
"text": "BTST.W #15, @H'E826",
|
|
"mnemonic": "BTST.W",
|
|
"operands": "#15, @H'E826",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 7,
|
|
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|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 59430,
|
|
"name": null,
|
|
"symbol": "mem_E826",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
"block": 11782,
|
|
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|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
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|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
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|
|
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|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11786,
|
|
"address_region": "program_or_external",
|
|
"bytes": "270A",
|
|
"text": "BEQ loc_2E16",
|
|
"mnemonic": "BEQ",
|
|
"operands": "loc_2E16",
|
|
"kind": "branch",
|
|
"targets": [
|
|
11798
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
}
|
|
},
|
|
{
|
|
"address": 11788,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F791C6",
|
|
"text": "BSET.B #6, @H'F791",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#6, @H'F791",
|
|
"kind": "normal",
|
|
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|
|
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|
|
"cycles": 9,
|
|
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|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63377,
|
|
"name": null,
|
|
"symbol": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11792,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F713C4",
|
|
"text": "BSET.B #4, @H'F713",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#4, @H'F713",
|
|
"kind": "normal",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63251,
|
|
"name": null,
|
|
"symbol": "ram_F713",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
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|
|
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|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11796,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2008",
|
|
"text": "BRA loc_2E1E",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2E1E",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11806
|
|
],
|
|
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|
|
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|
|
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|
|
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|
|
"cycles": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
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|
|
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|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11798,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F791D6",
|
|
"text": "BCLR.B #6, @H'F791",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#6, @H'F791",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
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|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63377,
|
|
"name": null,
|
|
"symbol": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
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|
|
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|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
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|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11802,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F713D4",
|
|
"text": "BCLR.B #4, @H'F713",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#4, @H'F713",
|
|
"kind": "normal",
|
|
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|
|
"cycles": {
|
|
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|
|
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|
|
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|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63251,
|
|
"name": null,
|
|
"symbol": "ram_F713",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
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|
|
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|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11806,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DE826FE",
|
|
"text": "BTST.W #14, @H'E826",
|
|
"mnemonic": "BTST.W",
|
|
"operands": "#14, @H'E826",
|
|
"kind": "normal",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 59430,
|
|
"name": null,
|
|
"symbol": "mem_E826",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
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|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11810,
|
|
"address_region": "program_or_external",
|
|
"bytes": "270A",
|
|
"text": "BEQ loc_2E2E",
|
|
"mnemonic": "BEQ",
|
|
"operands": "loc_2E2E",
|
|
"kind": "branch",
|
|
"targets": [
|
|
11822
|
|
],
|
|
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|
|
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|
|
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|
|
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|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
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|
|
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|
|
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|
|
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|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11812,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F791C5",
|
|
"text": "BSET.B #5, @H'F791",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#5, @H'F791",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
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|
|
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|
|
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|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63377,
|
|
"name": null,
|
|
"symbol": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
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|
|
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|
|
{
|
|
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|
|
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|
|
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|
|
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|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11816,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F716C7",
|
|
"text": "BSET.B #7, @H'F716",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#7, @H'F716",
|
|
"kind": "normal",
|
|
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|
|
"cycles": {
|
|
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|
|
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|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63254,
|
|
"name": null,
|
|
"symbol": "ram_F716",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
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|
|
"block": 11812,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11820,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2008",
|
|
"text": "BRA loc_2E36",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2E36",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11830
|
|
],
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
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|
|
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|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11822,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F791D5",
|
|
"text": "BCLR.B #5, @H'F791",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#5, @H'F791",
|
|
"kind": "normal",
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63377,
|
|
"name": null,
|
|
"symbol": "ram_F791",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11822,
|
|
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|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11826,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F716D7",
|
|
"text": "BCLR.B #7, @H'F716",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#7, @H'F716",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
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|
|
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|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63254,
|
|
"name": null,
|
|
"symbol": "ram_F716",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11822,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11830,
|
|
"address_region": "program_or_external",
|
|
"bytes": "30FE6D",
|
|
"text": "BRA loc_2CA6",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2CA6",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11430
|
|
],
|
|
"cycles": {
|
|
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|
|
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|
|
"base_taken": 7,
|
|
"cycles": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11830,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11833,
|
|
"address_region": "program_or_external",
|
|
"bytes": "FCE00081",
|
|
"text": "MOV:G.W @(-H'2000,R4), R1",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "@(-H'2000,R4), R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 6,
|
|
"base_cycles": 6,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11833,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R1",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "memory_load"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R1 unknown after memory load"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 11837,
|
|
"address_region": "program_or_external",
|
|
"bytes": "A9FF",
|
|
"text": "BTST.W #15, R1",
|
|
"mnemonic": "BTST.W",
|
|
"operands": "#15, R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 3,
|
|
"base_cycles": 3,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11833,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11839,
|
|
"address_region": "program_or_external",
|
|
"bytes": "260E",
|
|
"text": "BNE loc_2E4F",
|
|
"mnemonic": "BNE",
|
|
"operands": "loc_2E4F",
|
|
"kind": "branch",
|
|
"targets": [
|
|
11855
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 8,
|
|
"base_taken": 7,
|
|
"alignment_adjustment_taken": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11833,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11841,
|
|
"address_region": "program_or_external",
|
|
"bytes": "A9FE",
|
|
"text": "BTST.W #14, R1",
|
|
"mnemonic": "BTST.W",
|
|
"operands": "#14, R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 3,
|
|
"base_cycles": 3,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11841,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11843,
|
|
"address_region": "program_or_external",
|
|
"bytes": "260A",
|
|
"text": "BNE loc_2E4F",
|
|
"mnemonic": "BNE",
|
|
"operands": "loc_2E4F",
|
|
"kind": "branch",
|
|
"targets": [
|
|
11855
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 8,
|
|
"base_taken": 7,
|
|
"alignment_adjustment_taken": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11841,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11845,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F711D0",
|
|
"text": "BCLR.B #0, @H'F711",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#0, @H'F711",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 8,
|
|
"base_cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63249,
|
|
"name": null,
|
|
"symbol": "ram_F711",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11845,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11849,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F716D5",
|
|
"text": "BCLR.B #5, @H'F716",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#5, @H'F716",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 8,
|
|
"base_cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63254,
|
|
"name": null,
|
|
"symbol": "ram_F716",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11845,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11853,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2008",
|
|
"text": "BRA loc_2E57",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2E57",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11863
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 8,
|
|
"base_taken": 7,
|
|
"alignment_adjustment_taken": 1,
|
|
"cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11845,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11855,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F711C0",
|
|
"text": "BSET.B #0, @H'F711",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#0, @H'F711",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 8,
|
|
"base_cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63249,
|
|
"name": null,
|
|
"symbol": "ram_F711",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11855,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11859,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F716C5",
|
|
"text": "BSET.B #5, @H'F716",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#5, @H'F716",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 8,
|
|
"base_cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63254,
|
|
"name": null,
|
|
"symbol": "ram_F716",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11855,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11863,
|
|
"address_region": "program_or_external",
|
|
"bytes": "30FE4C",
|
|
"text": "BRA loc_2CA6",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2CA6",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11430
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 8,
|
|
"base_taken": 7,
|
|
"alignment_adjustment_taken": 1,
|
|
"cycles": 8,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11863,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11866,
|
|
"address_region": "program_or_external",
|
|
"bytes": "FCE00081",
|
|
"text": "MOV:G.W @(-H'2000,R4), R1",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "@(-H'2000,R4), R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 7,
|
|
"base_cycles": 6,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11866,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R1",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "memory_load"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R1 unknown after memory load"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 11870,
|
|
"address_region": "program_or_external",
|
|
"bytes": "A9FF",
|
|
"text": "BTST.W #15, R1",
|
|
"mnemonic": "BTST.W",
|
|
"operands": "#15, R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 3,
|
|
"base_cycles": 3,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11866,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11872,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2606",
|
|
"text": "BNE loc_2E68",
|
|
"mnemonic": "BNE",
|
|
"operands": "loc_2E68",
|
|
"kind": "branch",
|
|
"targets": [
|
|
11880
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11866,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11874,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F711D1",
|
|
"text": "BCLR.B #1, @H'F711",
|
|
"mnemonic": "BCLR.B",
|
|
"operands": "#1, @H'F711",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
"base_cycles": 8,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63249,
|
|
"name": null,
|
|
"symbol": "ram_F711",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11874,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11878,
|
|
"address_region": "program_or_external",
|
|
"bytes": "2004",
|
|
"text": "BRA loc_2E6C",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2E6C",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11884
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"cycles": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11874,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11880,
|
|
"address_region": "program_or_external",
|
|
"bytes": "15F711C1",
|
|
"text": "BSET.B #1, @H'F711",
|
|
"mnemonic": "BSET.B",
|
|
"operands": "#1, @H'F711",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 9,
|
|
"base_cycles": 8,
|
|
"alignment_adjustment": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 63249,
|
|
"name": null,
|
|
"symbol": "ram_F711",
|
|
"region": "on_chip_ram",
|
|
"kind": "ram"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11880,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11884,
|
|
"address_region": "program_or_external",
|
|
"bytes": "30FE37",
|
|
"text": "BRA loc_2CA6",
|
|
"mnemonic": "BRA",
|
|
"operands": "loc_2CA6",
|
|
"kind": "jump",
|
|
"targets": [
|
|
11430
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 7,
|
|
"base_taken": 7,
|
|
"cycles": 7,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11884,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11887,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DE03081",
|
|
"text": "MOV:G.W @H'E030, R1",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "@H'E030, R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 6,
|
|
"base_cycles": 6,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 57392,
|
|
"name": null,
|
|
"symbol": "mem_E030",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11887,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R1",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "memory_load"
|
|
}
|
|
},
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R1 unknown after memory load"
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"address": 11891,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DE02E71",
|
|
"text": "CMP:G.W @H'E02E, R1",
|
|
"mnemonic": "CMP:G.W",
|
|
"operands": "@H'E02E, R1",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 6,
|
|
"base_cycles": 6,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 57390,
|
|
"name": null,
|
|
"symbol": "mem_E02E",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11887,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11895,
|
|
"address_region": "program_or_external",
|
|
"bytes": "270C",
|
|
"text": "BEQ loc_2E85",
|
|
"mnemonic": "BEQ",
|
|
"operands": "loc_2E85",
|
|
"kind": "branch",
|
|
"targets": [
|
|
11909
|
|
],
|
|
"cycles": {
|
|
"not_taken": 3,
|
|
"taken": 8,
|
|
"base_taken": 7,
|
|
"alignment_adjustment_taken": 1,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11887,
|
|
"changes": [],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11897,
|
|
"address_region": "program_or_external",
|
|
"bytes": "1DE82E91",
|
|
"text": "MOV:G.W R1, @H'E82E",
|
|
"mnemonic": "MOV:G.W",
|
|
"operands": "R1, @H'E82E",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 6,
|
|
"base_cycles": 6,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [
|
|
{
|
|
"address": 59438,
|
|
"name": null,
|
|
"symbol": "mem_E82E",
|
|
"region": "program_or_external",
|
|
"kind": "program"
|
|
}
|
|
],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11897,
|
|
"changes": [
|
|
{
|
|
"kind": "control",
|
|
"name": "CCR",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": false,
|
|
"reason": "flags"
|
|
}
|
|
}
|
|
],
|
|
"notes": []
|
|
}
|
|
},
|
|
{
|
|
"address": 11901,
|
|
"address_region": "program_or_external",
|
|
"bytes": "5280",
|
|
"text": "MOV:E.B #H'80, R2",
|
|
"mnemonic": "MOV:E.B",
|
|
"operands": "#H'80, R2",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 2,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11897,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R2",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R2 = 0x80"
|
|
],
|
|
"known_after": {
|
|
"registers": {
|
|
"R2": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
{
|
|
"address": 11903,
|
|
"address_region": "program_or_external",
|
|
"bytes": "5B0017",
|
|
"text": "MOV:I.W #H'0017, R3",
|
|
"mnemonic": "MOV:I.W",
|
|
"operands": "#H'0017, R3",
|
|
"kind": "normal",
|
|
"targets": [],
|
|
"cycles": {
|
|
"cycles": 3,
|
|
"source": "manual Appendix A.4, tables A-7/A-8",
|
|
"assumption": "on-chip instruction fetch/operand access, no external wait states"
|
|
},
|
|
"references": [],
|
|
"comment": "",
|
|
"valid": true,
|
|
"dataflow": {
|
|
"block": 11897,
|
|
"changes": [
|
|
{
|
|
"kind": "register",
|
|
"name": "R3",
|
|
"before": {
|
|
"known": false,
|
|
"reason": "block_entry"
|
|
},
|
|
"after": {
|
|
"known": true,
|
|
"value": 23,
|
|
"hex": "0x0017",
|
|
"width": 16,
|
|
"source": "MOV:I.W #H'0017, R3"
|
|
}
|
|
}
|
|
],
|
|
"notes": [
|
|
"R3 = 0x0017"
|
|
],
|
|
"known_after": {
|
|
"registers": {
|
|
"R2": {
|
|
"known": true,
|
|
"value": 128,
|
|
"hex": "0x80",
|
|
"width": 8,
|
|
"source": "MOV:E.B #H'80, R2"
|
|
},
|
|
"R3": {
|
|
"known": true,
|
|
"value": 23,
|
|
"hex": "0x0017",
|
|
"width": 16,
|
|
"source": "MOV:I.W #H'0017, R3"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
],
|
|
"decompiler_consistency": {
|
|
"kind": "decompiler_pseudocode_consistency",
|
|
"summary": "No byte-immediate-to-word destination cases found.",
|
|
"checks": []
|
|
},
|
|
"serial_semantics": {
|
|
"kind": "serial_semantics",
|
|
"protocol_semantics": [],
|
|
"fields": [],
|
|
"command_dispatch": null,
|
|
"commands": [],
|
|
"command_effects": [],
|
|
"response_candidates": [],
|
|
"response_schemas": [],
|
|
"response_schema": [],
|
|
"logical_table_map_candidates": [],
|
|
"table_map_candidates": [],
|
|
"state_variable_candidates": [],
|
|
"retry_error_model": null,
|
|
"gate_queue_model": null,
|
|
"tx_report_model": null,
|
|
"periodic_resend_model": null,
|
|
"timer_interrupt_model": null,
|
|
"confidence": "low",
|
|
"confidence_score": 0.0,
|
|
"caveat": "No protocol semantics are emitted without both RX and TX serial reconstruction candidates."
|
|
}
|
|
} |