import unittest from h8536.emulator.probe import DEFAULT_WATCH_PCS, parse_watch_pc, run_probe def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1100) -> bytearray: rom = bytearray([0xFF] * size) rom[0:2] = reset.to_bytes(2, "big") return rom class EmulatorProbeTest(unittest.TestCase): def test_parse_watch_pc_accepts_h8_hex_forms(self): self.assertEqual(parse_watch_pc("C08B"), 0xC08B) self.assertEqual(parse_watch_pc("0xC08B"), 0xC08B) self.assertEqual(parse_watch_pc("H'C08B"), 0xC08B) def test_default_watch_pcs_include_bit_bang_transfer_path(self): self.assertIn(0xC08B, DEFAULT_WATCH_PCS) self.assertIn(0xC0DB, DEFAULT_WATCH_PCS) self.assertIn(0xC121, DEFAULT_WATCH_PCS) self.assertIn(0xBFE0, DEFAULT_WATCH_PCS) self.assertIn(0xBFFE, DEFAULT_WATCH_PCS) self.assertIn(0xC059, DEFAULT_WATCH_PCS) def test_watch_snapshot_includes_bsr_return_address_on_stack(self): rom = rom_with_reset() rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7 rom[0x1003:0x1005] = b"\x0E\x03" # BSR H'1008, return H'1005 rom[0x1005:0x1008] = b"\x59\x12\x34" # MOV:I.W #H'1234, R1 rom[0x1008] = 0x19 # RTS report = run_probe( bytes(rom), max_steps=4, interval_steps=512, stop_on_tx=False, p9_log_limit=8, watch_pcs=(0x1008,), watch_snapshot_limit=4, watch_pc_limit=2, watch_min_interval=0, ) self.assertEqual(len(report.watch_snapshots), 1) snapshot = report.watch_snapshots[0] self.assertEqual(snapshot.pc, 0x1008) self.assertEqual(snapshot.sp, 0xFE7E) self.assertIn((0xFE7E, 0x1005), snapshot.stack_words) self.assertIn((0x1005, 0x1003), snapshot.callers) self.assertIn("H'1005<-H'1003", snapshot.line()) self.assertTrue(any("recent_watch_snapshots:" == line for line in report.lines())) if __name__ == "__main__": unittest.main()