import unittest from h8536.emulator import H8536Emulator, ON_CHIP_RAM_START from h8536.emulator.constants import ( FRT_TCR_OCIEA, FRT_TCSR_OCFA, FRT1_TCR, FRT1_TCSR, FRT2_TCR, FRT2_TCSR, IPRC, VECTOR_FRT1_OCIA, VECTOR_FRT2_OCIA, ) def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1040) -> bytearray: rom = bytearray([0xFF] * size) rom[0:2] = reset.to_bytes(2, "big") return rom def write_mov_b_abs_imm(rom: bytearray, address: int, target: int, value: int) -> int: rom[address : address + 5] = bytes([0x15, (target >> 8) & 0xFF, target & 0xFF, 0x06, value & 0xFF]) return address + 5 class Frt2OciaTimerTest(unittest.TestCase): def test_frt1_ocia_vector_can_fire_and_decrement_ram(self): rom = rom_with_reset() rom[VECTOR_FRT1_OCIA : VECTOR_FRT1_OCIA + 2] = (0x1020).to_bytes(2, "big") pc = 0x1000 rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7 pc += 3 # IPRC bits 6..4 are FRT1 and bits 2..0 are FRT2, so H'60 makes # only the FRT1 priority field high enough to pass interrupt mask 0. pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x60) pc = write_mov_b_abs_imm(rom, pc, FRT1_TCR, FRT_TCR_OCIEA) rom[pc : pc + 2] = b"\x20\xFE" # BRA self isr = 0x1020 rom[isr : isr + 4] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C]) isr += 4 rom[isr : isr + 4] = bytes([0x15, (FRT1_TCSR >> 8) & 0xFF, FRT1_TCSR & 0xFF, 0xD5]) rom[isr + 4] = 0x0A # RTE emulator = H8536Emulator(bytes(rom), frt1_ocia_steps=2) emulator.memory.write8(ON_CHIP_RAM_START, 3) emulator.run(max_steps=5) self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 2) self.assertFalse(emulator.memory.read8(FRT1_TCSR) & FRT_TCSR_OCFA) self.assertEqual(emulator.cpu.pc, isr + 4) def test_frt1_ocia_does_not_fire_when_ociea_disabled(self): rom = rom_with_reset() rom[VECTOR_FRT1_OCIA : VECTOR_FRT1_OCIA + 2] = (0x1020).to_bytes(2, "big") pc = 0x1000 rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7 pc += 3 pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x60) rom[pc : pc + 2] = b"\x20\xFE" # BRA self rom[0x1020 : 0x1024] = bytes( [0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C] ) rom[0x1024] = 0x0A # RTE emulator = H8536Emulator(bytes(rom), frt1_ocia_steps=1) emulator.memory.write8(ON_CHIP_RAM_START, 3) emulator.run(max_steps=8) self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 3) self.assertEqual(emulator.memory.read8(FRT1_TCSR) & FRT_TCSR_OCFA, 0) self.assertEqual(emulator.cpu.pc, pc) def test_frt2_ocia_vector_can_fire_and_decrement_ram(self): rom = rom_with_reset() rom[VECTOR_FRT2_OCIA : VECTOR_FRT2_OCIA + 2] = (0x1020).to_bytes(2, "big") pc = 0x1000 rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7 pc += 3 # IPRC bits 6..4 are FRT1 and bits 2..0 are FRT2, so H'06 makes # only the FRT2 priority field high enough to pass interrupt mask 0. pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x06) pc = write_mov_b_abs_imm(rom, pc, FRT2_TCR, FRT_TCR_OCIEA) rom[pc : pc + 2] = b"\x20\xFE" # BRA self isr = 0x1020 rom[isr : isr + 4] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C]) isr += 4 rom[isr : isr + 4] = bytes([0x15, (FRT2_TCSR >> 8) & 0xFF, FRT2_TCSR & 0xFF, 0xD5]) rom[isr + 4] = 0x0A # RTE emulator = H8536Emulator(bytes(rom), frt2_ocia_steps=2) emulator.memory.write8(ON_CHIP_RAM_START, 3) emulator.run(max_steps=5) self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 2) self.assertFalse(emulator.memory.read8(FRT2_TCSR) & FRT_TCSR_OCFA) self.assertEqual(emulator.cpu.pc, isr + 4) def test_frt2_ocia_does_not_fire_when_ociea_disabled(self): rom = rom_with_reset() rom[VECTOR_FRT2_OCIA : VECTOR_FRT2_OCIA + 2] = (0x1020).to_bytes(2, "big") pc = 0x1000 rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7 pc += 3 pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x06) rom[pc : pc + 2] = b"\x20\xFE" # BRA self rom[0x1020 : 0x1024] = bytes( [0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C] ) rom[0x1024] = 0x0A # RTE emulator = H8536Emulator(bytes(rom), frt2_ocia_steps=1) emulator.memory.write8(ON_CHIP_RAM_START, 3) emulator.run(max_steps=8) self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 3) self.assertEqual(emulator.memory.read8(FRT2_TCSR) & FRT_TCSR_OCFA, 0) self.assertEqual(emulator.cpu.pc, pc) if __name__ == "__main__": unittest.main()