from __future__ import annotations


BRANCH_NAMES = [
    "BRA",
    "BRN",
    "BHI",
    "BLS",
    "BCC",
    "BCS",
    "BNE",
    "BEQ",
    "BVC",
    "BVS",
    "BPL",
    "BMI",
    "BGE",
    "BLT",
    "BGT",
    "BLE",
]

FLOW_STOP = {"jump", "return", "rte", "sleep", "invalid"}


IO_REGISTERS: dict[int, str] = {
    0xFE80: "P1DDR",
    0xFE81: "P2DDR",
    0xFE82: "P1DR",
    0xFE83: "P2DR",
    0xFE84: "P3DDR",
    0xFE85: "P4DDR",
    0xFE86: "P3DR",
    0xFE87: "P4DR",
    0xFE88: "P5DDR",
    0xFE89: "P6DDR",
    0xFE8A: "P5DR",
    0xFE8B: "P6DR",
    0xFE8C: "P7DDR",
    0xFE8E: "P7DR",
    0xFE8F: "P8DR",
    0xFE90: "FRT1_TCR",
    0xFE91: "FRT1_TCSR",
    0xFE92: "FRT1_FRC_H",
    0xFE93: "FRT1_FRC_L",
    0xFE94: "FRT1_OCRA_L",
    0xFE95: "FRT1_OCRB_L",
    0xFE96: "FRT1_ICR_H",
    0xFE97: "FRT1_ICR_L",
    0xFEA0: "FRT2_TCR",
    0xFEA1: "FRT2_TCSR",
    0xFEA2: "FRT2_FRC_H",
    0xFEA3: "FRT2_FRC_L",
    0xFEA4: "FRT2_OCRA_H",
    0xFEA5: "FRT2_OCRA_L",
    0xFEA6: "FRT2_OCRB_H",
    0xFEA7: "FRT2_OCRB_L",
    0xFEA8: "FRT2_ICR_H",
    0xFEA9: "FRT2_ICR_L",
    0xFEB0: "FRT3_TCR",
    0xFEB1: "FRT3_TCSR",
    0xFEB2: "FRT3_FRC_H",
    0xFEB3: "FRT3_FRC_L",
    0xFEB4: "FRT3_OCRA_H",
    0xFEB5: "FRT3_OCRA_L",
    0xFEB6: "FRT3_OCRB_H",
    0xFEB7: "FRT3_OCRB_L",
    0xFEB8: "FRT3_ICR_H",
    0xFEB9: "FRT3_ICR_L",
    0xFEC0: "PWM1_TCR",
    0xFEC1: "PWM1_DTR",
    0xFEC2: "PWM1_TCNT",
    0xFEC4: "PWM2_TCR",
    0xFEC5: "PWM2_DTR",
    0xFEC6: "PWM2_TCNT",
    0xFEC8: "PWM3_TCR",
    0xFEC9: "PWM3_DTR",
    0xFECA: "PWM3_TCNT",
    0xFED0: "TMR_TCR",
    0xFED1: "TMR_TCSR",
    0xFED2: "TMR_TCORA",
    0xFED3: "TMR_TCORB",
    0xFED4: "TMR_TCNT",
    0xFED8: "SCI1_SMR",
    0xFED9: "SCI1_BRR",
    0xFEDA: "SCI1_SCR",
    0xFEDB: "SCI1_TDR",
    0xFEDC: "SCI1_SSR",
    0xFEDD: "SCI1_RDR",
    0xFEE0: "ADDRA_H",
    0xFEE1: "ADDRA_L",
    0xFEE2: "ADDRB_H",
    0xFEE3: "ADDRB_L",
    0xFEE4: "ADDRC_H",
    0xFEE5: "ADDRC_L",
    0xFEE6: "ADDRD_H",
    0xFEE7: "ADDRD_L",
    0xFEE8: "ADCSR",
    0xFEEC: "WDT_TCSR_R",
    0xFEED: "WDT_TCNT_R",
    0xFEF0: "SCI2_SMR",
    0xFEF1: "SCI2_BRR",
    0xFEF2: "SCI2_SCR",
    0xFEF3: "SCI2_TDR",
    0xFEF4: "SCI2_SSR",
    0xFEF5: "SCI2_RDR",
    0xFEFC: "SYSCR1",
    0xFEFD: "SYSCR2",
    0xFEFE: "P9DDR",
    0xFEFF: "P9DR",
    0xFF00: "IPRA",
    0xFF01: "IPRB",
    0xFF02: "IPRC",
    0xFF03: "IPRD",
    0xFF04: "IPRE",
    0xFF05: "IPRF",
    0xFF08: "DTEA",
    0xFF09: "DTEB",
    0xFF0A: "DTEC",
    0xFF0B: "DTED",
    0xFF0C: "DTEE",
    0xFF0D: "DTEF",
    0xFF10: "WCR",
    0xFF11: "RAMCR",
    0xFF12: "MDCR",
    0xFF13: "SBYCR",
    0xFF14: "RSTCSR_W",
    0xFF15: "RSTCSR_R",
}


_FRT_TCR_BITS = {
    7: "ICIE",
    6: "OCIEB",
    5: "OCIEA",
    4: "OVIE",
    3: "OEB",
    2: "OEA",
    1: "CKS1",
    0: "CKS0",
}

_FRT_TCSR_BITS = {
    7: "ICF",
    6: "OCFB",
    5: "OCFA",
    4: "OVF",
    3: "OLVLB",
    2: "OLVLA",
    1: "IEDG",
    0: "CCLRA",
}

_PWM_TCR_BITS = {
    7: "OE",
    6: "OS",
    2: "CKS2",
    1: "CKS1",
    0: "CKS0",
}

_SCI_SMR_BITS = {
    7: "C/A",
    6: "CHR",
    5: "PE",
    4: "O/E",
    3: "STOP",
    1: "CKS1",
    0: "CKS0",
}

_SCI_SCR_BITS = {
    7: "TIE",
    6: "RIE",
    5: "TE",
    4: "RE",
    1: "CKE1",
    0: "CKE0",
}

_SCI_SSR_BITS = {
    7: "TDRE",
    6: "RDRF",
    5: "ORER",
    4: "FER",
    3: "PER",
}


IO_BITFIELDS: dict[int, dict[int, str]] = {
    0xFE90: _FRT_TCR_BITS,
    0xFE91: _FRT_TCSR_BITS,
    0xFEA0: _FRT_TCR_BITS,
    0xFEA1: _FRT_TCSR_BITS,
    0xFEB0: _FRT_TCR_BITS,
    0xFEB1: _FRT_TCSR_BITS,
    0xFEC0: _PWM_TCR_BITS,
    0xFEC4: _PWM_TCR_BITS,
    0xFEC8: _PWM_TCR_BITS,
    0xFED0: {
        7: "CMIEB",
        6: "CMIEA",
        5: "OVIE",
        4: "CCLR1",
        3: "CCLR0",
        2: "CKS2",
        1: "CKS1",
        0: "CKS0",
    },
    0xFED1: {
        7: "CMFB",
        6: "CMFA",
        5: "OVF",
        3: "OS3",
        2: "OS2",
        1: "OS1",
        0: "OS0",
    },
    0xFED8: _SCI_SMR_BITS,
    0xFEDA: _SCI_SCR_BITS,
    0xFEDC: _SCI_SSR_BITS,
    0xFEE8: {
        7: "ADF",
        6: "ADIE",
        5: "ADST",
        4: "SCAN",
        3: "CKS",
        2: "CH2",
        1: "CH1",
        0: "CH0",
    },
    0xFEEC: {
        7: "OVF",
        6: "WT/IT",
        5: "TME",
        2: "CKS2",
        1: "CKS1",
        0: "CKS0",
    },
    0xFEF0: _SCI_SMR_BITS,
    0xFEF2: _SCI_SCR_BITS,
    0xFEF4: _SCI_SSR_BITS,
    0xFEFC: {
        6: "IRQ1E",
        5: "IRQ0E",
        4: "NMIEG",
        3: "BRLE",
    },
    0xFEFD: {
        6: "IRQ5E",
        5: "IRQ4E",
        4: "IRQ3E",
        3: "IRQ2E",
        2: "P6PWME",
        1: "P9PWME",
        0: "P9SCI2E",
    },
    0xFF10: {
        3: "WMS1",
        2: "WMS0",
        1: "WC1",
        0: "WC0",
    },
    0xFF11: {
        7: "RAME",
    },
    0xFF12: {
        2: "MDS2",
        1: "MDS1",
        0: "MDS0",
    },
    0xFF14: {
        7: "WRST",
        6: "RSTOE",
    },
    0xFF15: {
        7: "WRST",
        6: "RSTOE",
    },
}


VECTOR_NAMES_MIN: dict[int, str] = {
    0x0000: "reset",
    0x0002: "reserved_0002",
    0x0004: "invalid_instruction",
    0x0006: "zero_divide",
    0x0008: "trap_vs",
    0x0010: "address_error",
    0x0012: "trace",
    0x0016: "nmi",
    0x0040: "irq0",
    0x0042: "interval_timer",
    0x0048: "irq1",
    0x0050: "irq2",
    0x0052: "irq3",
    0x0058: "irq4",
    0x005A: "irq5",
    0x0060: "frt1_ici",
    0x0062: "frt1_ocia",
    0x0064: "frt1_ocib",
    0x0066: "frt1_fovi",
    0x0068: "frt2_ici",
    0x006A: "frt2_ocia",
    0x006C: "frt2_ocib",
    0x006E: "frt2_fovi",
    0x0070: "frt3_ici",
    0x0072: "frt3_ocia",
    0x0074: "frt3_ocib",
    0x0076: "frt3_fovi",
    0x0078: "tmr_cmia",
    0x007A: "tmr_cmib",
    0x007C: "tmr_ovi",
    0x0080: "sci1_eri",
    0x0082: "sci1_rxi",
    0x0084: "sci1_txi",
    0x0088: "sci2_eri",
    0x008A: "sci2_rxi",
    0x008C: "sci2_txi",
    0x0090: "ad_adi",
}

for trap in range(16):
    VECTOR_NAMES_MIN[0x0020 + trap * 2] = f"trapa_{trap:x}"