{ "vectors": [ { "address": 0, "name": "reset", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 4, "name": "invalid_instruction", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 6, "name": "zero_divide", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 8, "name": "trap_vs", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 16, "name": "address_error", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 18, "name": "trace", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 22, "name": "nmi", "target": 17299, "target_label": "vec_nmi_4393" }, { "address": 32, "name": "trapa_0", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 34, "name": "trapa_1", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 36, "name": "trapa_2", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 38, "name": "trapa_3", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 40, "name": "trapa_4", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 42, "name": "trapa_5", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 44, "name": "trapa_6", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 46, "name": "trapa_7", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 48, "name": "trapa_8", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 50, "name": "trapa_9", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 52, "name": "trapa_a", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 54, "name": "trapa_b", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 56, "name": "trapa_c", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 58, "name": "trapa_d", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 60, "name": "trapa_e", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 62, "name": "trapa_f", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 64, "name": "irq0", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 66, "name": "interval_timer", "target": 49092, "target_label": "vec_interval_timer_BFC4" }, { "address": 72, "name": "irq1", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 80, "name": "irq2", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 82, "name": "irq3", "target": 15408, "target_label": "vec_irq3_3C30" }, { "address": 88, "name": "irq4", "target": 15047, "target_label": "vec_irq4_3AC7" }, { "address": 90, "name": "irq5", "target": 4096, "target_label": "vec_reset_1000" }, { "address": 98, "name": "frt1_ocia", "target": 48874, "target_label": "vec_frt1_ocia_BEEA" }, { "address": 106, "name": "frt2_ocia", "target": 48931, "target_label": "vec_frt2_ocia_BF23" }, { "address": 128, "name": "sci1_eri", "target": 47959, "target_label": "vec_sci1_eri_BB57" }, { "address": 130, "name": "sci1_rxi", "target": 47975, "target_label": "vec_sci1_rxi_BB67" }, { "address": 132, "name": "sci1_txi", "target": 47748, "target_label": "vec_sci1_txi_BA84" }, { "address": 144, "name": "ad_adi", "target": 15769, "target_label": "vec_ad_adi_3D99" } ], "dtc_vectors": [], "memory_regions": [ { "name": "exception_vectors", "start": 0, "end": 159, "kind": "vectors", "manual": "section 2 address space" }, { "name": "dtc_vectors", "start": 160, "end": 255, "kind": "dtc_vectors", "manual": "section 2 address space" }, { "name": "program_or_external", "start": 256, "end": 63103, "kind": "program", "manual": "section 2/17 mode-dependent ROM or external space" }, { "name": "on_chip_ram", "start": 63104, "end": 65151, "kind": "ram", "manual": "section 16 RAM" }, { "name": "register_field", "start": 65152, "end": 65535, "kind": "registers", "manual": "appendix B register map" } ], "data_candidates": { "strings": [], "pointer_tables": [] }, "call_graph": { "nodes": [], "edges": [] }, "timing_summary": { "blocks": [], "loops": [] }, "sci": { "clock_hz": 20000000, "formulas": { "async": "B = clock_hz / (64 * 2^(2n) * (N + 1))", "sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))" }, "manual_references": [ "Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source", "Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source", "Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator", "Manual/0900766b802125d0.md:16303 asynchronous BRR formula", "Manual/0900766b802125d0.md:16379 synchronous BRR formula", "Manual/0900766b802125d0.md:16410 SCI clock source selection tables" ], "channels": { "SCI1": { "writes": [], "configurations": [] }, "SCI2": { "writes": [], "configurations": [] } } }, "sci_protocol": { "manual_references": [ "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" ], "channels": { "SCI1": { "events": [] }, "SCI2": { "events": [] } }, "events": [] }, "serial_reconstruction": { "kind": "serial_reconstruction", "candidates": [], "ram_roles": [], "evidence": [], "required_evidence": { "tx": [ "tx_buffer_region", "tx_checksum_seed", "checksum_byte", "xor_checksum_chain", "initial_send_from_buffer_start", "tx_index_initialized_to_one", "tx_isr_indexed_send", "tx_index_increment", "tx_index_compare_frame_length" ], "rx": [ "rx_rdr_read", "rx_indexed_store", "rx_index_increment_store", "rx_isr_compare_frame_length", "rx_complete_timer", "rx_processor_requires_six_bytes", "rx_copy_capture_to_frame_buffer", "rx_checksum_seed", "rx_xor_checksum_validation" ] } }, "board_profile": { "board": "sony_rcp_tx7", "name": "Sony RCP-TX7", "summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.", "manual_references": [ "Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD", "Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD", "Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals", "Manual/0900766b802125d0.md:11201 P96 is RXD1 input", "Manual/0900766b802125d0.md:11202 P95 is TXD1 output", "Manual/0900766b802125d0.md:15725 SCI1 RXD input pin", "Manual/0900766b802125d0.md:15726 SCI1 TXD output pin", "Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR", "Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR", "Manual/0900766b802125d0.md:15794 RDR receive data register", "Manual/0900766b802125d0.md:15823 TDR transmit data register", "Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions", "Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output", "Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input", "Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags", "Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions", "Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94" ], "traces": [ { "channel": "SCI1", "signal": "TXD", "h8_pin": 66, "h8_pin_name": "P95/TXD", "h8_function": "TXD1", "max202_pin": 11, "evidence": "MAX202 pin 11 traces to H8 pin 66" }, { "channel": "SCI1", "signal": "RXD", "h8_pin": 67, "h8_pin_name": "P96/RXD", "h8_function": "RXD1", "max202_pin": 12, "evidence": "MAX202 pin 12 traces to H8 pin 67" } ], "channels": { "SCI1": { "traced_to_max202": true, "path": "RS232/MAX202", "pins": [ { "channel": "SCI1", "signal": "TXD", "h8_pin": 66, "h8_pin_name": "P95/TXD", "h8_function": "TXD1", "max202_pin": 11, "evidence": "MAX202 pin 11 traces to H8 pin 66" }, { "channel": "SCI1", "signal": "RXD", "h8_pin": 67, "h8_pin_name": "P96/RXD", "h8_function": "RXD1", "max202_pin": 12, "evidence": "MAX202 pin 12 traces to H8 pin 67" } ], "scr": { "value": 12, "value_hex": "H'0C", "tie": false, "rie": false, "tx_enabled": false, "rx_enabled": false }, "accesses": [] }, "SCI2": { "traced_to_max202": false, "path": null, "note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.", "p9sci2e": false, "scr": { "value": 12, "value_hex": "H'0C", "tie": false, "rie": false, "tx_enabled": false, "rx_enabled": false }, "accesses": [] } }, "instructions": {}, "state": { "SYSCR2": { "value": 128, "value_hex": "H'80" }, "P9SCI2E": false } }, "peripheral_access": { "manual_references": [ "Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access", "Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte", "Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP", "Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP", "Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte" ], "warnings": [] }, "indirect_flow": { "sites": [] }, "dataflow": { "blocks": [ { "start": 8128, "instructions": [ 8128, 8132, 8137, 8139, 8142, 8145 ], "end": 8145, "end_exclusive": 8146 }, { "start": 8146, "instructions": [ 8146, 8150, 8154, 8159, 8161, 8164, 8167 ], "end": 8167, "end_exclusive": 8168 }, { "start": 8168, "instructions": [ 8168, 8172, 8174, 8178, 8180, 8183, 8186 ], "end": 8186, "end_exclusive": 8187 }, { "start": 8187, "instructions": [ 8187, 8191, 8193, 8197, 8199, 8202, 8205 ], "end": 8205, "end_exclusive": 8206 }, { "start": 8206, "instructions": [ 8206, 8210 ], "end": 8210, "end_exclusive": 8212 }, { "start": 8212, "instructions": [ 8212, 8217 ], "end": 8217, "end_exclusive": 8219 }, { "start": 8219, "instructions": [ 8219, 8223 ], "end": 8223, "end_exclusive": 8225 }, { "start": 8225, "instructions": [ 8225, 8229, 8231, 8235, 8237, 8240, 8243 ], "end": 8243, "end_exclusive": 8245 }, { "start": 8245, "instructions": [ 8245, 8249, 8251, 8255, 8257, 8260 ], "end": 8260, "end_exclusive": 8263 }, { "start": 8263, "instructions": [ 8263 ], "end": 8263, "end_exclusive": 8264 }, { "start": 8264, "instructions": [ 8264, 8268 ], "end": 8268, "end_exclusive": 8270 }, { "start": 8270, "instructions": [ 8270, 8275 ], "end": 8275, "end_exclusive": 8277 }, { "start": 8277, "instructions": [ 8277, 8281 ], "end": 8281, "end_exclusive": 8283 }, { "start": 8283, "instructions": [ 8283, 8289, 8291, 8294, 8297, 8301, 8306 ], "end": 8306, "end_exclusive": 8308 }, { "start": 8308, "instructions": [ 8308, 8312, 8316, 8320, 8324, 8327, 8331, 8336, 8340, 8344, 8349 ], "end": 8349, "end_exclusive": 8352 }, { "start": 8352, "instructions": [ 8352 ], "end": 8352, "end_exclusive": 8353 }, { "start": 8353, "instructions": [ 8353, 8357, 8361 ], "end": 8361, "end_exclusive": 8363 }, { "start": 8363, "instructions": [ 8363, 8365 ], "end": 8365, "end_exclusive": 8367 }, { "start": 8367, "instructions": [ 8367 ], "end": 8367, "end_exclusive": 8369 }, { "start": 8369, "instructions": [ 8369, 8373, 8375, 8378, 8381 ], "end": 8381, "end_exclusive": 8382 }, { "start": 8382, "instructions": [ 8382, 8386 ], "end": 8386, "end_exclusive": 8388 }, { "start": 8388, "instructions": [ 8388, 8393 ], "end": 8393, "end_exclusive": 8395 }, { "start": 8395, "instructions": [ 8395, 8399 ], "end": 8399, "end_exclusive": 8401 }, { "start": 8401, "instructions": [ 8401, 8404 ], "end": 8404, "end_exclusive": 8406 }, { "start": 8406, "instructions": [ 8406, 8410, 8412 ], "end": 8412, "end_exclusive": 8414 }, { "start": 8414, "instructions": [ 8414 ], "end": 8414, "end_exclusive": 8416 } ], "registers": [ "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7" ], "control_registers": [ "CCR", "BR", "EP", "DP", "TP", "SR" ] }, "symbols": { "symbols": [ { "address": 57382, "name": "mem_E026", "region": "program_or_external", "kind": "memory", "access_count": 4, "read_count": 4, "write_count": 0, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8168, "last_access": 8245, "accesses": [ { "address": 57382, "instruction_address": 8168, "instruction": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "direction": "read", "width": "word", "operand": "@H'E026", "operand_index": 0 }, { "address": 57382, "instruction_address": 8187, "instruction": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "direction": "read", "width": "word", "operand": "@H'E026", "operand_index": 0 }, { "address": 57382, "instruction_address": 8225, "instruction": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "direction": "read", "width": "word", "operand": "@H'E026", "operand_index": 0 }, { "address": 57382, "instruction_address": 8245, "instruction": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "direction": "read", "width": "word", "operand": "@H'E026", "operand_index": 0 } ] }, { "address": 57386, "name": "mem_E02A", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 1, "write_count": 0, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8353, "last_access": 8353, "accesses": [ { "address": 57386, "instruction_address": 8353, "instruction": "MOV:G.W @H'E02A, R0", "mnemonic": "MOV:G.W", "direction": "read", "width": "word", "operand": "@H'E02A", "operand_index": 0 } ] }, { "address": 57414, "name": "mem_E046", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8316, "last_access": 8316, "accesses": [ { "address": 57414, "instruction_address": 8316, "instruction": "CLR.W @H'E046", "mnemonic": "CLR.W", "direction": "write", "width": "word", "operand": "@H'E046", "operand_index": 0 } ] }, { "address": 57616, "name": "mem_E110", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 1, "write_count": 0, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8395, "last_access": 8395, "accesses": [ { "address": 57616, "instruction_address": 8395, "instruction": "TST.W @H'E110", "mnemonic": "TST.W", "direction": "read", "width": "word", "operand": "@H'E110", "operand_index": 0 } ] }, { "address": 57652, "name": "mem_E134", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 1, "write_count": 0, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8406, "last_access": 8406, "accesses": [ { "address": 57652, "instruction_address": 8406, "instruction": "MOV:G.W @H'E134, R0", "mnemonic": "MOV:G.W", "direction": "read", "width": "word", "operand": "@H'E134", "operand_index": 0 } ] }, { "address": 59428, "name": "mem_E824", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8154, "last_access": 8154, "accesses": [ { "address": 59428, "instruction_address": 8154, "instruction": "MOV:G.W #H'00, @H'E824", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E824", "operand_index": 1 } ] }, { "address": 59430, "name": "mem_E826", "region": "program_or_external", "kind": "memory", "access_count": 4, "read_count": 0, "write_count": 4, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8174, "last_access": 8251, "accesses": [ { "address": 59430, "instruction_address": 8174, "instruction": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E826", "operand_index": 1 }, { "address": 59430, "instruction_address": 8193, "instruction": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E826", "operand_index": 1 }, { "address": 59430, "instruction_address": 8231, "instruction": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E826", "operand_index": 1 }, { "address": 59430, "instruction_address": 8251, "instruction": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E826", "operand_index": 1 } ] }, { "address": 59434, "name": "mem_E82A", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8369, "last_access": 8369, "accesses": [ { "address": 59434, "instruction_address": 8369, "instruction": "MOV:G.W R0, @H'E82A", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E82A", "operand_index": 1 } ] }, { "address": 59606, "name": "mem_E8D6", "region": "program_or_external", "kind": "memory", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8283, "last_access": 8283, "accesses": [ { "address": 59606, "instruction_address": 8283, "instruction": "MOV:G.W #H'8000, @H'E8D6", "mnemonic": "MOV:G.W", "direction": "write", "width": "word", "operand": "@H'E8D6", "operand_index": 1 } ] }, { "address": 63188, "name": "ram_F6D4", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 1, "write_count": 0, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8264, "last_access": 8264, "accesses": [ { "address": 63188, "instruction_address": 8264, "instruction": "BTST.B #6, @H'F6D4", "mnemonic": "BTST.B", "direction": "read", "width": "byte", "operand": "@H'F6D4", "operand_index": 1 } ] }, { "address": 63195, "name": "ram_F6DB", "region": "on_chip_ram", "kind": "ram", "access_count": 3, "read_count": 3, "write_count": 0, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8206, "last_access": 8382, "accesses": [ { "address": 63195, "instruction_address": 8206, "instruction": "BTST.B #7, @H'F6DB", "mnemonic": "BTST.B", "direction": "read", "width": "byte", "operand": "@H'F6DB", "operand_index": 1 }, { "address": 63195, "instruction_address": 8357, "instruction": "BTST.B #5, @H'F6DB", "mnemonic": "BTST.B", "direction": "read", "width": "byte", "operand": "@H'F6DB", "operand_index": 1 }, { "address": 63195, "instruction_address": 8382, "instruction": "BTST.B #3, @H'F6DB", "mnemonic": "BTST.B", "direction": "read", "width": "byte", "operand": "@H'F6DB", "operand_index": 1 } ] }, { "address": 63251, "name": "ram_F713", "region": "on_chip_ram", "kind": "ram", "access_count": 2, "read_count": 2, "write_count": 2, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8150, "last_access": 8327, "accesses": [ { "address": 63251, "instruction_address": 8150, "instruction": "BCLR.B #5, @H'F713", "mnemonic": "BCLR.B", "direction": "read_write", "width": "byte", "operand": "@H'F713", "operand_index": 1 }, { "address": 63251, "instruction_address": 8327, "instruction": "BSET.B #6, @H'F713", "mnemonic": "BSET.B", "direction": "read_write", "width": "byte", "operand": "@H'F713", "operand_index": 1 } ] }, { "address": 63270, "name": "ram_F726", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8331, "last_access": 8331, "accesses": [ { "address": 63270, "instruction_address": 8331, "instruction": "MOV:G.B #H'1E, @H'F726", "mnemonic": "MOV:G.B", "direction": "write", "width": "byte", "operand": "@H'F726", "operand_index": 1 } ] }, { "address": 63280, "name": "ram_F730", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 1, "write_count": 0, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8277, "last_access": 8277, "accesses": [ { "address": 63280, "instruction_address": 8277, "instruction": "BTST.B #7, @H'F730", "mnemonic": "BTST.B", "direction": "read", "width": "byte", "operand": "@H'F730", "operand_index": 1 } ] }, { "address": 63281, "name": "ram_F731", "region": "on_chip_ram", "kind": "ram", "access_count": 5, "read_count": 5, "write_count": 2, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8212, "last_access": 8388, "accesses": [ { "address": 63281, "instruction_address": 8212, "instruction": "CMP:G.B #H'03, @H'F731", "mnemonic": "CMP:G.B", "direction": "read", "width": "byte", "operand": "@H'F731", "operand_index": 1 }, { "address": 63281, "instruction_address": 8270, "instruction": "CMP:G.B #H'02, @H'F731", "mnemonic": "CMP:G.B", "direction": "read", "width": "byte", "operand": "@H'F731", "operand_index": 1 }, { "address": 63281, "instruction_address": 8297, "instruction": "BSET.B #7, @H'F731", "mnemonic": "BSET.B", "direction": "read_write", "width": "byte", "operand": "@H'F731", "operand_index": 1 }, { "address": 63281, "instruction_address": 8340, "instruction": "BSET.B #7, @H'F731", "mnemonic": "BSET.B", "direction": "read_write", "width": "byte", "operand": "@H'F731", "operand_index": 1 }, { "address": 63281, "instruction_address": 8388, "instruction": "CMP:G.B #H'03, @H'F731", "mnemonic": "CMP:G.B", "direction": "read", "width": "byte", "operand": "@H'F731", "operand_index": 1 } ] }, { "address": 63282, "name": "ram_F732", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8308, "last_access": 8308, "accesses": [ { "address": 63282, "instruction_address": 8308, "instruction": "CLR.W @H'F732", "mnemonic": "CLR.W", "direction": "write", "width": "word", "operand": "@H'F732", "operand_index": 0 } ] }, { "address": 63338, "name": "ram_F76A", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 0, "write_count": 1, "unknown_count": 0, "width_hints": [ "word" ], "width": "word", "first_access": 8320, "last_access": 8320, "accesses": [ { "address": 63338, "instruction_address": 8320, "instruction": "CLR.W @H'F76A", "mnemonic": "CLR.W", "direction": "write", "width": "word", "operand": "@H'F76A", "operand_index": 0 } ] }, { "address": 63342, "name": "ram_F76E", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 1, "write_count": 1, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8336, "last_access": 8336, "accesses": [ { "address": 63342, "instruction_address": 8336, "instruction": "BSET.B #6, @H'F76E", "mnemonic": "BSET.B", "direction": "read_write", "width": "byte", "operand": "@H'F76E", "operand_index": 1 } ] }, { "address": 63377, "name": "ram_F791", "region": "on_chip_ram", "kind": "ram", "access_count": 2, "read_count": 2, "write_count": 1, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8146, "last_access": 8219, "accesses": [ { "address": 63377, "instruction_address": 8146, "instruction": "BCLR.B #7, @H'F791", "mnemonic": "BCLR.B", "direction": "read_write", "width": "byte", "operand": "@H'F791", "operand_index": 1 }, { "address": 63377, "instruction_address": 8219, "instruction": "BTST.B #5, @H'F791", "mnemonic": "BTST.B", "direction": "read", "width": "byte", "operand": "@H'F791", "operand_index": 1 } ] }, { "address": 63384, "name": "ram_F798", "region": "on_chip_ram", "kind": "ram", "access_count": 2, "read_count": 0, "write_count": 2, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8301, "last_access": 8344, "accesses": [ { "address": 63384, "instruction_address": 8301, "instruction": "MOV:G.B #H'C8, @H'F798", "mnemonic": "MOV:G.B", "direction": "write", "width": "byte", "operand": "@H'F798", "operand_index": 1 }, { "address": 63384, "instruction_address": 8344, "instruction": "MOV:G.B #H'C8, @H'F798", "mnemonic": "MOV:G.B", "direction": "write", "width": "byte", "operand": "@H'F798", "operand_index": 1 } ] }, { "address": 64259, "name": "ram_FB03", "region": "on_chip_ram", "kind": "ram", "access_count": 1, "read_count": 1, "write_count": 1, "unknown_count": 0, "width_hints": [ "byte" ], "width": "byte", "first_access": 8312, "last_access": 8312, "accesses": [ { "address": 64259, "instruction_address": 8312, "instruction": "BCLR.B #7, @H'FB03", "mnemonic": "BCLR.B", "direction": "read_write", "width": "byte", "operand": "@H'FB03", "operand_index": 1 } ] } ], "by_address": { "57382": "mem_E026", "57386": "mem_E02A", "57414": "mem_E046", "57616": "mem_E110", "57652": "mem_E134", "59428": "mem_E824", "59430": "mem_E826", "59434": "mem_E82A", "59606": "mem_E8D6", "63188": "ram_F6D4", "63195": "ram_F6DB", "63251": "ram_F713", "63270": "ram_F726", "63280": "ram_F730", "63281": "ram_F731", "63282": "ram_F732", "63338": "ram_F76A", "63342": "ram_F76E", "63377": "ram_F791", "63384": "ram_F798", "64259": "ram_FB03" } }, "lcd_text": { "strings": [], "regions": [], "searches": [ { "term": "CONNECT", "literal_hits": [], "candidate_hits": [], "near_matches": [], "status": "not_found" } ], "notes": [ "LCD text scan is byte-oriented and conservative; strings may be inline script fields.", "Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes." ] }, "lcd_driver": { "addresses": [ { "address": 61952, "name": "lcd_status_control", "role": "status/control register inferred from busy polling and command writes" }, { "address": 61953, "name": "lcd_data", "role": "data register inferred from paired data reads/writes" } ], "accesses": [], "polling_loops": [], "routines": [], "instructions": {} }, "instructions": [ { "address": 8128, "address_region": "program_or_external", "bytes": "F713C51D", "text": "ROTR.B @(H'13C5,R7)", "mnemonic": "ROTR.B", "operands": "@(H'13C5,R7)", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8128, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8132, "address_region": "program_or_external", "bytes": "E824078000", "text": "MOV:G.W #H'8000, @(H'24,R0)", "mnemonic": "MOV:G.W", "operands": "#H'8000, @(H'24,R0)", "kind": "normal", "targets": [], "cycles": { "cycles": 11, "base_cycles": 9, "alignment_adjustment": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8128, "changes": [], "notes": [] } }, { "address": 8137, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8128, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8139, "address_region": "program_or_external", "bytes": "5B4012", "text": "MOV:I.W #H'4012, R3", "mnemonic": "MOV:I.W", "operands": "#H'4012, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8128, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 16402, "hex": "0x4012", "width": 16, "source": "MOV:I.W #H'4012, R3" } } ], "notes": [ "R3 = 0x4012" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 16402, "hex": "0x4012", "width": 16, "source": "MOV:I.W #H'4012, R3" } } } } }, { "address": 8142, "address_region": "program_or_external", "bytes": "1E1E83", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8128, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 16402, "hex": "0x4012", "width": 16, "source": "MOV:I.W #H'4012, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8145, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 13, "base_cycles": 8, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8128, "changes": [], "notes": [] } }, { "address": 8146, "address_region": "program_or_external", "bytes": "15F791D7", "text": "BCLR.B #7, @H'F791", "mnemonic": "BCLR.B", "operands": "#7, @H'F791", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63377, "name": null, "symbol": "ram_F791", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8150, "address_region": "program_or_external", "bytes": "15F713D5", "text": "BCLR.B #5, @H'F713", "mnemonic": "BCLR.B", "operands": "#5, @H'F713", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63251, "name": null, "symbol": "ram_F713", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [], "notes": [] } }, { "address": 8154, "address_region": "program_or_external", "bytes": "1DE8240600", "text": "MOV:G.W #H'00, @H'E824", "mnemonic": "MOV:G.W", "operands": "#H'00, @H'E824", "kind": "normal", "targets": [], "cycles": { "cycles": 11, "base_cycles": 9, "alignment_adjustment": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59428, "name": null, "symbol": "mem_E824", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [], "notes": [] } }, { "address": 8159, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8161, "address_region": "program_or_external", "bytes": "5B4012", "text": "MOV:I.W #H'4012, R3", "mnemonic": "MOV:I.W", "operands": "#H'4012, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 16402, "hex": "0x4012", "width": 16, "source": "MOV:I.W #H'4012, R3" } } ], "notes": [ "R3 = 0x4012" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 16402, "hex": "0x4012", "width": 16, "source": "MOV:I.W #H'4012, R3" } } } } }, { "address": 8164, "address_region": "program_or_external", "bytes": "1E1E6D", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 16402, "hex": "0x4012", "width": 16, "source": "MOV:I.W #H'4012, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8167, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 13, "base_cycles": 8, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8146, "changes": [], "notes": [] } }, { "address": 8168, "address_region": "program_or_external", "bytes": "1DE02680", "text": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "operands": "@H'E026, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57382, "name": null, "symbol": "mem_E026", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "memory_load" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "R0 unknown after memory load" ] } }, { "address": 8172, "address_region": "program_or_external", "bytes": "A8CF", "text": "BSET.W #15, R0", "mnemonic": "BSET.W", "operands": "#15, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "memory_load" }, "after": { "known": false, "reason": "unsupported:BSET.W" } } ], "notes": [ "unsupported operation invalidated R0" ] } }, { "address": 8174, "address_region": "program_or_external", "bytes": "1DE82690", "text": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "operands": "R0, @H'E826", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59430, "name": null, "symbol": "mem_E826", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [], "notes": [] } }, { "address": 8178, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8180, "address_region": "program_or_external", "bytes": "5B0013", "text": "MOV:I.W #H'0013, R3", "mnemonic": "MOV:I.W", "operands": "#H'0013, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } ], "notes": [ "R3 = 0x0013" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } } } }, { "address": 8183, "address_region": "program_or_external", "bytes": "1E1E5A", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 14, "base_cycles": 9, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "unsupported:BSET.W" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8186, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 12, "base_cycles": 8, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8168, "changes": [], "notes": [] } }, { "address": 8187, "address_region": "program_or_external", "bytes": "1DE02680", "text": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "operands": "@H'E026, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57382, "name": null, "symbol": "mem_E026", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "memory_load" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "R0 unknown after memory load" ] } }, { "address": 8191, "address_region": "program_or_external", "bytes": "A8DF", "text": "BCLR.W #15, R0", "mnemonic": "BCLR.W", "operands": "#15, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "memory_load" }, "after": { "known": false, "reason": "unsupported:BCLR.W" } } ], "notes": [ "unsupported operation invalidated R0" ] } }, { "address": 8193, "address_region": "program_or_external", "bytes": "1DE82690", "text": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "operands": "R0, @H'E826", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59430, "name": null, "symbol": "mem_E826", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [], "notes": [] } }, { "address": 8197, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8199, "address_region": "program_or_external", "bytes": "5B0013", "text": "MOV:I.W #H'0013, R3", "mnemonic": "MOV:I.W", "operands": "#H'0013, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } ], "notes": [ "R3 = 0x0013" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } } } }, { "address": 8202, "address_region": "program_or_external", "bytes": "1E1E47", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "unsupported:BCLR.W" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8205, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 13, "base_cycles": 8, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8187, "changes": [], "notes": [] } }, { "address": 8206, "address_region": "program_or_external", "bytes": "15F6DBF7", "text": "BTST.B #7, @H'F6DB", "mnemonic": "BTST.B", "operands": "#7, @H'F6DB", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63195, "name": null, "symbol": "ram_F6DB", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8206, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8210, "address_region": "program_or_external", "bytes": "2733", "text": "BEQ loc_2047", "mnemonic": "BEQ", "operands": "loc_2047", "kind": "branch", "targets": [ 8263 ], "cycles": { "not_taken": 3, "taken": 7, "base_taken": 7, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8206, "changes": [], "notes": [] } }, { "address": 8212, "address_region": "program_or_external", "bytes": "15F7310403", "text": "CMP:G.B #H'03, @H'F731", "mnemonic": "CMP:G.B", "operands": "#H'03, @H'F731", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63281, "name": null, "symbol": "ram_F731", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8212, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8217, "address_region": "program_or_external", "bytes": "222C", "text": "BHI loc_2047", "mnemonic": "BHI", "operands": "loc_2047", "kind": "branch", "targets": [ 8263 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8212, "changes": [], "notes": [] } }, { "address": 8219, "address_region": "program_or_external", "bytes": "15F791F5", "text": "BTST.B #5, @H'F791", "mnemonic": "BTST.B", "operands": "#5, @H'F791", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63377, "name": null, "symbol": "ram_F791", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8219, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8223, "address_region": "program_or_external", "bytes": "2614", "text": "BNE loc_2035", "mnemonic": "BNE", "operands": "loc_2035", "kind": "branch", "targets": [ 8245 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8219, "changes": [], "notes": [] } }, { "address": 8225, "address_region": "program_or_external", "bytes": "1DE02680", "text": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "operands": "@H'E026, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57382, "name": null, "symbol": "mem_E026", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "memory_load" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "R0 unknown after memory load" ] } }, { "address": 8229, "address_region": "program_or_external", "bytes": "A8CE", "text": "BSET.W #14, R0", "mnemonic": "BSET.W", "operands": "#14, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "memory_load" }, "after": { "known": false, "reason": "unsupported:BSET.W" } } ], "notes": [ "unsupported operation invalidated R0" ] } }, { "address": 8231, "address_region": "program_or_external", "bytes": "1DE82690", "text": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "operands": "R0, @H'E826", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59430, "name": null, "symbol": "mem_E826", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [], "notes": [] } }, { "address": 8235, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8237, "address_region": "program_or_external", "bytes": "5B0013", "text": "MOV:I.W #H'0013, R3", "mnemonic": "MOV:I.W", "operands": "#H'0013, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } ], "notes": [ "R3 = 0x0013" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } } } }, { "address": 8240, "address_region": "program_or_external", "bytes": "1E1E21", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "unsupported:BSET.W" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8243, "address_region": "program_or_external", "bytes": "2012", "text": "BRA loc_2047", "mnemonic": "BRA", "operands": "loc_2047", "kind": "jump", "targets": [ 8263 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "cycles": 8, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8225, "changes": [], "notes": [] } }, { "address": 8245, "address_region": "program_or_external", "bytes": "1DE02680", "text": "MOV:G.W @H'E026, R0", "mnemonic": "MOV:G.W", "operands": "@H'E026, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57382, "name": null, "symbol": "mem_E026", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8245, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "memory_load" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "R0 unknown after memory load" ] } }, { "address": 8249, "address_region": "program_or_external", "bytes": "A8DE", "text": "BCLR.W #14, R0", "mnemonic": "BCLR.W", "operands": "#14, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8245, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "memory_load" }, "after": { "known": false, "reason": "unsupported:BCLR.W" } } ], "notes": [ "unsupported operation invalidated R0" ] } }, { "address": 8251, "address_region": "program_or_external", "bytes": "1DE82690", "text": "MOV:G.W R0, @H'E826", "mnemonic": "MOV:G.W", "operands": "R0, @H'E826", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59430, "name": null, "symbol": "mem_E826", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8245, "changes": [], "notes": [] } }, { "address": 8255, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8245, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8257, "address_region": "program_or_external", "bytes": "5B0013", "text": "MOV:I.W #H'0013, R3", "mnemonic": "MOV:I.W", "operands": "#H'0013, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8245, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } ], "notes": [ "R3 = 0x0013" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" } } } } }, { "address": 8260, "address_region": "program_or_external", "bytes": "1E1E0D", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8245, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "unsupported:BCLR.W" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 19, "hex": "0x0013", "width": 16, "source": "MOV:I.W #H'0013, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8263, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 13, "base_cycles": 8, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8263, "changes": [], "notes": [] } }, { "address": 8264, "address_region": "program_or_external", "bytes": "15F6D4F6", "text": "BTST.B #6, @H'F6D4", "mnemonic": "BTST.B", "operands": "#6, @H'F6D4", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63188, "name": null, "symbol": "ram_F6D4", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8264, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8268, "address_region": "program_or_external", "bytes": "2752", "text": "BEQ loc_20A0", "mnemonic": "BEQ", "operands": "loc_20A0", "kind": "branch", "targets": [ 8352 ], "cycles": { "not_taken": 3, "taken": 7, "base_taken": 7, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8264, "changes": [], "notes": [] } }, { "address": 8270, "address_region": "program_or_external", "bytes": "15F7310402", "text": "CMP:G.B #H'02, @H'F731", "mnemonic": "CMP:G.B", "operands": "#H'02, @H'F731", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63281, "name": null, "symbol": "ram_F731", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8270, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8275, "address_region": "program_or_external", "bytes": "224B", "text": "BHI loc_20A0", "mnemonic": "BHI", "operands": "loc_20A0", "kind": "branch", "targets": [ 8352 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8270, "changes": [], "notes": [] } }, { "address": 8277, "address_region": "program_or_external", "bytes": "15F730F7", "text": "BTST.B #7, @H'F730", "mnemonic": "BTST.B", "operands": "#7, @H'F730", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63280, "name": null, "symbol": "ram_F730", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8277, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8281, "address_region": "program_or_external", "bytes": "2719", "text": "BEQ loc_2074", "mnemonic": "BEQ", "operands": "loc_2074", "kind": "branch", "targets": [ 8308 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8277, "changes": [], "notes": [] } }, { "address": 8283, "address_region": "program_or_external", "bytes": "1DE8D6078000", "text": "MOV:G.W #H'8000, @H'E8D6", "mnemonic": "MOV:G.W", "operands": "#H'8000, @H'E8D6", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 9, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59606, "name": null, "symbol": "mem_E8D6", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8289, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8291, "address_region": "program_or_external", "bytes": "5B006B", "text": "MOV:I.W #H'006B, R3", "mnemonic": "MOV:I.W", "operands": "#H'006B, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 107, "hex": "0x006B", "width": 16, "source": "MOV:I.W #H'006B, R3" } } ], "notes": [ "R3 = 0x006B" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 107, "hex": "0x006B", "width": 16, "source": "MOV:I.W #H'006B, R3" } } } } }, { "address": 8294, "address_region": "program_or_external", "bytes": "1E1DEB", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 107, "hex": "0x006B", "width": 16, "source": "MOV:I.W #H'006B, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8297, "address_region": "program_or_external", "bytes": "15F731C7", "text": "BSET.B #7, @H'F731", "mnemonic": "BSET.B", "operands": "#7, @H'F731", "kind": "normal", "targets": [], "cycles": { "cycles": 8, "base_cycles": 8, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63281, "name": null, "symbol": "ram_F731", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "call" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8301, "address_region": "program_or_external", "bytes": "15F79806C8", "text": "MOV:G.B #H'C8, @H'F798", "mnemonic": "MOV:G.B", "operands": "#H'C8, @H'F798", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63384, "name": null, "symbol": "ram_F798", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [], "notes": [] } }, { "address": 8306, "address_region": "program_or_external", "bytes": "202C", "text": "BRA loc_20A0", "mnemonic": "BRA", "operands": "loc_20A0", "kind": "jump", "targets": [ 8352 ], "cycles": { "not_taken": 3, "taken": 7, "base_taken": 7, "cycles": 7, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8283, "changes": [], "notes": [] } }, { "address": 8308, "address_region": "program_or_external", "bytes": "1DF73213", "text": "CLR.W @H'F732", "mnemonic": "CLR.W", "operands": "@H'F732", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63282, "name": null, "symbol": "ram_F732", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8312, "address_region": "program_or_external", "bytes": "15FB03D7", "text": "BCLR.B #7, @H'FB03", "mnemonic": "BCLR.B", "operands": "#7, @H'FB03", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 64259, "name": null, "symbol": "ram_FB03", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8316, "address_region": "program_or_external", "bytes": "1DE04613", "text": "CLR.W @H'E046", "mnemonic": "CLR.W", "operands": "@H'E046", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57414, "name": null, "symbol": "mem_E046", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8320, "address_region": "program_or_external", "bytes": "1DF76A13", "text": "CLR.W @H'F76A", "mnemonic": "CLR.W", "operands": "@H'F76A", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63338, "name": null, "symbol": "ram_F76A", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8324, "address_region": "program_or_external", "bytes": "1E2873", "text": "BSR loc_48FA", "mnemonic": "BSR", "operands": "loc_48FA", "kind": "call", "targets": [ 18682 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8327, "address_region": "program_or_external", "bytes": "15F713C6", "text": "BSET.B #6, @H'F713", "mnemonic": "BSET.B", "operands": "#6, @H'F713", "kind": "normal", "targets": [], "cycles": { "cycles": 8, "base_cycles": 8, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63251, "name": null, "symbol": "ram_F713", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "call" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8331, "address_region": "program_or_external", "bytes": "15F726061E", "text": "MOV:G.B #H'1E, @H'F726", "mnemonic": "MOV:G.B", "operands": "#H'1E, @H'F726", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63270, "name": null, "symbol": "ram_F726", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8336, "address_region": "program_or_external", "bytes": "15F76EC6", "text": "BSET.B #6, @H'F76E", "mnemonic": "BSET.B", "operands": "#6, @H'F76E", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63342, "name": null, "symbol": "ram_F76E", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8340, "address_region": "program_or_external", "bytes": "15F731C7", "text": "BSET.B #7, @H'F731", "mnemonic": "BSET.B", "operands": "#7, @H'F731", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63281, "name": null, "symbol": "ram_F731", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8344, "address_region": "program_or_external", "bytes": "15F79806C8", "text": "MOV:G.B #H'C8, @H'F798", "mnemonic": "MOV:G.B", "operands": "#H'C8, @H'F798", "kind": "normal", "targets": [], "cycles": { "cycles": 9, "base_cycles": 8, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63384, "name": null, "symbol": "ram_F798", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [], "notes": [] } }, { "address": 8349, "address_region": "program_or_external", "bytes": "1E3638", "text": "BSR loc_56D8", "mnemonic": "BSR", "operands": "loc_56D8", "kind": "call", "targets": [ 22232 ], "cycles": { "cycles": 14, "base_cycles": 9, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8308, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8352, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 12, "base_cycles": 8, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8352, "changes": [], "notes": [] } }, { "address": 8353, "address_region": "program_or_external", "bytes": "1DE02A80", "text": "MOV:G.W @H'E02A, R0", "mnemonic": "MOV:G.W", "operands": "@H'E02A, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57386, "name": null, "symbol": "mem_E02A", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8353, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "memory_load" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "R0 unknown after memory load" ] } }, { "address": 8357, "address_region": "program_or_external", "bytes": "15F6DBF5", "text": "BTST.B #5, @H'F6DB", "mnemonic": "BTST.B", "operands": "#5, @H'F6DB", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63195, "name": null, "symbol": "ram_F6DB", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8353, "changes": [], "notes": [] } }, { "address": 8361, "address_region": "program_or_external", "bytes": "2704", "text": "BEQ loc_20AF", "mnemonic": "BEQ", "operands": "loc_20AF", "kind": "branch", "targets": [ 8367 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8353, "changes": [], "notes": [] } }, { "address": 8363, "address_region": "program_or_external", "bytes": "A8CF", "text": "BSET.W #15, R0", "mnemonic": "BSET.W", "operands": "#15, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8363, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "unsupported:BSET.W" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "unsupported operation invalidated R0" ] } }, { "address": 8365, "address_region": "program_or_external", "bytes": "2002", "text": "BRA loc_20B1", "mnemonic": "BRA", "operands": "loc_20B1", "kind": "jump", "targets": [ 8369 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "cycles": 8, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8363, "changes": [], "notes": [] } }, { "address": 8367, "address_region": "program_or_external", "bytes": "A8DF", "text": "BCLR.W #15, R0", "mnemonic": "BCLR.W", "operands": "#15, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8367, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "unsupported:BCLR.W" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "unsupported operation invalidated R0" ] } }, { "address": 8369, "address_region": "program_or_external", "bytes": "1DE82A90", "text": "MOV:G.W R0, @H'E82A", "mnemonic": "MOV:G.W", "operands": "R0, @H'E82A", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 59434, "name": null, "symbol": "mem_E82A", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8369, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8373, "address_region": "program_or_external", "bytes": "5280", "text": "MOV:E.B #H'80, R2", "mnemonic": "MOV:E.B", "operands": "#H'80, R2", "kind": "normal", "targets": [], "cycles": { "cycles": 2, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8369, "changes": [ { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } ], "notes": [ "R2 = 0x80" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" } } } } }, { "address": 8375, "address_region": "program_or_external", "bytes": "5B0015", "text": "MOV:I.W #H'0015, R3", "mnemonic": "MOV:I.W", "operands": "#H'0015, R3", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8369, "changes": [ { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": true, "value": 21, "hex": "0x0015", "width": 16, "source": "MOV:I.W #H'0015, R3" } } ], "notes": [ "R3 = 0x0015" ], "known_after": { "registers": { "R2": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "R3": { "known": true, "value": 21, "hex": "0x0015", "width": 16, "source": "MOV:I.W #H'0015, R3" } } } } }, { "address": 8378, "address_region": "program_or_external", "bytes": "1E1D97", "text": "BSR loc_3E54", "mnemonic": "BSR", "operands": "loc_3E54", "kind": "call", "targets": [ 15956 ], "cycles": { "cycles": 13, "base_cycles": 9, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8369, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": true, "value": 128, "hex": "0x80", "width": 8, "source": "MOV:E.B #H'80, R2" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": true, "value": 21, "hex": "0x0015", "width": 16, "source": "MOV:I.W #H'0015, R3" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "flags" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8381, "address_region": "program_or_external", "bytes": "19", "text": "RTS", "mnemonic": "RTS", "operands": "", "kind": "return", "targets": [], "cycles": { "cycles": 13, "base_cycles": 8, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word pop from stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8369, "changes": [], "notes": [] } }, { "address": 8382, "address_region": "program_or_external", "bytes": "15F6DBF3", "text": "BTST.B #3, @H'F6DB", "mnemonic": "BTST.B", "operands": "#3, @H'F6DB", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63195, "name": null, "symbol": "ram_F6DB", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8382, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8386, "address_region": "program_or_external", "bytes": "272C", "text": "BEQ loc_20F0", "mnemonic": "BEQ", "operands": "loc_20F0", "kind": "branch", "targets": [ 8432 ], "cycles": { "not_taken": 3, "taken": 7, "base_taken": 7, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8382, "changes": [], "notes": [] } }, { "address": 8388, "address_region": "program_or_external", "bytes": "15F7310403", "text": "CMP:G.B #H'03, @H'F731", "mnemonic": "CMP:G.B", "operands": "#H'03, @H'F731", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 63281, "name": null, "symbol": "ram_F731", "region": "on_chip_ram", "kind": "ram" } ], "comment": "", "valid": true, "dataflow": { "block": 8388, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8393, "address_region": "program_or_external", "bytes": "2225", "text": "BHI loc_20F0", "mnemonic": "BHI", "operands": "loc_20F0", "kind": "branch", "targets": [ 8432 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8388, "changes": [], "notes": [] } }, { "address": 8395, "address_region": "program_or_external", "bytes": "1DE11016", "text": "TST.W @H'E110", "mnemonic": "TST.W", "operands": "@H'E110", "kind": "normal", "targets": [], "cycles": { "cycles": 6, "base_cycles": 6, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57616, "name": null, "symbol": "mem_E110", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8395, "changes": [ { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [] } }, { "address": 8399, "address_region": "program_or_external", "bytes": "2705", "text": "BEQ loc_20D6", "mnemonic": "BEQ", "operands": "loc_20D6", "kind": "branch", "targets": [ 8406 ], "cycles": { "not_taken": 3, "taken": 8, "base_taken": 7, "alignment_adjustment_taken": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8395, "changes": [], "notes": [] } }, { "address": 8401, "address_region": "program_or_external", "bytes": "1E0614", "text": "BSR loc_26E8", "mnemonic": "BSR", "operands": "loc_26E8", "kind": "call", "targets": [ 9960 ], "cycles": { "cycles": 14, "base_cycles": 9, "alignment_adjustment": 1, "stack_adjustment": 4, "note": "PC word push to stack", "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8401, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R1", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R2", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R3", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R4", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R5", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R6", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "register", "name": "R7", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "BR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "EP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "DP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "TP", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } }, { "kind": "control", "name": "SR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "call" } } ], "notes": [ "call clobbers tracked register state" ] } }, { "address": 8404, "address_region": "program_or_external", "bytes": "201A", "text": "BRA loc_20F0", "mnemonic": "BRA", "operands": "loc_20F0", "kind": "jump", "targets": [ 8432 ], "cycles": { "not_taken": 3, "taken": 7, "base_taken": 7, "cycles": 7, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8401, "changes": [], "notes": [] } }, { "address": 8406, "address_region": "program_or_external", "bytes": "1DE13480", "text": "MOV:G.W @H'E134, R0", "mnemonic": "MOV:G.W", "operands": "@H'E134, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 7, "base_cycles": 6, "alignment_adjustment": 1, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [ { "address": 57652, "name": null, "symbol": "mem_E134", "region": "program_or_external", "kind": "program" } ], "comment": "", "valid": true, "dataflow": { "block": 8406, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "memory_load" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "R0 unknown after memory load" ] } }, { "address": 8410, "address_region": "program_or_external", "bytes": "A8FB", "text": "BTST.W #11, R0", "mnemonic": "BTST.W", "operands": "#11, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8406, "changes": [], "notes": [] } }, { "address": 8412, "address_region": "program_or_external", "bytes": "2704", "text": "BEQ loc_20E2", "mnemonic": "BEQ", "operands": "loc_20E2", "kind": "branch", "targets": [ 8418 ], "cycles": { "not_taken": 3, "taken": 7, "base_taken": 7, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8406, "changes": [], "notes": [] } }, { "address": 8414, "address_region": "program_or_external", "bytes": "A8DB", "text": "BCLR.W #11, R0", "mnemonic": "BCLR.W", "operands": "#11, R0", "kind": "normal", "targets": [], "cycles": { "cycles": 3, "base_cycles": 3, "source": "manual Appendix A.4, tables A-7/A-8", "assumption": "on-chip instruction fetch/operand access, no external wait states" }, "references": [], "comment": "", "valid": true, "dataflow": { "block": 8414, "changes": [ { "kind": "register", "name": "R0", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "unsupported:BCLR.W" } }, { "kind": "control", "name": "CCR", "before": { "known": false, "reason": "block_entry" }, "after": { "known": false, "reason": "flags" } } ], "notes": [ "unsupported operation invalidated R0" ] } } ], "decompiler_consistency": { "kind": "decompiler_pseudocode_consistency", "summary": "1 byte-immediate-to-word destination case(s) require explicit zero-extension in pseudocode.", "checks": [ { "kind": "byte_immediate_to_word_destination", "status": "requires_zero_extend8_to16_pseudocode", "address": 8154, "address_hex": "H'1FDA", "instruction": "MOV:G.W #H'00, @H'E824", "expected_pseudocode_hint": "zero_extend8_to16", "zero_extended_value_hex": "0x0000", "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." } ] }, "serial_semantics": { "kind": "serial_semantics", "protocol_semantics": [], "fields": [], "command_dispatch": null, "commands": [], "command_effects": [], "response_candidates": [], "response_schemas": [], "response_schema": [], "logical_table_map_candidates": [], "table_map_candidates": [], "state_variable_candidates": [], "retry_error_model": null, "gate_queue_model": null, "tx_report_model": null, "periodic_resend_model": null, "timer_interrupt_model": null, "confidence": "low", "confidence_score": 0.0, "caveat": "No protocol semantics are emitted without both RX and TX serial reconstruction candidates." } }