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Emulator learnings folded back into decompiler

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Aiden
2026-05-25 19:11:22 +10:00
parent 1fabf6587d
commit d2e7609bbf
16 changed files with 1468 additions and 87 deletions
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45
tests/test_serial_pseudocode.py
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@@ -160,12 +160,23 @@ class SerialPseudocodeTest(unittest.TestCase):
self.assertIn("No SCI1 RXI/TXI DTC vector entries are present", text)
self.assertIn("MAX202 pin 11 traces to H8 pin 66", text)
self.assertIn("Manual/0900766b802125d0.md:15823 TDR transmit data register", text)
self.assertIn("#define SCI1_TX_FRAME_LENGTH 6u", text)
self.assertIn("#define SCI1_TX_FRAME_BASE 0xF858u", text)
self.assertIn("#define SCI1_TX_FRAME_BYTE(n) MEM8[(u16)(SCI1_TX_FRAME_BASE + (n))]", text)
self.assertIn("#define SCI1_TX_FRAME_CHECKSUM SCI1_TX_FRAME_BYTE(5u)", text)
self.assertIn("#define SCI1_TX_INDEX MEM8[0xF9C2u]", text)
self.assertIn("#define TX_FRAME(n) MEM8[(u16)(0xF858u + (n))]", text)
self.assertIn("#define RX_CAPTURE(n) MEM8[(u16)(0xF868u + (n))]", text)
self.assertIn("checksum ^= TX_FRAME(4);", text)
self.assertIn("TX_FRAME(5) = sci1_tx_candidate_checksum();", text)
self.assertIn("First byte is sent synchronously; TIE enables TXI for the remaining bytes.", text)
self.assertIn("SCI1_TDR = TX_FRAME(0);", text)
self.assertIn("TX_INDEX = 1u;", text)
self.assertIn("SCI1_SCR |= SCI_SCR_TIE;", text)
self.assertIn("void sci1_txi_candidate_isr(void)", text)
self.assertIn("TXI runs after hardware reasserts SSR.TDRE", text)
self.assertIn("if ((SCI1_SSR & SCI_SSR_TDRE) == 0u)", text)
self.assertIn("SCI1_TDR = TX_FRAME(TX_INDEX);", text)
self.assertIn("SCI1_SSR &= (u8)~SCI_SSR_RDRF;\n byte = SCI1_RDR;", text)
self.assertIn("RX_CAPTURE(RX_INDEX) = byte;", text)
self.assertIn("return sci1_process_rx_candidate_frame();", text)
@@ -344,6 +355,31 @@ class SerialPseudocodeTest(unittest.TestCase):
},
"evidence_addresses_hex": ["H'BE90", "H'BED5"],
},
"timer_interrupt_model": {
"source": "FRT1 OCIA",
"vector_address_hex": "H'BEEA",
"counters": [
{
"address": 0xF9C0,
"address_hex": "H'F9C0",
"name_candidate": "tx_report_gate_counter_candidate",
"role": "candidate report gate counter.",
},
{
"address": 0xF9C1,
"address_hex": "H'F9C1",
"name_candidate": "rx_interbyte_timeout_candidate",
"role": "candidate RX interbyte timeout counter.",
},
{
"address": 0xF9C6,
"address_hex": "H'F9C6",
"name_candidate": "periodic_resend_cadence_counter_candidate",
"role": "candidate periodic resend cadence counter.",
},
],
"evidence_addresses_hex": ["H'BEEA", "H'BEF4"],
},
}
]
}
@@ -374,6 +410,15 @@ class SerialPseudocodeTest(unittest.TestCase):
self.assertIn("heartbeat/periodic resend candidate:", text)
self.assertIn("F9C6 reload H'01F4", text)
self.assertIn("BED5 resend path", text)
self.assertIn("interrupt/timer architecture candidate:", text)
self.assertIn("FRT1 OCIA H'BEEA appears to be a periodic tick ISR", text)
self.assertIn("H'F9C0 tx_report_gate_counter_candidate: candidate report gate counter.", text)
self.assertIn("H'F9C1 rx_interbyte_timeout_candidate: candidate RX interbyte timeout counter.", text)
self.assertIn("H'F9C6 periodic_resend_cadence_counter_candidate: candidate periodic resend cadence counter.", text)
self.assertIn("void frt1_ocia_candidate_tick_isr(void)", text)
self.assertIn("MEM8[0xF9C0u] = (u8)(MEM8[0xF9C0u] - 1u);", text)
self.assertIn("MEM8[0xF9C1u] = (u8)(MEM8[0xF9C1u] - 1u);", text)
self.assertIn("MEM8[0xF9C6u] = (u8)(MEM8[0xF9C6u] - 1u);", text)
self.assertIn("candidate effect: table_write_candidate; target primary_value_table_candidate", text)
def test_tx_only_option_omits_rx_functions(self):