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Emulator learnings folded back into decompiler

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Aiden
2026-05-25 19:11:22 +10:00
parent 1fabf6587d
commit d2e7609bbf
16 changed files with 1468 additions and 87 deletions
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49
tests/test_sci_protocol.py
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@@ -72,11 +72,43 @@ class SciProtocolTest(unittest.TestCase):
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2200),
"enable SCI1 TX interrupt (TIE)",
"enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2204),
"disable SCI1 TX interrupt (TIE)",
"disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
)
def test_sci1_transmit_path_comments_tdr_tdre_and_tie_timing(self):
instructions = {
0xBA72: ins(0xBA72, "MOV:G.B", "R0, @SCI1_TDR", references=[0xFEDB]),
0xBA7B: ins(0xBA7B, "BCLR.B", "#7, @SCI1_SSR", references=[0xFEDC]),
0xBA7F: ins(0xBA7F, "BSET.B", "#7, @SCI1_SCR", references=[0xFEDA]),
0xBAB5: ins(0xBAB5, "MOV:G.B", "R1, @SCI1_TDR", references=[0xFEDB]),
0xBABB: ins(0xBABB, "BCLR.B", "#7, @SCI1_SSR", references=[0xFEDC]),
}
analysis = analyze_sci_protocol(instructions)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0xBA72),
"write RS232/SCI byte to SCI1 TDR for transmission",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0xBA7B),
"clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0xBA7F),
"enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0xBAB5),
"write RS232/SCI byte to SCI1 TDR for transmission",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0xBABB),
"clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
)
def test_receive_path_clears_rdrf_then_reads_received_byte(self):
@@ -89,7 +121,7 @@ class SciProtocolTest(unittest.TestCase):
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2300),
"clear SCI1 receive-data-full flag (RDRF)",
"clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2304),
@@ -107,15 +139,15 @@ class SciProtocolTest(unittest.TestCase):
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2400),
"clear SCI1 overrun error flag (ORER)",
"clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2404),
"clear SCI1 framing error flag (FER)",
"clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
)
self.assertEqual(
sci_protocol_comment_for_instruction(analysis, 0x2408),
"clear SCI1 parity error flag (PER)",
"clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
)
def test_immediate_scr_write_reports_protocol_control_bits(self):
@@ -126,7 +158,10 @@ class SciProtocolTest(unittest.TestCase):
analysis = analyze_sci_protocol(instructions)
comment = sci_protocol_comment_for_instruction(analysis, 0x2500)
self.assertIn("enable SCI2 TX interrupt (TIE)", comment)
self.assertIn(
"enable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
comment,
)
self.assertIn("disable SCI2 receive and receive-error interrupts (RIE)", comment)
self.assertIn("enable SCI2 transmitter (TE)", comment)
self.assertIn("enable SCI2 receiver (RE)", comment)