aiden/h8-536-decoder
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Emulator learnings folded back into decompiler

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Aiden
2026-05-25 19:11:22 +10:00
parent 1fabf6587d
commit d2e7609bbf
16 changed files with 1468 additions and 87 deletions
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40
build/rom_serial_pseudocode.c
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@@ -84,9 +84,14 @@ extern volatile u8 MEM8[0x10000];
#define SCI_SSR_FER 0x10u
#define SCI_SSR_PER 0x08u
#define TX_FRAME_LENGTH 6u
#define SCI1_TX_FRAME_LENGTH 6u
#define SCI1_TX_FRAME_BASE 0xF858u
#define SCI1_TX_FRAME_BYTE(n) MEM8[(u16)(SCI1_TX_FRAME_BASE + (n))]
#define SCI1_TX_FRAME_CHECKSUM SCI1_TX_FRAME_BYTE(5u)
#define SCI1_TX_INDEX MEM8[0xF9C2u]
#define TX_FRAME_LENGTH SCI1_TX_FRAME_LENGTH
#define TX_FRAME(n) MEM8[(u16)(0xF858u + (n))]
#define TX_INDEX MEM8[0xF9C2u]
#define TX_INDEX SCI1_TX_INDEX
#define RX_FRAME_LENGTH 6u
#define RX_CAPTURE(n) MEM8[(u16)(0xF868u + (n))]
@@ -204,6 +209,11 @@ extern volatile u8 MEM8[0x10000];
* - FAA3 mask H'80: Candidate bit/mask that marks an autonomous report pending.
* - BED5 resend path: Candidate periodic resend path feeding the TX staging/send-builder flow.
* - evidence: H'BB46, H'BEC5, H'BB4C, H'BB51, H'BECB, H'BED5
* interrupt/timer architecture candidate:
* - FRT1 OCIA H'BEEA appears to be a periodic tick ISR for serial gate/cadence counters.
* - H'F9C0 tx_report_gate_counter_candidate: candidate gate counter used before entering the report builder.
* - H'F9C1 rx_interbyte_timeout_candidate: candidate RX interbyte timeout counter.
* - H'F9C6 periodic_resend_cadence_counter_candidate: candidate periodic resend/heartbeat cadence counter.
*/
static u8 sci1_rx_candidate_command(void)
@@ -256,6 +266,26 @@ static bool sci1_candidate_periodic_resend_gate_open(void)
return pending && period_elapsed && resend_countdown_active;
}
void frt1_ocia_candidate_tick_isr(void)
{
/* Candidate periodic tick at H'BEEA: decrement nonzero serial gate/cadence counters. */
/* TX_REPORT_GATE_COUNTER_CANDIDATE: candidate gate counter used before entering the report builder. */
if (MEM8[0xF9C0u] != 0u) {
MEM8[0xF9C0u] = (u8)(MEM8[0xF9C0u] - 1u);
}
/* RX_INTERBYTE_TIMEOUT_CANDIDATE: candidate RX interbyte timeout counter. */
if (MEM8[0xF9C1u] != 0u) {
MEM8[0xF9C1u] = (u8)(MEM8[0xF9C1u] - 1u);
}
/* PERIODIC_RESEND_CADENCE_COUNTER_CANDIDATE: candidate periodic resend/heartbeat cadence counter. */
if (MEM8[0xF9C6u] != 0u) {
MEM8[0xF9C6u] = (u8)(MEM8[0xF9C6u] - 1u);
}
}
void sci1_process_candidate_protocol_command(void)
{
u8 command = sci1_rx_candidate_command();
@@ -359,6 +389,7 @@ void sci1_tx_start_candidate_frame(void)
/* wait for transmit data register empty */
}
/* First byte is sent synchronously; TIE enables TXI for the remaining bytes. */
SCI1_TDR = TX_FRAME(0);
TX_INDEX = 1u;
SCI1_SSR &= (u8)~SCI_SSR_TDRE;
@@ -367,6 +398,11 @@ void sci1_tx_start_candidate_frame(void)
void sci1_txi_candidate_isr(void)
{
/* TXI runs after hardware reasserts SSR.TDRE for the next transmit byte. */
if ((SCI1_SSR & SCI_SSR_TDRE) == 0u) {
return;
}
if (TX_INDEX < TX_FRAME_LENGTH) {
SCI1_TDR = TX_FRAME(TX_INDEX);
TX_INDEX = (u8)(TX_INDEX + 1u);