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Emulator learnings folded back into decompiler

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Aiden
2026-05-25 19:11:22 +10:00
parent 1fabf6587d
commit d2e7609bbf
16 changed files with 1468 additions and 87 deletions
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579
build/rom_decompiled.json
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@@ -15679,7 +15679,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -15911,7 +15911,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 transmit data register empty flag (TDRE)",
"comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -15939,7 +15939,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "enable SCI1 TX interrupt (TIE)",
"comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -15968,7 +15968,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16022,7 +16022,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 transmit data register empty flag (TDRE)",
"comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16050,7 +16050,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16079,7 +16079,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 overrun error flag (ORER)",
"comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16107,7 +16107,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 framing error flag (FER)",
"comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16135,7 +16135,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 parity error flag (PER)",
"comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16163,7 +16163,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 receive-data-full flag (RDRF)",
"comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16220,7 +16220,7 @@
"register": "SCR",
"register_address": 65266,
"register_address_hex": "H'FEF2",
"comment": "disable SCI2 TX interrupt (TIE)",
"comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16344,7 +16344,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16464,7 +16464,7 @@
"register": "SCR",
"register_address": 65266,
"register_address_hex": "H'FEF2",
"comment": "disable SCI2 TX interrupt (TIE)",
"comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16696,7 +16696,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 transmit data register empty flag (TDRE)",
"comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16724,7 +16724,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "enable SCI1 TX interrupt (TIE)",
"comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16753,7 +16753,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16807,7 +16807,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 transmit data register empty flag (TDRE)",
"comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16835,7 +16835,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16864,7 +16864,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 overrun error flag (ORER)",
"comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16892,7 +16892,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 framing error flag (FER)",
"comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16920,7 +16920,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 parity error flag (PER)",
"comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -16948,7 +16948,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 receive-data-full flag (RDRF)",
"comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -17016,6 +17016,39 @@
"checksum_seed": 90,
"checksum_seed_hex": "H'005A",
"checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
"roles": [
{
"name": "tx_frame",
"address": 63576,
"address_hex": "H'F858",
"end_address": 63581,
"end_address_hex": "H'F85D",
"summary": "evidence-supported candidate SCI1 TX frame buffer"
},
{
"name": "tx_checksum",
"address": 63581,
"address_hex": "H'F85D",
"checksum_seed": 90,
"checksum_seed_hex": "H'005A",
"summary": "evidence-supported candidate SCI1 TX XOR checksum byte"
},
{
"name": "tx_index",
"address": 63938,
"address_hex": "H'F9C2",
"summary": "evidence-supported candidate SCI1 TX frame index"
}
],
"tx_path": {
"kind": "interrupt_driven_txi",
"initial_tdr_write_address": 47730,
"initial_tdr_write_address_hex": "H'BA72",
"txi_indexed_tdr_write_address": 47797,
"txi_indexed_tdr_write_address_hex": "H'BAB5",
"summary": "initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted",
"tdre_caveat": "TDRE reassertion is hardware/emulator timing context; static evidence is the indexed TXI send path."
},
"confidence": "high",
"confidence_score": 0.95,
"confidence_reason": "all required independent evidence groups were observed",
@@ -17696,6 +17729,215 @@
"comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A"
}
],
"ram_roles": [
{
"kind": "candidate_ram_role",
"name": "post_tx_report_delay",
"address": 63936,
"address_hex": "H'F9C0",
"width_bits": 8,
"confidence": "candidate/evidence-supported",
"summary": "post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it",
"caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol",
"evidence": [
{
"kind": "frt1_ocia_periodic_tick_isr",
"summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"addresses": [
48874
],
"addresses_hex": [
"H'BEEA"
],
"instructions": [
"BCLR.B #5, @FRT1_TCSR"
],
"vector_address": 98,
"vector_address_hex": "H'0062",
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
},
{
"kind": "post_tx_report_delay_tick_decrement",
"summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"addresses": [
48878,
48884
],
"addresses_hex": [
"H'BEEE",
"H'BEF4"
],
"instructions": [
"TST.B @H'F9C0",
"ADD:Q.B #-1, @H'F9C0"
],
"role_name": "post_tx_report_delay",
"ram_address": 63936,
"ram_address_hex": "H'F9C0",
"width_bits": 8,
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
}
],
"evidence_addresses": {
"frt1_ocia_periodic_tick_isr": [
48874
],
"post_tx_report_delay_tick_decrement": [
48878,
48884
]
},
"evidence_addresses_hex": {
"frt1_ocia_periodic_tick_isr": [
"H'BEEA"
],
"post_tx_report_delay_tick_decrement": [
"H'BEEE",
"H'BEF4"
]
}
},
{
"kind": "candidate_ram_role",
"name": "secondary_tx_report_delay",
"address": 63937,
"address_hex": "H'F9C1",
"width_bits": 8,
"confidence": "candidate/evidence-supported",
"summary": "secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it",
"caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol",
"evidence": [
{
"kind": "frt1_ocia_periodic_tick_isr",
"summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"addresses": [
48874
],
"addresses_hex": [
"H'BEEA"
],
"instructions": [
"BCLR.B #5, @FRT1_TCSR"
],
"vector_address": 98,
"vector_address_hex": "H'0062",
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
},
{
"kind": "secondary_tx_report_delay_tick_decrement",
"summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"addresses": [
48888,
48894
],
"addresses_hex": [
"H'BEF8",
"H'BEFE"
],
"instructions": [
"TST.B @H'F9C1",
"ADD:Q.B #-1, @H'F9C1"
],
"role_name": "secondary_tx_report_delay",
"ram_address": 63937,
"ram_address_hex": "H'F9C1",
"width_bits": 8,
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
}
],
"evidence_addresses": {
"frt1_ocia_periodic_tick_isr": [
48874
],
"secondary_tx_report_delay_tick_decrement": [
48888,
48894
]
},
"evidence_addresses_hex": {
"frt1_ocia_periodic_tick_isr": [
"H'BEEA"
],
"secondary_tx_report_delay_tick_decrement": [
"H'BEF8",
"H'BEFE"
]
}
},
{
"kind": "candidate_ram_role",
"name": "periodic_report_countdown",
"address": 63942,
"address_hex": "H'F9C6",
"width_bits": 16,
"confidence": "candidate/evidence-supported",
"summary": "periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it",
"caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol",
"evidence": [
{
"kind": "frt1_ocia_periodic_tick_isr",
"summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"addresses": [
48874
],
"addresses_hex": [
"H'BEEA"
],
"instructions": [
"BCLR.B #5, @FRT1_TCSR"
],
"vector_address": 98,
"vector_address_hex": "H'0062",
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
},
{
"kind": "periodic_report_countdown_tick_decrement",
"summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
"addresses": [
48898,
48904
],
"addresses_hex": [
"H'BF02",
"H'BF08"
],
"instructions": [
"TST.W @H'F9C6",
"ADD:Q.W #-1, @H'F9C6"
],
"role_name": "periodic_report_countdown",
"ram_address": 63942,
"ram_address_hex": "H'F9C6",
"width_bits": 16,
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
}
],
"evidence_addresses": {
"frt1_ocia_periodic_tick_isr": [
48874
],
"periodic_report_countdown_tick_decrement": [
48898,
48904
]
},
"evidence_addresses_hex": {
"frt1_ocia_periodic_tick_isr": [
"H'BEEA"
],
"periodic_report_countdown_tick_decrement": [
"H'BF02",
"H'BF08"
]
}
}
],
"evidence": [
{
"kind": "tx_buffer_region",
@@ -18094,6 +18336,89 @@
"XOR.B @H'F864, R0",
"CMP:G.B @H'F865, R0"
]
},
{
"kind": "frt1_ocia_periodic_tick_isr",
"summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"addresses": [
48874
],
"addresses_hex": [
"H'BEEA"
],
"instructions": [
"BCLR.B #5, @FRT1_TCSR"
],
"vector_address": 98,
"vector_address_hex": "H'0062",
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
},
{
"kind": "post_tx_report_delay_tick_decrement",
"summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"addresses": [
48878,
48884
],
"addresses_hex": [
"H'BEEE",
"H'BEF4"
],
"instructions": [
"TST.B @H'F9C0",
"ADD:Q.B #-1, @H'F9C0"
],
"role_name": "post_tx_report_delay",
"ram_address": 63936,
"ram_address_hex": "H'F9C0",
"width_bits": 8,
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
},
{
"kind": "secondary_tx_report_delay_tick_decrement",
"summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"addresses": [
48888,
48894
],
"addresses_hex": [
"H'BEF8",
"H'BEFE"
],
"instructions": [
"TST.B @H'F9C1",
"ADD:Q.B #-1, @H'F9C1"
],
"role_name": "secondary_tx_report_delay",
"ram_address": 63937,
"ram_address_hex": "H'F9C1",
"width_bits": 8,
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
},
{
"kind": "periodic_report_countdown_tick_decrement",
"summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
"addresses": [
48898,
48904
],
"addresses_hex": [
"H'BF02",
"H'BF08"
],
"instructions": [
"TST.W @H'F9C6",
"ADD:Q.W #-1, @H'F9C6"
],
"role_name": "periodic_report_countdown",
"ram_address": 63942,
"ram_address_hex": "H'F9C6",
"width_bits": 16,
"isr_address": 48874,
"isr_address_hex": "H'BEEA"
}
],
"required_evidence": {
@@ -53154,7 +53479,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -53561,7 +53886,7 @@
"register": "SCR",
"register_address": 65266,
"register_address_hex": "H'FEF2",
"comment": "disable SCI2 TX interrupt (TIE)",
"comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -158900,7 +159225,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 transmit data register empty flag (TDRE)",
"comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -158991,7 +159316,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "enable SCI1 TX interrupt (TIE)",
"comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -159419,7 +159744,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -159913,7 +160238,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 transmit data register empty flag (TDRE)",
"comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -160134,7 +160459,7 @@
"register": "SCR",
"register_address": 65242,
"register_address_hex": "H'FEDA",
"comment": "disable SCI1 TX interrupt (TIE)",
"comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -162180,7 +162505,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 overrun error flag (ORER)",
"comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -162286,7 +162611,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 framing error flag (FER)",
"comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -162392,7 +162717,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 parity error flag (PER)",
"comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -162522,7 +162847,7 @@
"register": "SSR",
"register_address": 65244,
"register_address_hex": "H'FEDC",
"comment": "clear SCI1 receive-data-full flag (RDRF)",
"comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
"manual": [
"Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
"Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
@@ -175356,6 +175681,62 @@
],
"comment": "clear OCFA (bit 5) of FRT1_TCSR",
"valid": true,
"serial_reconstruction": [
{
"address": 48874,
"action": "serial_reconstruction_ram_role",
"role_name": "post_tx_report_delay",
"role_kind": "candidate_ram_role",
"role_address": 63936,
"role_address_hex": "H'F9C0",
"evidence": "frt1_ocia_periodic_tick_isr",
"evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"evidence_addresses": [
48874
],
"evidence_addresses_hex": [
"H'BEEA"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported"
},
{
"address": 48874,
"action": "serial_reconstruction_ram_role",
"role_name": "secondary_tx_report_delay",
"role_kind": "candidate_ram_role",
"role_address": 63937,
"role_address_hex": "H'F9C1",
"evidence": "frt1_ocia_periodic_tick_isr",
"evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"evidence_addresses": [
48874
],
"evidence_addresses_hex": [
"H'BEEA"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported"
},
{
"address": 48874,
"action": "serial_reconstruction_ram_role",
"role_name": "periodic_report_countdown",
"role_kind": "candidate_ram_role",
"role_address": 63942,
"role_address_hex": "H'F9C6",
"evidence": "frt1_ocia_periodic_tick_isr",
"evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
"evidence_addresses": [
48874
],
"evidence_addresses_hex": [
"H'BEEA"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48874,
"changes": [
@@ -175402,6 +175783,28 @@
],
"comment": "",
"valid": true,
"serial_reconstruction": [
{
"address": 48878,
"action": "serial_reconstruction_ram_role",
"role_name": "post_tx_report_delay",
"role_kind": "candidate_ram_role",
"role_address": 63936,
"role_address_hex": "H'F9C0",
"evidence": "post_tx_report_delay_tick_decrement",
"evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"evidence_addresses": [
48878,
48884
],
"evidence_addresses_hex": [
"H'BEEE",
"H'BEF4"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48874,
"changes": [],
@@ -175462,6 +175865,28 @@
],
"comment": "",
"valid": true,
"serial_reconstruction": [
{
"address": 48884,
"action": "serial_reconstruction_ram_role",
"role_name": "post_tx_report_delay",
"role_kind": "candidate_ram_role",
"role_address": 63936,
"role_address_hex": "H'F9C0",
"evidence": "post_tx_report_delay_tick_decrement",
"evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"evidence_addresses": [
48878,
48884
],
"evidence_addresses_hex": [
"H'BEEE",
"H'BEF4"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48884,
"changes": [
@@ -175508,6 +175933,28 @@
],
"comment": "",
"valid": true,
"serial_reconstruction": [
{
"address": 48888,
"action": "serial_reconstruction_ram_role",
"role_name": "secondary_tx_report_delay",
"role_kind": "candidate_ram_role",
"role_address": 63937,
"role_address_hex": "H'F9C1",
"evidence": "secondary_tx_report_delay_tick_decrement",
"evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"evidence_addresses": [
48888,
48894
],
"evidence_addresses_hex": [
"H'BEF8",
"H'BEFE"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48888,
"changes": [
@@ -175581,6 +176028,28 @@
],
"comment": "",
"valid": true,
"serial_reconstruction": [
{
"address": 48894,
"action": "serial_reconstruction_ram_role",
"role_name": "secondary_tx_report_delay",
"role_kind": "candidate_ram_role",
"role_address": 63937,
"role_address_hex": "H'F9C1",
"evidence": "secondary_tx_report_delay_tick_decrement",
"evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
"evidence_addresses": [
48888,
48894
],
"evidence_addresses_hex": [
"H'BEF8",
"H'BEFE"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48894,
"changes": [
@@ -175627,6 +176096,28 @@
],
"comment": "",
"valid": true,
"serial_reconstruction": [
{
"address": 48898,
"action": "serial_reconstruction_ram_role",
"role_name": "periodic_report_countdown",
"role_kind": "candidate_ram_role",
"role_address": 63942,
"role_address_hex": "H'F9C6",
"evidence": "periodic_report_countdown_tick_decrement",
"evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
"evidence_addresses": [
48898,
48904
],
"evidence_addresses_hex": [
"H'BF02",
"H'BF08"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48898,
"changes": [
@@ -175700,6 +176191,28 @@
],
"comment": "",
"valid": true,
"serial_reconstruction": [
{
"address": 48904,
"action": "serial_reconstruction_ram_role",
"role_name": "periodic_report_countdown",
"role_kind": "candidate_ram_role",
"role_address": 63942,
"role_address_hex": "H'F9C6",
"evidence": "periodic_report_countdown_tick_decrement",
"evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
"evidence_addresses": [
48898,
48904
],
"evidence_addresses_hex": [
"H'BF02",
"H'BF08"
],
"confidence": "candidate/evidence-supported",
"comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
}
],
"dataflow": {
"block": 48904,
"changes": [