aiden/h8-536-decoder
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LCD decompile

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Aiden
2026-05-25 15:10:32 +10:00
parent 1d7f00e59c
commit cdfb811c28
15 changed files with 8836 additions and 19 deletions
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12
build/rom_pseudocode.c
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@@ -2116,21 +2116,21 @@ void loc_3F40(void)
SR &= (uint16_t)(0x00FF); /* 3F42; ANDC.W #H'00FF, SR; cycles=4 */
SR |= (uint16_t)(0x0600); /* 3F46; ORC.W #H'0600, SR; cycles=4 */
do {
R0 = read_eclock(MEM8[0xF200]); /* 3F4A; MOVFPE.B @H'F200, R0; refs mem_F200; cycles=13 */
set_flags_btst(R0, 7); /* 3F4F; BTST.B #7, R0; cycles=2 */
} while (!Z); /* 3F51; BNE loc_3F4A; cycles=3/8 nt/t */
R0 = read_eclock(MEM8[0xF200]); /* 3F4A; MOVFPE.B @H'F200, R0; LCD status read from E-clock H'F200; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; refs mem_F200; cycles=13 */
set_flags_btst(R0, 7); /* 3F4F; BTST.B #7, R0; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=2 */
} while (!Z); /* 3F51; BNE loc_3F4A; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=3/8 nt/t */
set_flags_btst(R4, 8); /* 3F53; BTST.W #8, R4; cycles=3 */
if (!Z) goto loc_3F6D; /* 3F55; BNE loc_3F6D; cycles=3/8 nt/t */
set_flags_btst(R4, 9); /* 3F57; BTST.W #9, R4; cycles=3 */
if (!Z) goto loc_3F62; /* 3F59; BNE loc_3F62; cycles=3/8 nt/t */
write_eclock(MEM8[0xF200], R4); /* 3F5B; MOVTPE.B R4, @H'F200; refs mem_F200; cycles=13 */
write_eclock(MEM8[0xF200], R4); /* 3F5B; MOVTPE.B R4, @H'F200; LCD command/address write to E-clock H'F200; refs mem_F200; cycles=13 */
goto loc_3F72; /* 3F60; BRA loc_3F72; cycles=7 */
loc_3F62:
write_eclock(MEM8[0xF201], R4); /* 3F62; MOVTPE.B R4, @H'F201; refs mem_F201; cycles=13 */
write_eclock(MEM8[0xF201], R4); /* 3F62; MOVTPE.B R4, @H'F201; LCD data write to E-clock H'F201; refs mem_F201; cycles=13 */
MEM16[0xFB00] += (uint16_t)(1); /* 3F67; ADD:Q.W #1, @H'FB00; refs ram_FB00; cycles=8 */
goto loc_3F72; /* 3F6B; BRA loc_3F72; cycles=8 */
loc_3F6D:
R4 = read_eclock(MEM8[0xF201]); /* 3F6D; MOVFPE.B @H'F201, R4; refs mem_F201; cycles=13 */
R4 = read_eclock(MEM8[0xF201]); /* 3F6D; MOVFPE.B @H'F201, R4; LCD data read from E-clock H'F201; refs mem_F201; cycles=13 */
loc_3F72:
SR = (uint16_t)(MEM16[R7++]); /* 3F72; LDC.W @R7+, SR; cycles=7 */
return; /* 3F74; RTS; cycles=12 */