Serial TX/RX builder
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Aiden
144
tests/test_serial_pseudocode.py
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144
tests/test_serial_pseudocode.py
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import json
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import tempfile
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import unittest
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from pathlib import Path
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from h8536.serial_pseudocode import (
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SerialPseudocodeOptions,
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generate_serial_pseudocode,
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write_serial_pseudocode,
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)
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def candidate_payload() -> dict:
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return {
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"instructions": [],
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"sci_protocol": {
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"manual_references": [
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"Manual/0900766b802125d0.md:15794 RDR receive data register",
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"Manual/0900766b802125d0.md:15823 TDR transmit data register",
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],
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},
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"board_profile": {
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"summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.",
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"manual_references": [
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"Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD",
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],
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"traces": [
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{
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"signal": "TXD",
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"h8_pin": 66,
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"h8_pin_name": "P95/TXD",
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"max202_pin": 11,
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"evidence": "MAX202 pin 11 traces to H8 pin 66",
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},
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{
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"signal": "RXD",
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"h8_pin": 67,
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"h8_pin_name": "P96/RXD",
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"max202_pin": 12,
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"evidence": "MAX202 pin 12 traces to H8 pin 67",
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},
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],
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},
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"serial_reconstruction": {
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"candidates": [
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{
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"kind": "candidate_sci1_tx_frame",
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"channel": "SCI1",
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"frame_length": 6,
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"buffer_start": 0xF858,
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"buffer_start_hex": "H'F858",
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"buffer_end": 0xF85D,
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"buffer_end_hex": "H'F85D",
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"checksum_address": 0xF85D,
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"tx_index_address": 0xF9C2,
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"tdr_address": 0xFEDB,
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"checksum_seed": 0x5A,
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"checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
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"confidence": "high",
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"confidence_score": 0.95,
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"confidence_reason": "all required independent evidence groups were observed",
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"comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis",
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"evidence_addresses_hex": {
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"tx_checksum_seed": ["H'BA4E"],
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"xor_checksum_chain": ["H'BA50", "H'BA54"],
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},
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},
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{
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"kind": "candidate_sci1_rx_frame",
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"channel": "SCI1",
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"frame_length": 6,
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"capture_buffer_start": 0xF868,
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"capture_buffer_start_hex": "H'F868",
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"capture_buffer_end": 0xF86D,
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"capture_buffer_end_hex": "H'F86D",
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"validation_buffer_start": 0xF860,
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"validation_buffer_end": 0xF865,
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"checksum_address": 0xF865,
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"rx_index_address": 0xF9C3,
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"rdr_address": 0xFEDD,
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"interbyte_timeout_address": 0xF9C1,
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"complete_timer_address": 0xF9C5,
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"checksum_seed": 0x5A,
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"checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
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"confidence": "high",
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"confidence_score": 0.9,
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"confidence_reason": "RX count, copy, and checksum-validation evidence were observed",
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"caveat": "candidate frame means six consecutive bytes, not a proven delimited packet",
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"comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis",
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"evidence_addresses_hex": {
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"rx_rdr_read": ["H'BB6D"],
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"rx_xor_checksum_validation": ["H'BBD6", "H'BBEC"],
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},
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},
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],
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},
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}
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class SerialPseudocodeTest(unittest.TestCase):
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def test_generates_focused_tx_and_rx_candidate_paths(self):
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text = generate_serial_pseudocode(candidate_payload(), source_name="rom.json")
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self.assertIn("focused SCI RX/TX pseudocode from rom.json", text)
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self.assertIn("SCI1 TX 6-byte frame at H'F858-H'F85D", text)
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self.assertIn("SCI1 RX 6-byte frame captured at H'F868-H'F86D", text)
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self.assertIn("MAX202 pin 11 traces to H8 pin 66", text)
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self.assertIn("Manual/0900766b802125d0.md:15823 TDR transmit data register", text)
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self.assertIn("#define TX_FRAME(n) MEM8[(u16)(0xF858u + (n))]", text)
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self.assertIn("#define RX_CAPTURE(n) MEM8[(u16)(0xF868u + (n))]", text)
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self.assertIn("checksum ^= TX_FRAME(4);", text)
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self.assertIn("TX_FRAME(5) = sci1_tx_candidate_checksum();", text)
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self.assertIn("SCI1_TDR = TX_FRAME(0);", text)
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self.assertIn("void sci1_txi_candidate_isr(void)", text)
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self.assertIn("SCI1_SSR &= (u8)~SCI_SSR_RDRF;\n byte = SCI1_RDR;", text)
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self.assertIn("RX_CAPTURE(RX_INDEX) = byte;", text)
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self.assertIn("return sci1_process_rx_candidate_frame();", text)
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self.assertIn("rx_xor_checksum_validation: H'BBD6, H'BBEC", text)
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def test_tx_only_option_omits_rx_functions(self):
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text = generate_serial_pseudocode(
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candidate_payload(),
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options=SerialPseudocodeOptions(include_rx=False),
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)
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self.assertIn("void sci1_tx_start_candidate_frame(void)", text)
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self.assertNotIn("sci1_rx_byte_received_candidate_isr", text)
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def test_write_serial_pseudocode_writes_output_file(self):
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with tempfile.TemporaryDirectory() as tmp:
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input_path = Path(tmp) / "rom.json"
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output_path = Path(tmp) / "serial.c"
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input_path.write_text(
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json.dumps(candidate_payload()),
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encoding="utf-8",
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)
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write_serial_pseudocode(input_path, output_path, SerialPseudocodeOptions())
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self.assertIn("sci1_process_rx_candidate_frame", output_path.read_text(encoding="utf-8"))
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if __name__ == "__main__":
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unittest.main()
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