1
0
This commit is contained in:
Aiden
2026-05-27 11:50:10 +10:00
parent 0d099235c5
commit c0304c575c
55 changed files with 26035 additions and 16 deletions

View File

@@ -39,6 +39,7 @@ from .cpu import CPUState, mask, s8, s16, sign_bit
from .errors import EmulatorError, UnsupportedInstruction
from .fast_paths import P9FastPath, P9FastPathConfig
from .memory import MemoryMap
from .panel import PanelAction, PanelInjection, PanelInput, resolve_panel_input, set_bit
from .sci import SCI1
from .timers import FrtOciaScheduler, FrtRegisters
from .uart import UartTiming
@@ -134,6 +135,38 @@ class H8536Emulator:
def inject_sci1_rx_byte(self, value: int) -> None:
self.memory.inject_sci1_rx_byte(value)
def inject_panel_input(self, panel_input: PanelInput | str, *, pressed: bool = True) -> PanelInjection:
resolved = resolve_panel_input(panel_input) if isinstance(panel_input, str) else panel_input
action = PanelAction(resolved, pressed=pressed)
shadow_before = self.memory.read8(resolved.shadow)
source_before = self.memory.external.get(resolved.source, shadow_before)
previous_before = self.memory.read8(resolved.previous)
dirty_before = self.memory.read8(resolved.dirty)
source_after = set_bit(source_before, resolved.bit, pressed)
shadow_after = set_bit(shadow_before, resolved.bit, pressed)
previous_after = set_bit(previous_before, resolved.bit, not pressed)
dirty_after = dirty_before | (1 << resolved.dirty_bit)
self.memory.write8(resolved.source, source_after)
self.memory.write8(resolved.shadow, shadow_after)
# The ROM's loc_1Bxx dispatchers act on shadow XOR previous-shadow.
# Force the previous sample opposite at this bit so the main loop sees one clean edge.
self.memory.write8(resolved.previous, previous_after)
self.memory.write8(resolved.dirty, dirty_after)
return PanelInjection(
action=action,
source_before=source_before,
source_after=source_after,
shadow_before=shadow_before,
shadow_after=shadow_after,
previous_before=previous_before,
previous_after=previous_after,
dirty_before=dirty_before,
dirty_after=dirty_after,
)
def step(self) -> str:
pc = self.cpu.pc
cycles_before = self.cpu.cycles