further digging and basic emulator
This commit is contained in:
Aiden
480
h8536/emulator.py
Normal file
480
h8536/emulator.py
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@@ -0,0 +1,480 @@
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from __future__ import annotations
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import argparse
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from dataclasses import dataclass, field
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from pathlib import Path
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from typing import Iterable
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from .decoder import H8536Decoder
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from .formatting import h8, h16
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from .memory import MEMORY_REGIONS, MemoryRegion, region_for
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from .rom import DecodeError, Rom
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from .vectors import read_vectors_min
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SCI1_SMR = 0xFED8
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SCI1_BRR = 0xFED9
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SCI1_SCR = 0xFEDA
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SCI1_TDR = 0xFEDB
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SCI1_SSR = 0xFEDC
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SCI1_RDR = 0xFEDD
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SCI_SCR_TIE = 0x80
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SCI_SCR_RIE = 0x40
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SCI_SCR_TE = 0x20
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SCI_SCR_RE = 0x10
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SCI_SSR_TDRE = 0x80
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SCI_SSR_RDRF = 0x40
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SCI_SSR_ORER = 0x20
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SCI_SSR_FER = 0x10
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SCI_SSR_PER = 0x08
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ON_CHIP_RAM_START = 0xF680
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ON_CHIP_RAM_END = 0xFE7F
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REGISTER_FIELD_START = 0xFE80
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REGISTER_FIELD_END = 0xFFFF
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RAMCR = 0xFF11
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HEARTBEAT_FRAME = bytes([0x00, 0x00, 0x00, 0x00, 0x80, 0xDA])
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class EmulatorError(Exception):
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pass
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class UnsupportedInstruction(EmulatorError):
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def __init__(self, pc: int, raw: bytes, text: str) -> None:
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raw_text = " ".join(f"{byte:02X}" for byte in raw)
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super().__init__(f"unsupported instruction at {h16(pc)}: {raw_text} {text}".rstrip())
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self.pc = pc
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self.raw = raw
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self.text = text
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@dataclass
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class SciTxEvent:
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address: int
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value: int
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scr: int
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ssr: int
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emitted: bool
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@dataclass
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class SCI1:
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"""Small SCI1 model for the H8/536 serial path.
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Manual anchors:
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- RDR/TDR/SCR/SSR live at H'FEDD/H'FEDB/H'FEDA/H'FEDC for SCI1.
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- SCR bit 7 TIE, bit 6 RIE, bit 5 TE, bit 4 RE.
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- SSR bit 7 TDRE, bit 6 RDRF, bits 5..3 ORER/FER/PER.
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- Software normally writes TDR after TDRE=1, then clears SSR.TDRE.
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"""
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smr: int = 0x00
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brr: int = 0xFF
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scr: int = 0x0C
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tdr: int = 0xFF
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ssr: int = 0x87
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rdr: int = 0x00
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tx_bytes: list[int] = field(default_factory=list)
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tx_events: list[SciTxEvent] = field(default_factory=list)
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tx_frames: list[bytes] = field(default_factory=list)
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_frame_buffer: bytearray = field(default_factory=bytearray)
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def read(self, address: int) -> int:
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if address == SCI1_SMR:
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return self.smr
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if address == SCI1_BRR:
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return self.brr
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if address == SCI1_SCR:
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return self.scr
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if address == SCI1_TDR:
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return self.tdr
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if address == SCI1_SSR:
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return self.ssr
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if address == SCI1_RDR:
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return self.rdr
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raise KeyError(address)
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def write(self, address: int, value: int) -> None:
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value &= 0xFF
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if address == SCI1_SMR:
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self.smr = value
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elif address == SCI1_BRR:
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self.brr = value
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elif address == SCI1_SCR:
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self.scr = value
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elif address == SCI1_TDR:
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self.tdr = value
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self._write_tdr(value)
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elif address == SCI1_SSR:
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# The real SSR is R/(W)*: writable zeroes clear latched flags after
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# the required read sequence. This scaffold applies zero bits
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# directly so ROM BCLR/BSET style accesses can be modeled.
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self.ssr = value
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elif address == SCI1_RDR:
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self.rdr = value
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else:
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raise KeyError(address)
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def _write_tdr(self, value: int) -> None:
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emitted = bool(self.scr & SCI_SCR_TE)
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if emitted:
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self.tx_bytes.append(value)
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self._frame_buffer.append(value)
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if len(self._frame_buffer) == len(HEARTBEAT_FRAME):
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self.tx_frames.append(bytes(self._frame_buffer))
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self._frame_buffer.clear()
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self.ssr |= SCI_SSR_TDRE
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self.tx_events.append(SciTxEvent(SCI1_TDR, value, self.scr, self.ssr, emitted))
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def inject_rx(self, value: int) -> None:
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self.rdr = value & 0xFF
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self.ssr |= SCI_SSR_RDRF
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def saw_heartbeat(self) -> bool:
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return HEARTBEAT_FRAME in self.tx_frames
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@dataclass
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class MemoryAccess:
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address: int
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size: int
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value: int
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kind: str
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region: str
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class MemoryMap:
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def __init__(self, rom_bytes: bytes, sci1: SCI1 | None = None) -> None:
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self.rom = Rom(rom_bytes, base=0)
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self.sci1 = sci1 if sci1 is not None else SCI1()
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self.ram = bytearray(ON_CHIP_RAM_END - ON_CHIP_RAM_START + 1)
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self.registers = bytearray(REGISTER_FIELD_END - REGISTER_FIELD_START + 1)
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self.external: dict[int, int] = {}
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self.access_log: list[MemoryAccess] = []
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self._set_register(SCI1_SMR, self.sci1.smr)
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self._set_register(SCI1_BRR, self.sci1.brr)
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self._set_register(SCI1_SCR, self.sci1.scr)
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self._set_register(SCI1_TDR, self.sci1.tdr)
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self._set_register(SCI1_SSR, self.sci1.ssr)
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self._set_register(SCI1_RDR, self.sci1.rdr)
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def region(self, address: int) -> MemoryRegion:
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return region_for(address & 0xFFFF)
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def read8(self, address: int) -> int:
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address &= 0xFFFF
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if address in (SCI1_SMR, SCI1_BRR, SCI1_SCR, SCI1_TDR, SCI1_SSR, SCI1_RDR):
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value = self.sci1.read(address)
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self._set_register(address, value)
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elif ON_CHIP_RAM_START <= address <= ON_CHIP_RAM_END:
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value = self.ram[address - ON_CHIP_RAM_START]
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elif REGISTER_FIELD_START <= address <= REGISTER_FIELD_END:
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value = self.registers[address - REGISTER_FIELD_START]
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elif self.rom.contains(address):
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value = self.rom.u8(address)
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else:
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value = self.external.get(address, 0xFF)
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self._log("read", address, 1, value)
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return value
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def read16(self, address: int) -> int:
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high = self.read8(address)
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low = self.read8((address + 1) & 0xFFFF)
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return (high << 8) | low
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def write8(self, address: int, value: int) -> None:
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address &= 0xFFFF
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value &= 0xFF
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if address in (SCI1_SMR, SCI1_BRR, SCI1_SCR, SCI1_TDR, SCI1_SSR, SCI1_RDR):
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self.sci1.write(address, value)
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self._set_register(address, self.sci1.read(address))
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elif ON_CHIP_RAM_START <= address <= ON_CHIP_RAM_END:
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self.ram[address - ON_CHIP_RAM_START] = value
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elif REGISTER_FIELD_START <= address <= REGISTER_FIELD_END:
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self._set_register(address, value)
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elif self.rom.contains(address):
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# ROM writes are logged but ignored. This keeps the scaffold useful
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# for accidental writes without mutating the loaded image.
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pass
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else:
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self.external[address] = value
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self._log("write", address, 1, value)
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def write16(self, address: int, value: int) -> None:
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self.write8(address, (value >> 8) & 0xFF)
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self.write8((address + 1) & 0xFFFF, value & 0xFF)
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def _set_register(self, address: int, value: int) -> None:
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self.registers[address - REGISTER_FIELD_START] = value & 0xFF
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def _log(self, kind: str, address: int, size: int, value: int) -> None:
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self.access_log.append(MemoryAccess(address, size, value, kind, self.region(address).name))
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@dataclass
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class CPUState:
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pc: int = 0
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sr: int = 0
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br: int = 0
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regs: list[int] = field(default_factory=lambda: [0] * 8)
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cycles: int = 0
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steps: int = 0
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z: bool = False
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@dataclass
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class RunReport:
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steps: int
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cycles: int
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pc: int
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stopped_reason: str
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tx_bytes: bytes
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tx_frames: list[bytes]
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heartbeat_seen: bool
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unsupported: str | None = None
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trace: list[str] = field(default_factory=list)
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def summary_lines(self) -> list[str]:
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lines = [
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f"steps={self.steps}",
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f"cycles={self.cycles}",
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f"pc={h16(self.pc)}",
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f"stopped={self.stopped_reason}",
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"tx_bytes=" + self.tx_bytes.hex(" ").upper(),
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"tx_frames=" + ", ".join(frame.hex(" ").upper() for frame in self.tx_frames),
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f"heartbeat_seen={self.heartbeat_seen}",
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]
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if self.unsupported:
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lines.append(f"unsupported={self.unsupported}")
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lines.append("next_todo=implement the stopped opcode, then add interrupt scheduling for SCI1 TXI and interval/watchdog timer overflow")
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return lines
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class H8536Emulator:
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def __init__(self, rom_bytes: bytes) -> None:
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if not rom_bytes:
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raise ValueError("ROM image is empty")
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self.sci1 = SCI1()
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self.memory = MemoryMap(rom_bytes, self.sci1)
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self.cpu = CPUState()
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self.vectors = read_vectors_min(self.memory.rom)
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self.reset()
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def reset(self) -> None:
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self.cpu = CPUState(pc=self.reset_vector())
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def reset_vector(self) -> int:
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if self.memory.rom.contains(0, 2):
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return self.memory.rom.u16(0)
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raise DecodeError("ROM does not contain a reset vector at H'0000")
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def step(self) -> str:
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pc = self.cpu.pc
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decoder = H8536Decoder(self.memory.rom, br=self.cpu.br)
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ins = decoder.decode(pc)
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if not ins.valid:
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raise UnsupportedInstruction(pc, ins.raw, ins.text)
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next_pc = (pc + ins.size) & 0xFFFF
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raw = ins.raw
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text = ins.text
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if raw[0] == 0x00:
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pass
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elif 0x58 <= raw[0] <= 0x5F and len(raw) == 3:
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self.cpu.regs[raw[0] & 0x07] = int.from_bytes(raw[1:3], "big")
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elif raw[:2] == bytes([0x0C, 0x07]) and len(raw) == 4:
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self.cpu.sr = int.from_bytes(raw[2:4], "big")
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elif raw[0] in (0x15, 0x1D) and len(raw) >= 4:
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next_pc = self._execute_general_abs(raw, pc, next_pc)
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elif raw[0] in range(0x20, 0x30) and len(raw) == 2:
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next_pc = self._branch8(raw, pc, next_pc)
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elif raw[0] in range(0x30, 0x40) and len(raw) == 3:
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next_pc = self._branch16(raw, pc, next_pc)
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else:
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raise UnsupportedInstruction(pc, raw, text)
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self.cpu.pc = next_pc
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self.cpu.steps += 1
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self.cpu.cycles += self._rough_cycles(raw)
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return f"{h16(pc)}: {' '.join(f'{byte:02X}' for byte in raw):<17} {text}"
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def run(self, max_steps: int, trace: bool = False, stop_on_heartbeat: bool = False) -> RunReport:
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trace_lines: list[str] = []
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stopped_reason = "max_steps"
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unsupported: str | None = None
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for _ in range(max_steps):
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try:
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line = self.step()
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except UnsupportedInstruction as exc:
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stopped_reason = "unsupported_instruction"
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unsupported = str(exc)
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break
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if trace:
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trace_lines.append(line)
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if stop_on_heartbeat and self.sci1.saw_heartbeat():
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stopped_reason = "heartbeat"
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break
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return RunReport(
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steps=self.cpu.steps,
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cycles=self.cpu.cycles,
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pc=self.cpu.pc,
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stopped_reason=stopped_reason,
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tx_bytes=bytes(self.sci1.tx_bytes),
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tx_frames=list(self.sci1.tx_frames),
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heartbeat_seen=self.sci1.saw_heartbeat(),
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unsupported=unsupported,
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trace=trace_lines,
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)
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def _execute_general_abs(self, raw: bytes, pc: int, next_pc: int) -> int:
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size = "W" if raw[0] == 0x1D else "B"
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address = int.from_bytes(raw[1:3], "big")
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op = raw[3]
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if op == 0x06:
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value = raw[4]
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self.memory.write8(address, value)
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elif op == 0x07:
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value = int.from_bytes(raw[4:6], "big")
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self.memory.write16(address, value)
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elif 0x90 <= op <= 0x97:
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reg = self.cpu.regs[op & 0x07]
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if size == "W":
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self.memory.write16(address, reg)
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else:
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self.memory.write8(address, reg & 0xFF)
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elif 0x80 <= op <= 0x87:
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reg = op & 0x07
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self.cpu.regs[reg] = self.memory.read16(address) if size == "W" else self.memory.read8(address)
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elif 0xC0 <= op <= 0xCF:
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bit = op & 0x0F
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self.memory.write8(address, self.memory.read8(address) | (1 << bit))
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elif 0xD0 <= op <= 0xDF:
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bit = op & 0x0F
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self.memory.write8(address, self.memory.read8(address) & ~(1 << bit))
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elif 0xF0 <= op <= 0xFF:
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bit = op & 0x0F
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self.cpu.z = not bool(self.memory.read8(address) & (1 << bit))
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elif op in (0x04, 0x05):
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if op == 0x04:
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value = raw[4]
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actual = self.memory.read8(address)
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else:
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value = int.from_bytes(raw[4:6], "big")
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actual = self.memory.read16(address)
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self.cpu.z = actual == value
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elif op == 0x08:
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value = self.memory.read16(address) if size == "W" else self.memory.read8(address)
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value = (value + 1) & (0xFFFF if size == "W" else 0xFF)
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if size == "W":
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self.memory.write16(address, value)
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else:
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self.memory.write8(address, value)
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self.cpu.z = value == 0
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else:
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raise UnsupportedInstruction(pc, raw, H8536Decoder(self.memory.rom, br=self.cpu.br).decode(pc).text)
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return next_pc
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def _branch8(self, raw: bytes, pc: int, next_pc: int) -> int:
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cond = raw[0] & 0x0F
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disp = _s8(raw[1])
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target = (pc + 2 + disp) & 0xFFFF
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if cond == 0x0:
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return target
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if cond == 0x7 and self.cpu.z:
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return target
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if cond == 0x6 and not self.cpu.z:
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return target
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return next_pc
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def _branch16(self, raw: bytes, pc: int, next_pc: int) -> int:
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cond = raw[0] & 0x0F
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disp = _s16(int.from_bytes(raw[1:3], "big"))
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target = (pc + 3 + disp) & 0xFFFF
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if cond == 0x0:
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return target
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if cond == 0x7 and self.cpu.z:
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return target
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if cond == 0x6 and not self.cpu.z:
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return target
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return next_pc
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def _rough_cycles(self, raw: bytes) -> int:
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if raw[0] in (0x15, 0x1D):
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return 9
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if raw[0] in range(0x20, 0x40):
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return 8 if (raw[0] & 0x0F) == 0 else 4
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return 3
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def _s8(value: int) -> int:
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return value - 0x100 if value & 0x80 else value
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def _s16(value: int) -> int:
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return value - 0x10000 if value & 0x8000 else value
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def discover_rom_path(root: Path) -> Path | None:
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candidates = [
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root / "ROM" / "M27C512@DIP28_1.BIN",
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root / "rom.bin",
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]
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candidates.extend(sorted((root / "ROM").glob("*.BIN")) if (root / "ROM").exists() else [])
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candidates.extend(sorted((root / "ROM").glob("*.bin")) if (root / "ROM").exists() else [])
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for candidate in candidates:
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if candidate.is_file():
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return candidate
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return None
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def load_rom(path: Path | None = None, root: Path | None = None) -> tuple[bytes, Path]:
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root = root if root is not None else Path.cwd()
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rom_path = path if path is not None else discover_rom_path(root)
|
||||
if rom_path is None:
|
||||
raise FileNotFoundError(
|
||||
"could not discover ROM bytes; pass --rom PATH, expected ROM/M27C512@DIP28_1.BIN or another ROM/*.BIN"
|
||||
)
|
||||
return rom_path.read_bytes(), rom_path
|
||||
|
||||
|
||||
def describe_regions(regions: Iterable[MemoryRegion] = MEMORY_REGIONS) -> str:
|
||||
return "\n".join(f"{h16(region.start)}-{h16(region.end)} {region.name} {region.kind}" for region in regions)
|
||||
|
||||
|
||||
def build_arg_parser() -> argparse.ArgumentParser:
|
||||
parser = argparse.ArgumentParser(description="Minimal H8/536 emulation harness scaffold")
|
||||
parser.add_argument("--rom", type=Path, help="ROM image path; defaults to ROM/M27C512@DIP28_1.BIN when present")
|
||||
parser.add_argument("--max-steps", type=int, default=64, help="maximum CPU steps to execute")
|
||||
parser.add_argument("--trace", action="store_true", help="print decoded/executed instruction trace")
|
||||
parser.add_argument("--stop-on-heartbeat", action="store_true", help="stop only when 00 00 00 00 80 DA is emitted through SCI1 TDR")
|
||||
parser.add_argument("--memory-map", action="store_true", help="print the scaffolded memory map before running")
|
||||
return parser
|
||||
|
||||
|
||||
def main(argv: list[str] | None = None) -> int:
|
||||
args = build_arg_parser().parse_args(argv)
|
||||
try:
|
||||
rom_bytes, rom_path = load_rom(args.rom)
|
||||
except FileNotFoundError as exc:
|
||||
print(str(exc))
|
||||
return 2
|
||||
|
||||
emulator = H8536Emulator(rom_bytes)
|
||||
print(f"rom={rom_path}")
|
||||
print(f"reset_vector={h16(emulator.reset_vector())}")
|
||||
if args.memory_map:
|
||||
print(describe_regions())
|
||||
report = emulator.run(args.max_steps, trace=args.trace, stop_on_heartbeat=args.stop_on_heartbeat)
|
||||
if args.trace:
|
||||
for line in report.trace:
|
||||
print(line)
|
||||
for line in report.summary_lines():
|
||||
print(line)
|
||||
if not report.heartbeat_seen:
|
||||
print("heartbeat_status=not reached; no heartbeat is reported unless bytes are emitted via SCI1_TDR")
|
||||
return 0
|
||||
Reference in New Issue
Block a user