aiden/h8-536-decoder
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command advance sweep

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Aiden
2026-05-26 15:21:52 +10:00
parent 74a2e2fd2c
commit a48fa0ed18
14 changed files with 821 additions and 78 deletions
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29
tests/test_emulator_sci_timing.py
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@@ -83,6 +83,35 @@ class SciTimingTest(unittest.TestCase):
self.assertAlmostEqual(timing.micros_per_character(), 260.416666, places=3)
self.assertEqual(timing.cycles_per_character(10_000_000), 2604)
def test_uart_8e1_38400_byte_timing_matches_bench_link(self):
timing = UartTiming.from_format("8E1", baud=38_400)
self.assertEqual(timing.bits_per_character, 11)
self.assertAlmostEqual(timing.micros_per_character(), 286.458333, places=3)
self.assertEqual(timing.cycles_per_character(10_000_000), 2865)
self.assertEqual(timing.summary(10_000_000).split()[0], "uart_8E1")
def test_uart_timing_can_be_derived_from_sci_smr(self):
timing = UartTiming.from_sci_smr(0x24, baud=38_400)
self.assertEqual((timing.data_bits, timing.parity, timing.stop_bits), (8, "E", 1))
def test_tdr_write_can_use_uart_character_time_for_tdre(self):
sci = SCI1()
sci.configure_tx_timing(UartTiming.from_format("8E1", baud=38_400), clock_hz=10_000_000)
sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
sci.write(SCI1_TDR, 0x42)
sci.write(SCI1_SSR, sci.read(SCI1_SSR) & ~SCI_SSR_TDRE)
self.assertTrue(sci.tx_busy())
self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
sci.tick(2864)
self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
sci.tick(1)
self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
self.assertFalse(sci.tx_busy())
if __name__ == "__main__":
unittest.main()