command advance sweep

tests/test_connect_ok_advance_sweep.py

@@ -0,0 +1,52 @@
+import io
+import unittest
+
+from h8536.connect_ok_advance_sweep import build_cases, main, _matches_target
+
+
+class ConnectOkAdvanceSweepTest(unittest.TestCase):
+    def test_core_suite_starts_with_ack_then_refresh(self):
+        cases = build_cases("core")
+
+        self.assertEqual([case.name for case in cases], ["ack-0040", "refresh-ok"])
+        self.assertEqual(cases[0].frame.hex().upper(), "05004000001F")
+        self.assertEqual(cases[1].frame.hex().upper(), "0400008000DE")
+
+    def test_latch_suite_includes_special_clear_candidates(self):
+        names = [case.name for case in build_cases("latch")]
+
+        self.assertIn("ack-0096", names)
+        self.assertIn("ack-00f8", names)
+
+    def test_dry_run_defaults_to_reactive_active_report_window(self):
+        stdout = io.StringIO()
+
+        exit_code = main(["--dry-run", "--suite", "core", "--limit", "1"], stdout=stdout)
+
+        self.assertEqual(exit_code, 0)
+        output = stdout.getvalue()
+        self.assertIn("device=COM5 38400 8E1", output)
+        self.assertIn("target_mode=active", output)
+        self.assertIn("baseline[1]=04 00 00 80 00 DE checksum_ok=1", output)
+        self.assertIn("case[1]=ack-0040 frame=05 00 40 00 00 1F checksum_ok=1", output)
+
+    def test_custom_candidate_accepts_five_bytes_and_computes_checksum(self):
+        stdout = io.StringIO()
+
+        exit_code = main(["--dry-run", "--candidate", "probe=05 00 6D 00 00"], stdout=stdout)
+
+        self.assertEqual(exit_code, 0)
+        self.assertIn("case[1]=probe frame=05 00 6D 00 00 32 checksum_ok=1", stdout.getvalue())
+
+    def test_active_target_ignores_heartbeat_but_accepts_report(self):
+        self.assertFalse(_matches_target(bytes.fromhex("0000000080DA"), "active"))
+        self.assertTrue(_matches_target(bytes.fromhex("02000200005A"), "active"))
+        self.assertTrue(_matches_target(bytes.fromhex("07804040A07D"), "active"))
+
+    def test_connect_ok_target_requires_known_ok_response(self):
+        self.assertTrue(_matches_target(bytes.fromhex("02000200005A"), "connect-ok"))
+        self.assertFalse(_matches_target(bytes.fromhex("010012000049"), "connect-ok"))
+
+
+if __name__ == "__main__":
+    unittest.main()

tests/test_emulator.py

@@ -176,6 +176,21 @@ class EmulatorHarnessTest(unittest.TestCase):
 
         self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 0x99)
 
+    def test_memory_access_log_records_executing_pc(self):
+        rom = rom_with_reset(size=0x1010)
+        rom[0x1000:0x1005] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x06, 0x77])
+
+        emulator = H8536Emulator(bytes(rom))
+        emulator.run(max_steps=1)
+
+        writes = [
+            access
+            for access in emulator.memory.access_log
+            if access.kind == "write" and access.address == ON_CHIP_RAM_START
+        ]
+        self.assertEqual(writes[-1].value, 0x77)
+        self.assertEqual(writes[-1].pc, 0x1000)
+
 
 if __name__ == "__main__":
     unittest.main()

tests/test_emulator_sci_timing.py

@@ -83,6 +83,35 @@ class SciTimingTest(unittest.TestCase):
         self.assertAlmostEqual(timing.micros_per_character(), 260.416666, places=3)
         self.assertEqual(timing.cycles_per_character(10_000_000), 2604)
 
+    def test_uart_8e1_38400_byte_timing_matches_bench_link(self):
+        timing = UartTiming.from_format("8E1", baud=38_400)
+
+        self.assertEqual(timing.bits_per_character, 11)
+        self.assertAlmostEqual(timing.micros_per_character(), 286.458333, places=3)
+        self.assertEqual(timing.cycles_per_character(10_000_000), 2865)
+        self.assertEqual(timing.summary(10_000_000).split()[0], "uart_8E1")
+
+    def test_uart_timing_can_be_derived_from_sci_smr(self):
+        timing = UartTiming.from_sci_smr(0x24, baud=38_400)
+
+        self.assertEqual((timing.data_bits, timing.parity, timing.stop_bits), (8, "E", 1))
+
+    def test_tdr_write_can_use_uart_character_time_for_tdre(self):
+        sci = SCI1()
+        sci.configure_tx_timing(UartTiming.from_format("8E1", baud=38_400), clock_hz=10_000_000)
+        sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
+
+        sci.write(SCI1_TDR, 0x42)
+        sci.write(SCI1_SSR, sci.read(SCI1_SSR) & ~SCI_SSR_TDRE)
+
+        self.assertTrue(sci.tx_busy())
+        self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+        sci.tick(2864)
+        self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+        sci.tick(1)
+        self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+        self.assertFalse(sci.tx_busy())
+
 
 if __name__ == "__main__":
     unittest.main()