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command advance sweep

This commit is contained in:
Aiden
2026-05-26 15:21:52 +10:00
parent 74a2e2fd2c
commit a48fa0ed18
14 changed files with 821 additions and 78 deletions

View File

@@ -17,6 +17,7 @@ from .constants import (
SCI_SSR_RDRF,
SCI_SSR_TDRE,
)
from .uart import UartTiming
@dataclass
@@ -53,6 +54,8 @@ class SCI1:
_frame_buffer: bytearray = field(default_factory=bytearray)
tx_ready_delay: int = 0
tx_ready_ticks: int = 2
clock_hz: int = 10_000_000
tx_timing: UartTiming | None = None
_tx_ready_pending: bool = False
def read(self, address: int) -> int:
@@ -96,7 +99,7 @@ class SCI1:
if len(self._frame_buffer) == len(HEARTBEAT_FRAME):
self.tx_frames.append(bytes(self._frame_buffer))
self._frame_buffer.clear()
self.tx_ready_delay = max(0, self.tx_ready_ticks)
self.tx_ready_delay = self._tx_ready_delay()
self._tx_ready_pending = True
self.tx_events.append(SciTxEvent(SCI1_TDR, value, self.scr, self.ssr, emitted))
@@ -116,9 +119,22 @@ class SCI1:
def saw_heartbeat(self) -> bool:
return HEARTBEAT_FRAME in self.tx_frames
def tick(self) -> None:
def configure_tx_timing(self, timing: UartTiming | None, *, clock_hz: int | None = None) -> None:
self.tx_timing = timing
if clock_hz is not None:
self.clock_hz = max(1, clock_hz)
def tx_busy(self) -> bool:
return self._tx_ready_pending and self.tx_ready_delay > 0
def tick(self, cycles: int = 1) -> None:
if self._tx_ready_pending and self.tx_ready_delay:
self.tx_ready_delay -= 1
self.tx_ready_delay = max(0, self.tx_ready_delay - max(1, cycles))
if self._tx_ready_pending and self.tx_ready_delay == 0 and not (self.ssr & SCI_SSR_TDRE):
self.ssr |= SCI_SSR_TDRE
self._tx_ready_pending = False
def _tx_ready_delay(self) -> int:
if self.tx_timing is None:
return max(0, self.tx_ready_ticks)
return self.tx_timing.cycles_per_character(self.clock_hz)