aiden/h8-536-decoder
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Emulator improvements

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This commit is contained in:
Aiden
2026-05-25 17:55:07 +10:00
parent b264037e82
commit 9d93d88840
2 changed files with 523 additions and 59 deletions
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66
tests/test_emulator.py
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@@ -3,6 +3,8 @@ from pathlib import Path
from h8536.emulator import (
HEARTBEAT_FRAME,
IPRA,
IPRE,
ON_CHIP_RAM_START,
REGISTER_FIELD_START,
SCI1_SCR,
@@ -18,6 +20,12 @@ from h8536.emulator import (
)
def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1100) -> bytearray:
rom = bytearray([0xFF] * size)
rom[0:2] = reset.to_bytes(2, "big")
return rom
class EmulatorHarnessTest(unittest.TestCase):
def test_memory_map_routes_rom_ram_register_and_external(self):
memory = MemoryMap(bytes([0x12, 0x34, 0x56, 0x78]))
@@ -71,6 +79,64 @@ class EmulatorHarnessTest(unittest.TestCase):
self.assertEqual(report.steps, 4)
self.assertFalse(report.heartbeat_seen)
def test_scb_false_decrements_and_branches_until_zero(self):
rom = rom_with_reset()
rom[0x1000:0x1003] = b"\x58\x00\x03" # MOV:I.W #H'0003, R0
rom[0x1003:0x1006] = b"\x01\xB8\xFD" # SCB/F R0, H'1003
emulator = H8536Emulator(bytes(rom))
report = emulator.run(max_steps=4)
self.assertEqual(report.stopped_reason, "max_steps")
self.assertEqual(emulator.cpu.regs[0], 0)
self.assertEqual(emulator.cpu.pc, 0x1006)
def test_bsr_rts_and_stack_restore_return_to_caller(self):
rom = rom_with_reset()
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
rom[0x1003:0x1005] = b"\x0E\x03" # BSR H'1008
rom[0x1005:0x1008] = b"\x59\x12\x34" # MOV:I.W #H'1234, R1
rom[0x1008:0x100B] = b"\x58\xAB\xCD" # MOV:I.W #H'ABCD, R0
rom[0x100B] = 0x19 # RTS
emulator = H8536Emulator(bytes(rom))
emulator.run(max_steps=5)
self.assertEqual(emulator.cpu.regs[0], 0xABCD)
self.assertEqual(emulator.cpu.regs[1], 0x1234)
self.assertEqual(emulator.cpu.regs[7], 0xFE80)
def test_sci1_txi_interrupt_can_emit_through_tdr(self):
rom = rom_with_reset(size=0x1040)
rom[0x0084:0x0086] = (0x1010).to_bytes(2, "big")
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
rom[0x1003:0x1008] = bytes([0x15, (IPRE >> 8) & 0xFF, IPRE & 0xFF, 0x06, 0x50])
rom[0x1008:0x100D] = bytes([0x15, (SCI1_SCR >> 8) & 0xFF, SCI1_SCR & 0xFF, 0x06, 0xA0])
rom[0x100D] = 0x00 # NOP after interrupt return
rom[0x1010:0x1015] = bytes([0x15, (SCI1_SCR >> 8) & 0xFF, SCI1_SCR & 0xFF, 0x06, SCI_SCR_TE])
rom[0x1015:0x101A] = bytes([0x15, (SCI1_TDR >> 8) & 0xFF, SCI1_TDR & 0xFF, 0x06, 0x42])
rom[0x101A] = 0x0A # RTE
emulator = H8536Emulator(bytes(rom))
report = emulator.run(max_steps=8)
self.assertEqual(bytes(emulator.sci1.tx_bytes), b"\x42")
self.assertFalse(report.heartbeat_seen)
def test_interval_interrupt_vector_can_fire(self):
rom = rom_with_reset(size=0x1040)
rom[0x0042:0x0044] = (0x1020).to_bytes(2, "big")
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
rom[0x1003:0x1008] = bytes([0x15, (IPRA >> 8) & 0xFF, IPRA & 0xFF, 0x06, 0x70])
rom[0x1008:0x100A] = b"\x20\xFC" # BRA H'1006-ish idle loop
rom[0x1020:0x1025] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x06, 0x99])
rom[0x1025] = 0x0A # RTE
emulator = H8536Emulator(bytes(rom), interval_steps=2)
emulator.run(max_steps=8)
self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 0x99)
if __name__ == "__main__":
unittest.main()