DTC and SCI improvements

h8536/tables.py

@@ -43,10 +43,12 @@ IO_REGISTERS: dict[int, str] = {
     0xFE91: "FRT1_TCSR",
     0xFE92: "FRT1_FRC_H",
     0xFE93: "FRT1_FRC_L",
-    0xFE94: "FRT1_OCRA_L",
-    0xFE95: "FRT1_OCRB_L",
-    0xFE96: "FRT1_ICR_H",
-    0xFE97: "FRT1_ICR_L",
+    0xFE94: "FRT1_OCRA_H",
+    0xFE95: "FRT1_OCRA_L",
+    0xFE96: "FRT1_OCRB_H",
+    0xFE97: "FRT1_OCRB_L",
+    0xFE98: "FRT1_ICR_H",
+    0xFE99: "FRT1_ICR_L",
     0xFEA0: "FRT2_TCR",
     0xFEA1: "FRT2_TCSR",
     0xFEA2: "FRT2_FRC_H",
@@ -129,6 +131,54 @@ IO_REGISTERS: dict[int, str] = {
 }
 
 
+IO_PRIORITY_FIELDS: dict[int, tuple[tuple[int, str], ...]] = {
+    0xFF00: ((4, "irq0"), (0, "irq1")),
+    0xFF01: ((4, "irq2/irq3"), (0, "irq4/irq5")),
+    0xFF02: ((4, "FRT1"), (0, "FRT2")),
+    0xFF03: ((4, "FRT3"), (0, "8-bit timer")),
+    0xFF04: ((4, "SCI1"), (0, "SCI2")),
+    0xFF05: ((4, "A/D"),),
+}
+
+
+IO_DTE_BITS: dict[int, dict[int, str]] = {
+    0xFF08: {
+        4: "irq0",
+        0: "irq1",
+    },
+    0xFF09: {
+        5: "irq3",
+        4: "irq2",
+        1: "irq5",
+        0: "irq4",
+    },
+    0xFF0A: {
+        6: "FRT1 OCIB",
+        5: "FRT1 OCIA",
+        4: "FRT1 ICI",
+        2: "FRT2 OCIB",
+        1: "FRT2 OCIA",
+        0: "FRT2 ICI",
+    },
+    0xFF0B: {
+        6: "FRT3 OCIB",
+        5: "FRT3 OCIA",
+        4: "FRT3 ICI",
+        1: "8-bit timer CMIB",
+        0: "8-bit timer CMIA",
+    },
+    0xFF0C: {
+        6: "SCI1 TXI",
+        5: "SCI1 RXI",
+        2: "SCI2 TXI",
+        1: "SCI2 RXI",
+    },
+    0xFF0D: {
+        4: "A/D ADI",
+    },
+}
+
+
 _FRT_TCR_BITS = {
     7: "ICIE",
     6: "OCIEB",