aiden/h8-536-decoder
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DTC and SCI improvements

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Aiden
2026-05-25 14:22:32 +10:00
parent 62d1c3c876
commit 80819448cf
21 changed files with 13823 additions and 86 deletions
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30
build/rom_pseudocode.c
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@@ -32,7 +32,7 @@ extern volatile u8 P7DR; /* 0xFE8E */
extern volatile u8 FRT1_TCR; /* 0xFE90 */
extern volatile u8 FRT1_TCSR; /* 0xFE91 */
extern volatile u16 FRT1_FRC_H; /* 0xFE92 */
extern volatile u16 FRT1_OCRA_L; /* 0xFE94 */
extern volatile u16 FRT1_OCRA_H; /* 0xFE94 */
extern volatile u8 FRT2_TCR; /* 0xFEA0 */
extern volatile u8 FRT2_TCSR; /* 0xFEA1 */
extern volatile u16 FRT2_FRC_H; /* 0xFEA2 */
@@ -180,12 +180,12 @@ void vec_reset_1000(void)
SYSCR2 = (uint8_t)(0x84); /* 1034; MOV:G.B #H'84, @SYSCR2; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); cycles=9 */
FRT1_TCR = (uint8_t)(0x02); /* 1039; MOV:G.B #H'02, @FRT1_TCR; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 */
FRT1_TCSR = (uint8_t)(0x01); /* 103E; MOV:G.B #H'01, @FRT1_TCSR; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 */
FRT1_FRC_H = (uint16_t)(0x00); /* 1043; MOV:G.W #H'00, @FRT1_FRC_H; FRT1_FRC_H = H'00; cycles=9 */
FRT1_OCRA_L = (uint16_t)(0x009C); /* 1048; MOV:G.W #H'009C, @FRT1_OCRA_L; FRT1_OCRA_L = H'9C; cycles=11 */
FRT1_FRC_H = (uint16_t)(0x00); /* 1043; MOV:G.W #H'00, @FRT1_FRC_H; FRT1_FRC_H = H'00; FRT1_FRC W write high TEMP access; cycles=9 */
FRT1_OCRA_H = (uint16_t)(0x009C); /* 1048; MOV:G.W #H'009C, @FRT1_OCRA_H; FRT1_OCRA_H = H'9C; FRT1_OCRA W write high TEMP access; cycles=11 */
FRT2_TCR = (uint8_t)(0x02); /* 104E; MOV:G.B #H'02, @FRT2_TCR; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 */
FRT2_TCSR = (uint8_t)(0x01); /* 1053; MOV:G.B #H'01, @FRT2_TCSR; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 */
FRT2_FRC_H = (uint16_t)(0x00); /* 1058; MOV:G.W #H'00, @FRT2_FRC_H; FRT2_FRC_H = H'00; cycles=11 */
FRT2_OCRA_H = (uint16_t)(0x7A12); /* 105D; MOV:G.W #H'7A12, @FRT2_OCRA_H; FRT2_OCRA_H = H'7A12; cycles=9 */
FRT2_FRC_H = (uint16_t)(0x00); /* 1058; MOV:G.W #H'00, @FRT2_FRC_H; FRT2_FRC_H = H'00; FRT2_FRC W write high TEMP access; cycles=11 */
FRT2_OCRA_H = (uint16_t)(0x7A12); /* 105D; MOV:G.W #H'7A12, @FRT2_OCRA_H; FRT2_OCRA_H = H'7A12; FRT2_OCRA W write high TEMP access; cycles=9 */
FRT3_TCR = (uint8_t)(0x00); /* 1063; MOV:G.B #H'00, @FRT3_TCR; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 */
FRT3_TCSR = (uint8_t)(0x00); /* 1068; MOV:G.B #H'00, @FRT3_TCSR; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 */
TMR_TCR = (uint8_t)(0x00); /* 106D; MOV:G.B #H'00, @TMR_TCR; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 */
@@ -198,10 +198,10 @@ void vec_reset_1000(void)
PWM3_DTR = (uint8_t)(0x7D); /* 1090; MOV:G.B #H'7D, @PWM3_DTR; PWM3_DTR = H'7D; cycles=9 */
SCI1_SMR = (uint8_t)(0x24); /* 1095; MOV:G.B #H'24, @SCI1_SMR; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9 */
SCI1_SCR = (uint8_t)(0x3C); /* 109A; MOV:G.B #H'3C, @SCI1_SCR; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); cycles=9 */
SCI1_BRR = (uint8_t)(0x07); /* 109F; MOV:G.B #H'07, @SCI1_BRR; SCI1_BRR = H'07; cycles=9 */
SCI1_BRR = (uint8_t)(0x07); /* 109F; MOV:G.B #H'07, @SCI1_BRR; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; cycles=9 */
SCI2_SMR = (uint8_t)(0x24); /* 10A4; MOV:G.B #H'24, @SCI2_SMR; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9 */
SCI2_SCR = (uint8_t)(0x0C); /* 10A9; MOV:G.B #H'0C, @SCI2_SCR; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); cycles=9 */
SCI2_BRR = (uint8_t)(0x07); /* 10AE; MOV:G.B #H'07, @SCI2_BRR; SCI2_BRR = H'07; cycles=9 */
SCI2_BRR = (uint8_t)(0x07); /* 10AE; MOV:G.B #H'07, @SCI2_BRR; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; cycles=9 */
ADCSR = (uint8_t)(0x19); /* 10B3; MOV:G.B #H'19, @ADCSR; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 */
MEM8[0xFEE9] = (uint8_t)(0x7F); /* 10B8; MOV:G.B #H'7F, @H'FEE9; cycles=9 */
WCR = (uint8_t)(0xF0); /* 10BD; MOV:G.B #H'F0, @WCR; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 */
@@ -1629,7 +1629,7 @@ void vec_ad_adi_3D99(void)
push_registers(R0, R1, R2, R3, R4, R5); /* 3D9D; STM.W {R0,R1,R2,R3,R4,R5}, @-SP; cycles=24 */
R0 = (uint8_t)(MEM8[0xF68A]); /* 3D9F; MOV:G.B @H'F68A, R0; cycles=6 */
R0 = mulxu8(R0, 0x14); /* 3DA3; MULXU.B #H'14, R0; cycles=19 */
R1 = (uint16_t)(ADDRA_H); /* 3DA6; MOV:G.W @ADDRA_H, R1; cycles=7 */
R1 = (uint16_t)(ADDRA_H); /* 3DA6; MOV:G.W @ADDRA_H, R1; ADDRA W read high TEMP access; cycles=7 */
R1 = swap_bytes(R1); /* 3DAA; SWAP.B R1; cycles=3 */
R1 = zero_extend8(R1); /* 3DAC; EXTU.B R1; cycles=3 */
R1 = (uint8_t)(MEM8[R1 - 0x304A]); /* 3DAE; MOV:G.B @(-H'304A,R1), R1; cycles=7 */
@@ -1668,7 +1668,7 @@ loc_3DFA:
loc_3E08:
R0 = (uint8_t)(MEM8[0xF68B]); /* 3E08; MOV:G.B @H'F68B, R0; cycles=7 */
R0 = mulxu8(R0, 0x14); /* 3E0C; MULXU.B #H'14, R0; cycles=19 */
R1 = (uint16_t)(ADDRB_H); /* 3E0F; MOV:G.W @ADDRB_H, R1; cycles=6 */
R1 = (uint16_t)(ADDRB_H); /* 3E0F; MOV:G.W @ADDRB_H, R1; ADDRB W read high TEMP access; cycles=6 */
R1 = swap_bytes(R1); /* 3E13; SWAP.B R1; cycles=3 */
R1 = zero_extend8(R1); /* 3E15; EXTU.B R1; cycles=3 */
R0 += (uint16_t)(R1); /* 3E17; ADD:G.W R1, R0; cycles=3 */
@@ -2138,12 +2138,12 @@ void loc_4324(void)
void loc_434C(void)
{
IPRA = (uint8_t)(0x70); /* 434C; MOV:G.B #H'70, @IPRA; IPRA = H'70; cycles=9 */
IPRB = (uint8_t)(0x44); /* 4351; MOV:G.B #H'44, @IPRB; IPRB = H'44; cycles=9 */
IPRC = (uint8_t)(0x66); /* 4356; MOV:G.B #H'66, @IPRC; IPRC = H'66; cycles=9 */
IPRD = (uint8_t)(0x00); /* 435B; MOV:G.B #H'00, @IPRD; IPRD = H'00; cycles=9 */
IPRE = (uint8_t)(0x50); /* 4360; MOV:G.B #H'50, @IPRE; IPRE = H'50; cycles=9 */
IPRF = (uint8_t)(0x40); /* 4365; MOV:G.B #H'40, @IPRF; IPRF = H'40; cycles=9 */
IPRA = (uint8_t)(0x70); /* 434C; MOV:G.B #H'70, @IPRA; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9 */
IPRB = (uint8_t)(0x44); /* 4351; MOV:G.B #H'44, @IPRB; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9 */
IPRC = (uint8_t)(0x66); /* 4356; MOV:G.B #H'66, @IPRC; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9 */
IPRD = (uint8_t)(0x00); /* 435B; MOV:G.B #H'00, @IPRD; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9 */
IPRE = (uint8_t)(0x50); /* 4360; MOV:G.B #H'50, @IPRE; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9 */
IPRF = (uint8_t)(0x40); /* 4365; MOV:G.B #H'40, @IPRF; IPRF = H'40 (A/D priority=4); cycles=9 */
SCI1_SCR |= BIT(6); /* 436A; BSET.B #6, @SCI1_SCR; set RIE (bit 6) of SCI1_SCR; cycles=9 */
FRT1_TCR |= BIT(5); /* 436E; BSET.B #5, @FRT1_TCR; set OCIEA (bit 5) of FRT1_TCR; cycles=9 */
FRT2_TCR |= BIT(5); /* 4372; BSET.B #5, @FRT2_TCR; set OCIEA (bit 5) of FRT2_TCR; cycles=9 */