aiden/h8-536-decoder
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DTC and SCI improvements

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Aiden
2026-05-25 14:22:32 +10:00
parent 62d1c3c876
commit 80819448cf
21 changed files with 13823 additions and 86 deletions
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116
build/rom_decompiled.asm
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@@ -9,6 +9,8 @@
; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC.
; - The register field is H'FE80-H'FFFF; names below come from appendix B.
; - @aa:8 short absolute operands use BR as the upper address byte.
; - SCI baud inference uses section 14.2.8 BRR formulas when SMR/BRR are known.
; - Pass --clock-hz to convert SCI BRR settings into numeric baud rates.
; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states.
; Memory Map
@@ -138,6 +140,92 @@
; ptrtbl H'B7CC count=3 -> H'F772, H'1627, H'11A0
; ptrtbl H'C212 count=5 -> H'1700, H'1682, H'1664, H'1647, H'1630
; Timing Summary
; Straight-line blocks
; block H'1000-H'10CB vec_reset_1000 ins=42 cycles=371 unknown=0
; block H'10CE-H'1356 loc_10CE ins=217 cycles=1416 unknown=0
; block H'15E0-H'15E7 loc_15E0 ins=3 cycles=24-29 unknown=0
; block H'15E9-H'15F6 loc_15E9 ins=5 cycles=30 unknown=0
; block H'15F9-H'15FD loc_15F9 ins=2 cycles=9-14 unknown=0
; block H'15FF-H'1603 loc_15FF ins=2 cycles=11-16 unknown=0
; block H'1605-H'1605 loc_1605 ins=1 cycles=14 unknown=0
; block H'1608-H'160C loc_1608 ins=2 cycles=12-16 unknown=0
; block H'160E-H'160E loc_160E ins=1 cycles=13 unknown=0
; block H'1611-H'1615 loc_1611 ins=2 cycles=11-16 unknown=0
; block H'1617-H'1617 loc_1617 ins=1 cycles=14 unknown=0
; block H'161A-H'1622 loc_161A ins=3 cycles=21-25 unknown=0
; block H'1624-H'1624 loc_1624 ins=1 cycles=13 unknown=0
; block H'1627-H'162B loc_1627 ins=2 cycles=11-16 unknown=0
; block H'162D-H'162D loc_162D ins=1 cycles=14 unknown=0
; block H'1630-H'1634 loc_1630 ins=2 cycles=12-16 unknown=0
; block H'1636-H'1636 loc_1636 ins=1 cycles=13 unknown=0
; block H'1639-H'1639 loc_1639 ins=1 cycles=8 unknown=0
; block H'163D-H'1641 loc_163D ins=2 cycles=9-14 unknown=0
; block H'1643-H'1647 loc_1643 ins=2 cycles=11-16 unknown=0
; block H'1649-H'1649 loc_1649 ins=1 cycles=14 unknown=0
; block H'164C-H'1650 loc_164C ins=2 cycles=12-16 unknown=0
; block H'1652-H'1652 loc_1652 ins=1 cycles=13 unknown=0
; block H'1655-H'1659 loc_1655 ins=2 cycles=11-16 unknown=0
; block H'165B-H'165B loc_165B ins=1 cycles=14 unknown=0
; block H'165E-H'1662 loc_165E ins=2 cycles=12-16 unknown=0
; block H'1664-H'1664 loc_1664 ins=1 cycles=13 unknown=0
; block H'1667-H'166B loc_1667 ins=2 cycles=11-16 unknown=0
; block H'166D-H'166D loc_166D ins=1 cycles=14 unknown=0
; block H'1670-H'1674 loc_1670 ins=2 cycles=12-16 unknown=0
; block H'1676-H'1676 loc_1676 ins=1 cycles=13 unknown=0
; block H'1679-H'167D loc_1679 ins=2 cycles=11-16 unknown=0
; block H'167F-H'167F loc_167F ins=1 cycles=14 unknown=0
; block H'1682-H'1682 loc_1682 ins=1 cycles=9 unknown=0
; block H'1686-H'168A loc_1686 ins=2 cycles=10-14 unknown=0
; block H'168C-H'1690 loc_168C ins=2 cycles=12-16 unknown=0
; block H'1692-H'1692 loc_1692 ins=1 cycles=13 unknown=0
; block H'1695-H'1699 loc_1695 ins=2 cycles=11-16 unknown=0
; block H'169B-H'169B loc_169B ins=1 cycles=14 unknown=0
; block H'169E-H'16A2 loc_169E ins=2 cycles=12-16 unknown=0
; ... 750 more blocks
; Backward-branch loop candidates
; loop H'1A4B-H'1A55 loc_1A4B delay_loop_candidate cycles/iteration=18-28 back_edge=H'1A55
; loop H'1A5B-H'1A65 loc_1A5B delay_loop_candidate cycles/iteration=18-28 back_edge=H'1A65
; loop H'1A7F-H'1A89 loc_1A7F unconditional_loop cycles/iteration=23-28 back_edge=H'1A89
; loop H'1A45-H'1A8B loc_1A45 loop_with_call cycles/iteration=147-182 back_edge=H'1A8B
; loop H'1A90-H'1A94 loc_1A90 counter_delay_loop cycles/iteration=9-18 back_edge=H'1A94
; loop H'1AAF-H'1AB8 loc_1AAF delay_loop_candidate cycles/iteration=17-21 back_edge=H'1AB8
; loop H'1ABC-H'1AC5 loc_1ABC delay_loop_candidate cycles/iteration=16-21 back_edge=H'1AC5
; loop H'1C0E-H'1C22 loc_1C0E loop_with_call cycles/iteration=67-75 back_edge=H'1C22
; loop H'289F-H'2CB6 loc_289F loop_with_call cycles/iteration=97 back_edge=H'2CB6
; loop H'3933-H'395F loc_3933 counter_delay_loop cycles/iteration=87-107 back_edge=H'395F
; loop H'3E68-H'3E74 loc_3E68 unconditional_loop cycles/iteration=26-34 back_edge=H'3E74
; loop H'3E82-H'3E98 loc_3E82 loop_with_call cycles/iteration=70-75 back_edge=H'3E98
; loop H'3EAE-H'3EBD loc_3EAE unconditional_loop cycles/iteration=30-38 back_edge=H'3EBD
; loop H'3F04-H'3F18 loc_3F04 loop_with_call cycles/iteration=55-63 back_edge=H'3F18
; loop H'3F4A-H'3F51 loc_3F4A delay_loop_candidate cycles/iteration=18-23 back_edge=H'3F51
; loop H'3F7C-H'3F80 loc_3F7C counter_delay_loop cycles/iteration=12-17 back_edge=H'3F80
; loop H'3F83-H'3F87 loc_3F83 counter_delay_loop cycles/iteration=11-17 back_edge=H'3F87
; loop H'3F8C-H'3F9D loc_3F8C delay_loop_candidate cycles/iteration=37-42 back_edge=H'3F9D
; loop H'2806-H'3FC8 loc_2806 loop_with_call cycles/iteration=3796-4199 back_edge=H'3FC8
; loop H'3930-H'3FCB loc_3930 loop_with_call cycles/iteration=3496-3854 back_edge=H'3FCB
; loop H'15E0-H'3FCE loc_15E0 loop_with_call cycles/iteration=7589-8520 back_edge=H'3FCE
; loop H'3FB1-H'3FD1 loc_3FB1 loop_with_call cycles/iteration=133 back_edge=H'3FD1
; loop H'4077-H'4091 loc_4077 delay_loop_candidate cycles/iteration=49-58 back_edge=H'4091
; loop H'40BE-H'40DE loc_40BE delay_loop_candidate cycles/iteration=52-56 back_edge=H'40DE
; loop H'4106-H'4182 loc_4106 loop_with_call cycles/iteration=311-315 back_edge=H'4182
; loop H'4187-H'41AD loc_4187 counter_loop cycles/iteration=96-102 back_edge=H'41AD
; loop H'41D5-H'4213 loc_41D5 counter_loop cycles/iteration=214-220 back_edge=H'4213
; loop H'3ECC-H'42C6 loc_3ECC loop_with_call cycles/iteration=2362-2508 back_edge=H'42C6
; loop H'3ECC-H'42FC loc_3ECC loop_with_call cycles/iteration=2450-2596 back_edge=H'42FC
; loop H'3ECC-H'4302 loc_3ECC loop_with_call cycles/iteration=2466-2612 back_edge=H'4302
; loop H'3ECC-H'4308 loc_3ECC loop_with_call cycles/iteration=2482-2628 back_edge=H'4308
; loop H'3ECC-H'432A loc_3ECC loop_with_call cycles/iteration=2571-2717 back_edge=H'432A
; loop H'3ECC-H'4333 loc_3ECC loop_with_call cycles/iteration=2591-2737 back_edge=H'4333
; loop H'3ECC-H'433C loc_3ECC loop_with_call cycles/iteration=2610-2756 back_edge=H'433C
; loop H'3ECC-H'4345 loc_3ECC loop_with_call cycles/iteration=2630-2776 back_edge=H'4345
; loop H'10CE-H'4348 loc_10CE loop_with_call cycles/iteration=10922-11937 back_edge=H'4348
; loop H'19A2-H'43CA loc_19A2 loop_with_call cycles/iteration=7631-8356 back_edge=H'43CA
; loop H'1A35-H'43D6 loc_1A35 loop_with_call cycles/iteration=7458-8150 back_edge=H'43D6
; loop H'1A9C-H'43E2 loc_1A9C loop_with_call cycles/iteration=7288-7935 back_edge=H'43E2
; loop H'1AE4-H'43EE loc_1AE4 loop_with_call cycles/iteration=7186-7815 back_edge=H'43EE
; ... 35 more loops
vec_reset_1000:
1000: 5F FE 80 MOV:I.W #H'FE80, R7 ; cycles=3
@@ -154,12 +242,12 @@ vec_reset_1000:
1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); cycles=9
1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9
103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9
1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; cycles=9
1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_L ; FRT1_OCRA_L = H'9C; cycles=11
1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; FRT1_FRC word write; TEMP byte-order hazard avoided; cycles=9
1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_H ; FRT1_OCRA_H = H'9C; FRT1_OCRA word write; TEMP byte-order hazard avoided; cycles=11
104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9
1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9
1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; cycles=11
105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; cycles=9
1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; FRT2_FRC word write; TEMP byte-order hazard avoided; cycles=11
105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; FRT2_OCRA word write; TEMP byte-order hazard avoided; cycles=9
1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9
1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9
106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9
@@ -172,10 +260,10 @@ vec_reset_1000:
1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D; cycles=9
1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9
109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); cycles=9
109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; cycles=9
109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; cycles=9
10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9
10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); cycles=9
10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; cycles=9
10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; cycles=9
10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9
10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field; cycles=9
10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9
@@ -1748,7 +1836,7 @@ vec_ad_adi_3D99:
3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24
3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs H'F68A in on_chip_ram; cycles=6
3DA3: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19
3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; refs ADDRA_H in register_field; cycles=7
3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; ADDRA word read; TEMP byte-order hazard avoided; refs ADDRA_H in register_field; cycles=7
3DAA: A1 10 SWAP.B R1 ; cycles=3
3DAC: A1 12 EXTU.B R1 ; cycles=3
3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 ; cycles=7
@@ -1790,7 +1878,7 @@ loc_3DFA:
loc_3E08:
3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs H'F68B in on_chip_ram; cycles=7
3E0C: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19
3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; refs ADDRB_H in register_field; cycles=6
3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; ADDRB word read; TEMP byte-order hazard avoided; refs ADDRB_H in register_field; cycles=6
3E13: A1 10 SWAP.B R1 ; cycles=3
3E15: A1 12 EXTU.B R1 ; cycles=3
3E17: A9 20 ADD:G.W R1, R0 ; cycles=3
@@ -2322,12 +2410,12 @@ loc_4324:
434B: 19 RTS ; cycles=13
loc_434C:
434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70; cycles=9
4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44; cycles=9
4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66; cycles=9
435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00; cycles=9
4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50; cycles=9
4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40; cycles=9
434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9
4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9
4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9
435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9
4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9
4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40 (A/D priority=4); cycles=9
436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR; cycles=9
436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR; cycles=9
4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR; cycles=9

11296
build/rom_decompiled.json
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File diff suppressed because it is too large Load Diff

30
build/rom_pseudocode.c
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@@ -32,7 +32,7 @@ extern volatile u8 P7DR; /* 0xFE8E */
extern volatile u8 FRT1_TCR; /* 0xFE90 */
extern volatile u8 FRT1_TCSR; /* 0xFE91 */
extern volatile u16 FRT1_FRC_H; /* 0xFE92 */
extern volatile u16 FRT1_OCRA_L; /* 0xFE94 */
extern volatile u16 FRT1_OCRA_H; /* 0xFE94 */
extern volatile u8 FRT2_TCR; /* 0xFEA0 */
extern volatile u8 FRT2_TCSR; /* 0xFEA1 */
extern volatile u16 FRT2_FRC_H; /* 0xFEA2 */
@@ -180,12 +180,12 @@ void vec_reset_1000(void)
SYSCR2 = (uint8_t)(0x84); /* 1034; MOV:G.B #H'84, @SYSCR2; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); cycles=9 */
FRT1_TCR = (uint8_t)(0x02); /* 1039; MOV:G.B #H'02, @FRT1_TCR; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 */
FRT1_TCSR = (uint8_t)(0x01); /* 103E; MOV:G.B #H'01, @FRT1_TCSR; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 */
FRT1_FRC_H = (uint16_t)(0x00); /* 1043; MOV:G.W #H'00, @FRT1_FRC_H; FRT1_FRC_H = H'00; cycles=9 */
FRT1_OCRA_L = (uint16_t)(0x009C); /* 1048; MOV:G.W #H'009C, @FRT1_OCRA_L; FRT1_OCRA_L = H'9C; cycles=11 */
FRT1_FRC_H = (uint16_t)(0x00); /* 1043; MOV:G.W #H'00, @FRT1_FRC_H; FRT1_FRC_H = H'00; FRT1_FRC W write high TEMP access; cycles=9 */
FRT1_OCRA_H = (uint16_t)(0x009C); /* 1048; MOV:G.W #H'009C, @FRT1_OCRA_H; FRT1_OCRA_H = H'9C; FRT1_OCRA W write high TEMP access; cycles=11 */
FRT2_TCR = (uint8_t)(0x02); /* 104E; MOV:G.B #H'02, @FRT2_TCR; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 */
FRT2_TCSR = (uint8_t)(0x01); /* 1053; MOV:G.B #H'01, @FRT2_TCSR; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 */
FRT2_FRC_H = (uint16_t)(0x00); /* 1058; MOV:G.W #H'00, @FRT2_FRC_H; FRT2_FRC_H = H'00; cycles=11 */
FRT2_OCRA_H = (uint16_t)(0x7A12); /* 105D; MOV:G.W #H'7A12, @FRT2_OCRA_H; FRT2_OCRA_H = H'7A12; cycles=9 */
FRT2_FRC_H = (uint16_t)(0x00); /* 1058; MOV:G.W #H'00, @FRT2_FRC_H; FRT2_FRC_H = H'00; FRT2_FRC W write high TEMP access; cycles=11 */
FRT2_OCRA_H = (uint16_t)(0x7A12); /* 105D; MOV:G.W #H'7A12, @FRT2_OCRA_H; FRT2_OCRA_H = H'7A12; FRT2_OCRA W write high TEMP access; cycles=9 */
FRT3_TCR = (uint8_t)(0x00); /* 1063; MOV:G.B #H'00, @FRT3_TCR; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 */
FRT3_TCSR = (uint8_t)(0x00); /* 1068; MOV:G.B #H'00, @FRT3_TCSR; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 */
TMR_TCR = (uint8_t)(0x00); /* 106D; MOV:G.B #H'00, @TMR_TCR; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 */
@@ -198,10 +198,10 @@ void vec_reset_1000(void)
PWM3_DTR = (uint8_t)(0x7D); /* 1090; MOV:G.B #H'7D, @PWM3_DTR; PWM3_DTR = H'7D; cycles=9 */
SCI1_SMR = (uint8_t)(0x24); /* 1095; MOV:G.B #H'24, @SCI1_SMR; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9 */
SCI1_SCR = (uint8_t)(0x3C); /* 109A; MOV:G.B #H'3C, @SCI1_SCR; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); cycles=9 */
SCI1_BRR = (uint8_t)(0x07); /* 109F; MOV:G.B #H'07, @SCI1_BRR; SCI1_BRR = H'07; cycles=9 */
SCI1_BRR = (uint8_t)(0x07); /* 109F; MOV:G.B #H'07, @SCI1_BRR; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; cycles=9 */
SCI2_SMR = (uint8_t)(0x24); /* 10A4; MOV:G.B #H'24, @SCI2_SMR; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); cycles=9 */
SCI2_SCR = (uint8_t)(0x0C); /* 10A9; MOV:G.B #H'0C, @SCI2_SCR; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); cycles=9 */
SCI2_BRR = (uint8_t)(0x07); /* 10AE; MOV:G.B #H'07, @SCI2_BRR; SCI2_BRR = H'07; cycles=9 */
SCI2_BRR = (uint8_t)(0x07); /* 10AE; MOV:G.B #H'07, @SCI2_BRR; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; cycles=9 */
ADCSR = (uint8_t)(0x19); /* 10B3; MOV:G.B #H'19, @ADCSR; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 */
MEM8[0xFEE9] = (uint8_t)(0x7F); /* 10B8; MOV:G.B #H'7F, @H'FEE9; cycles=9 */
WCR = (uint8_t)(0xF0); /* 10BD; MOV:G.B #H'F0, @WCR; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 */
@@ -1629,7 +1629,7 @@ void vec_ad_adi_3D99(void)
push_registers(R0, R1, R2, R3, R4, R5); /* 3D9D; STM.W {R0,R1,R2,R3,R4,R5}, @-SP; cycles=24 */
R0 = (uint8_t)(MEM8[0xF68A]); /* 3D9F; MOV:G.B @H'F68A, R0; cycles=6 */
R0 = mulxu8(R0, 0x14); /* 3DA3; MULXU.B #H'14, R0; cycles=19 */
R1 = (uint16_t)(ADDRA_H); /* 3DA6; MOV:G.W @ADDRA_H, R1; cycles=7 */
R1 = (uint16_t)(ADDRA_H); /* 3DA6; MOV:G.W @ADDRA_H, R1; ADDRA W read high TEMP access; cycles=7 */
R1 = swap_bytes(R1); /* 3DAA; SWAP.B R1; cycles=3 */
R1 = zero_extend8(R1); /* 3DAC; EXTU.B R1; cycles=3 */
R1 = (uint8_t)(MEM8[R1 - 0x304A]); /* 3DAE; MOV:G.B @(-H'304A,R1), R1; cycles=7 */
@@ -1668,7 +1668,7 @@ loc_3DFA:
loc_3E08:
R0 = (uint8_t)(MEM8[0xF68B]); /* 3E08; MOV:G.B @H'F68B, R0; cycles=7 */
R0 = mulxu8(R0, 0x14); /* 3E0C; MULXU.B #H'14, R0; cycles=19 */
R1 = (uint16_t)(ADDRB_H); /* 3E0F; MOV:G.W @ADDRB_H, R1; cycles=6 */
R1 = (uint16_t)(ADDRB_H); /* 3E0F; MOV:G.W @ADDRB_H, R1; ADDRB W read high TEMP access; cycles=6 */
R1 = swap_bytes(R1); /* 3E13; SWAP.B R1; cycles=3 */
R1 = zero_extend8(R1); /* 3E15; EXTU.B R1; cycles=3 */
R0 += (uint16_t)(R1); /* 3E17; ADD:G.W R1, R0; cycles=3 */
@@ -2138,12 +2138,12 @@ void loc_4324(void)
void loc_434C(void)
{
IPRA = (uint8_t)(0x70); /* 434C; MOV:G.B #H'70, @IPRA; IPRA = H'70; cycles=9 */
IPRB = (uint8_t)(0x44); /* 4351; MOV:G.B #H'44, @IPRB; IPRB = H'44; cycles=9 */
IPRC = (uint8_t)(0x66); /* 4356; MOV:G.B #H'66, @IPRC; IPRC = H'66; cycles=9 */
IPRD = (uint8_t)(0x00); /* 435B; MOV:G.B #H'00, @IPRD; IPRD = H'00; cycles=9 */
IPRE = (uint8_t)(0x50); /* 4360; MOV:G.B #H'50, @IPRE; IPRE = H'50; cycles=9 */
IPRF = (uint8_t)(0x40); /* 4365; MOV:G.B #H'40, @IPRF; IPRF = H'40; cycles=9 */
IPRA = (uint8_t)(0x70); /* 434C; MOV:G.B #H'70, @IPRA; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9 */
IPRB = (uint8_t)(0x44); /* 4351; MOV:G.B #H'44, @IPRB; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9 */
IPRC = (uint8_t)(0x66); /* 4356; MOV:G.B #H'66, @IPRC; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9 */
IPRD = (uint8_t)(0x00); /* 435B; MOV:G.B #H'00, @IPRD; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9 */
IPRE = (uint8_t)(0x50); /* 4360; MOV:G.B #H'50, @IPRE; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9 */
IPRF = (uint8_t)(0x40); /* 4365; MOV:G.B #H'40, @IPRF; IPRF = H'40 (A/D priority=4); cycles=9 */
SCI1_SCR |= BIT(6); /* 436A; BSET.B #6, @SCI1_SCR; set RIE (bit 6) of SCI1_SCR; cycles=9 */
FRT1_TCR |= BIT(5); /* 436E; BSET.B #5, @FRT1_TCR; set OCIEA (bit 5) of FRT1_TCR; cycles=9 */
FRT2_TCR |= BIT(5); /* 4372; BSET.B #5, @FRT2_TCR; set OCIEA (bit 5) of FRT2_TCR; cycles=9 */