more serial improvements
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@@ -88,6 +88,11 @@ class SerialReconstructionTest(unittest.TestCase):
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def test_candidate_sci1_rx_frame_length_and_checksum_validation_pattern(self):
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instructions = {
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0x4FF0: ins(0x4FF0, "BSET.B", "#7, @H'FAA4", [0xFAA4]),
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0x4FF4: ins(0x4FF4, "BCLR.B", "#5, @SCI1_SSR", [0xFEDC]),
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0x4FF8: ins(0x4FF8, "BCLR.B", "#4, @SCI1_SSR", [0xFEDC]),
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0x4FFC: ins(0x4FFC, "BCLR.B", "#3, @SCI1_SSR", [0xFEDC]),
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0x4FFE: ins(0x4FFE, "BCLR.B", "#6, @SCI1_SSR", [0xFEDC]),
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0x5000: ins(0x5000, "MOV:G.B", "@SCI1_RDR, R0", [0xFEDD]),
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0x5004: ins(0x5004, "MOV:G.B", "R0, @(-H'0798,R1)", []),
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0x5008: ins(0x5008, "ADD:Q.B", "#1, R1", []),
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@@ -119,11 +124,24 @@ class SerialReconstructionTest(unittest.TestCase):
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self.assertEqual(candidate["checksum_address"], 0xF865)
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self.assertEqual(candidate["checksum_seed"], 0x5A)
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self.assertIn("no explicit header", candidate["confidence_reason"])
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self.assertIn("rx_rdrf_clear_before_rdr_read", candidate["evidence_addresses"])
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self.assertIn("rx_eri_falls_through_to_rxi", candidate["evidence_addresses"])
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self.assertTrue(candidate["rx_error_handling"]["fallthrough_to_rx_byte_path"])
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self.assertTrue(candidate["rx_error_handling"]["rdrf_clear_before_rdr_read"])
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self.assertEqual(candidate["rx_error_handling"]["error_latch_address"], 0xFAA4)
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comment = serial_reconstruction_comment_for_instruction(analysis, 0x5138)
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self.assertIn("candidate/evidence-supported SCI1 6-byte RX frame", comment)
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self.assertIn("checksum H'F865", comment)
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self.assertIn("confidence high", comment)
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self.assertIn(
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"ROM clears SCI1 SSR.RDRF before reading SCI1_RDR",
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serial_reconstruction_comment_for_instruction(analysis, 0x4FFE),
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)
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self.assertIn(
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"SCI1 ERI latches FAA4.bit7",
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serial_reconstruction_comment_for_instruction(analysis, 0x4FF0),
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)
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def test_lone_tdr_write_does_not_emit_reconstruction(self):
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instructions = {
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