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135
build/rom_0013_handler_linear.asm
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135
build/rom_0013_handler_linear.asm
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; H8/536 ROM disassembly
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; input: ROM\M27C512@DIP28_1.BIN
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; bytes: 65536
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; vector mode: min
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; analysis: linear sweep
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;
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; Notes from the manual:
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; - H8/536 uses the H8/500 CPU instruction set.
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; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC.
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; - The register field is H'FE80-H'FFFF; names below come from appendix B.
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; - @aa:8 short absolute operands use BR as the upper address byte.
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; - SCI baud inference uses section 14.2.8 BRR formulas when SMR/BRR are known.
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; - LCD inference treats E-clock H'F200/H'F201 accesses as status/control and data candidates.
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; Memory Map
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; H'0000-H'009F exception_vectors vectors
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; H'00A0-H'00FF dtc_vectors dtc_vectors
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; H'0100-H'F67F program_or_external program
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; H'F680-H'FE7F on_chip_ram ram
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; H'FE80-H'FFFF register_field registers
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; Vectors
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; H'0000 reset -> vec_reset_1000 (H'1000)
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; H'0004 invalid_instruction -> vec_reset_1000 (H'1000)
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; H'0006 zero_divide -> vec_reset_1000 (H'1000)
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; H'0008 trap_vs -> vec_reset_1000 (H'1000)
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; H'0010 address_error -> vec_reset_1000 (H'1000)
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; H'0012 trace -> vec_reset_1000 (H'1000)
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; H'0016 nmi -> vec_nmi_4393 (H'4393)
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; H'0020 trapa_0 -> vec_reset_1000 (H'1000)
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; H'0022 trapa_1 -> vec_reset_1000 (H'1000)
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; H'0024 trapa_2 -> vec_reset_1000 (H'1000)
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; H'0026 trapa_3 -> vec_reset_1000 (H'1000)
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; H'0028 trapa_4 -> vec_reset_1000 (H'1000)
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; H'002A trapa_5 -> vec_reset_1000 (H'1000)
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; H'002C trapa_6 -> vec_reset_1000 (H'1000)
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; H'002E trapa_7 -> vec_reset_1000 (H'1000)
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; H'0030 trapa_8 -> vec_reset_1000 (H'1000)
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; H'0032 trapa_9 -> vec_reset_1000 (H'1000)
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; H'0034 trapa_a -> vec_reset_1000 (H'1000)
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; H'0036 trapa_b -> vec_reset_1000 (H'1000)
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; H'0038 trapa_c -> vec_reset_1000 (H'1000)
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; H'003A trapa_d -> vec_reset_1000 (H'1000)
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; H'003C trapa_e -> vec_reset_1000 (H'1000)
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; H'003E trapa_f -> vec_reset_1000 (H'1000)
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; H'0040 irq0 -> vec_reset_1000 (H'1000)
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; H'0042 interval_timer -> vec_interval_timer_BFC4 (H'BFC4)
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; H'0048 irq1 -> vec_reset_1000 (H'1000)
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; H'0050 irq2 -> vec_reset_1000 (H'1000)
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; H'0052 irq3 -> vec_irq3_3C30 (H'3C30)
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; H'0058 irq4 -> vec_irq4_3AC7 (H'3AC7)
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; H'005A irq5 -> vec_reset_1000 (H'1000)
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; H'0062 frt1_ocia -> vec_frt1_ocia_BEEA (H'BEEA)
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; H'006A frt2_ocia -> vec_frt2_ocia_BF23 (H'BF23)
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; H'0080 sci1_eri -> vec_sci1_eri_BB57 (H'BB57)
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; H'0082 sci1_rxi -> vec_sci1_rxi_BB67 (H'BB67)
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; H'0084 sci1_txi -> vec_sci1_txi_BA84 (H'BA84)
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; H'0090 ad_adi -> vec_ad_adi_3D99 (H'3D99)
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; Symbols
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; mem_E02E H'E02E program_or_external memory r=1 w=0 width=word
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; mem_E030 H'E030 program_or_external memory r=1 w=0 width=word
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; mem_E826 H'E826 program_or_external memory r=2 w=0 width=word
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; mem_E82E H'E82E program_or_external memory r=0 w=1 width=word
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; ram_F711 H'F711 on_chip_ram ram r=4 w=4 width=byte
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; ram_F713 H'F713 on_chip_ram ram r=2 w=2 width=byte
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; ram_F716 H'F716 on_chip_ram ram r=4 w=4 width=byte
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; ram_F791 H'F791 on_chip_ram ram r=4 w=4 width=byte
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; Board Profile
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; Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.
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; H8 pin 66 P95/TXD (TXD) -> MAX202 pin 11
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; H8 pin 67 P96/RXD (RXD) -> MAX202 pin 12
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; SCI2 pin routing is disabled by SYSCR2.P9SCI2E=0 in the observed setup.
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; LCD/Text Scan
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; search 'CONNECT': not literal, hits=0
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2E00: 30 FE A3 BRA loc_2CA6
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2E03: 30 FE A0 BRA loc_2CA6
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2E06: 1D E8 26 FF BTST.W #15, @H'E826 ; refs mem_E826 in program_or_external
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2E0A: 27 0A BEQ loc_2E16
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2E0C: 15 F7 91 C6 BSET.B #6, @H'F791 ; refs ram_F791 in on_chip_ram
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2E10: 15 F7 13 C4 BSET.B #4, @H'F713 ; refs ram_F713 in on_chip_ram
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2E14: 20 08 BRA loc_2E1E
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loc_2E16:
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2E16: 15 F7 91 D6 BCLR.B #6, @H'F791 ; refs ram_F791 in on_chip_ram
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2E1A: 15 F7 13 D4 BCLR.B #4, @H'F713 ; refs ram_F713 in on_chip_ram
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loc_2E1E:
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2E1E: 1D E8 26 FE BTST.W #14, @H'E826 ; refs mem_E826 in program_or_external
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2E22: 27 0A BEQ loc_2E2E
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2E24: 15 F7 91 C5 BSET.B #5, @H'F791 ; refs ram_F791 in on_chip_ram
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2E28: 15 F7 16 C7 BSET.B #7, @H'F716 ; refs ram_F716 in on_chip_ram
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2E2C: 20 08 BRA loc_2E36
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loc_2E2E:
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2E2E: 15 F7 91 D5 BCLR.B #5, @H'F791 ; refs ram_F791 in on_chip_ram
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2E32: 15 F7 16 D7 BCLR.B #7, @H'F716 ; refs ram_F716 in on_chip_ram
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loc_2E36:
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2E36: 30 FE 6D BRA loc_2CA6
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2E39: FC E0 00 81 MOV:G.W @(-H'2000,R4), R1
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2E3D: A9 FF BTST.W #15, R1
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2E3F: 26 0E BNE loc_2E4F
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2E41: A9 FE BTST.W #14, R1
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2E43: 26 0A BNE loc_2E4F
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2E45: 15 F7 11 D0 BCLR.B #0, @H'F711 ; refs ram_F711 in on_chip_ram
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2E49: 15 F7 16 D5 BCLR.B #5, @H'F716 ; refs ram_F716 in on_chip_ram
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2E4D: 20 08 BRA loc_2E57
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loc_2E4F:
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2E4F: 15 F7 11 C0 BSET.B #0, @H'F711 ; refs ram_F711 in on_chip_ram
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2E53: 15 F7 16 C5 BSET.B #5, @H'F716 ; refs ram_F716 in on_chip_ram
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loc_2E57:
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2E57: 30 FE 4C BRA loc_2CA6
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2E5A: FC E0 00 81 MOV:G.W @(-H'2000,R4), R1
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2E5E: A9 FF BTST.W #15, R1
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2E60: 26 06 BNE loc_2E68
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2E62: 15 F7 11 D1 BCLR.B #1, @H'F711 ; refs ram_F711 in on_chip_ram
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2E66: 20 04 BRA loc_2E6C
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loc_2E68:
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2E68: 15 F7 11 C1 BSET.B #1, @H'F711 ; refs ram_F711 in on_chip_ram
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loc_2E6C:
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2E6C: 30 FE 37 BRA loc_2CA6
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2E6F: 1D E0 30 81 MOV:G.W @H'E030, R1 ; refs mem_E030 in program_or_external
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2E73: 1D E0 2E 71 CMP:G.W @H'E02E, R1 ; refs mem_E02E in program_or_external
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2E77: 27 0C BEQ loc_2E85
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2E79: 1D E8 2E 91 MOV:G.W R1, @H'E82E ; refs mem_E82E in program_or_external
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2E7D: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80
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2E7F: 5B 00 17 MOV:I.W #H'0017, R3 ; dataflow R3=H'0017
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