From 3e1d30527fc1fea717ae0fd4f6b1f92cf2341676 Mon Sep 17 00:00:00 2001 From: Aiden <68633820+awils27@users.noreply.github.com> Date: Tue, 26 May 2026 16:17:24 +1000 Subject: [PATCH] Intresting --- README.md | 4 +- build/rom_others_menu.asm | 4263 + build/rom_others_menu.json | 219643 +++++++++++++++++++++ build/rom_others_menu_deep.asm | 4219 + build/rom_others_menu_deep.json | 220100 +++++++++++++++++++++ build/rom_others_menu_gate.asm | 4295 + build/rom_others_menu_gate.json | 221410 +++++++++++++++++++++ build/rom_others_page1.asm | 4642 + build/rom_others_page1.json | 239015 +++++++++++++++++++++++ docs/pt2-copy-state-machine.md | 125 + docs/pt2-menu-state-machine.md | 124 + docs/pt2-protocol.md | 23 +- scenarios/others-copy-gate-probe.json | 49 + 13 files changed, 917909 insertions(+), 3 deletions(-) create mode 100644 build/rom_others_menu.asm create mode 100644 build/rom_others_menu.json create mode 100644 build/rom_others_menu_deep.asm create mode 100644 build/rom_others_menu_deep.json create mode 100644 build/rom_others_menu_gate.asm create mode 100644 build/rom_others_menu_gate.json create mode 100644 build/rom_others_page1.asm create mode 100644 build/rom_others_page1.json create mode 100644 docs/pt2-copy-state-machine.md create mode 100644 docs/pt2-menu-state-machine.md create mode 100644 scenarios/others-copy-gate-probe.json diff --git a/README.md b/README.md index 5aee244..f255259 100644 --- a/README.md +++ b/README.md @@ -62,7 +62,7 @@ To start the current emulator harness: The real-device bench helper uses `pyserial`; install repo dependencies with `.\.venv\Scripts\python.exe -m pip install -r requirements.txt` if needed. -The current PT2/protocol reconstruction is documented in [docs/pt2-protocol.md](docs/pt2-protocol.md). +The current PT2/protocol reconstruction is documented in [docs/pt2-protocol.md](docs/pt2-protocol.md), with focused mini-notes for [COPY state](docs/pt2-copy-state-machine.md) and [menu state](docs/pt2-menu-state-machine.md). ## Real Bench Serial Format @@ -150,7 +150,7 @@ Current serial observations: - Bench serial-format finding: real hardware talks `38400 8E1`. Earlier `8N1` captures primarily exercised SCI1 parity/error handling and retry echoes, not the normal command path. After switching bench scripts to even parity, the selector-zero CONNECT path can reach `CONNECT: OK`. - Bench CONNECT recovery finding: `CONNECT:NOT ACT` is recoverable without a power cycle. This makes it a normal no-active-session/cleared-state display rather than a terminal latch; tests can now probe from the idle NOT ACT state directly, then separately check whether OK is held or needs periodic CCU-like refresh traffic. - Bench CONNECT cadence finding: the `40 -> 80 -> C0` sequence stayed at `CONNECT:NOT ACT` with 10 ms, 50 ms, and 150 ms gaps, but produced `CONNECT: OK` then returned to `CONNECT:NOT ACT` with 700 ms and 1.5 s gaps. At 700 ms, single `40`/`80`/`C0` frames did not work, but all tested two-frame pairs did. Repeated `80 -> 80` at about 700 ms also worked, so the values do not need to differ. The no-power-cycle NOT ACT recovery capture produced repeated `02 00 02 00 00 5A` OK-path responses before heartbeat traffic resumed. -- Bench special-selector finding: in the CONNECT OK advance sweep, command-5 selector `0x006C` (`05 00 6C 00 00 33`) produced `CONNECT OK` then a blank LCD with the CAM POWER lamp still on, while selector `0x006D` (`05 00 6D 00 00 32`) produced `CONNECT OK` then `COPY IN PROGRESS` then `CONNECT NOT ACT`. A later fresh isolated `ack-006d` run in `captures/connect-ok-advance-special-20260526-153339.txt` reproduced the copy path after a relay power-cycle. Forced ROM decoding confirms `0x006C -> H'2FAF` and `0x006D -> H'3015`; the `0x006D` path sets display selector `F732=H'1903`, a long `F798` countdown, and the ROM contains the `COPY IN PROGRESS` LCD string. LCD dispatch now traces through `493E[0x19] -> H'930A`, with local table entry `H'9F6A` building `COPY IN PROGRESS` and entry `H'9FDA` building `COPY COMPLETED`; `0x006C` appears to be the completion/exit sibling only after `0x006D` has set the `F795.6/F795.7` copy flags. The RCP-TX7 manual identifies `COPY IN PROGRESS` as the multi-camera `COPY TO SLAVES` transfer state over the RS232C command-link system, with controls locked until `COPY COMPLETED`. +- Bench special-selector finding: in the CONNECT OK advance sweep, command-5 selector `0x006C` (`05 00 6C 00 00 33`) produced `CONNECT OK` then a blank LCD with the CAM POWER lamp still on, while selector `0x006D` (`05 00 6D 00 00 32`) produced `CONNECT OK` then `COPY IN PROGRESS` then `CONNECT NOT ACT`. A later fresh isolated `ack-006d` run in `captures/connect-ok-advance-special-20260526-153339.txt` reproduced the copy path after a relay power-cycle. Forced ROM decoding confirms `0x006C -> H'2FAF` and `0x006D -> H'3015`; the `0x006D` path sets display selector `F732=H'1903`, a long `F798` countdown, and the ROM contains the `COPY IN PROGRESS` LCD string. LCD dispatch now traces through `493E[0x19] -> H'930A`, with local table entry `H'9F6A` building `COPY IN PROGRESS` and entry `H'9FDA` building `COPY COMPLETED`; `0x006C` appears to be the completion/exit sibling only after `0x006D` has set the `F795.6/F795.7` copy flags. The RCP-side menu trace now also identifies page `0x01` table entry `H'6FF0` as `OTHERS / COPY TO SLAVES`; it is gated by `E400[0x0015]`, and its local copy-start branch also requires `F791.7` before setting `F76E.6`, `F795.7`, `F731.7`, `F798=H'C8`, `F711.7`, and `F726=H'64`. The RCP-TX7 manual identifies `COPY IN PROGRESS` as the multi-camera `COPY TO SLAVES` transfer state over the RS232C command-link system, with controls locked until `COPY COMPLETED`. - ROM report-source finding: the active `02/01 ...` frames exposed during CONNECT OK attempts are autonomous `F870 -> BAF2 -> BA26` report-queue transmissions, not ordinary command-1 readbacks. The ROM sets `FAA2.3/FAA3.7` after sending them, so the CCU probably needs to answer in that continuation window with command `4`, `5`, or `6` to consume the report queue and keep the session alive. - Board/P9 finding: traced MCU pin 62 `P91` reaches X24164 pin 6 `SCL`, and MCU pin 68 `P97` reaches the shared X24164 pin 5 `SDA` node. The emulator now treats the ROM's `C121/C08B/C0DB/C10C/C142` P9 routines as an X24164-style two-wire EEPROM bus, with ROM logical addresses `0x000-0x7FF` on the `H'A0/H'A1` control-byte family and `0x800-0xFFF` on `H'E0/H'E1`. - EEPROM role finding: `loc_40BB` checks `P7DR.7` and the `F402 == H'6B6F` signature before defaulting EEPROM/shadow tables; `loc_4103` writes ROM default words through `BFE0`, `loc_41D2` reads sixteen 8-byte records into `F7B0-F82F`, and the command-4 path at `BD2B-BD5F` can persist serial table writes when `F76E.7` is set. diff --git a/build/rom_others_menu.asm b/build/rom_others_menu.asm new file mode 100644 index 0000000..e3b8641 --- /dev/null +++ b/build/rom_others_menu.asm @@ -0,0 +1,4263 @@ +; H8/536 ROM disassembly +; input: ROM\M27C512@DIP28_1.BIN +; bytes: 65536 +; vector mode: min +; analysis: recursive trace from vectors +; +; Notes from the manual: +; - H8/536 uses the H8/500 CPU instruction set. +; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC. +; - The register field is H'FE80-H'FFFF; names below come from appendix B. +; - @aa:8 short absolute operands use BR as the upper address byte. +; - SCI baud inference uses section 14.2.8 BRR formulas when SMR/BRR are known. +; - LCD inference treats E-clock H'F200/H'F201 accesses as status/control and data candidates. +; - Pass --clock-hz to convert SCI BRR settings into numeric baud rates. +; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states. + +; Memory Map +; H'0000-H'009F exception_vectors vectors +; H'00A0-H'00FF dtc_vectors dtc_vectors +; H'0100-H'F67F program_or_external program +; H'F680-H'FE7F on_chip_ram ram +; H'FE80-H'FFFF register_field registers + +; Vectors +; H'0000 reset -> vec_reset_1000 (H'1000) +; H'0004 invalid_instruction -> vec_reset_1000 (H'1000) +; H'0006 zero_divide -> vec_reset_1000 (H'1000) +; H'0008 trap_vs -> vec_reset_1000 (H'1000) +; H'0010 address_error -> vec_reset_1000 (H'1000) +; H'0012 trace -> vec_reset_1000 (H'1000) +; H'0016 nmi -> vec_nmi_4393 (H'4393) +; H'0020 trapa_0 -> vec_reset_1000 (H'1000) +; H'0022 trapa_1 -> vec_reset_1000 (H'1000) +; H'0024 trapa_2 -> vec_reset_1000 (H'1000) +; H'0026 trapa_3 -> vec_reset_1000 (H'1000) +; H'0028 trapa_4 -> vec_reset_1000 (H'1000) +; H'002A trapa_5 -> vec_reset_1000 (H'1000) +; H'002C trapa_6 -> vec_reset_1000 (H'1000) +; H'002E trapa_7 -> vec_reset_1000 (H'1000) +; H'0030 trapa_8 -> vec_reset_1000 (H'1000) +; H'0032 trapa_9 -> vec_reset_1000 (H'1000) +; H'0034 trapa_a -> vec_reset_1000 (H'1000) +; H'0036 trapa_b -> vec_reset_1000 (H'1000) +; H'0038 trapa_c -> vec_reset_1000 (H'1000) +; H'003A trapa_d -> vec_reset_1000 (H'1000) +; H'003C trapa_e -> vec_reset_1000 (H'1000) +; H'003E trapa_f -> vec_reset_1000 (H'1000) +; H'0040 irq0 -> vec_reset_1000 (H'1000) +; H'0042 interval_timer -> vec_interval_timer_BFC4 (H'BFC4) +; H'0048 irq1 -> vec_reset_1000 (H'1000) +; H'0050 irq2 -> vec_reset_1000 (H'1000) +; H'0052 irq3 -> vec_irq3_3C30 (H'3C30) +; H'0058 irq4 -> vec_irq4_3AC7 (H'3AC7) +; H'005A irq5 -> vec_reset_1000 (H'1000) +; H'0062 frt1_ocia -> vec_frt1_ocia_BEEA (H'BEEA) +; H'006A frt2_ocia -> vec_frt2_ocia_BF23 (H'BF23) +; H'0080 sci1_eri -> vec_sci1_eri_BB57 (H'BB57) +; H'0082 sci1_rxi -> vec_sci1_rxi_BB67 (H'BB67) +; H'0084 sci1_txi -> vec_sci1_txi_BA84 (H'BA84) +; H'0090 ad_adi -> vec_ad_adi_3D99 (H'3D99) + +; Unreached Data Candidates +; string H'2A52 len=11 '78785=5=5=,' +; string H'2BBA len=7 '8*8B8Z8' +; string H'41B2 len=32 '01020304050607080910111213141516' +; string H'57A4 len=7 'Z [ ' +; string H'582A len=6 'Z [ ' +; string H'5B55 len=10 '0123456789' +; string H'5B60 len=40 ' 0 1 2 3 4 5 6 7 8 910111213141516171819' +; string H'60F6 len=16 '0123456789ABCDEF' +; string H'630C len=9 'm*mDm^mxm' +; string H'633E len=6 'vpwhx6' +; string H'63D7 len=10 'OPERATION ' +; string H'63F5 len=10 ' PAINT ' +; string H'6410 len=18 ' ADV~Xd' +; string H'6443 len=10 'OPERATION ' +; string H'6461 len=10 'IRIS/M.BLK' +; string H'6490 len=10 'OPERATION ' +; string H'64AE len=10 ' LOCK ' +; string H'652F len=19 ' DYNA LATITUDE Xe/' +; string H'6551 len=18 'HIGH LOW~XeP' +; string H'6578 len=18 'STD OFF~Xew' +; string H'65C9 len=18 ' BLACK STR Xe' +; string H'6644 len=19 ' BLACK STR XfD' +; string H'6665 len=19 ' STRETCH LEVEL Xfe' +; string H'6683 len=18 'POINT1 POINT2Xf' +; string H'6706 len=18 ' BLACK STR Xg' +; string H'6727 len=19 " COMPRESS LEVEL Xg'" +; string H'6745 len=19 'POINT1 POINT2XgE' +; string H'67E0 len=18 ' TLCS Xg' +; string H'6802 len=17 'ON OFF~Xh' +; string H'681F len=18 ' AGC GAIN AE Xh' +; string H'686A len=136 ' CL F16 F11 F8 F5.6F4 F2.8F2 F1.8F1.4 OP DPR HYP HIGHMID LOW 36dB30dB24dB18dB12dB 9dB 6dB 3dB 0dB-3dB' +; string H'693B len=19 ' AUTO FUNC Xi;' +; string H'695C len=19 ' ATW Xi\\' +; string H'6984 len=17 'ON OFF~Xi' +; string H'6A4F len=19 ' AUTO FUNC XjO' +; string H'6A71 len=18 'STD SPOT.L~Xjp' +; string H'6A8E len=18 ' A.IRIS MODE Xj' +; string H'6AAD len=17 'AI BACK.L~Xj' +; string H'6B3D len=19 ' AUTO FUNC Xk=' +; string H'6B5E len=19 ' AUTO FOCUS Xk^' +; ptrtbl H'1A1E count=4 -> H'F6F8, H'FAFC, H'FDFE, H'FF00 +; ptrtbl H'1EB0 count=4 -> H'F730, H'F727, H'2815, H'F731 +; ptrtbl H'28A8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28B6 count=10 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'28DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28F2 count=29 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'292E count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'293C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2944 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'294C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2954 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'295C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2964 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'296C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2974 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2982 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'29AE count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29B8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29FA count=13 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A20 count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2A34 count=15 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A62 count=24 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A98 count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2AA2 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2AC8 count=115 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2BC4 count=113 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'33A0 count=3 -> H'FF26, H'11A9, H'F726 +; ptrtbl H'3478 count=3 -> H'F790, H'F727, H'441D +; ptrtbl H'35DC count=3 -> H'FE27, H'1215, H'F717 +; ptrtbl H'4698 count=3 -> H'F750, H'1627, H'10FB +; ptrtbl H'47AE count=3 -> H'F752, H'1627, H'10FB +; ptrtbl H'48AA count=4 -> H'FB03, H'F726, H'1215, H'F6D1 +; ptrtbl H'505A count=3 -> H'1627, H'5515, H'FB03 +; ptrtbl H'5A22 count=3 -> H'1AF8, H'F74C, H'1627 +; ptrtbl H'62EE count=4 -> H'FCE2, H'FC62, H'FA84, H'11DC +; ptrtbl H'74FC count=3 -> H'F772, H'1627, H'12A8 +; ptrtbl H'80F2 count=3 -> H'FC80, H'FC84, H'11DC +; ptrtbl H'9E10 count=3 -> H'FE1E, H'BC7D, H'5500 +; ptrtbl H'B5E0 count=3 -> H'F772, H'1627, H'11A0 + +; Symbols +; mem_1011 H'1011 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_10FB H'10FB program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1161 H'1161 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1170 H'1170 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1179 H'1179 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1188 H'1188 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1197 H'1197 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11A0 H'11A0 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_11A9 H'11A9 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11DC H'11DC program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1206 H'1206 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1215 H'1215 program_or_external memory r=0 w=0 width=unknown xrefs=3 +; mem_12A8 H'12A8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1314 H'1314 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1617 H'1617 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1627 H'1627 program_or_external memory r=0 w=0 width=unknown xrefs=7 +; mem_1630 H'1630 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1647 H'1647 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1664 H'1664 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1682 H'1682 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1700 H'1700 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1819 H'1819 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1A00 H'1A00 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1AF8 H'1AF8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2815 H'2815 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2CA6 H'2CA6 program_or_external memory r=0 w=0 width=unknown xrefs=429 +; mem_441D H'441D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449C H'449C program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449E H'449E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_44A0 H'44A0 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5500 H'5500 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5515 H'5515 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_602E H'602E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6030 H'6030 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6032 H'6032 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_BC7D H'BC7D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_E000 H'E000 program_or_external memory r=0 w=1 width=word +; mem_E004 H'E004 program_or_external memory r=1 w=0 width=word +; mem_E006 H'E006 program_or_external memory r=0 w=1 width=word +; mem_E046 H'E046 program_or_external memory r=0 w=1 width=word +; mem_E080 H'E080 program_or_external memory r=0 w=1 width=word +; mem_E102 H'E102 program_or_external memory r=2 w=0 width=word +; mem_E124 H'E124 program_or_external memory r=2 w=0 width=word +; mem_E126 H'E126 program_or_external memory r=5 w=0 width=word +; mem_E14E H'E14E program_or_external memory r=1 w=0 width=word +; mem_E16E H'E16E program_or_external memory r=1 w=0 width=word +; mem_E172 H'E172 program_or_external memory r=1 w=0 width=word +; mem_E1EC H'E1EC program_or_external memory r=2 w=0 width=word +; mem_E220 H'E220 program_or_external memory r=1 w=0 width=word +; mem_E800 H'E800 program_or_external memory r=0 w=1 width=word +; mem_E806 H'E806 program_or_external memory r=0 w=1 width=word +; mem_E880 H'E880 program_or_external memory r=0 w=1 width=word +; mem_E902 H'E902 program_or_external memory r=0 w=1 width=word +; mem_E924 H'E924 program_or_external memory r=0 w=1 width=word +; mem_E9EC H'E9EC program_or_external memory r=0 w=1 width=word +; mem_F000 H'F000 program_or_external memory r=2 w=0 width=byte +; mem_F001 H'F001 program_or_external memory r=2 w=1 width=byte +; mem_F002 H'F002 program_or_external memory r=2 w=1 width=mixed +; mem_F003 H'F003 program_or_external memory r=1 w=1 width=byte +; mem_F004 H'F004 program_or_external memory r=2 w=1 width=mixed +; mem_F005 H'F005 program_or_external memory r=1 w=1 width=byte +; mem_F006 H'F006 program_or_external memory r=2 w=0 width=mixed +; mem_F007 H'F007 program_or_external memory r=1 w=0 width=byte +; mem_F008 H'F008 program_or_external memory r=2 w=0 width=mixed +; mem_F009 H'F009 program_or_external memory r=1 w=1 width=byte +; mem_F00A H'F00A program_or_external memory r=2 w=1 width=mixed +; mem_F00B H'F00B program_or_external memory r=0 w=1 width=byte +; mem_F00C H'F00C program_or_external memory r=2 w=1 width=mixed +; mem_F00D H'F00D program_or_external memory r=0 w=1 width=byte +; mem_F00E H'F00E program_or_external memory r=0 w=1 width=byte +; mem_F00F H'F00F program_or_external memory r=1 w=1 width=byte +; mem_F100 H'F100 program_or_external memory r=2 w=0 width=byte +; mem_F101 H'F101 program_or_external memory r=2 w=1 width=byte +; mem_F102 H'F102 program_or_external memory r=2 w=1 width=mixed +; mem_F103 H'F103 program_or_external memory r=1 w=1 width=byte +; mem_F104 H'F104 program_or_external memory r=2 w=1 width=mixed +; mem_F105 H'F105 program_or_external memory r=1 w=1 width=byte +; mem_F106 H'F106 program_or_external memory r=2 w=0 width=mixed +; mem_F107 H'F107 program_or_external memory r=1 w=0 width=byte +; mem_F108 H'F108 program_or_external memory r=2 w=0 width=mixed +; ... 235 more symbols omitted from listing header + +; Board Profile +; Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver. +; H8 pin 66 P95/TXD (TXD) -> MAX202 pin 11 +; H8 pin 67 P96/RXD (RXD) -> MAX202 pin 12 +; SCI2 pin routing is disabled by SYSCR2.P9SCI2E=0 in the observed setup. + +; Serial Protocol Reconstruction +; TX candidate: 6 bytes H'F858-H'F85D, checksum H'F85D seeded by H'005A (confidence high 0.95) +; TX path: initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted +; RX candidate: 6 bytes capture H'F868-H'F86D, validate H'F860-H'F865 checksum H'F865 seeded by H'005A (confidence high 0.9) +; caveat: candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet +; Serial RAM role candidates +; H'F9C0: post_tx_report_delay - post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C1: secondary_tx_report_delay - secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C6: periodic_report_countdown - periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it + +; LCD/Text Scan +; search 'CONNECT': not literal, hits=0 +; near: H'A025 'COMPLETED', H'8E79 'ON CONT1 OFF~X', H'8F55 'ON CONT2 OFF~X', H'94A9 'ON' +; LCD text regions +; region H'63D7-H'6758 count=15 'OPERATION', 'PAINT', 'OPERATION', 'IRIS/M.BLK' +; region H'67E0-H'6831 count=2 'TLCS Xg', 'AGC GAIN AE Xh' +; region H'6A4F-H'6C47 count=8 'AUTO FUNC XjO', 'A.IRIS MODE Xj', 'AI BACK.L~Xj', 'AUTO FUNC Xk=' +; region H'6F84-H'6FC0 count=2 'OTHERS Xo', 'SHUTTER Xo' +; region H'7052-H'7477 count=15 'SET RCP', 'MASTER', 'OTHERS Xp', 'COPY TO SLAVES~Xp' +; region H'757A-H'7824 count=14 'BARS TYPE Xuz', 'SMPTE Xu', 'SPLIT Xu', 'FULLFIELD 75% Xu' +; region H'78B5-H'792F count=4 'OTHERS Xx', 'WHITE BLACK~Xx', 'COMM LINK ITEM-2Xx', 'FLARE Xy' +; region H'819C-H'87A9 count=28 'SHADING X', 'WHITE~X', 'SHADING AUTO SETX', 'BLACK~X' +; region H'883D-H'8959 count=7 'MATRIX X', 'STD FL~X', 'PRESET MATRIX X', 'H.SAT SPCL~X' +; region H'8A0C-H'8BAC count=7 'MATRIX X', 'ON SKIN OFF~X', 'SAT HUE X', 'MATRIX X' +; region H'8CB7-H'8CFD count=2 'FILTER X', '1 2 3 4 X' +; region H'8E57-H'8EA7 count=3 'LENS X', 'ON CONT1 OFF~X', 'FOCUS ZOOM X' +; ... 23 more LCD text regions +; LCD text candidates +; text H'41B0 len=35 medium '01020304050607080910111213141516X' +; text H'5B55 len=10 high '0123456789' xrefs=2 +; text H'60F6 len=16 high '0123456789ABCDEF' +; text H'63D7 len=10 high 'OPERATION' xrefs=1 +; text H'63F5 len=10 high 'PAINT' xrefs=1 +; text H'6443 len=10 high 'OPERATION' xrefs=1 +; text H'6461 len=10 high 'IRIS/M.BLK' xrefs=1 +; text H'6490 len=10 high 'OPERATION' xrefs=1 +; text H'64AE len=10 high 'LOCK' xrefs=1 +; text H'652F len=19 high 'DYNA LATITUDE Xe/' xrefs=1 +; text H'6551 len=18 medium 'HIGH LOW~XeP' xrefs=1 +; text H'65C9 len=18 medium 'BLACK STR Xe' xrefs=1 +; text H'6644 len=19 medium 'BLACK STR XfD' xrefs=1 +; text H'6665 len=19 medium 'STRETCH LEVEL Xfe' xrefs=1 +; text H'6683 len=18 high 'POINT1 POINT2Xf' xrefs=1 +; text H'6706 len=18 medium 'BLACK STR Xg' xrefs=1 +; text H'6727 len=19 medium "COMPRESS LEVEL Xg'" xrefs=1 +; text H'6745 len=19 high 'POINT1 POINT2XgE' xrefs=1 +; text H'67E0 len=18 medium 'TLCS Xg' xrefs=1 +; text H'681F len=18 medium 'AGC GAIN AE Xh' xrefs=1 +; text H'693B len=19 medium 'AUTO FUNC Xi;' xrefs=1 +; text H'6A4F len=19 medium 'AUTO FUNC XjO' xrefs=1 +; text H'6A8E len=18 medium 'A.IRIS MODE Xj' xrefs=1 +; text H'6AAD len=17 medium 'AI BACK.L~Xj' xrefs=1 +; text H'6B3D len=19 medium 'AUTO FUNC Xk=' xrefs=1 +; text H'6B5E len=19 medium 'AUTO FOCUS Xk^' xrefs=1 +; text H'6BEF len=18 medium 'DIAG Xk' xrefs=1 +; text H'6C16 len=18 medium 'DIAG DATA Xl' xrefs=1 +; text H'6C35 len=18 medium 'RESET REQ~Xl4' xrefs=1 +; text H'6F84 len=18 medium 'OTHERS Xo' xrefs=1 +; text H'6FAE len=18 medium 'SHUTTER Xo' xrefs=2 +; text H'7052 len=14 medium 'SET RCP' xrefs=1 +; text H'706F len=14 medium 'MASTER' xrefs=1 +; text H'709F len=18 medium 'OTHERS Xp' xrefs=2 +; text H'70C0 len=18 medium 'COPY TO SLAVES~Xp' xrefs=2 +; text H'7144 len=19 medium 'CAM ID SET~XqD' xrefs=1 +; text H'71C9 len=18 medium 'OTHERS Xq' xrefs=1 +; text H'71F9 len=18 medium 'CAM ID IND Xq' xrefs=1 +; text H'7213 len=18 medium 'TITLE IND Xr' xrefs=1 +; text H'72A5 len=18 medium 'OTHERS Xr' xrefs=1 +; text H'72C7 len=17 medium 'CAM BARS~Xr' xrefs=1 +; text H'72E4 len=18 medium 'CLOCK IND Xr' xrefs=1 +; text H'7369 len=19 medium 'OTHERS Xsi' xrefs=1 +; text H'7393 len=18 high 'CENTER MARKER Xs' xrefs=1 +; text H'7425 len=19 medium 'OTHERS Xt%' xrefs=1 +; text H'7464 len=19 medium 'SAFETY ZONE Xtd' xrefs=1 +; text H'757A len=19 medium 'BARS TYPE Xuz' xrefs=1 +; text H'75A4 len=18 medium 'SMPTE Xu' xrefs=1 +; ... 192 more LCD text candidates + +; LCD Driver Candidates +; H'F200 lcd_status_control status/control register inferred from busy polling and command writes +; H'F201 lcd_data data register inferred from paired data reads/writes +; LCD routines +; routine H'3F40-H'3F74 lcd_wait_and_transfer lcd_command_or_address_write, lcd_data_read, lcd_data_write, lcd_status_read +; LCD busy loops +; loop H'3F4A->H'3F51 LCD busy-flag poll: read H'F200, test bit 7, branch until clear + + +vec_reset_1000: +1000: 5F FE 80 MOV:I.W #H'FE80, R7 ; dataflow R7=H'FE80; cycles=3 +1003: 0C 07 00 88 LDC.W #H'0700, SR ; dataflow SR=H'0700; cycles=6 +1007: 15 FE 80 06 FF MOV:G.B #H'FF, @P1DDR ; P1DDR = H'FF; cycles=9 +100C: 15 FE 82 06 00 MOV:G.B #H'00, @P1DR ; P1DR = H'00; cycles=9 +1011: 15 FE 89 06 F9 MOV:G.B #H'F9, @P6DDR ; P6DDR = H'F9; cycles=9 +1016: 15 FE 8B 06 F1 MOV:G.B #H'F1, @P6DR ; P6DR = H'F1; cycles=9 +101B: 15 FE 8C 06 00 MOV:G.B #H'00, @P7DDR ; P7DDR = H'00; cycles=9 +1020: 15 FE 8E 06 00 MOV:G.B #H'00, @P7DR ; P7DR = H'00; cycles=9 +1025: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +102A: 15 FE FF 06 00 MOV:G.B #H'00, @P9DR ; P9DR = H'00; cycles=9 +102F: 15 FE FC 06 87 MOV:G.B #H'87, @SYSCR1 ; SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled); cycles=9 +1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; FRT1_FRC word write; TEMP byte-order hazard avoided; cycles=9 +1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_H ; FRT1_OCRA_H = H'9C; FRT1_OCRA word write; TEMP byte-order hazard avoided; cycles=11 +104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; FRT2_FRC word write; TEMP byte-order hazard avoided; cycles=11 +105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; FRT2_OCRA word write; TEMP byte-order hazard avoided; cycles=9 +1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 +1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 +106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1072: 15 FE D1 06 10 MOV:G.B #H'10, @TMR_TCSR ; TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0); cycles=9 +1077: 15 FE C0 06 38 MOV:G.B #H'38, @PWM1_TCR ; PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +107C: 15 FE C1 06 FF MOV:G.B #H'FF, @PWM1_DTR ; PWM1_DTR = H'FF; cycles=9 +1081: 15 FE C4 06 38 MOV:G.B #H'38, @PWM2_TCR ; PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1086: 15 FE C5 06 FF MOV:G.B #H'FF, @PWM2_DTR ; PWM2_DTR = H'FF; cycles=9 +108B: 15 FE C8 06 3B MOV:G.B #H'3B, @PWM3_TCR ; PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1); cycles=9 +1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D; cycles=9 +1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI1 receive and receive-error interrupts (RIE); enable SCI1 transmitter (TE); enable SCI1 receiver (RE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI2 receive and receive-error interrupts (RIE); disable SCI2 transmitter (TE); disable SCI2 receiver (RE); SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 +10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field; cycles=9 +10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 +10C2: 15 FF 11 06 FF MOV:G.B #H'FF, @RAMCR ; RAMCR = H'FF (RAME=1; on-chip RAM enabled); cycles=9 +10C7: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=8 +10CB: 30 2E A8 BRA loc_3F76 ; cycles=8 + +loc_10CE: +10CE: 5C 00 40 MOV:I.W #H'0040, R4 ; dataflow R4=H'0040; cycles=3 +10D1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10D4: 1E 2D F5 BSR loc_3ECC ; cycles=13 +10D7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10DA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10DD: 1E 2D EC BSR loc_3ECC ; cycles=14 +10E0: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10E3: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10E6: 1E 2D E3 BSR loc_3ECC ; cycles=13 +10E9: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10EC: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10EF: 1E 2D DA BSR loc_3ECC ; cycles=14 +10F2: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +10F5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10F8: 1E 2D D1 BSR loc_3ECC ; cycles=13 +10FB: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +10FE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1101: 1E 2D C8 BSR loc_3ECC ; cycles=14 +1104: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1107: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +110A: 1E 2D BF BSR loc_3ECC ; cycles=13 +110D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1110: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1113: 1E 2D B6 BSR loc_3ECC ; cycles=14 +1116: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1119: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +111C: 1E 2D AD BSR loc_3ECC ; cycles=13 +111F: 5C 00 48 MOV:I.W #H'0048, R4 ; dataflow R4=H'0048; cycles=3 +1122: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1125: 1E 2D A4 BSR loc_3ECC ; cycles=14 +1128: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +112B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +112E: 1E 2D 9B BSR loc_3ECC ; cycles=13 +1131: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1134: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1137: 1E 2D 92 BSR loc_3ECC ; cycles=14 +113A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +113D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1140: 1E 2D 89 BSR loc_3ECC ; cycles=13 +1143: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1146: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1149: 1E 2D 80 BSR loc_3ECC ; cycles=14 +114C: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +114F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1152: 1E 2D 77 BSR loc_3ECC ; cycles=13 +1155: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1158: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +115B: 1E 2D 6E BSR loc_3ECC ; cycles=14 +115E: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1161: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1164: 1E 2D 65 BSR loc_3ECC ; cycles=13 +1167: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +116A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +116D: 1E 2D 5C BSR loc_3ECC ; cycles=14 +1170: 5C 00 50 MOV:I.W #H'0050, R4 ; dataflow R4=H'0050; cycles=3 +1173: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1176: 1E 2D 53 BSR loc_3ECC ; cycles=13 +1179: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +117C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +117F: 1E 2D 4A BSR loc_3ECC ; cycles=14 +1182: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1185: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1188: 1E 2D 41 BSR loc_3ECC ; cycles=13 +118B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +118E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1191: 1E 2D 38 BSR loc_3ECC ; cycles=14 +1194: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +1197: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +119A: 1E 2D 2F BSR loc_3ECC ; cycles=13 +119D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11A3: 1E 2D 26 BSR loc_3ECC ; cycles=14 +11A6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11AC: 1E 2D 1D BSR loc_3ECC ; cycles=13 +11AF: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11B2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11B5: 1E 2D 14 BSR loc_3ECC ; cycles=14 +11B8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11BB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11BE: 1E 2D 0B BSR loc_3ECC ; cycles=13 +11C1: 5C 00 58 MOV:I.W #H'0058, R4 ; dataflow R4=H'0058; cycles=3 +11C4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11C7: 1E 2D 02 BSR loc_3ECC ; cycles=14 +11CA: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11CD: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D0: 1E 2C F9 BSR loc_3ECC ; cycles=13 +11D3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11D6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D9: 1E 2C F0 BSR loc_3ECC ; cycles=14 +11DC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11DF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11E2: 1E 2C E7 BSR loc_3ECC ; cycles=13 +11E5: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +11E8: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11EB: 1E 2C DE BSR loc_3ECC ; cycles=14 +11EE: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11F1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11F4: 1E 2C D5 BSR loc_3ECC ; cycles=13 +11F7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11FA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11FD: 1E 2C CC BSR loc_3ECC ; cycles=14 +1200: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1203: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1206: 1E 2C C3 BSR loc_3ECC ; cycles=13 +1209: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +120C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +120F: 1E 2C BA BSR loc_3ECC ; cycles=14 +1212: 5C 00 60 MOV:I.W #H'0060, R4 ; dataflow R4=H'0060; cycles=3 +1215: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1218: 1E 2C B1 BSR loc_3ECC ; cycles=13 +121B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +121E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1221: 1E 2C A8 BSR loc_3ECC ; cycles=14 +1224: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1227: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +122A: 1E 2C 9F BSR loc_3ECC ; cycles=13 +122D: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1230: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1233: 1E 2C 96 BSR loc_3ECC ; cycles=14 +1236: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1239: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +123C: 1E 2C 8D BSR loc_3ECC ; cycles=13 +123F: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1242: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1245: 1E 2C 84 BSR loc_3ECC ; cycles=14 +1248: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +124B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +124E: 1E 2C 7B BSR loc_3ECC ; cycles=13 +1251: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1254: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1257: 1E 2C 72 BSR loc_3ECC ; cycles=14 +125A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +125D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1260: 1E 2C 69 BSR loc_3ECC ; cycles=13 +1263: 5C 00 68 MOV:I.W #H'0068, R4 ; dataflow R4=H'0068; cycles=3 +1266: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1269: 1E 2C 60 BSR loc_3ECC ; cycles=14 +126C: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +126F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1272: 1E 2C 57 BSR loc_3ECC ; cycles=13 +1275: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1278: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +127B: 1E 2C 4E BSR loc_3ECC ; cycles=14 +127E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1281: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1284: 1E 2C 45 BSR loc_3ECC ; cycles=13 +1287: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +128A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +128D: 1E 2C 3C BSR loc_3ECC ; cycles=14 +1290: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1293: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1296: 1E 2C 33 BSR loc_3ECC ; cycles=13 +1299: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +129C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +129F: 1E 2C 2A BSR loc_3ECC ; cycles=14 +12A2: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12A5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12A8: 1E 2C 21 BSR loc_3ECC ; cycles=13 +12AB: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12AE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12B1: 1E 2C 18 BSR loc_3ECC ; cycles=14 +12B4: 5C 00 70 MOV:I.W #H'0070, R4 ; dataflow R4=H'0070; cycles=3 +12B7: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12BA: 1E 2C 0F BSR loc_3ECC ; cycles=13 +12BD: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12C3: 1E 2C 06 BSR loc_3ECC ; cycles=14 +12C6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12CC: 1E 2B FD BSR loc_3ECC ; cycles=13 +12CF: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12D2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12D5: 1E 2B F4 BSR loc_3ECC ; cycles=14 +12D8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12DB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12DE: 1E 2B EB BSR loc_3ECC ; cycles=13 +12E1: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12E4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12E7: 1E 2B E2 BSR loc_3ECC ; cycles=14 +12EA: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12ED: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F0: 1E 2B D9 BSR loc_3ECC ; cycles=13 +12F3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12F6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F9: 1E 2B D0 BSR loc_3ECC ; cycles=14 +12FC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12FF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1302: 1E 2B C7 BSR loc_3ECC ; cycles=13 +1305: 5C 00 78 MOV:I.W #H'0078, R4 ; dataflow R4=H'0078; cycles=3 +1308: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +130B: 1E 2B BE BSR loc_3ECC ; cycles=14 +130E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1311: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1314: 1E 2B B5 BSR loc_3ECC ; cycles=13 +1317: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +131A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +131D: 1E 2B AC BSR loc_3ECC ; cycles=14 +1320: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1323: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1326: 1E 2B A3 BSR loc_3ECC ; cycles=13 +1329: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +132C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +132F: 1E 2B 9A BSR loc_3ECC ; cycles=14 +1332: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1335: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1338: 1E 2B 91 BSR loc_3ECC ; cycles=13 +133B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +133E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1341: 1E 2B 88 BSR loc_3ECC ; cycles=14 +1344: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1347: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +134A: 1E 2B 7F BSR loc_3ECC ; cycles=13 +134D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1350: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1353: 1E 2B 76 BSR loc_3ECC ; cycles=14 +1356: 19 RTS ; cycles=12 + +loc_15E0: +15E0: 1E 10 6D BSR loc_2650 ; cycles=13 +15E3: 15 F6 89 D7 BCLR.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=8 +15E7: 27 10 BEQ loc_15F9 ; cycles=3/8 nt/t +15E9: 1D F6 8E 81 MOV:G.W @H'F68E, R1 ; refs ram_F68E in on_chip_ram; cycles=6 +15ED: 1D E9 02 91 MOV:G.W R1, @H'E902 ; refs mem_E902 in program_or_external; cycles=6 +15F1: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +15F3: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +15F6: 1E 28 5B BSR loc_3E54 ; cycles=13 + +loc_15F9: +15F9: 15 F6 F0 16 TST.B @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +15FD: 27 3E BEQ loc_163D ; cycles=3/8 nt/t +15FF: 15 F6 F0 D7 BCLR.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1603: 27 03 BEQ loc_1608 ; cycles=3/8 nt/t +1605: 18 43 94 JSR @loc_4394 ; cycles=14 + +loc_1608: +1608: 15 F6 F0 D6 BCLR.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +160C: 27 03 BEQ loc_1611 ; cycles=3/7 nt/t +160E: 18 44 57 JSR @loc_4457 ; cycles=13 + +loc_1611: +1611: 15 F6 F0 D5 BCLR.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1615: 27 03 BEQ loc_161A ; cycles=3/8 nt/t +1617: 18 45 1A JSR @loc_451A ; cycles=14 + +loc_161A: +161A: 15 F6 F0 D4 BCLR.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +161E: 15 F6 F0 D3 BCLR.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1622: 27 03 BEQ loc_1627 ; cycles=3/7 nt/t +1624: 18 17 05 JSR @loc_1705 ; cycles=13 + +loc_1627: +1627: 15 F6 F0 D2 BCLR.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +162B: 27 03 BEQ loc_1630 ; cycles=3/8 nt/t +162D: 18 17 4D JSR @loc_174D ; cycles=14 + +loc_1630: +1630: 15 F6 F0 D1 BCLR.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1634: 27 03 BEQ loc_1639 ; cycles=3/7 nt/t +1636: 18 17 95 JSR @loc_1795 ; cycles=13 + +loc_1639: +1639: 15 F6 F0 D0 BCLR.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 + +loc_163D: +163D: 15 F6 F1 16 TST.B @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=6 +1641: 27 43 BEQ loc_1686 ; cycles=3/8 nt/t +1643: 15 F6 F1 D7 BCLR.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1647: 27 03 BEQ loc_164C ; cycles=3/8 nt/t +1649: 18 17 C9 JSR @loc_17C9 ; cycles=14 + +loc_164C: +164C: 15 F6 F1 D6 BCLR.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1650: 27 03 BEQ loc_1655 ; cycles=3/7 nt/t +1652: 18 17 FB JSR @loc_17FB ; cycles=13 + +loc_1655: +1655: 15 F6 F1 D5 BCLR.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1659: 27 03 BEQ loc_165E ; cycles=3/8 nt/t +165B: 18 18 2D JSR @loc_182D ; cycles=14 + +loc_165E: +165E: 15 F6 F1 D4 BCLR.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1662: 27 03 BEQ loc_1667 ; cycles=3/7 nt/t +1664: 18 18 91 JSR @loc_1891 ; cycles=13 + +loc_1667: +1667: 15 F6 F1 D3 BCLR.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +166B: 27 03 BEQ loc_1670 ; cycles=3/8 nt/t +166D: 18 18 E7 JSR @loc_18E7 ; cycles=14 + +loc_1670: +1670: 15 F6 F1 D2 BCLR.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1674: 27 03 BEQ loc_1679 ; cycles=3/7 nt/t +1676: 18 19 4A JSR @loc_194A ; cycles=13 + +loc_1679: +1679: 15 F6 F1 D1 BCLR.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +167D: 27 03 BEQ loc_1682 ; cycles=3/8 nt/t +167F: 18 19 79 JSR @loc_1979 ; cycles=14 + +loc_1682: +1682: 15 F6 F1 D0 BCLR.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 + +loc_1686: +1686: 15 F6 F2 16 TST.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=7 +168A: 27 48 BEQ loc_16D4 ; cycles=3/7 nt/t +168C: 15 F6 F2 D7 BCLR.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +1690: 27 03 BEQ loc_1695 ; cycles=3/7 nt/t +1692: 18 1B 2D JSR @loc_1B2D ; cycles=13 + +loc_1695: +1695: 15 F6 F2 D6 BCLR.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +1699: 27 03 BEQ loc_169E ; cycles=3/8 nt/t +169B: 18 1B 44 JSR @loc_1B44 ; cycles=14 + +loc_169E: +169E: 15 F6 F2 D5 BCLR.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16A2: 27 03 BEQ loc_16A7 ; cycles=3/7 nt/t +16A4: 18 1B 5B JSR @loc_1B5B ; cycles=13 + +loc_16A7: +16A7: 15 F6 F2 D4 BCLR.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16AB: 27 03 BEQ loc_16B0 ; cycles=3/8 nt/t +16AD: 18 1B A0 JSR @loc_1BA0 ; cycles=14 + +loc_16B0: +16B0: 15 F6 F2 D3 BCLR.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16B4: 27 03 BEQ loc_16B9 ; cycles=3/7 nt/t +16B6: 18 1B B6 JSR @loc_1BB6 ; cycles=13 + +loc_16B9: +16B9: 15 F6 F2 D2 BCLR.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16BD: 27 03 BEQ loc_16C2 ; cycles=3/8 nt/t +16BF: 18 1B CC JSR @loc_1BCC ; cycles=14 + +loc_16C2: +16C2: 15 F6 F2 D1 BCLR.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16C6: 27 03 BEQ loc_16CB ; cycles=3/7 nt/t +16C8: 18 1B 72 JSR @loc_1B72 ; cycles=13 + +loc_16CB: +16CB: 15 F6 F2 D0 BCLR.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16CF: 27 03 BEQ loc_16D4 ; cycles=3/8 nt/t +16D1: 18 1B 89 JSR @loc_1B89 ; cycles=14 + +loc_16D4: +16D4: 15 F6 F3 16 TST.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=7 +16D8: 27 2A BEQ loc_1704 ; cycles=3/7 nt/t +16DA: 15 F6 F3 D7 BCLR.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16DE: 15 F6 F3 D6 BCLR.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E2: 15 F6 F3 D5 BCLR.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E6: 15 F6 F3 D4 BCLR.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16EA: 27 03 BEQ loc_16EF ; cycles=3/7 nt/t +16EC: 18 1B E2 JSR @loc_1BE2 ; cycles=13 + +loc_16EF: +16EF: 15 F6 F3 D3 BCLR.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=8 +16F3: 27 03 BEQ loc_16F8 ; cycles=3/8 nt/t +16F5: 18 1B F8 JSR @loc_1BF8 ; cycles=14 + +loc_16F8: +16F8: 15 F6 F3 D2 BCLR.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16FC: 15 F6 F3 D1 BCLR.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +1700: 15 F6 F3 D0 BCLR.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 + +loc_1704: +1704: 19 RTS ; cycles=12 + +loc_1705: +1705: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +170A: 22 38 BHI loc_1744 ; cycles=3/7 nt/t +170C: 1D E1 4E FF BTST.W #15, @H'E14E ; refs mem_E14E in program_or_external; cycles=7 +1710: 26 24 BNE loc_1736 ; cycles=3/7 nt/t +1712: 15 F7 30 F6 BTST.B #6, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1716: 26 1E BNE loc_1736 ; cycles=3/7 nt/t +1718: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +171C: 26 08 BNE loc_1726 ; cycles=3/7 nt/t +171E: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +1722: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_1726: +1726: 1D F7 32 07 1C 07 MOV:G.W #H'1C07, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +172C: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1731: 1E 31 C6 BSR loc_48FA ; cycles=14 +1734: 20 0E BRA loc_1744 ; cycles=7 + +loc_1736: +1736: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +173A: 1D F6 B6 34 SUB.W @H'F6B6, R4 ; refs ram_F6B6 in on_chip_ram; cycles=7 +173E: 5B 00 A9 MOV:I.W #H'00A9, R3 ; dataflow R3=H'00A9; cycles=3 +1741: 1E 02 5E BSR loc_19A2 ; cycles=14 + +loc_1744: +1744: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +1748: 1D F6 B6 94 MOV:G.W R4, @H'F6B6 ; refs ram_F6B6 in on_chip_ram; cycles=7 +174C: 19 RTS ; cycles=12 + +loc_174D: +174D: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1752: 22 38 BHI loc_178C ; cycles=3/7 nt/t +1754: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1758: 27 32 BEQ loc_178C ; cycles=3/7 nt/t +175A: 1D E1 6E FD BTST.W #13, @H'E16E ; refs mem_E16E in program_or_external; cycles=7 +175E: 26 1E BNE loc_177E ; cycles=3/7 nt/t +1760: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +1764: 26 08 BNE loc_176E ; cycles=3/7 nt/t +1766: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +176A: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_176E: +176E: 1D F7 32 07 1C 06 MOV:G.W #H'1C06, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +1774: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1779: 1E 31 7E BSR loc_48FA ; cycles=14 +177C: 20 0E BRA loc_178C ; cycles=7 + +loc_177E: +177E: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1782: 1D F6 B4 34 SUB.W @H'F6B4, R4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1786: 5B 00 C5 MOV:I.W #H'00C5, R3 ; dataflow R3=H'00C5; cycles=3 +1789: 1E 02 16 BSR loc_19A2 ; cycles=14 + +loc_178C: +178C: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1790: 1D F6 B4 94 MOV:G.W R4, @H'F6B4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1794: 19 RTS ; cycles=12 + +loc_1795: +1795: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +179A: 22 24 BHI loc_17C0 ; cycles=3/7 nt/t +179C: 1D E1 72 FD BTST.W #13, @H'E172 ; refs mem_E172 in program_or_external; cycles=7 +17A0: 26 05 BNE loc_17A7 ; cycles=3/7 nt/t +17A2: 1E 09 82 BSR loc_2127 ; cycles=13 +17A5: 20 19 BRA loc_17C0 ; cycles=8 + +loc_17A7: +17A7: 1D E2 20 FF BTST.W #15, @H'E220 ; refs mem_E220 in program_or_external; cycles=6 +17AB: 27 05 BEQ loc_17B2 ; cycles=3/8 nt/t +17AD: 1E 09 77 BSR loc_2127 ; cycles=14 +17B0: 20 0E BRA loc_17C0 ; cycles=7 + +loc_17B2: +17B2: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17B6: 1D F6 B2 34 SUB.W @H'F6B2, R4 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17BA: 5B 00 BC MOV:I.W #H'00BC, R3 ; dataflow R3=H'00BC; cycles=3 +17BD: 1E 01 E2 BSR loc_19A2 ; cycles=14 + +loc_17C0: +17C0: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17C4: 1D F6 B2 94 MOV:G.W R4, @H'F6B2 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17C8: 19 RTS ; cycles=12 + +loc_17C9: +17C9: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +17CE: 22 22 BHI loc_17F2 ; cycles=3/7 nt/t +17D0: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +17D4: 27 1C BEQ loc_17F2 ; cycles=3/7 nt/t +17D6: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17DA: 1D F6 CE 34 SUB.W @H'F6CE, R4 ; refs ram_F6CE in on_chip_ram; cycles=7 +17DE: 5B 00 A3 MOV:I.W #H'00A3, R3 ; dataflow R3=H'00A3; cycles=3 +17E1: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +17E5: 27 08 BEQ loc_17EF ; cycles=3/8 nt/t +17E7: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +17EB: 27 02 BEQ loc_17EF ; cycles=3/8 nt/t +17ED: AB CE BSET.W #14, R3 ; cycles=3 + +loc_17EF: +17EF: 1E 01 B0 BSR loc_19A2 ; cycles=14 + +loc_17F2: +17F2: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17F6: 1D F6 CE 94 MOV:G.W R4, @H'F6CE ; refs ram_F6CE in on_chip_ram; cycles=7 +17FA: 19 RTS ; cycles=12 + +loc_17FB: +17FB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1800: 22 22 BHI loc_1824 ; cycles=3/7 nt/t +1802: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +1806: 27 1C BEQ loc_1824 ; cycles=3/7 nt/t +1808: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +180C: 1D F6 CC 34 SUB.W @H'F6CC, R4 ; refs ram_F6CC in on_chip_ram; cycles=7 +1810: 5B 00 A4 MOV:I.W #H'00A4, R3 ; dataflow R3=H'00A4; cycles=3 +1813: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1817: 27 08 BEQ loc_1821 ; cycles=3/8 nt/t +1819: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +181D: 27 02 BEQ loc_1821 ; cycles=3/8 nt/t +181F: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1821: +1821: 1E 01 7E BSR loc_19A2 ; cycles=14 + +loc_1824: +1824: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +1828: 1D F6 CC 94 MOV:G.W R4, @H'F6CC ; refs ram_F6CC in on_chip_ram; cycles=7 +182C: 19 RTS ; cycles=12 + +loc_182D: +182D: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1831: 26 32 BNE loc_1865 ; cycles=3/8 nt/t +1833: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1838: 22 22 BHI loc_185C ; cycles=3/7 nt/t +183A: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +183E: 27 1C BEQ loc_185C ; cycles=3/7 nt/t +1840: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1844: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1848: 5B 00 A5 MOV:I.W #H'00A5, R3 ; dataflow R3=H'00A5; cycles=3 +184B: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +184F: 27 08 BEQ loc_1859 ; cycles=3/8 nt/t +1851: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1855: 27 02 BEQ loc_1859 ; cycles=3/8 nt/t +1857: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1859: +1859: 1E 01 46 BSR loc_19A2 ; cycles=14 + +loc_185C: +185C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1860: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1864: 19 RTS ; cycles=12 + +loc_1865: +1865: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +186A: 22 1C BHI loc_1888 ; cycles=3/7 nt/t +186C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1870: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1874: 5B 00 D8 MOV:I.W #H'00D8, R3 ; dataflow R3=H'00D8; cycles=3 +1877: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +187B: 27 08 BEQ loc_1885 ; cycles=3/8 nt/t +187D: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1881: 27 02 BEQ loc_1885 ; cycles=3/8 nt/t +1883: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1885: +1885: 1E 01 1A BSR loc_19A2 ; cycles=14 + +loc_1888: +1888: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +188C: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1890: 19 RTS ; cycles=12 + +loc_1891: +1891: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1895: 26 24 BNE loc_18BB ; cycles=3/8 nt/t +1897: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +189C: 22 14 BHI loc_18B2 ; cycles=3/7 nt/t +189E: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18A2: 27 0E BEQ loc_18B2 ; cycles=3/7 nt/t +18A4: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18A8: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18AC: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +18AF: 1E 00 F0 BSR loc_19A2 ; cycles=14 + +loc_18B2: +18B2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18B6: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18BA: 19 RTS ; cycles=12 + +loc_18BB: +18BB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18C0: 22 1C BHI loc_18DE ; cycles=3/7 nt/t +18C2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18C6: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18CA: 5B 00 D9 MOV:I.W #H'00D9, R3 ; dataflow R3=H'00D9; cycles=3 +18CD: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +18D1: 27 08 BEQ loc_18DB ; cycles=3/8 nt/t +18D3: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +18D7: 27 02 BEQ loc_18DB ; cycles=3/8 nt/t +18D9: AB CE BSET.W #14, R3 ; cycles=3 + +loc_18DB: +18DB: 1E 00 C4 BSR loc_19A2 ; cycles=14 + +loc_18DE: +18DE: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18E2: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18E6: 19 RTS ; cycles=12 + +loc_18E7: +18E7: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +18EB: 26 32 BNE loc_191F ; cycles=3/8 nt/t +18ED: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18F2: 22 22 BHI loc_1916 ; cycles=3/7 nt/t +18F4: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18F8: 27 1C BEQ loc_1916 ; cycles=3/7 nt/t +18FA: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +18FE: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +1902: 5B 00 A6 MOV:I.W #H'00A6, R3 ; dataflow R3=H'00A6; cycles=3 +1905: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1909: 27 08 BEQ loc_1913 ; cycles=3/8 nt/t +190B: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +190F: 27 02 BEQ loc_1913 ; cycles=3/8 nt/t +1911: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1913: +1913: 1E 00 8C BSR loc_19A2 ; cycles=14 + +loc_1916: +1916: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +191A: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=7 +191E: 19 RTS ; cycles=12 + +loc_191F: +191F: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1924: 22 1B BHI loc_1941 ; cycles=3/7 nt/t +1926: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +192A: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +192E: 5B 00 DA MOV:I.W #H'00DA, R3 ; dataflow R3=H'00DA; cycles=3 +1931: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1935: 27 08 BEQ loc_193F ; cycles=3/8 nt/t +1937: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +193B: 27 02 BEQ loc_193F ; cycles=3/8 nt/t +193D: AB CE BSET.W #14, R3 ; cycles=3 + +loc_193F: +193F: 0E 61 BSR loc_19A2 ; cycles=14 + +loc_1941: +1941: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=6 +1945: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=6 +1949: 19 RTS ; cycles=13 + +loc_194A: +194A: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +194F: 22 1F BHI loc_1970 ; cycles=3/8 nt/t +1951: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=6 +1955: 1D F6 C4 34 SUB.W @H'F6C4, R4 ; refs ram_F6C4 in on_chip_ram; cycles=6 +1959: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +195D: 26 00 BNE loc_195F ; cycles=3/8 nt/t + +loc_195F: +195F: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +1962: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +1966: 27 02 BEQ loc_196A ; cycles=3/7 nt/t +1968: AB CE BSET.W #14, R3 ; cycles=3 + +loc_196A: +196A: 0E 36 BSR loc_19A2 ; cycles=13 +196C: 15 F7 6D C7 BSET.B #7, @H'F76D ; refs ram_F76D in on_chip_ram; cycles=9 + +loc_1970: +1970: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=7 +1974: 1D F6 C4 94 MOV:G.W R4, @H'F6C4 ; refs ram_F6C4 in on_chip_ram; cycles=7 +1978: 19 RTS ; cycles=12 + +loc_1979: +1979: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +197E: 22 19 BHI loc_1999 ; cycles=3/7 nt/t +1980: 1D F6 A2 80 MOV:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +1984: 1D F6 C2 30 SUB.W @H'F6C2, R0 ; refs ram_F6C2 in on_chip_ram; cycles=7 +1988: 1D F6 8C A8 MULXU.W @H'F68C, R0 ; refs ram_F68C in on_chip_ram; cycles=26 +198C: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +198F: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1993: 27 02 BEQ loc_1997 ; cycles=3/8 nt/t +1995: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1997: +1997: 0E 42 BSR loc_19DB ; cycles=14 + +loc_1999: +1999: 1D F6 A2 84 MOV:G.W @H'F6A2, R4 ; refs ram_F6A2 in on_chip_ram; cycles=6 +199D: 1D F6 C2 94 MOV:G.W R4, @H'F6C2 ; refs ram_F6C2 in on_chip_ram; cycles=6 +19A1: 19 RTS ; cycles=13 + +loc_19A2: +19A2: AB 85 MOV:G.W R3, R5 ; cycles=3 +19A4: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19A8: AB 1A SHLL.W R3 ; cycles=3 +19AA: FB E4 00 80 MOV:G.W @(-H'1C00,R3), R0 ; cycles=7 +19AE: 48 FC 00 CMP:I #H'FC00, R0 ; cycles=3 +19B1: 22 03 BHI loc_19B6 ; cycles=3/8 nt/t +19B3: 58 FE 00 MOV:I.W #H'FE00, R0 ; dataflow R0=H'FE00; cycles=3 + +loc_19B6: +19B6: A8 15 NOT.W R0 ; cycles=3 +19B8: A8 08 ADD:Q.W #1, R0 ; cycles=4 +19BA: 4C 00 0F CMP:I #H'000F, R4 ; cycles=3 +19BD: 23 14 BLS loc_19D3 ; cycles=3/8 nt/t +19BF: 4C FF F0 CMP:I #H'FFF0, R4 ; cycles=3 +19C2: 24 0F BCC loc_19D3 ; cycles=3/7 nt/t +19C4: 4C 80 00 CMP:I #H'8000, R4 ; cycles=3 +19C7: 24 05 BCC loc_19CE ; cycles=3/8 nt/t +19C9: 5C 00 1A MOV:I.W #H'001A, R4 ; dataflow R4=H'001A; cycles=3 +19CC: 20 09 BRA loc_19D7 ; cycles=7 + +loc_19CE: +19CE: 5C FF 1C MOV:I.W #H'FF1C, R4 ; dataflow R4=H'FF1C; cycles=3 +19D1: 20 04 BRA loc_19D7 ; cycles=8 + +loc_19D3: +19D3: F4 1A 25 84 MOV:G.B @(H'1A25,R4), R4 ; cycles=6 + +loc_19D7: +19D7: AC A8 MULXU.W R4, R0 ; cycles=25 +19D9: 20 08 BRA loc_19E3 ; cycles=8 + +loc_19DB: +19DB: AB 85 MOV:G.W R3, R5 ; cycles=3 +19DD: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19E1: AB 1A SHLL.W R3 ; cycles=3 + +loc_19E3: +19E3: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +19E7: A8 21 ADD:G.W R0, R1 ; cycles=3 +19E9: A9 82 MOV:G.W R1, R2 ; cycles=3 +19EB: 25 0C BCS loc_19F9 ; cycles=3/8 nt/t +19ED: A8 32 SUB.W R0, R2 ; cycles=3 +19EF: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +19F2: 23 0F BLS loc_1A03 ; cycles=3/7 nt/t +19F4: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +19F7: 20 0A BRA loc_1A03 ; cycles=8 + +loc_19F9: +19F9: AA 30 SUB.W R2, R0 ; cycles=3 +19FB: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +19FE: 23 03 BLS loc_1A03 ; cycles=3/7 nt/t +1A00: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_1A03: +1A03: FB E0 00 71 CMP:G.W @(-H'2000,R3), R1 ; cycles=6 +1A07: 27 0B BEQ loc_1A14 ; cycles=3/8 nt/t +1A09: FB E8 00 91 MOV:G.W R1, @(-H'1800,R3) ; cycles=6 +1A0D: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A0F: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A11: 1E 24 40 BSR loc_3E54 ; cycles=14 + +loc_1A14: +1A14: 19 RTS ; cycles=12 + +loc_1A35: +1A35: AB 85 MOV:G.W R3, R5 ; cycles=3 +1A37: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +1A3B: AB 1A SHLL.W R3 ; cycles=3 +1A3D: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +1A41: 27 3A BEQ loc_1A7D ; cycles=3/8 nt/t +1A43: 0E 48 BSR loc_1A8D ; cycles=14 + +loc_1A45: +1A45: AC 16 TST.W R4 ; cycles=3 +1A47: 26 10 BNE loc_1A59 ; cycles=3/8 nt/t +1A49: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A4B: +1A4B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A4F: A8 1B SHLR.W R0 ; cycles=3 +1A51: 27 16 BEQ loc_1A69 ; cycles=3/8 nt/t +1A53: A8 51 AND.W R0, R1 ; cycles=3 +1A55: 27 F4 BEQ loc_1A4B ; cycles=3/8 nt/t +1A57: 20 12 BRA loc_1A6B ; cycles=8 + +loc_1A59: +1A59: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A5B: +1A5B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A5F: A8 1A SHLL.W R0 ; cycles=3 +1A61: 27 06 BEQ loc_1A69 ; cycles=3/8 nt/t +1A63: A8 51 AND.W R0, R1 ; cycles=3 +1A65: 27 F4 BEQ loc_1A5B ; cycles=3/8 nt/t +1A67: 20 02 BRA loc_1A6B ; cycles=8 + +loc_1A69: +1A69: AA 80 MOV:G.W R2, R0 ; cycles=3 + +loc_1A6B: +1A6B: FB E0 00 70 CMP:G.W @(-H'2000,R3), R0 ; cycles=6 +1A6F: 27 0B BEQ loc_1A7C ; cycles=3/8 nt/t +1A71: FB E8 00 90 MOV:G.W R0, @(-H'1800,R3) ; cycles=6 +1A75: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A77: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A79: 1E 23 D8 BSR loc_3E54 ; cycles=14 + +loc_1A7C: +1A7C: 19 RTS ; cycles=12 + +loc_1A7D: +1A7D: A8 CF BSET.W #15, R0 ; cycles=3 + +loc_1A7F: +1A7F: A8 81 MOV:G.W R0, R1 ; cycles=3 +1A81: FB E4 00 51 AND.W @(-H'1C00,R3), R1 ; cycles=6 +1A85: 26 04 BNE loc_1A8B ; cycles=3/8 nt/t +1A87: A8 1B SHLR.W R0 ; cycles=3 +1A89: 20 F4 BRA loc_1A7F ; cycles=8 + +loc_1A8B: +1A8B: 20 B8 BRA loc_1A45 ; cycles=8 + +loc_1A8D: +1A8D: 59 00 0F MOV:I.W #H'000F, R1 ; dataflow R1=H'000F; cycles=3 + +loc_1A90: +1A90: A8 79 BTST.W R1, R0 ; cycles=3 +1A92: 26 03 BNE loc_1A97 ; cycles=3/7 nt/t +1A94: 01 B9 F9 SCB/F R1, loc_1A90 ; cycles=3/4/8 false/-1/t + +loc_1A97: +1A97: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +1A99: A8 49 BSET.W R1, R0 ; cycles=3 +1A9B: 19 RTS ; cycles=13 + +loc_1A9C: +1A9C: AB 16 TST.W R3 ; cycles=3 +1A9E: 27 32 BEQ loc_1AD2 ; cycles=3/7 nt/t +1AA0: AB 1A SHLL.W R3 ; cycles=3 +1AA2: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +1AA6: A0 15 NOT.B R0 ; cycles=2 +1AA8: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AAB: AC 16 TST.W R4 ; cycles=3 +1AAD: 26 0D BNE loc_1ABC ; cycles=3/8 nt/t + +loc_1AAF: +1AAF: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1AB1: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AB4: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=7 +1AB8: 27 F5 BEQ loc_1AAF ; cycles=3/7 nt/t +1ABA: 20 0B BRA loc_1AC7 ; cycles=7 + +loc_1ABC: +1ABC: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1ABE: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AC1: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=6 +1AC5: 27 F5 BEQ loc_1ABC ; cycles=3/8 nt/t + +loc_1AC7: +1AC7: A0 15 NOT.B R0 ; cycles=2 +1AC9: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1ACC: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +1AD0: 20 0E BRA loc_1AE0 ; cycles=7 + +loc_1AD2: +1AD2: AC 16 TST.W R4 ; cycles=3 +1AD4: 26 06 BNE loc_1ADC ; cycles=3/7 nt/t +1AD6: 15 F7 33 08 ADD:Q.B #1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +1ADA: 20 04 BRA loc_1AE0 ; cycles=7 + +loc_1ADC: +1ADC: 15 F7 33 0C ADD:Q.B #-1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 + +loc_1AE0: +1AE0: 1E 2E 17 BSR loc_48FA ; cycles=13 +1AE3: 19 RTS ; cycles=13 + +loc_1AE4: +1AE4: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=7 +1AE8: A0 12 EXTU.B R0 ; cycles=3 +1AEA: F0 F7 5D 81 MOV:G.B @(-H'08A3,R0), R1 ; cycles=7 +1AEE: AC 16 TST.W R4 ; cycles=3 +1AF0: 26 0A BNE loc_1AFC ; cycles=3/7 nt/t +1AF2: A1 08 ADD:Q.B #1, R1 ; cycles=4 +1AF4: 41 2E CMP:E #H'2E, R1 ; cycles=2 +1AF6: 23 0B BLS loc_1B03 ; cycles=3/7 nt/t +1AF8: 51 00 MOV:E.B #H'00, R1 ; dataflow R1=H'00; cycles=2 +1AFA: 20 07 BRA loc_1B03 ; cycles=7 + +loc_1AFC: +1AFC: 04 01 31 SUB.B #H'01, R1 ; cycles=3 +1AFF: 24 02 BCC loc_1B03 ; cycles=3/8 nt/t +1B01: 51 2E MOV:E.B #H'2E, R1 ; dataflow R1=H'2E; cycles=2 + +loc_1B03: +1B03: F0 F7 5D 91 MOV:G.B R1, @(-H'08A3,R0) ; cycles=6 +1B07: 1E 2D F0 BSR loc_48FA ; cycles=14 +1B0A: 19 RTS ; cycles=12 + +loc_1B0B: +1B0B: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=6 +1B0F: AC 16 TST.W R4 ; cycles=3 +1B11: 26 0A BNE loc_1B1D ; cycles=3/8 nt/t +1B13: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1B15: 40 08 CMP:E #H'08, R0 ; cycles=2 +1B17: 23 0C BLS loc_1B25 ; cycles=3/8 nt/t +1B19: 50 08 MOV:E.B #H'08, R0 ; dataflow R0=H'08; cycles=2 +1B1B: 20 08 BRA loc_1B25 ; cycles=8 + +loc_1B1D: +1B1D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1B1F: 40 01 CMP:E #H'01, R0 ; cycles=2 +1B21: 24 02 BCC loc_1B25 ; cycles=3/8 nt/t +1B23: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_1B25: +1B25: 15 F7 5B 90 MOV:G.B R0, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=6 +1B29: 1E 2D CE BSR loc_48FA ; cycles=14 +1B2C: 19 RTS ; cycles=12 + +loc_1B2D: +1B2D: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B31: 15 F6 E7 64 XOR.B @H'F6E7, R4 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B35: 5D 00 7E MOV:I.W #H'007E, R5 ; dataflow R5=H'007E; cycles=3 +1B38: 1E 00 D3 BSR loc_1C0E ; cycles=13 +1B3B: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B3F: 15 F6 E7 94 MOV:G.B R4, @H'F6E7 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B43: 19 RTS ; cycles=13 + +loc_1B44: +1B44: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B48: 15 F6 E6 64 XOR.B @H'F6E6, R4 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B4C: 5D 00 6E MOV:I.W #H'006E, R5 ; dataflow R5=H'006E; cycles=3 +1B4F: 1E 00 BC BSR loc_1C0E ; cycles=14 +1B52: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B56: 15 F6 E6 94 MOV:G.B R4, @H'F6E6 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B5A: 19 RTS ; cycles=12 + +loc_1B5B: +1B5B: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B5F: 15 F6 E5 64 XOR.B @H'F6E5, R4 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B63: 5D 00 5E MOV:I.W #H'005E, R5 ; dataflow R5=H'005E; cycles=3 +1B66: 1E 00 A5 BSR loc_1C0E ; cycles=13 +1B69: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B6D: 15 F6 E5 94 MOV:G.B R4, @H'F6E5 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B71: 19 RTS ; cycles=13 + +loc_1B72: +1B72: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B76: 15 F6 E1 64 XOR.B @H'F6E1, R4 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B7A: 5D 00 1E MOV:I.W #H'001E, R5 ; dataflow R5=H'001E; cycles=3 +1B7D: 1E 00 8E BSR loc_1C0E ; cycles=14 +1B80: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B84: 15 F6 E1 94 MOV:G.B R4, @H'F6E1 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B88: 19 RTS ; cycles=12 + +loc_1B89: +1B89: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B8D: 15 F6 E0 64 XOR.B @H'F6E0, R4 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B91: 5D 00 0E MOV:I.W #H'000E, R5 ; dataflow R5=H'000E; cycles=3 +1B94: 1E 00 77 BSR loc_1C0E ; cycles=13 +1B97: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B9B: 15 F6 E0 94 MOV:G.B R4, @H'F6E0 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B9F: 19 RTS ; cycles=13 + +loc_1BA0: +1BA0: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=7 +1BA4: 15 F6 E4 64 XOR.B @H'F6E4, R4 ; refs ram_F6E4 in on_chip_ram; cycles=7 +1BA8: 5D 00 4E MOV:I.W #H'004E, R5 ; dataflow R5=H'004E; cycles=3 +1BAB: 0E 61 BSR loc_1C0E ; cycles=14 +1BAD: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=6 +1BB1: 15 F6 E4 94 MOV:G.B R4, @H'F6E4 ; refs ram_F6E4 in on_chip_ram; cycles=6 +1BB5: 19 RTS ; cycles=13 + +loc_1BB6: +1BB6: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=7 +1BBA: 15 F6 E3 64 XOR.B @H'F6E3, R4 ; refs ram_F6E3 in on_chip_ram; cycles=7 +1BBE: 5D 00 3E MOV:I.W #H'003E, R5 ; dataflow R5=H'003E; cycles=3 +1BC1: 0E 4B BSR loc_1C0E ; cycles=14 +1BC3: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=6 +1BC7: 15 F6 E3 94 MOV:G.B R4, @H'F6E3 ; refs ram_F6E3 in on_chip_ram; cycles=6 +1BCB: 19 RTS ; cycles=13 + +loc_1BCC: +1BCC: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=7 +1BD0: 15 F6 E2 64 XOR.B @H'F6E2, R4 ; refs ram_F6E2 in on_chip_ram; cycles=7 +1BD4: 5D 00 2E MOV:I.W #H'002E, R5 ; dataflow R5=H'002E; cycles=3 +1BD7: 0E 35 BSR loc_1C0E ; cycles=14 +1BD9: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=6 +1BDD: 15 F6 E2 94 MOV:G.B R4, @H'F6E2 ; refs ram_F6E2 in on_chip_ram; cycles=6 +1BE1: 19 RTS ; cycles=13 + +loc_1BE2: +1BE2: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=7 +1BE6: 15 F6 EC 64 XOR.B @H'F6EC, R4 ; refs ram_F6EC in on_chip_ram; cycles=7 +1BEA: 5D 00 CE MOV:I.W #H'00CE, R5 ; dataflow R5=H'00CE; cycles=3 +1BED: 0E 1F BSR loc_1C0E ; cycles=14 +1BEF: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=6 +1BF3: 15 F6 EC 94 MOV:G.B R4, @H'F6EC ; refs ram_F6EC in on_chip_ram; cycles=6 +1BF7: 19 RTS ; cycles=13 + +loc_1BF8: +1BF8: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=7 +1BFC: 15 F6 EB 64 XOR.B @H'F6EB, R4 ; refs ram_F6EB in on_chip_ram; cycles=7 +1C00: 5D 00 BE MOV:I.W #H'00BE, R5 ; dataflow R5=H'00BE; cycles=3 +1C03: 0E 09 BSR loc_1C0E ; cycles=14 +1C05: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=6 +1C09: 15 F6 EB 94 MOV:G.B R4, @H'F6EB ; refs ram_F6EB in on_chip_ram; cycles=6 +1C0D: 19 RTS ; cycles=13 + +loc_1C0E: +1C0E: A4 1A SHLL.B R4 ; cycles=2 +1C10: 24 0A BCC loc_1C1C ; cycles=3/7 nt/t +1C12: FD 27 06 80 MOV:G.W @(H'2706,R5), R0 ; cycles=7 +1C16: 12 30 STM.W {R4,R5}, @-SP ; cycles=12 +1C18: 11 D8 JSR @R0 ; JSR @R0 uses R0; target not resolved; cycles=13 +1C1A: 02 30 LDM.W @SP+, {R4,R5} ; cycles=14 + +loc_1C1C: +1C1C: A4 16 TST.B R4 ; cycles=2 +1C1E: 27 04 BEQ loc_1C24 ; cycles=3/7 nt/t +1C20: AD 0D ADD:Q.W #-2, R5 ; cycles=4 +1C22: 20 EA BRA loc_1C0E ; cycles=7 + +loc_1C24: +1C24: 19 RTS ; cycles=12 + +loc_2127: +2127: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=8 +212B: 26 08 BNE loc_2135 ; cycles=3/8 nt/t +212D: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=6 +2131: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=6 + +loc_2135: +2135: 1D F7 32 07 1C 03 MOV:G.W #H'1C03, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +213B: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +2140: 1E 27 B7 BSR loc_48FA ; cycles=13 +2143: 19 RTS ; cycles=13 + +loc_2650: +2650: 15 F6 F6 D5 BCLR.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +2654: 37 00 68 BEQ loc_26BF ; cycles=3/7 nt/t +2657: 1D E1 24 80 MOV:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +265B: A8 1A SHLL.W R0 ; cycles=3 +265D: A0 10 SWAP.B R0 ; cycles=3 +265F: 15 F6 F6 F6 BTST.B #6, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=6 +2663: 26 08 BNE loc_266D ; cycles=3/8 nt/t +2665: A0 08 ADD:Q.B #1, R0 ; cycles=4 +2667: 24 1A BCC loc_2683 ; cycles=3/8 nt/t +2669: 50 FF MOV:E.B #H'FF, R0 ; dataflow R0=H'FF; cycles=2 +266B: 20 16 BRA loc_2683 ; cycles=8 + +loc_266D: +266D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +266F: 1D E0 04 FD BTST.W #13, @H'E004 ; refs mem_E004 in program_or_external; cycles=6 +2673: 26 08 BNE loc_267D ; cycles=3/8 nt/t +2675: 40 49 CMP:E #H'49, R0 ; cycles=2 +2677: 24 0A BCC loc_2683 ; cycles=3/8 nt/t +2679: 50 49 MOV:E.B #H'49, R0 ; dataflow R0=H'49; cycles=2 +267B: 20 06 BRA loc_2683 ; cycles=8 + +loc_267D: +267D: 40 16 CMP:E #H'16, R0 ; cycles=2 +267F: 24 02 BCC loc_2683 ; cycles=3/8 nt/t +2681: 50 16 MOV:E.B #H'16, R0 ; dataflow R0=H'16; cycles=2 + +loc_2683: +2683: A0 12 EXTU.B R0 ; cycles=3 +2685: A0 10 SWAP.B R0 ; cycles=3 +2687: A8 1B SHLR.W R0 ; cycles=3 +2689: A8 CF BSET.W #15, R0 ; cycles=3 +268B: 1D E1 24 70 CMP:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +268F: 27 2E BEQ loc_26BF ; cycles=3/8 nt/t +2691: 1D E9 24 90 MOV:G.W R0, @H'E924 ; refs mem_E924 in program_or_external; cycles=6 +2695: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +2697: 5B 00 92 MOV:I.W #H'0092, R3 ; dataflow R3=H'0092; cycles=3 +269A: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +269E: 27 08 BEQ loc_26A8 ; cycles=3/7 nt/t +26A0: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs mem_F404 in program_or_external; cycles=7 +26A4: 27 02 BEQ loc_26A8 ; cycles=3/7 nt/t +26A6: AB CE BSET.W #14, R3 ; cycles=3 + +loc_26A8: +26A8: 1E 17 A9 BSR loc_3E54 ; cycles=13 +26AB: 15 F6 F6 C0 BSET.B #0, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=8 +26AF: 26 08 BNE loc_26B9 ; cycles=3/8 nt/t +26B1: 1D F6 F4 07 07 D0 MOV:G.W #H'07D0, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 +26B7: 20 06 BRA loc_26BF ; cycles=8 + +loc_26B9: +26B9: 1D F6 F4 07 00 C8 MOV:G.W #H'00C8, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_26BF: +26BF: 19 RTS ; cycles=13 + +loc_2806: +2806: 15 F9 B9 81 MOV:G.B @H'F9B9, R1 ; refs ram_F9B9 in on_chip_ram; cycles=7 +280A: A1 12 EXTU.B R1 ; cycles=3 +280C: 15 F9 B4 71 CMP:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +2810: 26 03 BNE loc_2815 ; cycles=3/7 nt/t +2812: 30 04 91 BRA loc_2CA6 ; cycles=7 + +loc_2815: +2815: A9 80 MOV:G.W R1, R0 ; cycles=3 +2817: A8 1A SHLL.W R0 ; cycles=3 +2819: F8 F9 70 80 MOV:G.W @(-H'0690,R0), R0 ; cycles=6 +281D: A1 08 ADD:Q.B #1, R1 ; cycles=4 +281F: 04 1F 51 AND.B #H'1F, R1 ; cycles=3 +2822: 15 F9 B9 91 MOV:G.B R1, @H'F9B9 ; refs ram_F9B9 in on_chip_ram; cycles=7 +2826: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +282A: A8 85 MOV:G.W R0, R5 ; cycles=3 +282C: 1E 39 D7 BSR loc_6206 ; cycles=13 +282F: A8 84 MOV:G.W R0, R4 ; cycles=3 +2831: AC 1A SHLL.W R4 ; cycles=3 +2833: A8 16 TST.W R0 ; cycles=3 +2835: 27 68 BEQ loc_289F ; cycles=3/8 nt/t +2837: 1D F7 36 81 MOV:G.W @H'F736, R1 ; refs ram_F736 in on_chip_ram; cycles=6 +283B: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +283F: A9 70 CMP:G.W R1, R0 ; cycles=3 +2841: 37 04 67 BEQ loc_2CAB ; cycles=3/8 nt/t +2844: 1D F7 38 81 MOV:G.W @H'F738, R1 ; refs ram_F738 in on_chip_ram; cycles=7 +2848: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +284C: A9 70 CMP:G.W R1, R0 ; cycles=3 +284E: 37 04 5A BEQ loc_2CAB ; cycles=3/7 nt/t +2851: 1D F7 3A 81 MOV:G.W @H'F73A, R1 ; refs ram_F73A in on_chip_ram; cycles=6 +2855: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2859: A9 70 CMP:G.W R1, R0 ; cycles=3 +285B: 37 04 4D BEQ loc_2CAB ; cycles=3/8 nt/t +285E: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs ram_F73C in on_chip_ram; cycles=7 +2862: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2866: A9 70 CMP:G.W R1, R0 ; cycles=3 +2868: 37 04 40 BEQ loc_2CAB ; cycles=3/7 nt/t +286B: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +286F: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2873: A9 70 CMP:G.W R1, R0 ; cycles=3 +2875: 37 04 33 BEQ loc_2CAB ; cycles=3/8 nt/t +2878: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs ram_F740 in on_chip_ram; cycles=7 +287C: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2880: A9 70 CMP:G.W R1, R0 ; cycles=3 +2882: 37 04 26 BEQ loc_2CAB ; cycles=3/7 nt/t +2885: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +2889: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +288D: A9 70 CMP:G.W R1, R0 ; cycles=3 +288F: 37 04 19 BEQ loc_2CAB ; cycles=3/8 nt/t +2892: 1D F7 54 81 MOV:G.W @H'F754, R1 ; refs ram_F754 in on_chip_ram; cycles=7 +2896: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +289A: A9 70 CMP:G.W R1, R0 ; cycles=3 +289C: 37 04 0C BEQ loc_2CAB ; cycles=3/7 nt/t + +loc_289F: +289F: FC 28 A6 81 MOV:G.W @(H'28A6,R4), R1 ; cycles=6 +28A3: 11 D1 JMP @R1 ; JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets); cycles=7 + +loc_2CA6: +2CA6: 15 F7 69 D7 BCLR.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CAA: 19 RTS ; cycles=12 + +loc_2CAB: +2CAB: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +2CAD: 1E 1C 4A BSR loc_48FA ; cycles=14 +2CB0: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 +2CB2: 15 F7 69 C7 BSET.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CB6: 30 FB E6 BRA loc_289F ; cycles=7 + +loc_3930: +3930: 58 00 07 MOV:I.W #H'0007, R0 ; dataflow R0=H'0007; cycles=3 + +loc_3933: +3933: 15 FE 8E 78 BTST.B R0, @P7DR ; refs P7DR in register_field; cycles=6 +3937: 27 0A BEQ loc_3943 ; cycles=3/8 nt/t +3939: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 +393D: F0 F6 80 C0 BSET.B #0, @(-H'0980,R0) ; cycles=8 +3941: 20 04 BRA loc_3947 ; cycles=8 + +loc_3943: +3943: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 + +loc_3947: +3947: F0 F6 80 04 FF CMP:G.B #H'FF, @(-H'0980,R0) ; cycles=6 +394C: 26 06 BNE loc_3954 ; cycles=3/7 nt/t +394E: 15 F6 88 48 BSET.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=9 +3952: 20 0B BRA loc_395F ; cycles=7 + +loc_3954: +3954: F0 F6 80 04 00 CMP:G.B #H'00, @(-H'0980,R0) ; cycles=7 +3959: 26 04 BNE loc_395F ; cycles=3/8 nt/t +395B: 15 F6 88 58 BCLR.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=8 + +loc_395F: +395F: 01 B8 D1 SCB/F R0, loc_3933 ; cycles=3/4/9 false/-1/t +3962: 15 F7 22 08 ADD:Q.B #1, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=9 +3966: 15 F7 22 04 3C CMP:G.B #H'3C, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +396B: 27 0F BEQ loc_397C ; cycles=3/8 nt/t +396D: 15 F7 22 04 78 CMP:G.B #H'78, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=6 +3972: 27 0B BEQ loc_397F ; cycles=3/7 nt/t +3974: 15 F7 22 04 B4 CMP:G.B #H'B4, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +3979: 27 08 BEQ loc_3983 ; cycles=3/8 nt/t +397B: 19 RTS ; cycles=13 + +loc_397C: +397C: 0E 17 BSR loc_3995 ; cycles=13 +397E: 19 RTS ; cycles=12 + +loc_397F: +397F: 1E 00 AC BSR loc_3A2E ; cycles=14 +3982: 19 RTS ; cycles=12 + +loc_3983: +3983: 0E 05 BSR loc_398A ; cycles=14 +3985: 15 F7 22 13 CLR.B @H'F722 ; refs ram_F722 in on_chip_ram; cycles=8 +3989: 19 RTS ; cycles=13 + +loc_398A: +398A: 15 FE E8 F7 BTST.B #7, @ADCSR ; refs ADCSR in register_field; cycles=7 +398E: 26 04 BNE loc_3994 ; cycles=3/7 nt/t +3990: 15 FE E8 C5 BSET.B #5, @ADCSR ; set ADST (bit 5) of ADCSR; cycles=9 + +loc_3994: +3994: 19 RTS ; cycles=12 + +loc_3995: +3995: 15 F7 20 16 TST.B @H'F720 ; refs ram_F720 in on_chip_ram; cycles=6 +3999: 36 00 91 BNE loc_3A2D ; cycles=3/8 nt/t +399C: 15 F1 01 06 A0 MOV:G.B #H'A0, @H'F101 ; refs mem_F101 in program_or_external; cycles=9 +39A1: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +39A5: 37 00 85 BEQ loc_3A2D ; cycles=3/8 nt/t +39A8: 15 F7 1B 80 MOV:G.B @H'F71B, R0 ; refs ram_F71B in on_chip_ram; cycles=7 +39AC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39B0: 15 F7 13 50 AND.B @H'F713, R0 ; refs ram_F713 in on_chip_ram; cycles=7 +39B4: 15 F1 02 90 MOV:G.B R0, @H'F102 ; refs mem_F102 in program_or_external; cycles=7 +39B8: 15 F7 1A 80 MOV:G.B @H'F71A, R0 ; refs ram_F71A in on_chip_ram; cycles=7 +39BC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39C0: 15 F7 12 50 AND.B @H'F712, R0 ; refs ram_F712 in on_chip_ram; cycles=7 +39C4: 15 F1 03 90 MOV:G.B R0, @H'F103 ; refs mem_F103 in program_or_external; cycles=7 +39C8: 15 F7 19 80 MOV:G.B @H'F719, R0 ; refs ram_F719 in on_chip_ram; cycles=7 +39CC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39D0: 15 F7 11 50 AND.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=7 +39D4: 15 F1 04 90 MOV:G.B R0, @H'F104 ; refs mem_F104 in program_or_external; cycles=7 +39D8: 15 F7 18 80 MOV:G.B @H'F718, R0 ; refs ram_F718 in on_chip_ram; cycles=7 +39DC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39E0: 15 F7 10 50 AND.B @H'F710, R0 ; refs ram_F710 in on_chip_ram; cycles=7 +39E4: 15 F1 05 90 MOV:G.B R0, @H'F105 ; refs mem_F105 in program_or_external; cycles=7 +39E8: 15 F7 02 80 MOV:G.B @H'F702, R0 ; refs ram_F702 in on_chip_ram; cycles=7 +39EC: 15 F1 09 90 MOV:G.B R0, @H'F109 ; refs mem_F109 in program_or_external; cycles=7 +39F0: 15 F7 03 80 MOV:G.B @H'F703, R0 ; refs ram_F703 in on_chip_ram; cycles=7 +39F4: 15 F1 0A 90 MOV:G.B R0, @H'F10A ; refs mem_F10A in program_or_external; cycles=7 +39F8: 15 F7 04 80 MOV:G.B @H'F704, R0 ; refs ram_F704 in on_chip_ram; cycles=7 +39FC: 15 F1 0B 90 MOV:G.B R0, @H'F10B ; refs mem_F10B in program_or_external; cycles=7 +3A00: 15 F7 05 80 MOV:G.B @H'F705, R0 ; refs ram_F705 in on_chip_ram; cycles=7 +3A04: 15 F1 0C 90 MOV:G.B R0, @H'F10C ; refs mem_F10C in program_or_external; cycles=7 +3A08: 15 F7 00 80 MOV:G.B @H'F700, R0 ; refs ram_F700 in on_chip_ram; cycles=7 +3A0C: 15 F1 0D 90 MOV:G.B R0, @H'F10D ; refs mem_F10D in program_or_external; cycles=7 +3A10: 15 F7 01 80 MOV:G.B @H'F701, R0 ; refs ram_F701 in on_chip_ram; cycles=7 +3A14: 15 F1 0E 90 MOV:G.B R0, @H'F10E ; refs mem_F10E in program_or_external; cycles=7 +3A18: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=7 +3A1C: A0 15 NOT.B R0 ; cycles=2 +3A1E: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3A21: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3A24: 15 F1 0F 90 MOV:G.B R0, @H'F10F ; refs mem_F10F in program_or_external; cycles=7 +3A28: 15 F7 20 06 03 MOV:G.B #H'03, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=9 + +loc_3A2D: +3A2D: 19 RTS ; cycles=13 + +loc_3A2E: +3A2E: 15 F7 21 16 TST.B @H'F721 ; refs ram_F721 in on_chip_ram; cycles=7 +3A32: 36 00 91 BNE loc_3AC6 ; cycles=3/7 nt/t +3A35: 15 F0 01 06 A0 MOV:G.B #H'A0, @H'F001 ; refs mem_F001 in program_or_external; cycles=9 +3A3A: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3A3E: 37 00 85 BEQ loc_3AC6 ; cycles=3/7 nt/t +3A41: 15 F7 1F 80 MOV:G.B @H'F71F, R0 ; refs ram_F71F in on_chip_ram; cycles=6 +3A45: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A49: 15 F7 17 50 AND.B @H'F717, R0 ; refs ram_F717 in on_chip_ram; cycles=6 +3A4D: 15 F0 02 90 MOV:G.B R0, @H'F002 ; refs mem_F002 in program_or_external; cycles=6 +3A51: 15 F7 1E 80 MOV:G.B @H'F71E, R0 ; refs ram_F71E in on_chip_ram; cycles=6 +3A55: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A59: 15 F7 16 50 AND.B @H'F716, R0 ; refs ram_F716 in on_chip_ram; cycles=6 +3A5D: 15 F0 03 90 MOV:G.B R0, @H'F003 ; refs mem_F003 in program_or_external; cycles=6 +3A61: 15 F7 1D 80 MOV:G.B @H'F71D, R0 ; refs ram_F71D in on_chip_ram; cycles=6 +3A65: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A69: 15 F7 15 50 AND.B @H'F715, R0 ; refs ram_F715 in on_chip_ram; cycles=6 +3A6D: 15 F0 04 90 MOV:G.B R0, @H'F004 ; refs mem_F004 in program_or_external; cycles=6 +3A71: 15 F7 1C 80 MOV:G.B @H'F71C, R0 ; refs ram_F71C in on_chip_ram; cycles=6 +3A75: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A79: 15 F7 14 50 AND.B @H'F714, R0 ; refs ram_F714 in on_chip_ram; cycles=6 +3A7D: 15 F0 05 90 MOV:G.B R0, @H'F005 ; refs mem_F005 in program_or_external; cycles=6 +3A81: 15 F7 08 80 MOV:G.B @H'F708, R0 ; refs ram_F708 in on_chip_ram; cycles=6 +3A85: 15 F0 09 90 MOV:G.B R0, @H'F009 ; refs mem_F009 in program_or_external; cycles=6 +3A89: 15 F7 09 80 MOV:G.B @H'F709, R0 ; refs ram_F709 in on_chip_ram; cycles=6 +3A8D: 15 F0 0A 90 MOV:G.B R0, @H'F00A ; refs mem_F00A in program_or_external; cycles=6 +3A91: 15 F7 0A 80 MOV:G.B @H'F70A, R0 ; refs ram_F70A in on_chip_ram; cycles=6 +3A95: 15 F0 0B 90 MOV:G.B R0, @H'F00B ; refs mem_F00B in program_or_external; cycles=6 +3A99: 15 F7 0B 80 MOV:G.B @H'F70B, R0 ; refs ram_F70B in on_chip_ram; cycles=6 +3A9D: 15 F0 0C 90 MOV:G.B R0, @H'F00C ; refs mem_F00C in program_or_external; cycles=6 +3AA1: 15 F7 06 80 MOV:G.B @H'F706, R0 ; refs ram_F706 in on_chip_ram; cycles=6 +3AA5: 15 F0 0D 90 MOV:G.B R0, @H'F00D ; refs mem_F00D in program_or_external; cycles=6 +3AA9: 15 F7 07 80 MOV:G.B @H'F707, R0 ; refs ram_F707 in on_chip_ram; cycles=6 +3AAD: 15 F0 0E 90 MOV:G.B R0, @H'F00E ; refs mem_F00E in program_or_external; cycles=6 +3AB1: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=6 +3AB5: A0 15 NOT.B R0 ; cycles=2 +3AB7: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3ABA: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3ABD: 15 F0 0F 90 MOV:G.B R0, @H'F00F ; refs mem_F00F in program_or_external; cycles=6 +3AC1: 15 F7 21 06 03 MOV:G.B #H'03, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3AC6: +3AC6: 19 RTS ; cycles=12 + +vec_irq4_3AC7: +3AC7: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +3AC9: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +3ACD: 36 01 5D BNE loc_3C2D ; cycles=3/8 nt/t +3AD0: 15 F1 0F 80 MOV:G.B @H'F10F, R0 ; refs mem_F10F in program_or_external; cycles=7 +3AD4: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3AD6: 27 08 BEQ loc_3AE0 ; cycles=3/7 nt/t +3AD8: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3ADA: 37 00 85 BEQ loc_3B62 ; cycles=3/7 nt/t +3ADD: 30 01 4D BRA loc_3C2D ; cycles=8 + +loc_3AE0: +3AE0: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3AE4: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3AE7: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3AEB: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3AEF: 1D F6 9A 70 CMP:G.W @H'F69A, R0 ; refs ram_F69A in on_chip_ram; cycles=6 +3AF3: 27 08 BEQ loc_3AFD ; cycles=3/8 nt/t +3AF5: 15 F6 F0 C5 BSET.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3AF9: 1D F6 9A 90 MOV:G.W R0, @H'F69A ; refs ram_F69A in on_chip_ram; cycles=6 + +loc_3AFD: +3AFD: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B01: 1D F6 98 70 CMP:G.W @H'F698, R0 ; refs ram_F698 in on_chip_ram; cycles=6 +3B05: 27 08 BEQ loc_3B0F ; cycles=3/8 nt/t +3B07: 15 F6 F0 C4 BSET.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B0B: 1D F6 98 90 MOV:G.W R0, @H'F698 ; refs ram_F698 in on_chip_ram; cycles=6 + +loc_3B0F: +3B0F: 1D F1 08 80 MOV:G.W @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3B13: 1D F6 96 70 CMP:G.W @H'F696, R0 ; refs ram_F696 in on_chip_ram; cycles=6 +3B17: 27 08 BEQ loc_3B21 ; cycles=3/8 nt/t +3B19: 15 F6 F0 C3 BSET.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B1D: 1D F6 96 90 MOV:G.W R0, @H'F696 ; refs ram_F696 in on_chip_ram; cycles=6 + +loc_3B21: +3B21: 1D F1 06 80 MOV:G.W @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3B25: 1D F6 94 70 CMP:G.W @H'F694, R0 ; refs ram_F694 in on_chip_ram; cycles=6 +3B29: 27 08 BEQ loc_3B33 ; cycles=3/8 nt/t +3B2B: 15 F6 F0 C2 BSET.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B2F: 1D F6 94 90 MOV:G.W R0, @H'F694 ; refs ram_F694 in on_chip_ram; cycles=6 + +loc_3B33: +3B33: 1D F1 04 80 MOV:G.W @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3B37: 1D F6 92 70 CMP:G.W @H'F692, R0 ; refs ram_F692 in on_chip_ram; cycles=6 +3B3B: 27 08 BEQ loc_3B45 ; cycles=3/8 nt/t +3B3D: 15 F6 F0 C1 BSET.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B41: 1D F6 92 90 MOV:G.W R0, @H'F692 ; refs ram_F692 in on_chip_ram; cycles=6 + +loc_3B45: +3B45: 1D F1 02 80 MOV:G.W @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3B49: 1D F6 90 70 CMP:G.W @H'F690, R0 ; refs ram_F690 in on_chip_ram; cycles=6 +3B4D: 27 08 BEQ loc_3B57 ; cycles=3/8 nt/t +3B4F: 15 F6 F0 C0 BSET.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B53: 1D F6 90 90 MOV:G.W R0, @H'F690 ; refs ram_F690 in on_chip_ram; cycles=6 + +loc_3B57: +3B57: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3B5B: 15 F7 20 D0 BCLR.B #0, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 +3B5F: 30 00 CB BRA loc_3C2D ; cycles=8 + +loc_3B62: +3B62: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3B66: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3B69: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3B6D: 15 F6 F2 13 CLR.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3B71: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3B75: 1D F6 9E 70 CMP:G.W @H'F69E, R0 ; refs ram_F69E in on_chip_ram; cycles=6 +3B79: 27 08 BEQ loc_3B83 ; cycles=3/8 nt/t +3B7B: 15 F6 F0 C7 BSET.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B7F: 1D F6 9E 90 MOV:G.W R0, @H'F69E ; refs ram_F69E in on_chip_ram; cycles=6 + +loc_3B83: +3B83: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B87: 1D F6 9C 70 CMP:G.W @H'F69C, R0 ; refs ram_F69C in on_chip_ram; cycles=6 +3B8B: 27 08 BEQ loc_3B95 ; cycles=3/8 nt/t +3B8D: 15 F6 F0 C6 BSET.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B91: 1D F6 9C 90 MOV:G.W R0, @H'F69C ; refs ram_F69C in on_chip_ram; cycles=6 + +loc_3B95: +3B95: 15 F1 09 80 MOV:G.B @H'F109, R0 ; refs mem_F109 in program_or_external; cycles=6 +3B99: 15 F6 D0 70 CMP:G.B @H'F6D0, R0 ; refs ram_F6D0 in on_chip_ram; cycles=6 +3B9D: 27 08 BEQ loc_3BA7 ; cycles=3/8 nt/t +3B9F: 15 F6 F2 C0 BSET.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BA3: 15 F6 D0 90 MOV:G.B R0, @H'F6D0 ; refs ram_F6D0 in on_chip_ram; cycles=6 + +loc_3BA7: +3BA7: 15 F1 08 80 MOV:G.B @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3BAB: 15 F6 D1 70 CMP:G.B @H'F6D1, R0 ; refs ram_F6D1 in on_chip_ram; cycles=6 +3BAF: 27 08 BEQ loc_3BB9 ; cycles=3/8 nt/t +3BB1: 15 F6 F2 C1 BSET.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BB5: 15 F6 D1 90 MOV:G.B R0, @H'F6D1 ; refs ram_F6D1 in on_chip_ram; cycles=6 + +loc_3BB9: +3BB9: 15 F1 07 80 MOV:G.B @H'F107, R0 ; refs mem_F107 in program_or_external; cycles=6 +3BBD: 15 F6 D2 70 CMP:G.B @H'F6D2, R0 ; refs ram_F6D2 in on_chip_ram; cycles=6 +3BC1: 27 08 BEQ loc_3BCB ; cycles=3/8 nt/t +3BC3: 15 F6 F2 C2 BSET.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BC7: 15 F6 D2 90 MOV:G.B R0, @H'F6D2 ; refs ram_F6D2 in on_chip_ram; cycles=6 + +loc_3BCB: +3BCB: 15 F1 06 80 MOV:G.B @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3BCF: 15 F6 D3 70 CMP:G.B @H'F6D3, R0 ; refs ram_F6D3 in on_chip_ram; cycles=6 +3BD3: 27 08 BEQ loc_3BDD ; cycles=3/8 nt/t +3BD5: 15 F6 F2 C3 BSET.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BD9: 15 F6 D3 90 MOV:G.B R0, @H'F6D3 ; refs ram_F6D3 in on_chip_ram; cycles=6 + +loc_3BDD: +3BDD: 15 F1 05 80 MOV:G.B @H'F105, R0 ; refs mem_F105 in program_or_external; cycles=6 +3BE1: 15 F6 D4 70 CMP:G.B @H'F6D4, R0 ; refs ram_F6D4 in on_chip_ram; cycles=6 +3BE5: 27 08 BEQ loc_3BEF ; cycles=3/8 nt/t +3BE7: 15 F6 F2 C4 BSET.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BEB: 15 F6 D4 90 MOV:G.B R0, @H'F6D4 ; refs ram_F6D4 in on_chip_ram; cycles=6 + +loc_3BEF: +3BEF: 15 F1 04 80 MOV:G.B @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3BF3: 15 F6 D5 70 CMP:G.B @H'F6D5, R0 ; refs ram_F6D5 in on_chip_ram; cycles=6 +3BF7: 27 08 BEQ loc_3C01 ; cycles=3/8 nt/t +3BF9: 15 F6 F2 C5 BSET.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BFD: 15 F6 D5 90 MOV:G.B R0, @H'F6D5 ; refs ram_F6D5 in on_chip_ram; cycles=6 + +loc_3C01: +3C01: 15 F1 03 80 MOV:G.B @H'F103, R0 ; refs mem_F103 in program_or_external; cycles=6 +3C05: 15 F6 D6 70 CMP:G.B @H'F6D6, R0 ; refs ram_F6D6 in on_chip_ram; cycles=6 +3C09: 27 08 BEQ loc_3C13 ; cycles=3/8 nt/t +3C0B: 15 F6 F2 C6 BSET.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C0F: 15 F6 D6 90 MOV:G.B R0, @H'F6D6 ; refs ram_F6D6 in on_chip_ram; cycles=6 + +loc_3C13: +3C13: 15 F1 02 80 MOV:G.B @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3C17: 15 F6 D7 70 CMP:G.B @H'F6D7, R0 ; refs ram_F6D7 in on_chip_ram; cycles=6 +3C1B: 27 08 BEQ loc_3C25 ; cycles=3/8 nt/t +3C1D: 15 F6 F2 C7 BSET.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C21: 15 F6 D7 90 MOV:G.B R0, @H'F6D7 ; refs ram_F6D7 in on_chip_ram; cycles=6 + +loc_3C25: +3C25: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3C29: 15 F7 20 D1 BCLR.B #1, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 + +loc_3C2D: +3C2D: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +3C2F: 0A RTE ; cycles=14 + +vec_irq3_3C30: +3C30: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +3C32: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3C36: 36 01 5D BNE loc_3D96 ; cycles=3/7 nt/t +3C39: 15 F0 0F 80 MOV:G.B @H'F00F, R0 ; refs mem_F00F in program_or_external; cycles=6 +3C3D: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3C3F: 27 08 BEQ loc_3C49 ; cycles=3/8 nt/t +3C41: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3C43: 37 00 85 BEQ loc_3CCB ; cycles=3/8 nt/t +3C46: 30 01 4D BRA loc_3D96 ; cycles=7 + +loc_3C49: +3C49: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3C4D: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3C50: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3C54: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3C58: 1D F6 AA 70 CMP:G.W @H'F6AA, R0 ; refs ram_F6AA in on_chip_ram; cycles=7 +3C5C: 27 08 BEQ loc_3C66 ; cycles=3/7 nt/t +3C5E: 15 F6 F1 C5 BSET.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C62: 1D F6 AA 90 MOV:G.W R0, @H'F6AA ; refs ram_F6AA in on_chip_ram; cycles=7 + +loc_3C66: +3C66: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3C6A: 1D F6 A8 70 CMP:G.W @H'F6A8, R0 ; refs ram_F6A8 in on_chip_ram; cycles=7 +3C6E: 27 08 BEQ loc_3C78 ; cycles=3/7 nt/t +3C70: 15 F6 F1 C4 BSET.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C74: 1D F6 A8 90 MOV:G.W R0, @H'F6A8 ; refs ram_F6A8 in on_chip_ram; cycles=7 + +loc_3C78: +3C78: 1D F0 08 80 MOV:G.W @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3C7C: 1D F6 A6 70 CMP:G.W @H'F6A6, R0 ; refs ram_F6A6 in on_chip_ram; cycles=7 +3C80: 27 08 BEQ loc_3C8A ; cycles=3/7 nt/t +3C82: 15 F6 F1 C3 BSET.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C86: 1D F6 A6 90 MOV:G.W R0, @H'F6A6 ; refs ram_F6A6 in on_chip_ram; cycles=7 + +loc_3C8A: +3C8A: 1D F0 06 80 MOV:G.W @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3C8E: 1D F6 A4 70 CMP:G.W @H'F6A4, R0 ; refs ram_F6A4 in on_chip_ram; cycles=7 +3C92: 27 08 BEQ loc_3C9C ; cycles=3/7 nt/t +3C94: 15 F6 F1 C2 BSET.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C98: 1D F6 A4 90 MOV:G.W R0, @H'F6A4 ; refs ram_F6A4 in on_chip_ram; cycles=7 + +loc_3C9C: +3C9C: 1D F0 04 80 MOV:G.W @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3CA0: 1D F6 A2 70 CMP:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +3CA4: 27 08 BEQ loc_3CAE ; cycles=3/7 nt/t +3CA6: 15 F6 F1 C1 BSET.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CAA: 1D F6 A2 90 MOV:G.W R0, @H'F6A2 ; refs ram_F6A2 in on_chip_ram; cycles=7 + +loc_3CAE: +3CAE: 1D F0 02 80 MOV:G.W @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3CB2: 1D F6 A0 70 CMP:G.W @H'F6A0, R0 ; refs ram_F6A0 in on_chip_ram; cycles=7 +3CB6: 27 08 BEQ loc_3CC0 ; cycles=3/7 nt/t +3CB8: 15 F6 F1 C0 BSET.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CBC: 1D F6 A0 90 MOV:G.W R0, @H'F6A0 ; refs ram_F6A0 in on_chip_ram; cycles=7 + +loc_3CC0: +3CC0: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3CC4: 15 F7 21 D0 BCLR.B #0, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 +3CC8: 30 00 CB BRA loc_3D96 ; cycles=7 + +loc_3CCB: +3CCB: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3CCF: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3CD2: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3CD6: 15 F6 F3 13 CLR.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3CDA: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3CDE: 1D F6 AE 70 CMP:G.W @H'F6AE, R0 ; refs ram_F6AE in on_chip_ram; cycles=7 +3CE2: 27 08 BEQ loc_3CEC ; cycles=3/7 nt/t +3CE4: 15 F6 F1 C7 BSET.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CE8: 1D F6 AE 90 MOV:G.W R0, @H'F6AE ; refs ram_F6AE in on_chip_ram; cycles=7 + +loc_3CEC: +3CEC: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3CF0: 1D F6 AC 70 CMP:G.W @H'F6AC, R0 ; refs ram_F6AC in on_chip_ram; cycles=7 +3CF4: 27 08 BEQ loc_3CFE ; cycles=3/7 nt/t +3CF6: 15 F6 F1 C6 BSET.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CFA: 1D F6 AC 90 MOV:G.W R0, @H'F6AC ; refs ram_F6AC in on_chip_ram; cycles=7 + +loc_3CFE: +3CFE: 15 F0 09 80 MOV:G.B @H'F009, R0 ; refs mem_F009 in program_or_external; cycles=7 +3D02: 15 F6 D8 70 CMP:G.B @H'F6D8, R0 ; refs ram_F6D8 in on_chip_ram; cycles=7 +3D06: 27 08 BEQ loc_3D10 ; cycles=3/7 nt/t +3D08: 15 F6 F3 C0 BSET.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D0C: 15 F6 D8 90 MOV:G.B R0, @H'F6D8 ; refs ram_F6D8 in on_chip_ram; cycles=7 + +loc_3D10: +3D10: 15 F0 08 80 MOV:G.B @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3D14: 15 F6 D9 70 CMP:G.B @H'F6D9, R0 ; refs ram_F6D9 in on_chip_ram; cycles=7 +3D18: 27 08 BEQ loc_3D22 ; cycles=3/7 nt/t +3D1A: 15 F6 F3 C1 BSET.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D1E: 15 F6 D9 90 MOV:G.B R0, @H'F6D9 ; refs ram_F6D9 in on_chip_ram; cycles=7 + +loc_3D22: +3D22: 15 F0 07 80 MOV:G.B @H'F007, R0 ; refs mem_F007 in program_or_external; cycles=7 +3D26: 15 F6 DA 70 CMP:G.B @H'F6DA, R0 ; refs ram_F6DA in on_chip_ram; cycles=7 +3D2A: 27 08 BEQ loc_3D34 ; cycles=3/7 nt/t +3D2C: 15 F6 F3 C2 BSET.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D30: 15 F6 DA 90 MOV:G.B R0, @H'F6DA ; refs ram_F6DA in on_chip_ram; cycles=7 + +loc_3D34: +3D34: 15 F0 06 80 MOV:G.B @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3D38: 15 F6 DB 70 CMP:G.B @H'F6DB, R0 ; refs ram_F6DB in on_chip_ram; cycles=7 +3D3C: 27 08 BEQ loc_3D46 ; cycles=3/7 nt/t +3D3E: 15 F6 F3 C3 BSET.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D42: 15 F6 DB 90 MOV:G.B R0, @H'F6DB ; refs ram_F6DB in on_chip_ram; cycles=7 + +loc_3D46: +3D46: 15 F0 05 80 MOV:G.B @H'F005, R0 ; refs mem_F005 in program_or_external; cycles=7 +3D4A: 15 F6 DC 70 CMP:G.B @H'F6DC, R0 ; refs ram_F6DC in on_chip_ram; cycles=7 +3D4E: 27 08 BEQ loc_3D58 ; cycles=3/7 nt/t +3D50: 15 F6 F3 C4 BSET.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D54: 15 F6 DC 90 MOV:G.B R0, @H'F6DC ; refs ram_F6DC in on_chip_ram; cycles=7 + +loc_3D58: +3D58: 15 F0 04 80 MOV:G.B @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3D5C: 15 F6 DD 70 CMP:G.B @H'F6DD, R0 ; refs ram_F6DD in on_chip_ram; cycles=7 +3D60: 27 08 BEQ loc_3D6A ; cycles=3/7 nt/t +3D62: 15 F6 F3 C5 BSET.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D66: 15 F6 DD 90 MOV:G.B R0, @H'F6DD ; refs ram_F6DD in on_chip_ram; cycles=7 + +loc_3D6A: +3D6A: 15 F0 03 80 MOV:G.B @H'F003, R0 ; refs mem_F003 in program_or_external; cycles=7 +3D6E: 15 F6 DE 70 CMP:G.B @H'F6DE, R0 ; refs ram_F6DE in on_chip_ram; cycles=7 +3D72: 27 08 BEQ loc_3D7C ; cycles=3/7 nt/t +3D74: 15 F6 F3 C6 BSET.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D78: 15 F6 DE 90 MOV:G.B R0, @H'F6DE ; refs ram_F6DE in on_chip_ram; cycles=7 + +loc_3D7C: +3D7C: 15 F0 02 80 MOV:G.B @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3D80: 15 F6 DF 70 CMP:G.B @H'F6DF, R0 ; refs ram_F6DF in on_chip_ram; cycles=7 +3D84: 27 08 BEQ loc_3D8E ; cycles=3/7 nt/t +3D86: 15 F6 F3 C7 BSET.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D8A: 15 F6 DF 90 MOV:G.B R0, @H'F6DF ; refs ram_F6DF in on_chip_ram; cycles=7 + +loc_3D8E: +3D8E: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3D92: 15 F7 21 D1 BCLR.B #1, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3D96: +3D96: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +3D98: 0A RTE ; cycles=13 + +vec_ad_adi_3D99: +3D99: 15 FE E8 D5 BCLR.B #5, @ADCSR ; clear ADST (bit 5) of ADCSR; cycles=8 +3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DA3: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; ADDRA word read; TEMP byte-order hazard avoided; refs ADDRA_H in register_field; cycles=7 +3DAA: A1 10 SWAP.B R1 ; cycles=3 +3DAC: A1 12 EXTU.B R1 ; cycles=3 +3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 ; cycles=7 +3DB2: A9 20 ADD:G.W R1, R0 ; cycles=3 +3DB4: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3DB7: 15 F6 8A 70 CMP:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DBB: 27 4B BEQ loc_3E08 ; cycles=3/8 nt/t +3DBD: 15 F6 8A 82 MOV:G.B @H'F68A, R2 ; refs ram_F68A in on_chip_ram; cycles=6 +3DC1: 15 F6 8A 90 MOV:G.B R0, @H'F68A ; refs ram_F68A in on_chip_ram; cycles=6 +3DC5: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +3DCA: 22 3C BHI loc_3E08 ; cycles=3/7 nt/t +3DCC: A0 12 EXTU.B R0 ; cycles=3 +3DCE: A2 12 EXTU.B R2 ; cycles=3 +3DD0: 0C 01 01 A8 MULXU.W #H'0101, R0 ; cycles=25 +3DD4: 0C 01 01 AA MULXU.W #H'0101, R2 ; cycles=25 +3DD8: AB 31 SUB.W R3, R1 ; cycles=3 +3DDA: 1D E1 02 80 MOV:G.W @H'E102, R0 ; refs mem_E102 in program_or_external; cycles=7 +3DDE: A8 21 ADD:G.W R0, R1 ; cycles=3 +3DE0: A9 82 MOV:G.W R1, R2 ; cycles=3 +3DE2: 25 0C BCS loc_3DF0 ; cycles=3/7 nt/t +3DE4: A8 32 SUB.W R0, R2 ; cycles=3 +3DE6: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +3DE9: 23 0F BLS loc_3DFA ; cycles=3/8 nt/t +3DEB: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +3DEE: 20 0A BRA loc_3DFA ; cycles=7 + +loc_3DF0: +3DF0: AA 30 SUB.W R2, R0 ; cycles=3 +3DF2: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +3DF5: 23 03 BLS loc_3DFA ; cycles=3/8 nt/t +3DF7: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_3DFA: +3DFA: 1D E1 02 71 CMP:G.W @H'E102, R1 ; refs mem_E102 in program_or_external; cycles=7 +3DFE: 27 08 BEQ loc_3E08 ; cycles=3/7 nt/t +3E00: 1D F6 8E 91 MOV:G.W R1, @H'F68E ; refs ram_F68E in on_chip_ram; cycles=7 +3E04: 15 F6 89 C7 BSET.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=9 + +loc_3E08: +3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E0C: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; ADDRB word read; TEMP byte-order hazard avoided; refs ADDRB_H in register_field; cycles=6 +3E13: A1 10 SWAP.B R1 ; cycles=3 +3E15: A1 12 EXTU.B R1 ; cycles=3 +3E17: A9 20 ADD:G.W R1, R0 ; cycles=3 +3E19: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3E1C: 1D F6 8C 16 TST.W @H'F68C ; refs ram_F68C in on_chip_ram; cycles=7 +3E20: 27 06 BEQ loc_3E28 ; cycles=3/7 nt/t +3E22: 15 F6 8B 70 CMP:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E26: 27 25 BEQ loc_3E4D ; cycles=3/7 nt/t + +loc_3E28: +3E28: 15 F6 8B 90 MOV:G.B R0, @H'F68B ; refs ram_F68B in on_chip_ram; cycles=7 +3E2C: A0 12 EXTU.B R0 ; cycles=3 +3E2E: A8 83 MOV:G.W R0, R3 ; cycles=3 +3E30: A3 AB MULXU.B R3, R3 ; cycles=18 +3E32: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +3E34: 0C 00 C8 BA DIVXU.W #H'00C8, R2 ; cycles=29 +3E38: 04 04 A8 MULXU.B #H'04, R0 ; cycles=19 +3E3B: 0C 00 AB 20 ADD:G.W #H'00AB, R0 ; cycles=4 +3E3F: AB 20 ADD:G.W R3, R0 ; cycles=3 +3E41: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +3E45: 26 02 BNE loc_3E49 ; cycles=3/8 nt/t +3E47: A8 1B SHLR.W R0 ; cycles=3 + +loc_3E49: +3E49: 1D F6 8C 90 MOV:G.W R0, @H'F68C ; refs ram_F68C in on_chip_ram; cycles=6 + +loc_3E4D: +3E4D: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 +3E4F: 15 FE E8 D7 BCLR.B #7, @ADCSR ; clear ADF (bit 7) of ADCSR; cycles=8 +3E53: 0A RTE ; cycles=14 + +loc_3E54: +3E54: A2 F7 BTST.B #7, R2 ; cycles=2 +3E56: 27 42 BEQ loc_3E9A ; cycles=3/7 nt/t +3E58: 15 F9 B5 80 MOV:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=7 +3E5C: A0 12 EXTU.B R0 ; cycles=3 +3E5E: A8 1A SHLL.W R0 ; cycles=3 +3E60: 15 F9 B0 81 MOV:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E64: A1 12 EXTU.B R1 ; cycles=3 +3E66: A9 1A SHLL.W R1 ; cycles=3 + +loc_3E68: +3E68: A0 71 CMP:G.B R0, R1 ; cycles=2 +3E6A: 27 0A BEQ loc_3E76 ; cycles=3/7 nt/t +3E6C: F8 F8 70 73 CMP:G.W @(-H'0790,R0), R3 ; cycles=7 +3E70: 27 28 BEQ loc_3E9A ; cycles=3/7 nt/t +3E72: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3E74: 20 F2 BRA loc_3E68 ; cycles=7 + +loc_3E76: +3E76: F9 F8 70 93 MOV:G.W R3, @(-H'0790,R1) ; cycles=7 +3E7A: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +3E7E: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_3E82: +3E82: 15 F9 B0 80 MOV:G.B @H'F9B0, R0 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E86: A0 08 ADD:Q.B #1, R0 ; cycles=4 +3E88: 04 7F 50 AND.B #H'7F, R0 ; cycles=3 +3E8B: 15 F9 B5 70 CMP:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=6 +3E8F: 26 09 BNE loc_3E9A ; cycles=3/8 nt/t +3E91: 12 0C STM.W {R2,R3}, @-SP ; cycles=12 +3E93: 1E 01 3D BSR loc_3FD3 ; cycles=14 +3E96: 02 0C LDM.W @SP+, {R2,R3} ; cycles=14 +3E98: 20 E8 BRA loc_3E82 ; cycles=7 + +loc_3E9A: +3E9A: A2 F6 BTST.B #6, R2 ; cycles=2 +3E9C: 27 2D BEQ loc_3ECB ; cycles=3/7 nt/t +3E9E: 15 F9 B9 80 MOV:G.B @H'F9B9, R0 ; refs ram_F9B9 in on_chip_ram; cycles=7 +3EA2: A0 12 EXTU.B R0 ; cycles=3 +3EA4: A8 1A SHLL.W R0 ; cycles=3 +3EA6: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +3EAA: A1 12 EXTU.B R1 ; cycles=3 +3EAC: A9 1A SHLL.W R1 ; cycles=3 + +loc_3EAE: +3EAE: A0 71 CMP:G.B R0, R1 ; cycles=2 +3EB0: 27 0D BEQ loc_3EBF ; cycles=3/7 nt/t +3EB2: F8 F9 70 73 CMP:G.W @(-H'0690,R0), R3 ; cycles=7 +3EB6: 27 13 BEQ loc_3ECB ; cycles=3/7 nt/t +3EB8: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3EBA: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3EBD: 20 EF BRA loc_3EAE ; cycles=8 + +loc_3EBF: +3EBF: F9 F9 70 93 MOV:G.W R3, @(-H'0690,R1) ; cycles=6 +3EC3: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +3EC7: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_3ECB: +3ECB: 19 RTS ; cycles=13 + +loc_3ECC: +3ECC: 12 1F STM.W {R0,R1,R2,R3,R4}, @-SP ; cycles=21 +3ECE: A5 12 EXTU.B R5 ; cycles=3 +3ED0: 45 03 CMP:E #H'03, R5 ; cycles=2 +3ED2: 23 05 BLS loc_3ED9 ; cycles=3/7 nt/t +3ED4: 1E 00 69 BSR loc_3F40 ; cycles=13 +3ED7: 20 4C BRA loc_3F25 ; cycles=8 + +loc_3ED9: +3ED9: A5 83 MOV:G.B R5, R3 ; cycles=2 +3EDB: 45 00 CMP:E #H'00, R5 ; cycles=2 +3EDD: 27 0A BEQ loc_3EE9 ; cycles=3/8 nt/t +3EDF: 45 01 CMP:E #H'01, R5 ; cycles=2 +3EE1: 27 0B BEQ loc_3EEE ; cycles=3/8 nt/t +3EE3: 45 02 CMP:E #H'02, R5 ; cycles=2 +3EE5: 27 0C BEQ loc_3EF3 ; cycles=3/8 nt/t +3EE7: 20 0F BRA loc_3EF8 ; cycles=8 + +loc_3EE9: +3EE9: 5D 00 80 MOV:I.W #H'0080, R5 ; dataflow R5=H'0080; cycles=3 +3EEC: 20 0D BRA loc_3EFB ; cycles=7 + +loc_3EEE: +3EEE: 5D 00 C0 MOV:I.W #H'00C0, R5 ; dataflow R5=H'00C0; cycles=3 +3EF1: 20 08 BRA loc_3EFB ; cycles=8 + +loc_3EF3: +3EF3: 5D 00 90 MOV:I.W #H'0090, R5 ; dataflow R5=H'0090; cycles=3 +3EF6: 20 03 BRA loc_3EFB ; cycles=7 + +loc_3EF8: +3EF8: 5D 00 D0 MOV:I.W #H'00D0, R5 ; dataflow R5=H'00D0; cycles=3 + +loc_3EFB: +3EFB: 04 10 AB MULXU.B #H'10, R3 ; cycles=19 +3EFE: 0C FA B0 23 ADD:G.W #H'FAB0, R3 ; cycles=4 +3F02: A9 13 CLR.W R1 ; dataflow R1=H'0000; cycles=3 + +loc_3F04: +3F04: F1 FA F0 82 MOV:G.B @(-H'0510,R1), R2 ; cycles=7 +3F08: D3 72 CMP:G.B @R3, R2 ; cycles=6 +3F0A: 27 04 BEQ loc_3F10 ; cycles=3/7 nt/t +3F0C: D3 92 MOV:G.B R2, @R3 ; cycles=6 +3F0E: 0E 18 BSR loc_3F28 ; cycles=13 + +loc_3F10: +3F10: A1 08 ADD:Q.B #1, R1 ; cycles=4 +3F12: A3 08 ADD:Q.B #1, R3 ; cycles=4 +3F14: 41 10 CMP:E #H'10, R1 ; cycles=2 +3F16: 27 02 BEQ loc_3F1A ; cycles=3/7 nt/t +3F18: 20 EA BRA loc_3F04 ; cycles=7 + +loc_3F1A: +3F1A: 1D FB 00 07 00 E0 MOV:G.W #H'00E0, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=11 +3F20: 5C 00 E0 MOV:I.W #H'00E0, R4 ; dataflow R4=H'00E0; cycles=3 +3F23: 0E 1B BSR loc_3F40 ; cycles=14 + +loc_3F25: +3F25: 02 1F LDM.W @SP+, {R0,R1,R2,R3,R4} ; cycles=26 +3F27: 19 RTS ; cycles=13 + +loc_3F28: +3F28: AD 84 MOV:G.W R5, R4 ; cycles=3 +3F2A: A1 24 ADD:G.B R1, R4 ; cycles=2 +3F2C: 1D FB 00 74 CMP:G.W @H'FB00, R4 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F30: 27 06 BEQ loc_3F38 ; cycles=3/7 nt/t +3F32: 1D FB 00 94 MOV:G.W R4, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F36: 0E 08 BSR loc_3F40 ; cycles=13 + +loc_3F38: +3F38: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +3F3B: A2 24 ADD:G.B R2, R4 ; cycles=2 +3F3D: 0E 01 BSR loc_3F40 ; cycles=14 +3F3F: 19 RTS ; cycles=13 + +loc_3F40: +3F40: BF 98 STC.W SR, @-R7 ; cycles=8 +3F42: 0C 00 FF 58 ANDC.W #H'00FF, SR ; cycles=4 +3F46: 0C 06 00 48 ORC.W #H'0600, SR ; cycles=4 + +loc_3F4A: +3F4A: 15 F2 00 00 80 MOVFPE.B @H'F200, R0 ; LCD status read from E-clock H'F200; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; refs mem_F200 in program_or_external; cycles=13 +3F4F: A0 F7 BTST.B #7, R0 ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=2 +3F51: 26 F7 BNE loc_3F4A ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=3/8 nt/t +3F53: AC F8 BTST.W #8, R4 ; cycles=3 +3F55: 26 16 BNE loc_3F6D ; cycles=3/8 nt/t +3F57: AC F9 BTST.W #9, R4 ; cycles=3 +3F59: 26 07 BNE loc_3F62 ; cycles=3/8 nt/t +3F5B: 15 F2 00 00 94 MOVTPE.B R4, @H'F200 ; LCD command/address write to E-clock H'F200; refs mem_F200 in program_or_external; cycles=13 +3F60: 20 10 BRA loc_3F72 ; cycles=7 + +loc_3F62: +3F62: 15 F2 01 00 94 MOVTPE.B R4, @H'F201 ; LCD data write to E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 +3F67: 1D FB 00 08 ADD:Q.W #1, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=8 +3F6B: 20 05 BRA loc_3F72 ; cycles=8 + +loc_3F6D: +3F6D: 15 F2 01 00 84 MOVFPE.B @H'F201, R4 ; LCD data read from E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 + +loc_3F72: +3F72: CF 88 LDC.W @R7+, SR ; cycles=7 +3F74: 19 RTS ; cycles=12 + +loc_3F76: +3F76: 58 27 10 MOV:I.W #H'2710, R0 ; dataflow R0=H'2710; cycles=3 +3F79: 59 C3 50 MOV:I.W #H'C350, R1 ; dataflow R1=H'C350; cycles=3 + +loc_3F7C: +3F7C: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=9 +3F80: 01 B8 F9 SCB/F R0, loc_3F7C ; cycles=3/4/8 false/-1/t + +loc_3F83: +3F83: 15 FE 82 C7 BSET.B #7, @P1DR ; set bit 7 of P1DR; cycles=8 +3F87: 01 B9 F9 SCB/F R1, loc_3F83 ; cycles=3/4/9 false/-1/t +3F8A: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_3F8C: +3F8C: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=9 +3F90: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=9 +3F94: F8 F6 80 13 CLR.W @(-H'0980,R0) ; cycles=9 +3F98: A8 09 ADD:Q.W #2, R0 ; cycles=4 +3F9A: 48 08 00 CMP:I #H'0800, R0 ; cycles=3 +3F9D: 26 ED BNE loc_3F8C ; cycles=3/8 nt/t +3F9F: 1E 03 6A BSR loc_430C ; cycles=14 +3FA2: 1E 03 7F BSR loc_4324 ; cycles=13 +3FA5: 1E 00 EE BSR loc_4096 ; cycles=14 +3FA8: 1E 01 10 BSR loc_40BB ; cycles=13 +3FAB: 1E 02 69 BSR loc_4217 ; cycles=14 +3FAE: 1E 03 9B BSR loc_434C ; cycles=13 + +loc_3FB1: +3FB1: 1D FE EC 07 5A 00 MOV:G.W #H'5A00, @WDT_TCSR_R ; WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00); cycles=9 +3FB7: 15 F7 94 13 CLR.B @H'F794 ; refs ram_F794 in on_chip_ram; cycles=8 +3FBB: 0E 16 BSR loc_3FD3 ; cycles=14 +3FBD: 1E 7B EB BSR loc_BBAB ; cycles=14 +3FC0: 0E 2D BSR loc_3FEF ; cycles=13 +3FC2: 1E 00 81 BSR loc_4046 ; cycles=13 +3FC5: 1E 7E D6 BSR loc_BE9E ; cycles=14 +3FC8: 1E E8 3B BSR loc_2806 ; cycles=13 +3FCB: 1E F9 62 BSR loc_3930 ; cycles=14 +3FCE: 1E D6 0F BSR loc_15E0 ; cycles=13 +3FD1: 20 DE BRA loc_3FB1 ; cycles=8 + +loc_3FD3: +3FD3: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +3FD7: 26 15 BNE loc_3FEE ; cycles=3/8 nt/t +3FD9: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +3FDD: 27 06 BEQ loc_3FE5 ; cycles=3/8 nt/t +3FDF: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +3FE3: 26 09 BNE loc_3FEE ; cycles=3/8 nt/t + +loc_3FE5: +3FE5: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=6 +3FE9: 26 03 BNE loc_3FEE ; cycles=3/8 nt/t +3FEB: 1E 7B 04 BSR loc_BAF2 ; cycles=14 + +loc_3FEE: +3FEE: 19 RTS ; cycles=12 + +loc_3FEF: +3FEF: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +3FF3: 26 12 BNE loc_4007 ; cycles=3/8 nt/t +3FF5: 15 F9 B5 13 CLR.B @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +3FF9: 15 F9 B0 13 CLR.B @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=8 +3FFD: 15 FA A5 D7 BCLR.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 +4001: 27 08 BEQ loc_400B ; cycles=3/8 nt/t +4003: 0E 07 BSR loc_400C ; cycles=14 +4005: 20 04 BRA loc_400B ; cycles=8 + +loc_4007: +4007: 15 FA A5 C7 BSET.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 + +loc_400B: +400B: 19 RTS ; cycles=13 + +loc_400C: +400C: 15 F7 30 13 CLR.B @H'F730 ; refs ram_F730 in on_chip_ram; cycles=9 +4010: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=9 +4014: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=9 +4018: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=9 +401C: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=9 +4020: 1D F7 32 13 CLR.W @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +4024: 1D F7 5C 13 CLR.W @H'F75C ; refs ram_F75C in on_chip_ram; cycles=9 +4028: 15 FB 03 13 CLR.B @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +402C: 1D E0 46 13 CLR.W @H'E046 ; refs mem_E046 in program_or_external; cycles=9 +4030: 1D F7 6A 13 CLR.W @H'F76A ; refs ram_F76A in on_chip_ram; cycles=9 +4034: 15 F7 91 13 CLR.B @H'F791 ; refs ram_F791 in on_chip_ram; cycles=9 +4038: 15 F7 95 13 CLR.B @H'F795 ; refs ram_F795 in on_chip_ram; cycles=9 +403C: 15 F7 6E 13 CLR.B @H'F76E ; refs ram_F76E in on_chip_ram; cycles=9 +4040: 0E 33 BSR loc_4075 ; cycles=13 +4042: 1E 01 D2 BSR loc_4217 ; cycles=13 +4045: 19 RTS ; cycles=13 + +loc_4046: +4046: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=7 +404A: 26 0C BNE loc_4058 ; cycles=3/7 nt/t +404C: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +4050: 27 07 BEQ loc_4059 ; cycles=3/7 nt/t +4052: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +4056: 27 01 BEQ loc_4059 ; cycles=3/7 nt/t + +loc_4058: +4058: 19 RTS ; cycles=12 + +loc_4059: +4059: 15 F9 B0 82 MOV:G.B @H'F9B0, R2 ; refs ram_F9B0 in on_chip_ram; cycles=6 +405D: A2 12 EXTU.B R2 ; cycles=3 +405F: 15 F9 B5 72 CMP:G.B @H'F9B5, R2 ; refs ram_F9B5 in on_chip_ram; cycles=6 +4063: 26 0F BNE loc_4074 ; cycles=3/8 nt/t +4065: A2 1A SHLL.B R2 ; cycles=2 +4067: FA F8 70 06 00 MOV:G.W #H'00, @(-H'0790,R2) ; cycles=11 +406C: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +4070: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_4074: +4074: 19 RTS ; cycles=12 + +loc_4075: +4075: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_4077: +4077: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=8 +407B: F8 E4 00 13 CLR.W @(-H'1C00,R0) ; cycles=8 +407F: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=8 +4083: 48 02 00 CMP:I #H'0200, R0 ; cycles=3 +4086: 24 04 BCC loc_408C ; cycles=3/7 nt/t +4088: F8 EC 00 13 CLR.W @(-H'1400,R0) ; cycles=9 + +loc_408C: +408C: A8 09 ADD:Q.W #2, R0 ; cycles=4 +408E: 48 04 00 CMP:I #H'0400, R0 ; cycles=3 +4091: 26 E4 BNE loc_4077 ; cycles=3/8 nt/t +4093: 0E 01 BSR loc_4096 ; cycles=14 +4095: 19 RTS ; cycles=13 + +loc_4096: +4096: 1D E0 00 07 00 80 MOV:G.W #H'0080, @H'E000 ; refs mem_E000 in program_or_external; cycles=11 +409C: 1D E0 06 07 80 00 MOV:G.W #H'8000, @H'E006 ; refs mem_E006 in program_or_external; cycles=11 +40A2: 1D E0 80 07 FF FF MOV:G.W #H'FFFF, @H'E080 ; refs mem_E080 in program_or_external; cycles=11 +40A8: 1D E8 00 07 00 80 MOV:G.W #H'0080, @H'E800 ; refs mem_E800 in program_or_external; cycles=11 +40AE: 1D E8 06 07 80 00 MOV:G.W #H'8000, @H'E806 ; refs mem_E806 in program_or_external; cycles=11 +40B4: 1D E8 80 07 FF FF MOV:G.W #H'FFFF, @H'E880 ; refs mem_E880 in program_or_external; cycles=11 +40BA: 19 RTS ; cycles=12 + +loc_40BB: +40BB: 58 00 40 MOV:I.W #H'0040, R0 ; dataflow R0=H'0040; cycles=3 + +loc_40BE: +40BE: F8 F8 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0792,R0) ; cycles=9 +40C4: F8 F8 AE 07 FF FF MOV:G.W #H'FFFF, @(-H'0752,R0) ; cycles=9 +40CA: F8 F8 EE 07 FF FF MOV:G.W #H'FFFF, @(-H'0712,R0) ; cycles=9 +40D0: F8 F9 2E 07 FF FF MOV:G.W #H'FFFF, @(-H'06D2,R0) ; cycles=9 +40D6: F8 F9 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0692,R0) ; cycles=9 +40DC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +40DE: 26 DE BNE loc_40BE ; cycles=3/7 nt/t +40E0: 15 F9 C4 06 14 MOV:G.B #H'14, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +40E5: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +40EA: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +40EF: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +40F4: 15 FE 8E F7 BTST.B #7, @P7DR ; refs P7DR in register_field; cycles=7 +40F8: 27 09 BEQ loc_4103 ; cycles=3/7 nt/t +40FA: 1D F4 02 05 6B 6F CMP:G.W #H'6B6F, @H'F402 ; refs mem_F402 in program_or_external; cycles=7 +4100: 37 00 AD BEQ loc_41B0 ; cycles=3/7 nt/t + +loc_4103: +4103: 58 01 00 MOV:I.W #H'0100, R0 ; dataflow R0=H'0100; cycles=3 + +loc_4106: +4106: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +4108: F8 C9 64 85 MOV:G.W @(-H'369C,R0), R5 ; cycles=7 +410C: F8 F4 00 95 MOV:G.W R5, @(-H'0C00,R0) ; cycles=7 +4110: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +4112: A8 84 MOV:G.W R0, R4 ; cycles=3 +4114: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4117: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +411B: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +411E: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4122: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4125: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4129: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +412C: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4130: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4133: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4137: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +413A: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +413E: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4141: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4145: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4148: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +414C: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +414F: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4153: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4156: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +415A: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +415D: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4161: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4164: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4168: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +416B: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +416F: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4172: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4176: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4179: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +417D: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4180: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +4182: 26 82 BNE loc_4106 ; cycles=3/7 nt/t +4184: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_4187: +4187: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +4189: A8 84 MOV:G.W R0, R4 ; cycles=3 +418B: A4 10 SWAP.B R4 ; cycles=3 +418D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4190: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4193: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4195: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4198: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +419B: AC 09 ADD:Q.W #2, R4 ; cycles=4 +419D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A0: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41A3: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41A5: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A8: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41AB: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +41AD: 01 B8 D7 SCB/F R0, loc_4187 ; cycles=3/4/9 false/-1/t + +loc_41B0: +41B0: 20 20 BRA loc_41D2 ; cycles=7 + +loc_41D2: +41D2: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_41D5: +41D5: A8 81 MOV:G.W R0, R1 ; cycles=3 +41D7: A1 1A SHLL.B R1 ; cycles=2 +41D9: A1 1A SHLL.B R1 ; cycles=2 +41DB: A1 1A SHLL.B R1 ; cycles=2 +41DD: A8 84 MOV:G.W R0, R4 ; cycles=3 +41DF: A4 10 SWAP.B R4 ; cycles=3 +41E1: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41E3: 18 BF FE JSR @loc_BFFE ; cycles=14 +41E6: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41E8: F9 F7 B0 95 MOV:G.W R5, @(-H'0850,R1) ; cycles=7 +41EC: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41EE: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41F0: 18 BF FE JSR @loc_BFFE ; cycles=13 +41F3: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41F5: F9 F7 B2 95 MOV:G.W R5, @(-H'084E,R1) ; cycles=6 +41F9: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41FB: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41FD: 18 BF FE JSR @loc_BFFE ; cycles=14 +4200: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +4202: F9 F7 B4 95 MOV:G.W R5, @(-H'084C,R1) ; cycles=7 +4206: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4208: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +420A: 18 BF FE JSR @loc_BFFE ; cycles=13 +420D: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +420F: F9 F7 B6 95 MOV:G.W R5, @(-H'084A,R1) ; cycles=6 +4213: 01 B8 BF SCB/F R0, loc_41D5 ; cycles=3/4/9 false/-1/t +4216: 19 RTS ; cycles=12 + +loc_4217: +4217: 15 F7 98 13 CLR.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +421B: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +421F: 15 FE 82 D2 BCLR.B #2, @P1DR ; clear bit 2 of P1DR; cycles=8 +4223: 1D F7 00 07 24 24 MOV:G.W #H'2424, @H'F700 ; refs ram_F700 in on_chip_ram; cycles=9 +4229: 1D F7 02 07 24 24 MOV:G.W #H'2424, @H'F702 ; refs ram_F702 in on_chip_ram; cycles=9 +422F: 1D F7 04 07 24 24 MOV:G.W #H'2424, @H'F704 ; refs ram_F704 in on_chip_ram; cycles=9 +4235: 1D F7 06 07 24 24 MOV:G.W #H'2424, @H'F706 ; refs ram_F706 in on_chip_ram; cycles=9 +423B: 15 F7 08 06 7F MOV:G.B #H'7F, @H'F708 ; refs ram_F708 in on_chip_ram; cycles=9 +4240: 15 F7 09 06 24 MOV:G.B #H'24, @H'F709 ; refs ram_F709 in on_chip_ram; cycles=9 +4245: 1D F7 0A 07 24 24 MOV:G.W #H'2424, @H'F70A ; refs ram_F70A in on_chip_ram; cycles=9 +424B: 15 F7 10 13 CLR.B @H'F710 ; refs ram_F710 in on_chip_ram; cycles=8 +424F: 15 F7 11 13 CLR.B @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +4253: 15 F7 12 13 CLR.B @H'F712 ; refs ram_F712 in on_chip_ram; cycles=8 +4257: 15 F7 13 13 CLR.B @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +425B: 15 F7 14 13 CLR.B @H'F714 ; refs ram_F714 in on_chip_ram; cycles=8 +425F: 15 F7 15 13 CLR.B @H'F715 ; refs ram_F715 in on_chip_ram; cycles=8 +4263: 15 F7 16 13 CLR.B @H'F716 ; refs ram_F716 in on_chip_ram; cycles=8 +4267: 15 F7 17 13 CLR.B @H'F717 ; refs ram_F717 in on_chip_ram; cycles=8 +426B: 15 F7 18 06 FF MOV:G.B #H'FF, @H'F718 ; refs ram_F718 in on_chip_ram; cycles=9 +4270: 15 F7 19 06 FF MOV:G.B #H'FF, @H'F719 ; refs ram_F719 in on_chip_ram; cycles=9 +4275: 15 F7 1A 06 FF MOV:G.B #H'FF, @H'F71A ; refs ram_F71A in on_chip_ram; cycles=9 +427A: 15 F7 1B 06 FF MOV:G.B #H'FF, @H'F71B ; refs ram_F71B in on_chip_ram; cycles=9 +427F: 15 F7 1C 06 FF MOV:G.B #H'FF, @H'F71C ; refs ram_F71C in on_chip_ram; cycles=9 +4284: 15 F7 1D 06 FF MOV:G.B #H'FF, @H'F71D ; refs ram_F71D in on_chip_ram; cycles=9 +4289: 15 F7 1E 06 FF MOV:G.B #H'FF, @H'F71E ; refs ram_F71E in on_chip_ram; cycles=9 +428E: 15 F7 1F 06 FF MOV:G.B #H'FF, @H'F71F ; refs ram_F71F in on_chip_ram; cycles=9 +4293: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +4299: 1D FA F2 07 4F 4E MOV:G.W #H'4F4E, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +429F: 1D FA F4 07 4E 45 MOV:G.W #H'4E45, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42A5: 1D FA F6 07 43 54 MOV:G.W #H'4354, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42AB: 1D FA F8 07 3A 4E MOV:G.W #H'3A4E, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42B1: 1D FA FA 07 4F 54 MOV:G.W #H'4F54, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42B7: 1D FA FC 07 20 41 MOV:G.W #H'2041, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42BD: 1D FA FE 07 43 54 MOV:G.W #H'4354, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42C3: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +42C6: 1E FC 03 BSR loc_3ECC ; cycles=13 +42C9: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +42CF: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +42D5: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42DB: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42E1: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42E7: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42ED: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42F3: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42F9: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +42FC: 1E FB CD BSR loc_3ECC ; cycles=13 +42FF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +4302: 1E FB C7 BSR loc_3ECC ; cycles=13 +4305: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +4308: 1E FB C1 BSR loc_3ECC ; cycles=13 +430B: 19 RTS ; cycles=13 + +loc_430C: +430C: 15 FE 8B D0 BCLR.B #0, @P6DR ; clear bit 0 of P6DR; cycles=9 +4310: 15 F5 55 06 AA MOV:G.B #H'AA, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +4315: 15 F4 AA 06 55 MOV:G.B #H'55, @H'F4AA ; refs mem_F4AA in program_or_external; cycles=9 +431A: 15 F5 55 06 CC MOV:G.B #H'CC, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +431F: 15 FE 8B C0 BSET.B #0, @P6DR ; set bit 0 of P6DR; cycles=8 +4323: 19 RTS ; cycles=13 + +loc_4324: +4324: 5C 00 38 MOV:I.W #H'0038, R4 ; dataflow R4=H'0038; cycles=3 +4327: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +432A: 1E FB 9F BSR loc_3ECC ; cycles=13 +432D: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 +4330: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4333: 1E FB 96 BSR loc_3ECC ; cycles=14 +4336: 5C 00 0E MOV:I.W #H'000E, R4 ; dataflow R4=H'000E; cycles=3 +4339: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +433C: 1E FB 8D BSR loc_3ECC ; cycles=13 +433F: 5C 00 06 MOV:I.W #H'0006, R4 ; dataflow R4=H'0006; cycles=3 +4342: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4345: 1E FB 84 BSR loc_3ECC ; cycles=14 +4348: 1E CD 83 BSR loc_10CE ; cycles=13 +434B: 19 RTS ; cycles=13 + +loc_434C: +434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9 +4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9 +4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9 +435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9 +4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9 +4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40 (A/D priority=4); cycles=9 +436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR; enable SCI1 receive and receive-error interrupts (RIE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR; cycles=9 +4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR; cycles=9 +4376: 15 FE E8 C6 BSET.B #6, @ADCSR ; set ADIE (bit 6) of ADCSR; cycles=9 +437A: 15 FE FD C4 BSET.B #4, @SYSCR2 ; set IRQ3E (bit 4) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +437E: 15 FE FD C5 BSET.B #5, @SYSCR2 ; set IRQ4E (bit 5) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +4382: 15 FE 8E F6 BTST.B #6, @P7DR ; refs P7DR in register_field; cycles=7 +4386: 27 06 BEQ loc_438E ; cycles=3/7 nt/t +4388: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 + +loc_438E: +438E: 0C 03 00 88 LDC.W #H'0300, SR ; dataflow SR=H'0300; cycles=6 +4392: 19 RTS ; cycles=12 + +vec_nmi_4393: +4393: 0A RTE ; cycles=14 + +loc_4394: +4394: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +4399: 32 00 86 BHI loc_4422 ; cycles=3/8 nt/t +439C: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +43A0: 36 00 7F BNE loc_4422 ; cycles=3/7 nt/t +43A3: 1D F7 36 83 MOV:G.W @H'F736, R3 ; refs ram_F736 in on_chip_ram; cycles=6 +43A7: 37 00 78 BEQ loc_4422 ; cycles=3/8 nt/t +43AA: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +43AE: 1D F6 BE 34 SUB.W @H'F6BE, R4 ; refs ram_F6BE in on_chip_ram; cycles=7 +43B2: AB DF BCLR.W #15, R3 ; cycles=3 +43B4: 26 19 BNE loc_43CF ; cycles=3/7 nt/t +43B6: AB DE BCLR.W #14, R3 ; cycles=3 +43B8: 26 21 BNE loc_43DB ; cycles=3/7 nt/t +43BA: AB DD BCLR.W #13, R3 ; cycles=3 +43BC: 26 29 BNE loc_43E7 ; cycles=3/7 nt/t +43BE: AB DC BCLR.W #12, R3 ; cycles=3 +43C0: 26 31 BNE loc_43F3 ; cycles=3/7 nt/t +43C2: AB DB BCLR.W #11, R3 ; cycles=3 +43C4: 26 39 BNE loc_43FF ; cycles=3/7 nt/t +43C6: AB DA BCLR.W #10, R3 ; cycles=3 +43C8: 26 43 BNE loc_440D ; cycles=3/7 nt/t +43CA: 1E D5 D5 BSR loc_19A2 ; cycles=13 +43CD: 20 53 BRA loc_4422 ; cycles=8 + +loc_43CF: +43CF: 0E 5E BSR loc_442F ; cycles=14 +43D1: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43D4: 27 03 BEQ loc_43D9 ; cycles=3/7 nt/t +43D6: 1E D6 5C BSR loc_1A35 ; cycles=13 + +loc_43D9: +43D9: 20 47 BRA loc_4422 ; cycles=8 + +loc_43DB: +43DB: 0E 52 BSR loc_442F ; cycles=14 +43DD: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43E0: 27 03 BEQ loc_43E5 ; cycles=3/7 nt/t +43E2: 1E D6 B7 BSR loc_1A9C ; cycles=13 + +loc_43E5: +43E5: 20 3B BRA loc_4422 ; cycles=8 + +loc_43E7: +43E7: 0E 46 BSR loc_442F ; cycles=14 +43E9: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43EC: 27 03 BEQ loc_43F1 ; cycles=3/7 nt/t +43EE: 1E D6 F3 BSR loc_1AE4 ; cycles=13 + +loc_43F1: +43F1: 20 2F BRA loc_4422 ; cycles=8 + +loc_43F3: +43F3: 0E 3A BSR loc_442F ; cycles=14 +43F5: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43F8: 27 03 BEQ loc_43FD ; cycles=3/7 nt/t +43FA: 1E D7 0E BSR loc_1B0B ; cycles=13 + +loc_43FD: +43FD: 20 23 BRA loc_4422 ; cycles=8 + +loc_43FF: +43FF: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4404: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +4408: 1E 04 EF BSR loc_48FA ; cycles=13 +440B: 20 15 BRA loc_4422 ; cycles=8 + +loc_440D: +440D: 0E 20 BSR loc_442F ; cycles=14 +440F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4412: 27 0C BEQ loc_4420 ; cycles=3/7 nt/t +4414: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4419: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +441D: 1E 04 DA BSR loc_48FA ; cycles=14 + +loc_4420: +4420: 20 00 BRA loc_4422 ; cycles=7 + +loc_4422: +4422: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +4426: 1D F6 BE 94 MOV:G.W R4, @H'F6BE ; refs ram_F6BE in on_chip_ram; cycles=7 +442A: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +442E: 19 RTS ; cycles=12 + +loc_442F: +442F: 15 F6 F7 24 ADD:G.B @H'F6F7, R4 ; refs ram_F6F7 in on_chip_ram; cycles=6 +4433: 44 88 CMP:E #H'88, R4 ; cycles=2 +4435: 24 0D BCC loc_4444 ; cycles=3/8 nt/t +4437: 44 78 CMP:E #H'78, R4 ; cycles=2 +4439: 23 13 BLS loc_444E ; cycles=3/8 nt/t +443B: 15 F6 F7 94 MOV:G.B R4, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=6 +443F: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4442: 20 12 BRA loc_4456 ; cycles=7 + +loc_4444: +4444: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4449: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +444C: 20 08 BRA loc_4456 ; cycles=7 + +loc_444E: +444E: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4453: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4456: +4456: 19 RTS ; cycles=12 + +loc_4457: +4457: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +445C: 32 00 86 BHI loc_44E5 ; cycles=3/7 nt/t +445F: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=6 +4463: 36 00 7F BNE loc_44E5 ; cycles=3/8 nt/t +4466: 1D F7 38 83 MOV:G.W @H'F738, R3 ; refs ram_F738 in on_chip_ram; cycles=7 +446A: 37 00 78 BEQ loc_44E5 ; cycles=3/7 nt/t +446D: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +4471: 1D F6 BC 34 SUB.W @H'F6BC, R4 ; refs ram_F6BC in on_chip_ram; cycles=6 +4475: AB DF BCLR.W #15, R3 ; cycles=3 +4477: 26 19 BNE loc_4492 ; cycles=3/8 nt/t +4479: AB DE BCLR.W #14, R3 ; cycles=3 +447B: 26 21 BNE loc_449E ; cycles=3/8 nt/t +447D: AB DD BCLR.W #13, R3 ; cycles=3 +447F: 26 29 BNE loc_44AA ; cycles=3/8 nt/t +4481: AB DC BCLR.W #12, R3 ; cycles=3 +4483: 26 31 BNE loc_44B6 ; cycles=3/8 nt/t +4485: AB DB BCLR.W #11, R3 ; cycles=3 +4487: 26 39 BNE loc_44C2 ; cycles=3/8 nt/t +4489: AB DA BCLR.W #10, R3 ; cycles=3 +448B: 26 43 BNE loc_44D0 ; cycles=3/8 nt/t +448D: 1E D5 12 BSR loc_19A2 ; cycles=14 +4490: 20 53 BRA loc_44E5 ; cycles=7 + +loc_4492: +4492: 0E 5E BSR loc_44F2 ; cycles=13 +4494: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4497: 27 03 BEQ loc_449C ; cycles=3/8 nt/t +4499: 1E D5 99 BSR loc_1A35 ; cycles=14 + +loc_449C: +449C: 20 47 BRA loc_44E5 ; cycles=7 + +loc_449E: +449E: 0E 52 BSR loc_44F2 ; cycles=13 +44A0: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44A3: 27 03 BEQ loc_44A8 ; cycles=3/8 nt/t +44A5: 1E D5 F4 BSR loc_1A9C ; cycles=14 + +loc_44A8: +44A8: 20 3B BRA loc_44E5 ; cycles=7 + +loc_44AA: +44AA: 0E 46 BSR loc_44F2 ; cycles=13 +44AC: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44AF: 27 03 BEQ loc_44B4 ; cycles=3/8 nt/t +44B1: 1E D6 30 BSR loc_1AE4 ; cycles=14 + +loc_44B4: +44B4: 20 2F BRA loc_44E5 ; cycles=7 + +loc_44B6: +44B6: 0E 3A BSR loc_44F2 ; cycles=13 +44B8: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44BB: 27 03 BEQ loc_44C0 ; cycles=3/8 nt/t +44BD: 1E D6 4B BSR loc_1B0B ; cycles=14 + +loc_44C0: +44C0: 20 23 BRA loc_44E5 ; cycles=7 + +loc_44C2: +44C2: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44C7: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +44CB: 1E 04 2C BSR loc_48FA ; cycles=14 +44CE: 20 15 BRA loc_44E5 ; cycles=7 + +loc_44D0: +44D0: 0E 20 BSR loc_44F2 ; cycles=13 +44D2: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44D5: 27 0C BEQ loc_44E3 ; cycles=3/8 nt/t +44D7: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44DC: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +44E0: 1E 04 17 BSR loc_48FA ; cycles=13 + +loc_44E3: +44E3: 20 00 BRA loc_44E5 ; cycles=8 + +loc_44E5: +44E5: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +44E9: 1D F6 BC 94 MOV:G.W R4, @H'F6BC ; refs ram_F6BC in on_chip_ram; cycles=6 +44ED: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=8 +44F1: 19 RTS ; cycles=13 + +loc_44F2: +44F2: 15 F6 F8 24 ADD:G.B @H'F6F8, R4 ; refs ram_F6F8 in on_chip_ram; cycles=7 +44F6: 44 88 CMP:E #H'88, R4 ; cycles=2 +44F8: 24 0D BCC loc_4507 ; cycles=3/7 nt/t +44FA: 44 78 CMP:E #H'78, R4 ; cycles=2 +44FC: 23 13 BLS loc_4511 ; cycles=3/7 nt/t +44FE: 15 F6 F8 94 MOV:G.B R4, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=7 +4502: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4505: 20 12 BRA loc_4519 ; cycles=8 + +loc_4507: +4507: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +450C: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +450F: 20 08 BRA loc_4519 ; cycles=8 + +loc_4511: +4511: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +4516: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4519: +4519: 19 RTS ; cycles=13 + +loc_451A: +451A: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +451F: 32 00 86 BHI loc_45A8 ; cycles=3/8 nt/t +4522: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +4526: 36 00 7F BNE loc_45A8 ; cycles=3/7 nt/t +4529: 1D F7 3A 83 MOV:G.W @H'F73A, R3 ; refs ram_F73A in on_chip_ram; cycles=6 +452D: 37 00 78 BEQ loc_45A8 ; cycles=3/8 nt/t +4530: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +4534: 1D F6 BA 34 SUB.W @H'F6BA, R4 ; refs ram_F6BA in on_chip_ram; cycles=7 +4538: AB DF BCLR.W #15, R3 ; cycles=3 +453A: 26 19 BNE loc_4555 ; cycles=3/7 nt/t +453C: AB DE BCLR.W #14, R3 ; cycles=3 +453E: 26 21 BNE loc_4561 ; cycles=3/7 nt/t +4540: AB DD BCLR.W #13, R3 ; cycles=3 +4542: 26 29 BNE loc_456D ; cycles=3/7 nt/t +4544: AB DC BCLR.W #12, R3 ; cycles=3 +4546: 26 31 BNE loc_4579 ; cycles=3/7 nt/t +4548: AB DB BCLR.W #11, R3 ; cycles=3 +454A: 26 39 BNE loc_4585 ; cycles=3/7 nt/t +454C: AB DA BCLR.W #10, R3 ; cycles=3 +454E: 26 43 BNE loc_4593 ; cycles=3/7 nt/t +4550: 1E D4 4F BSR loc_19A2 ; cycles=13 +4553: 20 53 BRA loc_45A8 ; cycles=8 + +loc_4555: +4555: 0E 5E BSR loc_45B5 ; cycles=14 +4557: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +455A: 27 03 BEQ loc_455F ; cycles=3/7 nt/t +455C: 1E D4 D6 BSR loc_1A35 ; cycles=13 + +loc_455F: +455F: 20 47 BRA loc_45A8 ; cycles=8 + +loc_4561: +4561: 0E 52 BSR loc_45B5 ; cycles=14 +4563: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4566: 27 03 BEQ loc_456B ; cycles=3/7 nt/t +4568: 1E D5 31 BSR loc_1A9C ; cycles=13 + +loc_456B: +456B: 20 3B BRA loc_45A8 ; cycles=8 + +loc_456D: +456D: 0E 46 BSR loc_45B5 ; cycles=14 +456F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4572: 27 03 BEQ loc_4577 ; cycles=3/7 nt/t +4574: 1E D5 6D BSR loc_1AE4 ; cycles=13 + +loc_4577: +4577: 20 2F BRA loc_45A8 ; cycles=8 + +loc_4579: +4579: 0E 3A BSR loc_45B5 ; cycles=14 +457B: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +457E: 27 03 BEQ loc_4583 ; cycles=3/7 nt/t +4580: 1E D5 88 BSR loc_1B0B ; cycles=13 + +loc_4583: +4583: 20 23 BRA loc_45A8 ; cycles=8 + +loc_4585: +4585: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +458A: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +458E: 1E 03 69 BSR loc_48FA ; cycles=13 +4591: 20 15 BRA loc_45A8 ; cycles=8 + +loc_4593: +4593: 0E 20 BSR loc_45B5 ; cycles=14 +4595: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4598: 27 0C BEQ loc_45A6 ; cycles=3/7 nt/t +459A: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +459F: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +45A3: 1E 03 54 BSR loc_48FA ; cycles=14 + +loc_45A6: +45A6: 20 00 BRA loc_45A8 ; cycles=7 + +loc_45A8: +45A8: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +45AC: 1D F6 BA 94 MOV:G.W R4, @H'F6BA ; refs ram_F6BA in on_chip_ram; cycles=7 +45B0: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +45B4: 19 RTS ; cycles=12 + +loc_45B5: +45B5: 15 F6 F9 24 ADD:G.B @H'F6F9, R4 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45B9: 44 88 CMP:E #H'88, R4 ; cycles=2 +45BB: 24 0D BCC loc_45CA ; cycles=3/8 nt/t +45BD: 44 78 CMP:E #H'78, R4 ; cycles=2 +45BF: 23 13 BLS loc_45D4 ; cycles=3/8 nt/t +45C1: 15 F6 F9 94 MOV:G.B R4, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45C5: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +45C8: 20 12 BRA loc_45DC ; cycles=7 + +loc_45CA: +45CA: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45CF: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +45D2: 20 08 BRA loc_45DC ; cycles=7 + +loc_45D4: +45D4: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45D9: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_45DC: +45DC: 19 RTS ; cycles=12 + +loc_48EF: +48EF: 1D F7 34 80 MOV:G.W @H'F734, R0 ; refs ram_F734 in on_chip_ram; cycles=6 +48F3: 1D F7 32 90 MOV:G.W R0, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +48F7: 0E 01 BSR loc_48FA ; cycles=14 +48F9: 19 RTS ; cycles=13 + +loc_48FA: +48FA: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +48FE: 26 29 BNE loc_4929 ; cycles=3/7 nt/t +4900: 15 F7 32 04 1A CMP:G.B #H'1A, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=7 +4905: 27 22 BEQ loc_4929 ; cycles=3/8 nt/t +4907: 1D F7 32 05 19 00 CMP:G.W #H'1900, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +490D: 27 1A BEQ loc_4929 ; cycles=3/8 nt/t +490F: 1D E1 EC FD BTST.W #13, @H'E1EC ; refs mem_E1EC in program_or_external; cycles=6 +4913: 27 14 BEQ loc_4929 ; cycles=3/8 nt/t +4915: 1D E1 EC 80 MOV:G.W @H'E1EC, R0 ; refs mem_E1EC in program_or_external; cycles=6 +4919: 0C 9F FF 50 AND.W #H'9FFF, R0 ; cycles=4 +491D: 1D E9 EC 90 MOV:G.W R0, @H'E9EC ; refs mem_E9EC in program_or_external; cycles=6 +4921: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +4923: 5B 00 F6 MOV:I.W #H'00F6, R3 ; dataflow R3=H'00F6; cycles=3 +4926: 1E F5 2B BSR loc_3E54 ; cycles=13 + +loc_4929: +4929: 15 F7 6E F6 BTST.B #6, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +492D: 26 0E BNE loc_493D ; cycles=3/8 nt/t +492F: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +4933: A0 12 EXTU.B R0 ; cycles=3 +4935: A0 1A SHLL.B R0 ; cycles=2 +4937: F8 49 3E 80 MOV:G.W @(H'493E,R0), R0 ; cycles=6 +493B: 11 D8 JSR @R0 ; JSR @R0 uses R0 loaded from pointer table H'493E via R0 (1/52 decoded targets); cycles=14 + +loc_493D: +493D: 19 RTS ; cycles=13 + +loc_5500: +5500: 15 F7 95 F7 BTST.B #7, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +5504: 36 00 A6 BNE loc_55AD ; cycles=3/7 nt/t +5507: 15 F7 6E 82 MOV:G.B @H'F76E, R2 ; refs ram_F76E in on_chip_ram; cycles=6 +550B: 0C 00 0F 52 AND.W #H'000F, R2 ; cycles=4 +550F: AA 83 MOV:G.W R2, R3 ; cycles=3 +5511: A3 1A SHLL.B R3 ; cycles=2 +5513: A3 1A SHLL.B R3 ; cycles=2 +5515: A3 1A SHLL.B R3 ; cycles=2 +5517: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5519: 15 F7 5E 84 MOV:G.B @H'F75E, R4 ; refs ram_F75E in on_chip_ram; cycles=6 +551D: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5521: A5 10 SWAP.B R5 ; cycles=3 +5523: 15 F7 5F 84 MOV:G.B @H'F75F, R4 ; refs ram_F75F in on_chip_ram; cycles=6 +5527: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +552B: FB F7 B0 95 MOV:G.W R5, @(-H'0850,R3) ; cycles=6 +552F: AA 84 MOV:G.W R2, R4 ; cycles=3 +5531: A4 10 SWAP.B R4 ; cycles=3 +5533: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5535: 1E 6A A8 BSR loc_BFE0 ; cycles=14 +5538: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +553A: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +553C: 15 F7 60 84 MOV:G.B @H'F760, R4 ; refs ram_F760 in on_chip_ram; cycles=7 +5540: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5544: A5 10 SWAP.B R5 ; cycles=3 +5546: 15 F7 61 84 MOV:G.B @H'F761, R4 ; refs ram_F761 in on_chip_ram; cycles=7 +554A: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +554E: FB F7 B2 95 MOV:G.W R5, @(-H'084E,R3) ; cycles=7 +5552: AA 84 MOV:G.W R2, R4 ; cycles=3 +5554: A4 10 SWAP.B R4 ; cycles=3 +5556: AC 09 ADD:Q.W #2, R4 ; cycles=4 +5558: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +555A: 1E 6A 83 BSR loc_BFE0 ; cycles=13 +555D: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +555F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5561: 15 F7 62 84 MOV:G.B @H'F762, R4 ; refs ram_F762 in on_chip_ram; cycles=6 +5565: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5569: A5 10 SWAP.B R5 ; cycles=3 +556B: 15 F7 63 84 MOV:G.B @H'F763, R4 ; refs ram_F763 in on_chip_ram; cycles=6 +556F: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5573: FB F7 B4 95 MOV:G.W R5, @(-H'084C,R3) ; cycles=6 +5577: AA 84 MOV:G.W R2, R4 ; cycles=3 +5579: A4 10 SWAP.B R4 ; cycles=3 +557B: 0C 00 04 24 ADD:G.W #H'0004, R4 ; cycles=4 +557F: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5581: 1E 6A 5C BSR loc_BFE0 ; cycles=14 +5584: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +5586: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5588: 15 F7 64 84 MOV:G.B @H'F764, R4 ; refs ram_F764 in on_chip_ram; cycles=7 +558C: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5590: A5 10 SWAP.B R5 ; cycles=3 +5592: 15 F7 65 84 MOV:G.B @H'F765, R4 ; refs ram_F765 in on_chip_ram; cycles=7 +5596: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +559A: FB F7 B6 95 MOV:G.W R5, @(-H'084A,R3) ; cycles=7 +559E: AA 84 MOV:G.W R2, R4 ; cycles=3 +55A0: A4 10 SWAP.B R4 ; cycles=3 +55A2: 0C 00 06 24 ADD:G.W #H'0006, R4 ; cycles=4 +55A6: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +55A8: 1E 6A 35 BSR loc_BFE0 ; cycles=13 +55AB: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 + +loc_55AD: +55AD: AD 13 CLR.W R5 ; dataflow R5=H'0000; cycles=3 + +loc_55AF: +55AF: FD C5 64 84 MOV:G.W @(-H'3A9C,R5), R4 ; cycles=6 +55B3: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=6 +55B7: 27 06 BEQ loc_55BF ; cycles=3/8 nt/t +55B9: AC FE BTST.W #14, R4 ; cycles=3 +55BB: 27 13 BEQ loc_55D0 ; cycles=3/8 nt/t +55BD: 20 04 BRA loc_55C3 ; cycles=8 + +loc_55BF: +55BF: AC FD BTST.W #13, R4 ; cycles=3 +55C1: 27 0D BEQ loc_55D0 ; cycles=3/8 nt/t + +loc_55C3: +55C3: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55C5: AD 83 MOV:G.W R5, R3 ; cycles=3 +55C7: AB 1B SHLR.W R3 ; cycles=3 +55C9: 0C 02 00 43 OR.W #H'0200, R3 ; cycles=4 +55CD: 1E E8 84 BSR loc_3E54 ; cycles=14 + +loc_55D0: +55D0: AD 09 ADD:Q.W #2, R5 ; cycles=4 +55D2: 4D 04 00 CMP:I #H'0400, R5 ; cycles=3 +55D5: 25 D8 BCS loc_55AF ; cycles=3/8 nt/t +55D7: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55D9: 5B 00 6C MOV:I.W #H'006C, R3 ; dataflow R3=H'006C; cycles=3 +55DC: 1E E8 75 BSR loc_3E54 ; cycles=13 +55DF: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=8 +55E3: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=8 +55E7: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=8 +55EB: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=8 +55EF: 19 RTS ; cycles=13 + +loc_58F7: +58F7: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +58FD: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5903: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +5905: 15 F7 5E 82 MOV:G.B @H'F75E, R2 ; refs ram_F75E in on_chip_ram; cycles=6 +5909: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +590D: A1 10 SWAP.B R1 ; cycles=3 +590F: 15 F7 5F 82 MOV:G.B @H'F75F, R2 ; refs ram_F75F in on_chip_ram; cycles=6 +5913: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5917: 1D FA F4 91 MOV:G.W R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=6 +591B: 15 F7 60 82 MOV:G.B @H'F760, R2 ; refs ram_F760 in on_chip_ram; cycles=6 +591F: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5923: A1 10 SWAP.B R1 ; cycles=3 +5925: 15 F7 61 82 MOV:G.B @H'F761, R2 ; refs ram_F761 in on_chip_ram; cycles=6 +5929: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +592D: 1D FA F6 91 MOV:G.W R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=6 +5931: 15 F7 62 82 MOV:G.B @H'F762, R2 ; refs ram_F762 in on_chip_ram; cycles=6 +5935: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5939: A1 10 SWAP.B R1 ; cycles=3 +593B: 15 F7 63 82 MOV:G.B @H'F763, R2 ; refs ram_F763 in on_chip_ram; cycles=6 +593F: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5943: 1D FA F8 91 MOV:G.W R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=6 +5947: 15 F7 64 82 MOV:G.B @H'F764, R2 ; refs ram_F764 in on_chip_ram; cycles=6 +594B: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +594F: A1 10 SWAP.B R1 ; cycles=3 +5951: 15 F7 65 82 MOV:G.B @H'F765, R2 ; refs ram_F765 in on_chip_ram; cycles=6 +5955: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5959: 1D FA FA 91 MOV:G.W R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=6 +595D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5963: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5969: 19 RTS ; cycles=13 + +loc_596A: +596A: 40 00 CMP:E #H'00, R0 ; cycles=2 +596C: 27 0A BEQ loc_5978 ; cycles=3/7 nt/t +596E: 40 01 CMP:E #H'01, R0 ; cycles=2 +5970: 27 0B BEQ loc_597D ; cycles=3/7 nt/t +5972: 40 02 CMP:E #H'02, R0 ; cycles=2 +5974: 27 0C BEQ loc_5982 ; cycles=3/7 nt/t +5976: 20 0F BRA loc_5987 ; cycles=7 + +loc_5978: +5978: 5C 00 83 MOV:I.W #H'0083, R4 ; dataflow R4=H'0083; cycles=3 +597B: 20 0D BRA loc_598A ; cycles=8 + +loc_597D: +597D: 5C 00 C3 MOV:I.W #H'00C3, R4 ; dataflow R4=H'00C3; cycles=3 +5980: 20 08 BRA loc_598A ; cycles=7 + +loc_5982: +5982: 5C 00 93 MOV:I.W #H'0093, R4 ; dataflow R4=H'0093; cycles=3 +5985: 20 03 BRA loc_598A ; cycles=8 + +loc_5987: +5987: 5C 00 D3 MOV:I.W #H'00D3, R4 ; dataflow R4=H'00D3; cycles=3 + +loc_598A: +598A: 15 F7 5B 24 ADD:G.B @H'F75B, R4 ; refs ram_F75B in on_chip_ram; cycles=7 +598E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +5991: 1E E5 38 BSR loc_3ECC ; cycles=14 +5994: 19 RTS ; cycles=12 + +loc_5A7A: +5A7A: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=7 +5A7E: 26 10 BNE loc_5A90 ; cycles=3/7 nt/t +5A80: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A84: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A88: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A8C: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 + +loc_5A90: +5A90: 19 RTS ; cycles=12 + +loc_5A91: +5A91: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5A94: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5A98: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5A9B: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5A9F: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5AA2: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5AA6: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5AA9: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5AAD: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5AB0: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5AB4: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5AB7: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5ABB: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5ABE: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5AC2: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5AC5: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5AC9: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5ACC: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5AD0: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5AD3: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5AD7: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5ADA: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5ADE: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5AE1: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5AE5: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5AE8: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5AEC: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5AEF: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5AF3: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5AF6: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5AFA: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5AFD: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5B01: 19 RTS ; cycles=13 + +loc_5B02: +5B02: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=7 +5B06: A0 12 EXTU.B R0 ; cycles=3 +5B08: 40 01 CMP:E #H'01, R0 ; cycles=2 +5B0A: 23 48 BLS loc_5B54 ; cycles=3/7 nt/t +5B0C: 40 09 CMP:E #H'09, R0 ; cycles=2 +5B0E: 22 1D BHI loc_5B2D ; cycles=3/7 nt/t +5B10: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=7 +5B14: 15 FA FF 90 MOV:G.B R0, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=7 +5B18: 15 FA FE 06 2F MOV:G.B #H'2F, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5B1D: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=6 +5B21: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B23: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=6 +5B27: 15 FA FD 90 MOV:G.B R0, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5B2B: 20 27 BRA loc_5B54 ; cycles=8 + +loc_5B2D: +5B2D: A0 1A SHLL.B R0 ; cycles=2 +5B2F: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=6 +5B33: 1D FA FE 90 MOV:G.W R0, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=6 +5B37: 15 FA FD 06 2F MOV:G.B #H'2F, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=9 +5B3C: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +5B40: A0 12 EXTU.B R0 ; cycles=3 +5B42: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B44: A0 1A SHLL.B R0 ; cycles=2 +5B46: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=7 +5B4A: 15 FA FC 90 MOV:G.B R0, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5B4E: A0 10 SWAP.B R0 ; cycles=3 +5B50: 15 FA FB 90 MOV:G.B R0, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=7 + +loc_5B54: +5B54: 19 RTS ; cycles=12 + +loc_5C91: +5C91: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +5C95: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5C99: 27 62 BEQ loc_5CFD ; cycles=3/8 nt/t +5C9B: A9 1A SHLL.W R1 ; cycles=3 +5C9D: 1D F7 4E 16 TST.W @H'F74E ; refs ram_F74E in on_chip_ram; cycles=6 +5CA1: 27 10 BEQ loc_5CB3 ; cycles=3/8 nt/t +5CA3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CA7: 1D F7 4E 52 AND.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAB: 1D F7 4E 72 CMP:G.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAF: 27 12 BEQ loc_5CC3 ; cycles=3/8 nt/t +5CB1: 20 4A BRA loc_5CFD ; cycles=8 + +loc_5CB3: +5CB3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CB7: 1D F7 46 52 AND.W @H'F746, R2 ; refs ram_F746 in on_chip_ram; cycles=6 +5CBB: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CBF: 27 3C BEQ loc_5CFD ; cycles=3/8 nt/t +5CC1: 20 00 BRA loc_5CC3 ; cycles=8 + +loc_5CC3: +5CC3: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5CC6: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5CCA: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5CCD: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5CD1: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5CD4: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5CD8: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5CDB: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5CDF: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5CE2: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5CE6: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5CE9: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5CED: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5CF0: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5CF4: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5CF7: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5CFB: 20 18 BRA loc_5D15 ; cycles=8 + +loc_5CFD: +5CFD: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +5D03: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5D09: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +5D0F: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 + +loc_5D15: +5D15: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +5D19: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5D1D: 27 62 BEQ loc_5D81 ; cycles=3/8 nt/t +5D1F: A9 1A SHLL.W R1 ; cycles=3 +5D21: 1D F7 52 16 TST.W @H'F752 ; refs ram_F752 in on_chip_ram; cycles=6 +5D25: 27 10 BEQ loc_5D37 ; cycles=3/8 nt/t +5D27: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D2B: 1D F7 52 52 AND.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D2F: 1D F7 52 72 CMP:G.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D33: 27 12 BEQ loc_5D47 ; cycles=3/8 nt/t +5D35: 20 4A BRA loc_5D81 ; cycles=8 + +loc_5D37: +5D37: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D3B: 1D F7 4A 52 AND.W @H'F74A, R2 ; refs ram_F74A in on_chip_ram; cycles=6 +5D3F: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D43: 27 3C BEQ loc_5D81 ; cycles=3/8 nt/t +5D45: 20 00 BRA loc_5D47 ; cycles=8 + +loc_5D47: +5D47: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5D4A: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5D4E: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5D51: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5D55: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5D58: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5D5C: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5D5F: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5D63: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5D66: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5D6A: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5D6D: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5D71: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5D74: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5D78: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5D7B: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5D7F: 20 18 BRA loc_5D99 ; cycles=8 + +loc_5D81: +5D81: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +5D87: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +5D8D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5D93: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 + +loc_5D99: +5D99: 19 RTS ; cycles=13 + +loc_5FD2: +5FD2: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=7 +5FD6: 15 F7 2F 70 CMP:G.B @H'F72F, R0 ; refs ram_F72F in on_chip_ram; cycles=7 +5FDA: 27 41 BEQ loc_601D ; cycles=3/7 nt/t +5FDC: 1D F7 2C 13 CLR.W @H'F72C ; refs ram_F72C in on_chip_ram; cycles=9 +5FE0: 15 F7 2E 13 CLR.B @H'F72E ; refs ram_F72E in on_chip_ram; cycles=9 +5FE4: 15 F7 2F 90 MOV:G.B R0, @H'F72F ; refs ram_F72F in on_chip_ram; cycles=7 +5FE8: A4 12 EXTU.B R4 ; cycles=3 + +loc_5FEA: +5FEA: AC 80 MOV:G.W R4, R0 ; cycles=3 +5FEC: A0 1A SHLL.B R0 ; cycles=2 +5FEE: AB 20 ADD:G.W R3, R0 ; cycles=3 +5FF0: D8 80 MOV:G.W @R0, R0 ; cycles=6 +5FF2: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +5FF4: D8 81 MOV:G.W @R0, R1 ; cycles=6 +5FF6: 15 F7 31 71 CMP:G.B @H'F731, R1 ; refs ram_F731 in on_chip_ram; cycles=7 +5FFA: 25 1E BCS loc_601A ; cycles=3/7 nt/t +5FFC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +5FFE: D8 16 TST.W @R0 ; cycles=6 +6000: 27 10 BEQ loc_6012 ; cycles=3/7 nt/t + +loc_6002: +6002: D8 81 MOV:G.W @R0, R1 ; cycles=6 +6004: 27 14 BEQ loc_601A ; cycles=3/7 nt/t +6006: A9 1A SHLL.W R1 ; cycles=3 +6008: F9 E4 00 16 TST.W @(-H'1C00,R1) ; cycles=7 +600C: 26 04 BNE loc_6012 ; cycles=3/7 nt/t +600E: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +6010: 20 F0 BRA loc_6002 ; cycles=7 + +loc_6012: +6012: 1D F7 2C 4C BSET.W R4, @H'F72C ; refs ram_F72C in on_chip_ram; cycles=9 +6016: 15 F7 2E 08 ADD:Q.B #1, @H'F72E ; refs ram_F72E in on_chip_ram; cycles=9 + +loc_601A: +601A: 01 BC CD SCB/F R4, loc_5FEA ; cycles=3/4/8 false/-1/t + +loc_601D: +601D: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=6 +6021: 27 1D BEQ loc_6040 ; cycles=3/8 nt/t +6023: 15 F7 33 04 FF CMP:G.B #H'FF, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=6 +6028: 27 08 BEQ loc_6032 ; cycles=3/7 nt/t +602A: 15 F7 33 70 CMP:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +602E: 23 0A BLS loc_603A ; cycles=3/7 nt/t +6030: 20 20 BRA loc_6052 ; cycles=7 + +loc_6032: +6032: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +6034: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +6038: 20 18 BRA loc_6052 ; cycles=7 + +loc_603A: +603A: 15 F7 33 13 CLR.B @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +603E: 20 12 BRA loc_6052 ; cycles=7 + +loc_6040: +6040: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +6044: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +6049: 15 F7 2F 13 CLR.B @H'F72F ; refs ram_F72F in on_chip_ram; cycles=8 +604D: 5C FF FE MOV:I.W #H'FFFE, R4 ; dataflow R4=H'FFFE; cycles=3 +6050: 20 18 BRA loc_606A ; cycles=7 + +loc_6052: +6052: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +6056: A0 12 EXTU.B R0 ; cycles=3 +6058: 1D F7 2C 81 MOV:G.W @H'F72C, R1 ; refs ram_F72C in on_chip_ram; cycles=7 +605C: 5C 00 FF MOV:I.W #H'00FF, R4 ; dataflow R4=H'00FF; cycles=3 + +loc_605F: +605F: A4 08 ADD:Q.B #1, R4 ; cycles=4 +6061: A9 1B SHLR.W R1 ; cycles=3 +6063: 24 FA BCC loc_605F ; cycles=3/8 nt/t +6065: 01 B8 F7 SCB/F R0, loc_605F ; cycles=3/4/9 false/-1/t +6068: A4 1A SHLL.B R4 ; cycles=2 + +loc_606A: +606A: 19 RTS ; cycles=12 + +loc_606B: +606B: 1D F7 32 80 MOV:G.W @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +606F: 1D F7 5C 70 CMP:G.W @H'F75C, R0 ; refs ram_F75C in on_chip_ram; cycles=6 +6073: 27 65 BEQ loc_60DA ; cycles=3/8 nt/t +6075: 1D F7 5C 90 MOV:G.W R0, @H'F75C ; refs ram_F75C in on_chip_ram; cycles=6 +6079: A9 1A SHLL.W R1 ; cycles=3 +607B: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +607D: F1 E0 00 80 MOV:G.B @(-H'2000,R1), R0 ; cycles=6 +6081: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +6085: A2 10 SWAP.B R2 ; cycles=3 +6087: F1 E0 01 80 MOV:G.B @(-H'1FFF,R1), R0 ; cycles=6 +608B: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +608F: 1D F7 5E 92 MOV:G.W R2, @H'F75E ; refs ram_F75E in on_chip_ram; cycles=6 +6093: F1 E0 02 80 MOV:G.B @(-H'1FFE,R1), R0 ; cycles=6 +6097: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +609B: A2 10 SWAP.B R2 ; cycles=3 +609D: F1 E0 03 80 MOV:G.B @(-H'1FFD,R1), R0 ; cycles=6 +60A1: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60A5: 1D F7 60 92 MOV:G.W R2, @H'F760 ; refs ram_F760 in on_chip_ram; cycles=6 +60A9: F1 E0 04 80 MOV:G.B @(-H'1FFC,R1), R0 ; cycles=6 +60AD: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60B1: A2 10 SWAP.B R2 ; cycles=3 +60B3: F1 E0 05 80 MOV:G.B @(-H'1FFB,R1), R0 ; cycles=6 +60B7: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60BB: 1D F7 62 92 MOV:G.W R2, @H'F762 ; refs ram_F762 in on_chip_ram; cycles=6 +60BF: F1 E0 06 80 MOV:G.B @(-H'1FFA,R1), R0 ; cycles=6 +60C3: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60C7: A2 10 SWAP.B R2 ; cycles=3 +60C9: F1 E0 07 80 MOV:G.B @(-H'1FF9,R1), R0 ; cycles=6 +60CD: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60D1: 1D F7 64 92 MOV:G.W R2, @H'F764 ; refs ram_F764 in on_chip_ram; cycles=6 +60D5: 15 F7 5B 06 01 MOV:G.B #H'01, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=9 + +loc_60DA: +60DA: 19 RTS ; cycles=12 + +loc_6173: +6173: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +6179: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +617F: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +6185: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +618B: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +6191: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +6197: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +619D: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +61A3: 19 RTS ; cycles=13 + +loc_61D5: +61D5: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +61DB: 1D FA F2 07 55 52 MOV:G.W #H'5552, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +61E1: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +61E7: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +61ED: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +61F3: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +61F9: 1D FA FC 07 43 48 MOV:G.W #H'4348, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +61FF: 1D FA FE 07 52 20 MOV:G.W #H'5220, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +6205: 19 RTS ; cycles=13 + +loc_6206: +6206: 0C 01 FF 55 AND.W #H'01FF, R5 ; cycles=4 +620A: 4D 00 7F CMP:I #H'007F, R5 ; cycles=3 +620D: 23 07 BLS loc_6216 ; cycles=3/8 nt/t +620F: 4D 01 7F CMP:I #H'017F, R5 ; cycles=3 +6212: 23 04 BLS loc_6218 ; cycles=3/7 nt/t +6214: 20 0C BRA loc_6222 ; cycles=7 + +loc_6216: +6216: 20 12 BRA loc_622A ; cycles=7 + +loc_6218: +6218: 0C 00 80 35 SUB.W #H'0080, R5 ; cycles=4 +621C: 0C 01 00 25 ADD:G.W #H'0100, R5 ; cycles=4 +6220: 20 08 BRA loc_622A ; cycles=7 + +loc_6222: +6222: 0C 01 80 35 SUB.W #H'0180, R5 ; cycles=4 +6226: 0C 02 00 25 ADD:G.W #H'0200, R5 ; cycles=4 + +loc_622A: +622A: 19 RTS ; cycles=12 + +loc_622B: +622B: AD 84 MOV:G.W R5, R4 ; cycles=3 +622D: A5 12 EXTU.B R5 ; cycles=3 +622F: A4 10 SWAP.B R4 ; cycles=3 +6231: 04 07 54 AND.B #H'07, R4 ; cycles=3 +6234: 44 00 CMP:E #H'00, R4 ; cycles=2 +6236: 27 0C BEQ loc_6244 ; cycles=3/7 nt/t +6238: 44 01 CMP:E #H'01, R4 ; cycles=2 +623A: 27 11 BEQ loc_624D ; cycles=3/7 nt/t +623C: 44 02 CMP:E #H'02, R4 ; cycles=2 +623E: 27 16 BEQ loc_6256 ; cycles=3/7 nt/t +6240: 44 03 CMP:E #H'03, R4 ; cycles=2 +6242: 27 1B BEQ loc_625F ; cycles=3/7 nt/t + +loc_6244: +6244: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6246: 22 17 BHI loc_625F ; cycles=3/7 nt/t +6248: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +624B: 20 17 BRA loc_6264 ; cycles=8 + +loc_624D: +624D: 45 FF CMP:E #H'FF, R5 ; cycles=2 +624F: 22 0E BHI loc_625F ; cycles=3/8 nt/t +6251: 5C 00 80 MOV:I.W #H'0080, R4 ; dataflow R4=H'0080; cycles=3 +6254: 20 0E BRA loc_6264 ; cycles=7 + +loc_6256: +6256: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6258: 22 05 BHI loc_625F ; cycles=3/7 nt/t +625A: 5C 01 80 MOV:I.W #H'0180, R4 ; dataflow R4=H'0180; cycles=3 +625D: 20 05 BRA loc_6264 ; cycles=8 + +loc_625F: +625F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +6261: 5D 01 FF MOV:I.W #H'01FF, R5 ; dataflow R5=H'01FF; cycles=3 + +loc_6264: +6264: AC 25 ADD:G.W R4, R5 ; cycles=3 +6266: 19 RTS ; cycles=12 +6F69: 11 .db H'11 +6F84: 20 20 BRA loc_6FA6 ; cycles=7 + +loc_6FA6: +6FA6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +6FA9: 1E CF 20 BSR loc_3ECC ; cycles=14 +6FAC: 20 10 BRA loc_6FBE ; cycles=7 + +loc_6FBE: +6FBE: 58 6F AE MOV:I.W #H'6FAE, R0 ; LCD text xref H'6FAE 'SHUTTER Xo'; dataflow R0=H'6FAE; cycles=3 +6FC1: 1E EA CD BSR loc_5A91 ; cycles=14 +6FC4: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +6FC7: 1E CF 02 BSR loc_3ECC ; cycles=14 +6FCA: 20 10 BRA loc_6FDC ; cycles=7 + +loc_6FDC: +6FDC: 58 6F CC MOV:I.W #H'6FCC, R0 ; dataflow R0=H'6FCC; cycles=3 +6FDF: 1E EC AF BSR loc_5C91 ; cycles=14 +6FE2: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +6FE5: 1E CE E4 BSR loc_3ECC ; cycles=14 +6FE8: 19 RTS ; cycles=12 +7000: F7 .db H'F7 +7047: 1E E4 B6 BSR loc_5500 ; cycles=14 +704A: 20 51 BRA loc_709D ; cycles=7 + +loc_709D: +709D: 20 10 BRA loc_70AF ; cycles=8 + +loc_70AF: +70AF: 58 70 9F MOV:I.W #H'709F, R0 ; LCD text xref H'709F 'OTHERS Xp'; dataflow R0=H'709F; cycles=3 +70B2: 1E E9 DC BSR loc_5A91 ; cycles=13 +70B5: 1E EA 4A BSR loc_5B02 ; cycles=14 +70B8: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +70BB: 1E CE 0E BSR loc_3ECC ; cycles=14 +70BE: 20 10 BRA loc_70D0 ; cycles=7 +70CF: 7E 58 MOV:S.W R6, @BR:H'58 ; cycles=5 + +loc_70D0: +70D0: 58 70 C0 MOV:I.W #H'70C0, R0 ; LCD text xref H'70C0 'COPY TO SLAVES~Xp'; dataflow R0=H'70C0; cycles=3 +70D1: 70 C0 MOV:S.B R0, @BR:H'C0 ; cycles=5 +70D3: 1E E9 BB BSR loc_5A91 ; cycles=14 +70D6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +70D9: 1E CD F0 BSR loc_3ECC ; cycles=14 +70DC: 1E F0 94 BSR loc_6173 ; cycles=13 +70DF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +70E2: 1E CD E7 BSR loc_3ECC ; cycles=13 +70E5: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +70E8: 1E CD E1 BSR loc_3ECC ; cycles=13 +70EB: 1E E9 8C BSR loc_5A7A ; cycles=14 +70EE: 19 RTS ; cycles=12 +710E: 40 07 CMP:E #H'07, R0 ; cycles=2 +7110: 20 43 BRA loc_7155 ; cycles=7 + +loc_7155: +7155: 71 44 MOV:S.B R1, @BR:H'44 ; cycles=5 +7157: 1E E9 37 BSR loc_5A91 ; cycles=14 +715A: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +715D: 1E CD 6C BSR loc_3ECC ; cycles=14 +7160: 59 00 43 MOV:I.W #H'0043, R1 ; dataflow R1=H'0043; cycles=3 +7163: 1E EF 05 BSR loc_606B ; cycles=14 +7166: 1E E7 8E BSR loc_58F7 ; cycles=13 +7169: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +716C: 1E CD 5D BSR loc_3ECC ; cycles=13 +716F: 1E F0 63 BSR loc_61D5 ; cycles=14 +7172: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +7175: 1E CD 54 BSR loc_3ECC ; cycles=14 +7178: 58 00 02 MOV:I.W #H'0002, R0 ; dataflow R0=H'0002; cycles=3 +717B: 1E E7 EC BSR loc_596A ; cycles=14 +717E: 1E E8 F9 BSR loc_5A7A ; cycles=13 +7181: 19 RTS ; cycles=13 +930A: 5B 93 1C MOV:I.W #H'931C, R3 ; dataflow R3=H'931C; cycles=3 +930D: 54 04 MOV:E.B #H'04, R4 ; dataflow R4=H'04; cycles=2 +930F: 1E CC C0 BSR loc_5FD2 ; cycles=14 +9312: FC 93 1C 84 MOV:G.W @(-H'6CE4,R4), R4 ; cycles=7 +9316: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +9318: 19 RTS ; cycles=12 + +loc_BA26: +BA26: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=7 +BA2A: 26 FA BNE loc_BA26 ; cycles=3/7 nt/t +BA2C: 15 F9 C0 06 64 MOV:G.B #H'64, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BA31: 15 F9 C4 06 07 MOV:G.B #H'07, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +BA36: 1D F8 50 80 MOV:G.W @H'F850, R0 ; refs ram_F850 in on_chip_ram; cycles=7 +BA3A: 1D F8 58 90 MOV:G.W R0, @H'F858 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA3E: 1D F8 52 80 MOV:G.W @H'F852, R0 ; refs ram_F852 in on_chip_ram; cycles=7 +BA42: 1D F8 5A 90 MOV:G.W R0, @H'F85A ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA46: 15 F8 54 80 MOV:G.B @H'F854, R0 ; refs ram_F854 in on_chip_ram; cycles=7 +BA4A: 15 F8 5C 90 MOV:G.B R0, @H'F85C ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA4E: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high; dataflow R0=H'5A; cycles=2 +BA50: 15 F8 58 60 XOR.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA54: 15 F8 59 60 XOR.B @H'F859, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F859 in on_chip_ram; cycles=7 +BA58: 15 F8 5A 60 XOR.B @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA5C: 15 F8 5B 60 XOR.B @H'F85B, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85B in on_chip_ram; cycles=7 +BA60: 15 F8 5C 60 XOR.B @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA64: 15 F8 5D 90 MOV:G.B R0, @H'F85D ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85D in on_chip_ram; cycles=7 + +loc_BA68: +BA68: 15 FE DC F7 BTST.B #7, @SCI1_SSR ; wait for SCI1 transmit data register empty (TDRE=1); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR in register_field; cycles=7 +BA6C: 27 FA BEQ loc_BA68 ; repeat SCI1 transmit-empty wait while TDRE=0; cycles=3/7 nt/t +BA6E: 15 F8 58 80 MOV:G.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA72: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=7 +BA76: 15 F9 C2 06 01 MOV:G.B #H'01, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high; refs ram_F9C2 in on_chip_ram; cycles=9 +BA7B: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BA7F: 15 FE DA C7 BSET.B #7, @SCI1_SCR ; set TIE (bit 7) of SCI1_SCR; enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=8 +BA83: 19 RTS ; cycles=13 + +vec_sci1_txi_BA84: +BA84: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BA88: 27 1F BEQ loc_BAA9 ; cycles=3/7 nt/t +BA8A: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BA8E: 27 19 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA90: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BA94: 27 13 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA96: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BA9A: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BA9E: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BAA2: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAA7: 20 48 BRA loc_BAF1 ; cycles=8 + +loc_BAA9: +BAA9: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +BAAB: 15 F9 C2 80 MOV:G.B @H'F9C2, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAAF: A0 12 EXTU.B R0 ; cycles=3 +BAB1: F0 F8 58 80 MOV:G.B @(-H'07A8,R0), R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; cycles=6 +BAB5: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=6 +BAB9: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +BABB: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BABF: 15 F9 C2 08 ADD:Q.B #1, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high; refs ram_F9C2 in on_chip_ram; cycles=8 +BAC3: 15 F9 C2 04 06 CMP:G.B #H'06, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAC8: 26 27 BNE loc_BAF1 ; cycles=3/7 nt/t +BACA: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BACE: 15 F7 95 F6 BTST.B #6, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +BAD2: 26 14 BNE loc_BAE8 ; cycles=3/7 nt/t +BAD4: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +BAD8: 26 07 BNE loc_BAE1 ; cycles=3/7 nt/t +BADA: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BADF: 20 0C BRA loc_BAED ; cycles=8 + +loc_BAE1: +BAE1: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAE6: 20 05 BRA loc_BAED ; cycles=7 + +loc_BAE8: +BAE8: 15 F9 C0 06 F0 MOV:G.B #H'F0, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BAED: +BAED: 15 F9 C1 13 CLR.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=8 + +loc_BAF1: +BAF1: 0A RTE ; cycles=14 + +loc_BAF2: +BAF2: 15 F9 B5 81 MOV:G.B @H'F9B5, R1 ; refs ram_F9B5 in on_chip_ram; cycles=7 +BAF6: A1 12 EXTU.B R1 ; cycles=3 +BAF8: 15 F9 B0 71 CMP:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +BAFC: 26 02 BNE loc_BB00 ; cycles=3/7 nt/t +BAFE: 20 56 BRA loc_BB56 ; cycles=7 + +loc_BB00: +BB00: 15 FA A2 C3 BSET.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BB04: A9 80 MOV:G.W R1, R0 ; cycles=3 +BB06: A8 1A SHLL.W R0 ; cycles=3 +BB08: F8 F8 70 80 MOV:G.W @(-H'0790,R0), R0 ; cycles=7 +BB0C: A8 85 MOV:G.W R0, R5 ; cycles=3 +BB0E: 1E A6 F5 BSR loc_6206 ; cycles=13 +BB11: A8 81 MOV:G.W R0, R1 ; cycles=3 +BB13: A1 10 SWAP.B R1 ; cycles=3 +BB15: A1 1B SHLR.B R1 ; cycles=2 +BB17: A1 82 MOV:G.B R1, R2 ; cycles=2 +BB19: 04 07 51 AND.B #H'07, R1 ; cycles=3 +BB1C: 15 F8 50 91 MOV:G.B R1, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=7 +BB20: 15 F8 52 95 MOV:G.B R5, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BB24: A5 10 SWAP.B R5 ; cycles=3 +BB26: 04 78 52 AND.B #H'78, R2 ; cycles=3 +BB29: A2 45 OR.B R2, R5 ; cycles=2 +BB2B: 15 F8 51 95 MOV:G.B R5, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BB2F: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +BB33: A8 1A SHLL.W R0 ; cycles=3 +BB35: F8 E8 00 84 MOV:G.W @(-H'1800,R0), R4 ; cycles=6 +BB39: 15 F8 54 94 MOV:G.B R4, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BB3D: A4 10 SWAP.B R4 ; cycles=3 +BB3F: 15 F8 53 94 MOV:G.B R4, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=6 +BB43: 1E FE E0 BSR loc_BA26 ; cycles=14 +BB46: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=11 +BB4C: 15 F9 C8 06 14 MOV:G.B #H'14, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=9 +BB51: 15 FA A3 06 80 MOV:G.B #H'80, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 + +loc_BB56: +BB56: 19 RTS ; cycles=12 + +vec_sci1_eri_BB57: +BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; refs ram_FAA4 in on_chip_ram; cycles=8 +BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 + +vec_sci1_rxi_BB67: +BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR in register_field; cycles=6 +BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=6 +BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t +BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BB7B: 20 0D BRA loc_BB8A ; cycles=8 + +loc_BB7D: +BB7D: 15 F9 C3 04 05 CMP:G.B #H'05, @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +BB82: 23 06 BLS loc_BB8A ; cycles=3/7 nt/t +BB84: 15 FA A4 13 CLR.B @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=9 +BB88: 20 19 BRA loc_BBA3 ; cycles=7 + +loc_BB8A: +BB8A: 15 F9 C3 81 MOV:G.B @H'F9C3, R1 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BB8E: A1 12 EXTU.B R1 ; cycles=3 +BB90: F1 F8 68 90 MOV:G.B R0, @(-H'0798,R1) ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high; cycles=7 +BB94: A1 08 ADD:Q.B #1, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; cycles=4 +BB96: 15 F9 C3 91 MOV:G.B R1, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; refs ram_F9C3 in on_chip_ram; cycles=7 +BB9A: 41 06 CMP:E #H'06, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high; cycles=2 +BB9C: 26 05 BNE loc_BBA3 ; cycles=3/7 nt/t +BB9E: 15 F9 C5 06 14 MOV:G.B #H'14, @H'F9C5 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BBA3: +BBA3: 15 F9 C1 06 05 MOV:G.B #H'05, @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=9 +BBA8: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +BBAA: 0A RTE ; cycles=13 + +loc_BBAB: +BBAB: 15 F9 C3 04 06 CMP:G.B #H'06, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high; refs ram_F9C3 in on_chip_ram; cycles=6 +BBB0: 36 02 BC BNE loc_BE6F ; cycles=3/7 nt/t +BBB3: 1D F8 68 80 MOV:G.W @H'F868, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F868 in on_chip_ram; cycles=6 +BBB7: 1D F8 60 90 MOV:G.W R0, @H'F860 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=6 +BBBB: 1D F8 6A 80 MOV:G.W @H'F86A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86A in on_chip_ram; cycles=6 +BBBF: 1D F8 62 90 MOV:G.W R0, @H'F862 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=6 +BBC3: 1D F8 6C 80 MOV:G.W @H'F86C, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86C in on_chip_ram; cycles=6 +BBC7: 1D F8 64 90 MOV:G.W R0, @H'F864 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=6 +BBCB: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BBCF: 15 FA A4 F7 BTST.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=6 +BBD3: 36 02 53 BNE loc_BE29 ; cycles=3/8 nt/t +BBD6: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; dataflow R0=H'5A; cycles=2 +BBD8: 15 F8 60 60 XOR.B @H'F860, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=7 +BBDC: 15 F8 61 60 XOR.B @H'F861, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F861 in on_chip_ram; cycles=7 +BBE0: 15 F8 62 60 XOR.B @H'F862, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=7 +BBE4: 15 F8 63 60 XOR.B @H'F863, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F863 in on_chip_ram; cycles=7 +BBE8: 15 F8 64 60 XOR.B @H'F864, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=7 +BBEC: 15 F8 65 70 CMP:G.B @H'F865, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F865 in on_chip_ram; cycles=7 +BBF0: 36 02 36 BNE loc_BE29 ; cycles=3/7 nt/t +BBF3: 15 FA A6 13 CLR.B @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BBF7: 15 F8 61 85 MOV:G.B @H'F861, R5 ; refs ram_F861 in on_chip_ram; cycles=6 +BBFB: A5 10 SWAP.B R5 ; cycles=3 +BBFD: 15 F8 62 85 MOV:G.B @H'F862, R5 ; refs ram_F862 in on_chip_ram; cycles=6 +BC01: 1E A6 27 BSR loc_622B ; cycles=14 +BC04: AD 84 MOV:G.W R5, R4 ; cycles=3 +BC06: AC 1A SHLL.W R4 ; cycles=3 +BC08: 15 F8 60 80 MOV:G.B @H'F860, R0 ; refs ram_F860 in on_chip_ram; cycles=7 +BC0C: 04 07 50 AND.B #H'07, R0 ; cycles=3 +BC0F: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BC13: 26 25 BNE loc_BC3A ; cycles=3/8 nt/t + +loc_BC15: +BC15: 15 FA A2 C7 BSET.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC19: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=6 +BC1D: 36 00 EB BNE loc_BD0B ; cycles=3/8 nt/t +BC20: 40 00 CMP:E #H'00, R0 ; cycles=2 +BC22: 27 45 BEQ loc_BC69 ; cycles=3/7 nt/t +BC24: 40 01 CMP:E #H'01, R0 ; cycles=2 +BC26: 37 00 AE BEQ loc_BCD7 ; cycles=3/7 nt/t +BC29: 40 02 CMP:E #H'02, R0 ; cycles=2 +BC2B: 37 00 D6 BEQ loc_BD04 ; cycles=3/8 nt/t +BC2E: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC30: 37 01 D2 BEQ loc_BE05 ; cycles=3/7 nt/t +BC33: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC37: 30 02 35 BRA loc_BE6F ; cycles=8 + +loc_BC3A: +BC3A: A0 F2 BTST.B #2, R0 ; cycles=2 +BC3C: 27 1E BEQ loc_BC5C ; cycles=3/7 nt/t +BC3E: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=7 +BC42: 36 01 E2 BNE loc_BE27 ; cycles=3/7 nt/t +BC45: 40 04 CMP:E #H'04, R0 ; cycles=2 +BC47: 37 00 C4 BEQ loc_BD0E ; cycles=3/8 nt/t +BC4A: 40 05 CMP:E #H'05, R0 ; cycles=2 +BC4C: 37 01 31 BEQ loc_BD80 ; cycles=3/7 nt/t +BC4F: 40 06 CMP:E #H'06, R0 ; cycles=2 +BC51: 37 01 87 BEQ loc_BDDB ; cycles=3/8 nt/t +BC54: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC56: 37 01 AC BEQ loc_BE05 ; cycles=3/7 nt/t +BC59: 30 02 13 BRA loc_BE6F ; cycles=8 + +loc_BC5C: +BC5C: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BC60: 37 02 0C BEQ loc_BE6F ; cycles=3/7 nt/t +BC63: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BC67: 20 AC BRA loc_BC15 ; cycles=8 + +loc_BC69: +BC69: AD 16 TST.W R5 ; cycles=3 +BC6B: 26 1E BNE loc_BC8B ; cycles=3/8 nt/t +BC6D: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC71: A0 10 SWAP.B R0 ; cycles=3 +BC73: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BC75: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC79: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC7D: 15 F8 64 06 80 MOV:G.B #H'80, @H'F864 ; refs ram_F864 in on_chip_ram; cycles=9 +BC82: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BC86: 1E 01 E7 BSR loc_BE70 ; cycles=13 +BC89: 20 25 BRA loc_BCB0 ; cycles=8 + +loc_BC8B: +BC8B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC8F: A0 10 SWAP.B R0 ; cycles=3 +BC91: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BC95: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC99: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC9D: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BCA1: FC C5 64 81 MOV:G.W @(-H'3A9C,R4), R1 ; cycles=6 +BCA5: A1 12 EXTU.B R1 ; cycles=3 +BCA7: 27 04 BEQ loc_BCAD ; cycles=3/8 nt/t +BCA9: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 + +loc_BCAD: +BCAD: 1E 01 C0 BSR loc_BE70 ; cycles=14 + +loc_BCB0: +BCB0: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCB5: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=6 +BCB9: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BCBD: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=6 +BCC1: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BCC5: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BCC9: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BCCD: 1E FD 56 BSR loc_BA26 ; cycles=14 +BCD0: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BCD4: 30 01 98 BRA loc_BE6F ; cycles=7 + +loc_BCD7: +BCD7: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCDC: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BCE0: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCE4: 15 F8 62 80 MOV:G.B @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BCE8: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCEC: FC E0 00 80 MOV:G.W @(-H'2000,R4), R0 ; cycles=7 +BCF0: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BCF4: A0 10 SWAP.B R0 ; cycles=3 +BCF6: 15 F8 53 90 MOV:G.B R0, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=7 +BCFA: 1E FD 29 BSR loc_BA26 ; cycles=13 +BCFD: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD01: 30 01 6B BRA loc_BE6F ; cycles=8 + +loc_BD04: +BD04: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BD08: 30 01 64 BRA loc_BE6F ; cycles=7 + +loc_BD0B: +BD0B: 30 01 61 BRA loc_BE6F ; cycles=8 + +loc_BD0E: +BD0E: AD 16 TST.W R5 ; cycles=3 +BD10: 26 19 BNE loc_BD2B ; cycles=3/7 nt/t +BD12: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=7 +BD16: A0 10 SWAP.B R0 ; cycles=3 +BD18: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BD1A: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=7 +BD1E: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=7 +BD22: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BD26: 1E 01 47 BSR loc_BE70 ; cycles=13 +BD29: 20 3C BRA loc_BD67 ; cycles=8 + +loc_BD2B: +BD2B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BD2F: A0 10 SWAP.B R0 ; cycles=3 +BD31: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BD35: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BD39: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BD3D: F4 C5 65 81 MOV:G.B @(-H'3A9B,R4), R1 ; cycles=6 +BD41: A1 12 EXTU.B R1 ; cycles=3 +BD43: 27 1F BEQ loc_BD64 ; cycles=3/8 nt/t +BD45: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 +BD49: 15 F7 6E F7 BTST.B #7, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +BD4D: 27 15 BEQ loc_BD64 ; cycles=3/8 nt/t +BD4F: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +BD51: 15 F7 6E 84 MOV:G.B @H'F76E, R4 ; refs ram_F76E in on_chip_ram; cycles=6 +BD55: A4 10 SWAP.B R4 ; cycles=3 +BD57: A1 84 MOV:G.B R1, R4 ; cycles=2 +BD59: 0C 0F FE 54 AND.W #H'0FFE, R4 ; cycles=4 +BD5D: A8 85 MOV:G.W R0, R5 ; cycles=3 +BD5F: 1E 02 7E BSR loc_BFE0 ; cycles=14 +BD62: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 + +loc_BD64: +BD64: 1E 01 09 BSR loc_BE70 ; cycles=13 + +loc_BD67: +BD67: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BD6B: 27 08 BEQ loc_BD75 ; cycles=3/8 nt/t +BD6D: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BD71: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BD75: +BD75: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BD79: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD7D: 30 00 EF BRA loc_BE6F ; cycles=8 + +loc_BD80: +BD80: 4D 00 6C CMP:I #H'006C, R5 ; cycles=3 +BD83: 27 3A BEQ loc_BDBF ; cycles=3/8 nt/t +BD85: 4D 00 6D CMP:I #H'006D, R5 ; cycles=3 +BD88: 27 35 BEQ loc_BDBF ; cycles=3/7 nt/t +BD8A: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD8D: 27 30 BEQ loc_BDBF ; cycles=3/8 nt/t +BD8F: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD92: 27 2B BEQ loc_BDBF ; cycles=3/7 nt/t +BD94: 15 F7 31 F7 BTST.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +BD98: 27 28 BEQ loc_BDC2 ; cycles=3/7 nt/t +BD9A: 4D 00 6B CMP:I #H'006B, R5 ; cycles=3 +BD9D: 27 16 BEQ loc_BDB5 ; cycles=3/8 nt/t +BD9F: 4D 00 96 CMP:I #H'0096, R5 ; cycles=3 +BDA2: 27 11 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDA4: 4D 00 97 CMP:I #H'0097, R5 ; cycles=3 +BDA7: 27 0C BEQ loc_BDB5 ; cycles=3/8 nt/t +BDA9: 4D 00 C6 CMP:I #H'00C6, R5 ; cycles=3 +BDAC: 27 07 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDAE: 4D 00 F8 CMP:I #H'00F8, R5 ; cycles=3 +BDB1: 27 02 BEQ loc_BDB5 ; cycles=3/8 nt/t +BDB3: 20 0D BRA loc_BDC2 ; cycles=8 + +loc_BDB5: +BDB5: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +BDB9: 15 F7 90 D7 BCLR.B #7, @H'F790 ; refs ram_F790 in on_chip_ram; cycles=8 +BDBD: 20 03 BRA loc_BDC2 ; cycles=8 + +loc_BDBF: +BDBF: 1E 00 AE BSR loc_BE70 ; cycles=14 + +loc_BDC2: +BDC2: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BDC6: 27 08 BEQ loc_BDD0 ; cycles=3/7 nt/t +BDC8: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 +BDCC: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 + +loc_BDD0: +BDD0: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BDD4: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BDD8: 30 00 94 BRA loc_BE6F ; cycles=7 + +loc_BDDB: +BDDB: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BDDF: A0 10 SWAP.B R0 ; cycles=3 +BDE1: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BDE5: FC E4 00 90 MOV:G.W R0, @(-H'1C00,R4) ; cycles=6 +BDE9: F5 EC 00 C6 BSET.B #6, @(-H'1400,R5) ; cycles=8 +BDED: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BDF1: 27 08 BEQ loc_BDFB ; cycles=3/8 nt/t +BDF3: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BDF7: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BDFB: +BDFB: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BDFF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE03: 20 6A BRA loc_BE6F ; cycles=8 + +loc_BE05: +BE05: 1D F8 58 80 MOV:G.W @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=6 +BE09: 1D F8 50 90 MOV:G.W R0, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=6 +BE0D: 1D F8 5A 80 MOV:G.W @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=6 +BE11: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BE15: 1D F8 5C 80 MOV:G.W @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=6 +BE19: 1D F8 54 90 MOV:G.W R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BE1D: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE22: 1E FC 01 BSR loc_BA26 ; cycles=13 +BE25: 20 48 BRA loc_BE6F ; cycles=8 + +loc_BE27: +BE27: 20 46 BRA loc_BE6F ; cycles=8 + +loc_BE29: +BE29: 15 FA A4 D7 BCLR.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=8 +BE2D: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +BE31: 27 3A BEQ loc_BE6D ; cycles=3/8 nt/t +BE33: 15 FA A6 08 ADD:Q.B #1, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BE37: 15 FA A6 04 02 CMP:G.B #H'02, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=6 +BE3C: 25 0F BCS loc_BE4D ; cycles=3/7 nt/t +BE3E: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE43: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BE47: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE4B: 20 20 BRA loc_BE6D ; cycles=8 + +loc_BE4D: +BE4D: 15 F8 50 06 07 MOV:G.B #H'07, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BE52: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BE56: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BE5A: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BE5E: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BE62: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=7 +BE66: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BE6A: 1E FB B9 BSR loc_BA26 ; cycles=13 + +loc_BE6D: +BE6D: 20 00 BRA loc_BE6F ; cycles=8 + +loc_BE6F: +BE6F: 19 RTS ; cycles=13 + +loc_BE70: +BE70: 15 F9 B9 83 MOV:G.B @H'F9B9, R3 ; refs ram_F9B9 in on_chip_ram; cycles=7 +BE74: A3 12 EXTU.B R3 ; cycles=3 +BE76: AB 1A SHLL.W R3 ; cycles=3 +BE78: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +BE7C: A1 12 EXTU.B R1 ; cycles=3 +BE7E: A9 1A SHLL.W R1 ; cycles=3 + +loc_BE80: +BE80: A3 71 CMP:G.B R3, R1 ; cycles=2 +BE82: 27 0D BEQ loc_BE91 ; cycles=3/7 nt/t +BE84: FB F9 70 75 CMP:G.W @(-H'0690,R3), R5 ; cycles=7 +BE88: 27 13 BEQ loc_BE9D ; cycles=3/7 nt/t +BE8A: A3 09 ADD:Q.B #2, R3 ; cycles=4 +BE8C: 04 3F 53 AND.B #H'3F, R3 ; cycles=3 +BE8F: 20 EF BRA loc_BE80 ; cycles=8 + +loc_BE91: +BE91: F9 F9 70 95 MOV:G.W R5, @(-H'0690,R1) ; cycles=6 +BE95: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +BE99: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_BE9D: +BE9D: 19 RTS ; cycles=13 + +loc_BE9E: +BE9E: 15 FA A5 80 MOV:G.B @H'FAA5, R0 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BEA2: 04 80 50 AND.B #H'80, R0 ; cycles=3 +BEA5: 15 FA A3 50 AND.B @H'FAA3, R0 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEA9: 15 FA A3 90 MOV:G.B R0, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEAD: 26 06 BNE loc_BEB5 ; cycles=3/8 nt/t +BEAF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BEB3: 20 33 BRA loc_BEE8 ; cycles=8 + +loc_BEB5: +BEB5: 1D F9 C6 16 TST.W @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=6 +BEB9: 26 2D BNE loc_BEE8 ; cycles=3/8 nt/t +BEBB: 15 F9 C8 16 TST.B @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=6 +BEBF: 27 23 BEQ loc_BEE4 ; cycles=3/8 nt/t +BEC1: 15 F9 C8 0C ADD:Q.B #-1, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=8 +BEC5: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=9 +BECB: 15 FA A3 F7 BTST.B #7, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BECF: 27 17 BEQ loc_BEE8 ; cycles=3/8 nt/t +BED1: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BED5: 1E FB 4E BSR loc_BA26 ; cycles=14 +BED8: 20 0E BRA loc_BEE8 ; cycles=7 + +loc_BEE4: +BEE4: 15 F9 C5 13 CLR.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BEE8: +BEE8: 19 RTS ; cycles=12 + +vec_frt1_ocia_BEEA: +BEEA: 15 FE 91 D5 BCLR.B #5, @FRT1_TCSR ; clear OCFA (bit 5) of FRT1_TCSR; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; cycles=9 +BEEE: 15 F9 C0 16 TST.B @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=7 +BEF2: 27 04 BEQ loc_BEF8 ; cycles=3/7 nt/t +BEF4: 15 F9 C0 0C ADD:Q.B #-1, @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BEF8: +BEF8: 15 F9 C1 16 TST.B @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=7 +BEFC: 27 04 BEQ loc_BF02 ; cycles=3/7 nt/t +BEFE: 15 F9 C1 0C ADD:Q.B #-1, @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=9 + +loc_BF02: +BF02: 1D F9 C6 16 TST.W @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=7 +BF06: 27 04 BEQ loc_BF0C ; cycles=3/7 nt/t +BF08: 1D F9 C6 0C ADD:Q.W #-1, @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=9 + +loc_BF0C: +BF0C: 15 F6 F6 F7 BTST.B #7, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=7 +BF10: 27 10 BEQ loc_BF22 ; cycles=3/7 nt/t +BF12: 1D F6 F4 16 TST.W @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=7 +BF16: 26 06 BNE loc_BF1E ; cycles=3/7 nt/t +BF18: 15 F6 F6 C5 BSET.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +BF1C: 20 04 BRA loc_BF22 ; cycles=7 + +loc_BF1E: +BF1E: 1D F6 F4 0C ADD:Q.W #-1, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_BF22: +BF22: 0A RTE ; cycles=13 + +vec_frt2_ocia_BF23: +BF23: 15 FE A1 D5 BCLR.B #5, @FRT2_TCSR ; clear OCFA (bit 5) of FRT2_TCSR; cycles=8 +BF27: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=6 +BF2B: 27 04 BEQ loc_BF31 ; cycles=3/8 nt/t +BF2D: 15 F9 C4 0C ADD:Q.B #-1, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=8 + +loc_BF31: +BF31: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +BF35: 27 04 BEQ loc_BF3B ; cycles=3/8 nt/t +BF37: 15 F9 C5 0C ADD:Q.B #-1, @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=8 + +loc_BF3B: +BF3B: 15 F7 24 16 TST.B @H'F724 ; refs ram_F724 in on_chip_ram; cycles=6 +BF3F: 27 06 BEQ loc_BF47 ; cycles=3/8 nt/t +BF41: 15 F7 24 0C ADD:Q.B #-1, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=8 +BF45: 20 09 BRA loc_BF50 ; cycles=8 + +loc_BF47: +BF47: 15 F7 24 06 03 MOV:G.B #H'03, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=9 +BF4C: 15 F7 23 15 NOT.B @H'F723 ; refs ram_F723 in on_chip_ram; cycles=9 + +loc_BF50: +BF50: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +BF54: 27 17 BEQ loc_BF6D ; cycles=3/7 nt/t +BF56: 15 FB 02 16 TST.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=7 +BF5A: 27 06 BEQ loc_BF62 ; cycles=3/7 nt/t +BF5C: 15 FB 02 0C ADD:Q.B #-1, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +BF60: 20 0B BRA loc_BF6D ; cycles=7 + +loc_BF62: +BF62: 15 FB 03 D7 BCLR.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +BF66: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +BF68: 1E 89 84 BSR loc_48EF ; cycles=13 +BF6B: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 + +loc_BF6D: +BF6D: 15 F7 6C 16 TST.B @H'F76C ; refs ram_F76C in on_chip_ram; cycles=6 +BF71: 27 04 BEQ loc_BF77 ; cycles=3/8 nt/t +BF73: 15 F7 6C 0C ADD:Q.B #-1, @H'F76C ; refs ram_F76C in on_chip_ram; cycles=8 + +loc_BF77: +BF77: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BF7B: 27 04 BEQ loc_BF81 ; cycles=3/8 nt/t +BF7D: 15 F8 40 0C ADD:Q.B #-1, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=8 + +loc_BF81: +BF81: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=6 +BF85: 27 1C BEQ loc_BFA3 ; cycles=3/8 nt/t +BF87: 15 F7 26 0C ADD:Q.B #-1, @H'F726 ; refs ram_F726 in on_chip_ram; cycles=8 +BF8B: 26 16 BNE loc_BFA3 ; cycles=3/8 nt/t +BF8D: 15 F7 13 D6 BCLR.B #6, @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +BF91: 26 10 BNE loc_BFA3 ; cycles=3/8 nt/t +BF93: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF97: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9B: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9F: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 + +loc_BFA3: +BFA3: 15 F7 97 16 TST.B @H'F797 ; refs ram_F797 in on_chip_ram; cycles=6 +BFA7: 27 0A BEQ loc_BFB3 ; cycles=3/8 nt/t +BFA9: 15 F7 97 0C ADD:Q.B #-1, @H'F797 ; refs ram_F797 in on_chip_ram; cycles=8 +BFAD: 26 04 BNE loc_BFB3 ; cycles=3/8 nt/t +BFAF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFB3: +BFB3: 15 F7 98 16 TST.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=6 +BFB7: 27 0A BEQ loc_BFC3 ; cycles=3/8 nt/t +BFB9: 15 F7 98 0C ADD:Q.B #-1, @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +BFBD: 26 04 BNE loc_BFC3 ; cycles=3/8 nt/t +BFBF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFC3: +BFC3: 0A RTE ; cycles=14 + +vec_interval_timer_BFC4: +BFC4: 15 FE EC F7 BTST.B #7, @WDT_TCSR_R ; refs WDT_TCSR_R in register_field; cycles=7 +BFC8: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 +BFCE: 15 F7 94 08 ADD:Q.B #1, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=9 +BFD2: 15 F7 94 04 0A CMP:G.B #H'0A, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=7 +BFD7: 26 06 BNE loc_BFDF ; cycles=3/8 nt/t +BFD9: 1D FE EC 07 A5 7F MOV:G.W #H'A57F, @WDT_TCSR_R ; WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096); cycles=9 + +loc_BFDF: +BFDF: 0A RTE ; cycles=14 + +loc_BFE0: +BFE0: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 + +loc_BFE5: +BFE5: AD 82 MOV:G.W R5, R2 ; cycles=3 +BFE7: 0E 27 BSR loc_C010 ; cycles=14 +BFE9: 0E 4E BSR loc_C039 ; cycles=14 +BFEB: AA 75 CMP:G.W R2, R5 ; cycles=3 +BFED: 27 0E BEQ loc_BFFD ; cycles=3/8 nt/t +BFEF: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BFF3: 27 04 BEQ loc_BFF9 ; cycles=3/8 nt/t +BFF5: AA 85 MOV:G.W R2, R5 ; cycles=3 +BFF7: 20 EC BRA loc_BFE5 ; cycles=8 + +loc_BFF9: +BFF9: 15 F8 41 C7 BSET.B #7, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_BFFD: +BFFD: 19 RTS ; cycles=13 + +loc_BFFE: +BFFE: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 +C003: 0E 34 BSR loc_C039 ; cycles=14 +C005: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C009: 26 04 BNE loc_C00F ; cycles=3/8 nt/t +C00B: 15 F8 41 C6 BSET.B #6, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_C00F: +C00F: 19 RTS ; cycles=13 + +loc_C010: +C010: 0E 58 BSR loc_C06A ; cycles=13 + +loc_C012: +C012: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=7 +C016: 27 20 BEQ loc_C038 ; cycles=3/7 nt/t +C018: 1E 01 06 BSR loc_C121 ; cycles=13 +C01B: A3 80 MOV:G.B R3, R0 ; cycles=2 +C01D: 0E 6C BSR loc_C08B ; cycles=14 +C01F: 27 F1 BEQ loc_C012 ; cycles=3/8 nt/t +C021: A4 80 MOV:G.B R4, R0 ; cycles=2 +C023: 0E 66 BSR loc_C08B ; cycles=14 +C025: 27 EB BEQ loc_C012 ; cycles=3/8 nt/t +C027: AD 80 MOV:G.W R5, R0 ; cycles=3 +C029: A0 10 SWAP.B R0 ; cycles=3 +C02B: 0E 5E BSR loc_C08B ; cycles=14 +C02D: 27 E3 BEQ loc_C012 ; cycles=3/8 nt/t +C02F: A5 80 MOV:G.B R5, R0 ; cycles=2 +C031: 0E 58 BSR loc_C08B ; cycles=14 +C033: 27 DD BEQ loc_C012 ; cycles=3/8 nt/t +C035: 1E 01 0A BSR loc_C142 ; cycles=14 + +loc_C038: +C038: 19 RTS ; cycles=12 + +loc_C039: +C039: 0E 2F BSR loc_C06A ; cycles=14 + +loc_C03B: +C03B: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C03F: 27 28 BEQ loc_C069 ; cycles=3/8 nt/t +C041: 1E 00 DD BSR loc_C121 ; cycles=14 +C044: A3 80 MOV:G.B R3, R0 ; cycles=2 +C046: 0E 43 BSR loc_C08B ; cycles=13 +C048: 27 F1 BEQ loc_C03B ; cycles=3/7 nt/t +C04A: A4 80 MOV:G.B R4, R0 ; cycles=2 +C04C: 0E 3D BSR loc_C08B ; cycles=13 +C04E: 27 EB BEQ loc_C03B ; cycles=3/7 nt/t +C050: 1E 00 CE BSR loc_C121 ; cycles=13 +C053: A3 80 MOV:G.B R3, R0 ; cycles=2 +C055: A0 C0 BSET.B #0, R0 ; cycles=2 +C057: 0E 32 BSR loc_C08B ; cycles=14 +C059: 27 E0 BEQ loc_C03B ; cycles=3/8 nt/t +C05B: 1E 00 7D BSR loc_C0DB ; cycles=14 +C05E: A5 10 SWAP.B R5 ; cycles=3 +C060: 1E 00 A9 BSR loc_C10C ; cycles=13 +C063: 1E 00 75 BSR loc_C0DB ; cycles=14 +C066: 1E 00 D9 BSR loc_C142 ; cycles=13 + +loc_C069: +C069: 19 RTS ; cycles=13 + +loc_C06A: +C06A: 0C 0F FF 54 AND.W #H'0FFF, R4 ; cycles=4 +C06E: 4C 08 00 CMP:I #H'0800, R4 ; cycles=3 +C071: 24 0B BCC loc_C07E ; cycles=3/8 nt/t +C073: AC 83 MOV:G.W R4, R3 ; cycles=3 +C075: A3 10 SWAP.B R3 ; cycles=3 +C077: A3 1A SHLL.B R3 ; cycles=2 +C079: 04 A0 43 OR.B #H'A0, R3 ; cycles=3 +C07C: 20 0C BRA loc_C08A ; cycles=7 + +loc_C07E: +C07E: AC 83 MOV:G.W R4, R3 ; cycles=3 +C080: A3 10 SWAP.B R3 ; cycles=3 +C082: A3 1A SHLL.B R3 ; cycles=2 +C084: 04 0E 53 AND.B #H'0E, R3 ; cycles=3 +C087: 04 E0 43 OR.B #H'E0, R3 ; cycles=3 + +loc_C08A: +C08A: 19 RTS ; cycles=12 + +loc_C08B: +C08B: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C08E: +C08E: A0 1A SHLL.B R0 ; cycles=2 +C090: 24 06 BCC loc_C098 ; cycles=3/7 nt/t +C092: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C096: 20 04 BRA loc_C09C ; cycles=7 + +loc_C098: +C098: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 + +loc_C09C: +C09C: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A0: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A8: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0AC: 01 B9 DF SCB/F R1, loc_C08E ; cycles=3/4/8 false/-1/t +C0AF: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0B4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0B8: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0BC: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=7 +C0C0: 27 0D BEQ loc_C0CF ; cycles=3/7 nt/t +C0C2: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0C6: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0CB: 50 00 MOV:E.B #H'00, R0 ; dataflow R0=H'00; cycles=2 +C0CD: 20 0B BRA loc_C0DA ; cycles=8 + +loc_C0CF: +C0CF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0D3: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0D8: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_C0DA: +C0DA: 19 RTS ; cycles=12 + +loc_C0DB: +C0DB: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0E0: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C0E3: +C0E3: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0E7: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0EB: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=6 +C0EF: 27 04 BEQ loc_C0F5 ; cycles=3/8 nt/t +C0F1: A5 49 BSET.B R1, R5 ; cycles=2 +C0F3: 20 02 BRA loc_C0F7 ; cycles=8 + +loc_C0F5: +C0F5: A5 59 BCLR.B R1, R5 ; cycles=2 + +loc_C0F7: +C0F7: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FB: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C103: 01 B9 DD SCB/F R1, loc_C0E3 ; cycles=3/4/9 false/-1/t +C106: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C10B: 19 RTS ; cycles=13 + +loc_C10C: +C10C: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C110: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C114: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C118: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C11C: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C120: 19 RTS ; cycles=12 + +loc_C121: +C121: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=8 +C125: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C129: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C12D: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C131: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=8 +C135: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C139: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C13D: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C141: 19 RTS ; cycles=13 + +loc_C142: +C142: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C146: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14E: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C152: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C156: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15E: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C162: 19 RTS ; cycles=12 diff --git a/build/rom_others_menu.json b/build/rom_others_menu.json new file mode 100644 index 0000000..06b7ee9 --- /dev/null +++ b/build/rom_others_menu.json @@ -0,0 +1,219643 @@ +{ + "vectors": [ + { + "address": 0, + "name": "reset", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 4, + "name": "invalid_instruction", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 6, + "name": "zero_divide", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 8, + "name": "trap_vs", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 16, + "name": "address_error", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 18, + "name": "trace", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 22, + "name": "nmi", + "target": 17299, + "target_label": "vec_nmi_4393" + }, + { + "address": 32, + "name": "trapa_0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 34, + "name": "trapa_1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 36, + "name": "trapa_2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 38, + "name": "trapa_3", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 40, + "name": "trapa_4", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 42, + "name": "trapa_5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 44, + "name": "trapa_6", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 46, + "name": "trapa_7", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 48, + "name": "trapa_8", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 50, + "name": "trapa_9", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 52, + "name": "trapa_a", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 54, + "name": "trapa_b", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 56, + "name": "trapa_c", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 58, + "name": "trapa_d", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 60, + "name": "trapa_e", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 62, + "name": "trapa_f", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 64, + "name": "irq0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 66, + "name": "interval_timer", + "target": 49092, + "target_label": "vec_interval_timer_BFC4" + }, + { + "address": 72, + "name": "irq1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 80, + "name": "irq2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 82, + "name": "irq3", + "target": 15408, + "target_label": "vec_irq3_3C30" + }, + { + "address": 88, + "name": "irq4", + "target": 15047, + "target_label": "vec_irq4_3AC7" + }, + { + "address": 90, + "name": "irq5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 98, + "name": "frt1_ocia", + "target": 48874, + "target_label": "vec_frt1_ocia_BEEA" + }, + { + "address": 106, + "name": "frt2_ocia", + "target": 48931, + "target_label": "vec_frt2_ocia_BF23" + }, + { + "address": 128, + "name": "sci1_eri", + "target": 47959, + "target_label": "vec_sci1_eri_BB57" + }, + { + "address": 130, + "name": "sci1_rxi", + "target": 47975, + "target_label": "vec_sci1_rxi_BB67" + }, + { + "address": 132, + "name": "sci1_txi", + "target": 47748, + "target_label": "vec_sci1_txi_BA84" + }, + { + "address": 144, + "name": "ad_adi", + "target": 15769, + "target_label": "vec_ad_adi_3D99" + } + ], + "dtc_vectors": [], + "memory_regions": [ + { + "name": "exception_vectors", + "start": 0, + "end": 159, + "kind": "vectors", + "manual": "section 2 address space" + }, + { + "name": "dtc_vectors", + "start": 160, + "end": 255, + "kind": "dtc_vectors", + "manual": "section 2 address space" + }, + { + "name": "program_or_external", + "start": 256, + "end": 63103, + "kind": "program", + "manual": "section 2/17 mode-dependent ROM or external space" + }, + { + "name": "on_chip_ram", + "start": 63104, + "end": 65151, + "kind": "ram", + "manual": "section 16 RAM" + }, + { + "name": "register_field", + "start": 65152, + "end": 65535, + "kind": "registers", + "manual": "appendix B register map" + } + ], + "data_candidates": { + "strings": [ + { + "address": 10834, + "length": 11, + "text": "78785=5=5=,", + "terminated": false + }, + { + "address": 11194, + "length": 7, + "text": "8*8B8Z8", + "terminated": false + }, + { + "address": 16818, + "length": 32, + "text": "01020304050607080910111213141516", + "terminated": false + }, + { + "address": 22436, + "length": 7, + "text": "Z [ ", + "terminated": false + }, + { + "address": 22570, + "length": 6, + "text": "Z [ ", + "terminated": false + }, + { + "address": 23381, + "length": 10, + "text": "0123456789", + "terminated": true + }, + { + "address": 23392, + "length": 40, + "text": " 0 1 2 3 4 5 6 7 8 910111213141516171819", + "terminated": false + }, + { + "address": 24822, + "length": 16, + "text": "0123456789ABCDEF", + "terminated": false + }, + { + "address": 25356, + "length": 9, + "text": "m*mDm^mxm", + "terminated": false + }, + { + "address": 25406, + "length": 6, + "text": "vpwhx6", + "terminated": true + }, + { + "address": 25559, + "length": 10, + "text": "OPERATION ", + "terminated": false + }, + { + "address": 25589, + "length": 10, + "text": " PAINT ", + "terminated": false + }, + { + "address": 25616, + "length": 18, + "text": " ADV~Xd", + "terminated": false + }, + { + "address": 25667, + "length": 10, + "text": "OPERATION ", + "terminated": false + }, + { + "address": 25697, + "length": 10, + "text": "IRIS/M.BLK", + "terminated": false + }, + { + "address": 25744, + "length": 10, + "text": "OPERATION ", + "terminated": false + }, + { + "address": 25774, + "length": 10, + "text": " LOCK ", + "terminated": false + }, + { + "address": 25903, + "length": 19, + "text": " DYNA LATITUDE Xe/", + "terminated": false + }, + { + "address": 25937, + "length": 18, + "text": "HIGH LOW~XeP", + "terminated": false + }, + { + "address": 25976, + "length": 18, + "text": "STD OFF~Xew", + "terminated": false + }, + { + "address": 26057, + "length": 18, + "text": " BLACK STR Xe", + "terminated": false + }, + { + "address": 26180, + "length": 19, + "text": " BLACK STR XfD", + "terminated": false + }, + { + "address": 26213, + "length": 19, + "text": " STRETCH LEVEL Xfe", + "terminated": false + }, + { + "address": 26243, + "length": 18, + "text": "POINT1 POINT2Xf", + "terminated": false + }, + { + "address": 26374, + "length": 18, + "text": " BLACK STR Xg", + "terminated": false + }, + { + "address": 26407, + "length": 19, + "text": " COMPRESS LEVEL Xg'", + "terminated": false + }, + { + "address": 26437, + "length": 19, + "text": "POINT1 POINT2XgE", + "terminated": false + }, + { + "address": 26592, + "length": 18, + "text": " TLCS Xg", + "terminated": false + }, + { + "address": 26626, + "length": 17, + "text": "ON OFF~Xh", + "terminated": false + }, + { + "address": 26655, + "length": 18, + "text": " AGC GAIN AE Xh", + "terminated": false + }, + { + "address": 26730, + "length": 136, + "text": " CL F16 F11 F8 F5.6F4 F2.8F2 F1.8F1.4 OP DPR HYP HIGHMID LOW 36dB30dB24dB18dB12dB 9dB 6dB 3dB 0dB-3dB", + "terminated": true + }, + { + "address": 26939, + "length": 19, + "text": " AUTO FUNC Xi;", + "terminated": false + }, + { + "address": 26972, + "length": 19, + "text": " ATW Xi\\", + "terminated": false + }, + { + "address": 27012, + "length": 17, + "text": "ON OFF~Xi", + "terminated": false + }, + { + "address": 27215, + "length": 19, + "text": " AUTO FUNC XjO", + "terminated": false + }, + { + "address": 27249, + "length": 18, + "text": "STD SPOT.L~Xjp", + "terminated": false + }, + { + "address": 27278, + "length": 18, + "text": " A.IRIS MODE Xj", + "terminated": false + }, + { + "address": 27309, + "length": 17, + "text": "AI BACK.L~Xj", + "terminated": false + }, + { + "address": 27453, + "length": 19, + "text": " AUTO FUNC Xk=", + "terminated": false + }, + { + "address": 27486, + "length": 19, + "text": " AUTO FOCUS Xk^", + "terminated": false + }, + { + "address": 27526, + "length": 17, + "text": "ON OFF~Xk", + "terminated": false + }, + { + "address": 27631, + "length": 18, + "text": " DIAG Xk", + "terminated": false + }, + { + "address": 27670, + "length": 18, + "text": " DIAG DATA Xl", + "terminated": false + }, + { + "address": 27701, + "length": 18, + "text": "RESET REQ~Xl4", + "terminated": false + }, + { + "address": 28224, + "length": 19, + "text": " DIAG Xn@", + "terminated": false + }, + { + "address": 28550, + "length": 16, + "text": " OTHERS Xo", + "terminated": false + }, + { + "address": 28590, + "length": 16, + "text": " SHUTTER ", + "terminated": false + }, + { + "address": 28621, + "length": 15, + "text": "EVS ECS~", + "terminated": false + }, + { + "address": 28754, + "length": 14, + "text": " SET RCP ", + "terminated": false + }, + { + "address": 28783, + "length": 14, + "text": " MASTER ", + "terminated": false + }, + { + "address": 28831, + "length": 16, + "text": " OTHERS ", + "terminated": false + }, + { + "address": 28864, + "length": 15, + "text": " COPY TO SLAVES", + "terminated": false + }, + { + "address": 28963, + "length": 19, + "text": " OTHERS Xq#", + "terminated": false + }, + { + "address": 28996, + "length": 17, + "text": " CAM ID SET~X", + "terminated": false + }, + { + "address": 29129, + "length": 18, + "text": " OTHERS Xq", + "terminated": false + }, + { + "address": 29177, + "length": 18, + "text": " CAM ID IND Xq", + "terminated": false + }, + { + "address": 29203, + "length": 18, + "text": " TITLE IND Xr", + "terminated": false + }, + { + "address": 29234, + "length": 18, + "text": "ON OFF~Xr1", + "terminated": false + }, + { + "address": 29349, + "length": 18, + "text": " OTHERS Xr", + "terminated": false + }, + { + "address": 29383, + "length": 17, + "text": "CAM BARS~Xr", + "terminated": false + }, + { + "address": 29412, + "length": 18, + "text": " CLOCK IND Xr", + "terminated": false + }, + { + "address": 29442, + "length": 18, + "text": " OFF~Xs", + "terminated": false + }, + { + "address": 29545, + "length": 19, + "text": " OTHERS Xsi", + "terminated": false + }, + { + "address": 29587, + "length": 18, + "text": " CENTER MARKER Xs", + "terminated": false + }, + { + "address": 29618, + "length": 17, + "text": "ON OFF~Xs", + "terminated": false + }, + { + "address": 29733, + "length": 19, + "text": " OTHERS Xt%", + "terminated": false + }, + { + "address": 29767, + "length": 18, + "text": "80% 90%~XtF", + "terminated": false + }, + { + "address": 29796, + "length": 19, + "text": " SAFETY ZONE Xtd", + "terminated": false + }, + { + "address": 29826, + "length": 18, + "text": " OFF~Xt", + "terminated": false + }, + { + "address": 30011, + "length": 19, + "text": " OTHERS Xu;", + "terminated": false + }, + { + "address": 30045, + "length": 18, + "text": "ON TONE OFF~Xu\\", + "terminated": false + }, + { + "address": 30074, + "length": 19, + "text": " BARS TYPE Xuz", + "terminated": false + }, + { + "address": 30116, + "length": 18, + "text": " SMPTE Xu", + "terminated": false + }, + { + "address": 30140, + "length": 18, + "text": " SPLIT Xu", + "terminated": false + }, + { + "address": 30176, + "length": 18, + "text": " FULLFIELD 75% Xu", + "terminated": false + }, + { + "address": 30199, + "length": 18, + "text": " EBU 75% Xu", + "terminated": false + }, + { + "address": 30234, + "length": 18, + "text": " FULLFIELD100% Xv", + "terminated": false + }, + { + "address": 30257, + "length": 20, + "text": " EBU 100% Xv1 ", + "terminated": false + }, + { + "address": 30280, + "length": 20, + "text": " SNG XvH ", + "terminated": true + }, + { + "address": 30362, + "length": 18, + "text": " OTHERS Xv", + "terminated": false + }, + { + "address": 30404, + "length": 18, + "text": " SCREEN MODE Xv", + "terminated": false + }, + { + "address": 30484, + "length": 17, + "text": "4:3 16:9~Xw", + "terminated": false + }, + { + "address": 30506, + "length": 20, + "text": " 16:9 Xw* ", + "terminated": false + }, + { + "address": 30529, + "length": 19, + "text": " 4:3 XwA", + "terminated": false + }, + { + "address": 30666, + "length": 18, + "text": " OTHERS Xw", + "terminated": false + }, + { + "address": 30708, + "length": 18, + "text": "COMM LINK ITEM-1Xw", + "terminated": false + }, + { + "address": 30739, + "length": 17, + "text": "GAIN SHUTTER~Xx", + "terminated": false + }, + { + "address": 30901, + "length": 18, + "text": " OTHERS Xx", + "terminated": false + }, + { + "address": 30935, + "length": 17, + "text": "WHITE BLACK~Xx", + "terminated": false + }, + { + "address": 30964, + "length": 18, + "text": "COMM LINK ITEM-2Xx", + "terminated": false + }, + { + "address": 31006, + "length": 17, + "text": "FLARE Xy", + "terminated": false + }, + { + "address": 33180, + "length": 17, + "text": " SHADING X", + "terminated": false + }, + { + "address": 33213, + "length": 17, + "text": " WHITE~X", + "terminated": false + }, + { + "address": 33243, + "length": 17, + "text": "SHADING AUTO SETX", + "terminated": false + }, + { + "address": 33273, + "length": 17, + "text": " BLACK~X", + "terminated": false + }, + { + "address": 33361, + "length": 17, + "text": " SHADING X", + "terminated": false + }, + { + "address": 33394, + "length": 17, + "text": " WHITE V SAW X", + "terminated": false + }, + { + "address": 33424, + "length": 17, + "text": " RED GREEN BLUE X", + "terminated": false + }, + { + "address": 33545, + "length": 17, + "text": " SHADING X", + "terminated": false + }, + { + "address": 33578, + "length": 17, + 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+ { + "from": 17690, + "from_label": "loc_451A", + "to": 6709, + "to_label": "loc_1A35", + "call_site": 17756 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 6812, + "to_label": "loc_1A9C", + "call_site": 17768 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 6884, + "to_label": "loc_1AE4", + "call_site": 17780 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 6923, + "to_label": "loc_1B0B", + "call_site": 17792 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 17845, + "to_label": "loc_45B5", + "call_site": 17749 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 18682, + "to_label": "loc_48FA", + "call_site": 17806 + }, + { + "from": 18671, + "from_label": "loc_48EF", + "to": 18682, + "to_label": "loc_48FA", + "call_site": 18679 + }, + { + "from": 18682, + "from_label": "loc_48FA", + "to": 15956, + "to_label": "loc_3E54", + "call_site": 18726 + }, + { + "from": 21760, + "from_label": "loc_5500", + "to": 15956, + "to_label": "loc_3E54", + "call_site": 21965 + }, + { + "from": 21760, + "from_label": "loc_5500", + "to": 49120, + "to_label": "loc_BFE0", + "call_site": 21813 + }, + { + "from": 22890, + "from_label": "loc_596A", + "to": 16076, + "to_label": "loc_3ECC", + "call_site": 22929 + }, + { + "from": 47858, + "from_label": "loc_BAF2", + "to": 25094, + "to_label": "loc_6206", + "call_site": 47886 + }, + { + "from": 47858, + "from_label": "loc_BAF2", + "to": 47654, + "to_label": "loc_BA26", + "call_site": 47939 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 25131, + "to_label": "loc_622B", + "call_site": 48129 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 47654, + "to_label": "loc_BA26", + "call_site": 48378 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 48752, + "to_label": "loc_BE70", + "call_site": 48262 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 49120, + "to_label": "loc_BFE0", + "call_site": 48479 + }, + { + "from": 48798, + "from_label": "loc_BE9E", + "to": 47654, + "to_label": "loc_BA26", + "call_site": 48853 + }, + { + "from": 48931, + "from_label": "vec_frt2_ocia_BF23", + "to": 18671, + "to_label": "loc_48EF", + "call_site": 49000 + }, + { + "from": 49120, + "from_label": "loc_BFE0", + "to": 49168, + "to_label": "loc_C010", + "call_site": 49127 + }, + { + "from": 49120, + "from_label": "loc_BFE0", + "to": 49209, + "to_label": "loc_C039", + "call_site": 49129 + }, + { + "from": 49150, + "from_label": "loc_BFFE", + "to": 49209, + "to_label": "loc_C039", + "call_site": 49155 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49258, + "to_label": "loc_C06A", + "call_site": 49168 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49291, + "to_label": "loc_C08B", + "call_site": 49181 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49441, + "to_label": "loc_C121", + "call_site": 49176 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49474, + "to_label": "loc_C142", + "call_site": 49205 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49258, + "to_label": "loc_C06A", + "call_site": 49209 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49291, + "to_label": "loc_C08B", + "call_site": 49222 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49371, + "to_label": "loc_C0DB", + "call_site": 49243 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49420, + "to_label": "loc_C10C", + "call_site": 49248 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49441, + "to_label": "loc_C121", + "call_site": 49217 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49474, + "to_label": "loc_C142", + "call_site": 49254 + } + ] + }, + "timing_summary": { + "blocks": [], + "loops": [] + }, + "sci": { + "clock_hz": null, + "formulas": { + "async": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))" + }, + "manual_references": [ + "Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source", + "Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source", + "Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator", + "Manual/0900766b802125d0.md:16303 asynchronous BRR formula", + "Manual/0900766b802125d0.md:16379 synchronous BRR formula", + "Manual/0900766b802125d0.md:16410 SCI clock source selection tables" + ], + "channels": { + "SCI1": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ], + "configurations": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "SCI2": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "configurations": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + } + } + }, + "sci_protocol": { + "manual_references": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "channels": { + "SCI1": { + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "SCI2": { + "events": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ] + } + }, + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "serial_reconstruction": { + "kind": "serial_reconstruction", + "candidates": [ + { + "id": "sci1_tx_frame_f858_len6_candidate", + "kind": "candidate_sci1_tx_frame", + "channel": "SCI1", + "frame_length": 6, + "buffer_start": 63576, + "buffer_start_hex": "H'F858", + "buffer_end": 63581, + "buffer_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "tx_index_address": 63938, + "tx_index_address_hex": "H'F9C2", + "tdr_address": 65243, + "tdr_address_hex": "H'FEDB", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "roles": [ + { + "name": "tx_frame", + "address": 63576, + "address_hex": "H'F858", + "end_address": 63581, + "end_address_hex": "H'F85D", + "summary": "evidence-supported candidate SCI1 TX frame buffer" + }, + { + "name": "tx_checksum", + "address": 63581, + "address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "summary": "evidence-supported candidate SCI1 TX XOR checksum byte" + }, + { + "name": "tx_index", + "address": 63938, + "address_hex": "H'F9C2", + "summary": "evidence-supported candidate SCI1 TX frame index" + } + ], + "tx_path": { + "kind": "interrupt_driven_txi", + "initial_tdr_write_address": 47730, + "initial_tdr_write_address_hex": "H'BA72", + "txi_indexed_tdr_write_address": 47797, + "txi_indexed_tdr_write_address_hex": "H'BAB5", + "summary": "initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted", + "tdre_caveat": "TDRE reassertion is hardware/emulator timing context; static evidence is the indexed TXI send path." + }, + "confidence": "high", + "confidence_score": 0.95, + "confidence_reason": "all required independent evidence groups were observed", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "missing_evidence": [], + "evidence_addresses": { + "tx_buffer_region": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "tx_checksum_seed": [ + 47694 + ], + "checksum_byte": [ + 47716 + ], + "xor_checksum_chain": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "initial_send_from_buffer_start": [ + 47726, + 47730 + ], + "tx_index_initialized_to_one": [ + 47734 + ], + "tx_isr_indexed_send": [ + 47787, + 47793, + 47797 + ], + "tx_index_increment": [ + 47807 + ], + "tx_index_compare_frame_length": [ + 47811 + ] + }, + "evidence_addresses_hex": { + "tx_buffer_region": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "tx_checksum_seed": [ + "H'BA4E" + ], + "checksum_byte": [ + "H'BA64" + ], + "xor_checksum_chain": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "initial_send_from_buffer_start": [ + "H'BA6E", + "H'BA72" + ], + "tx_index_initialized_to_one": [ + "H'BA76" + ], + "tx_isr_indexed_send": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "tx_index_increment": [ + "H'BABF" + ], + "tx_index_compare_frame_length": [ + "H'BAC3" + ] + }, + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + } + ], + "short_comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis using buffer H'F858-H'F85D with checksum byte H'F85D seeded by H'005A" + }, + { + "id": "sci1_rx_frame_f868_len6_candidate", + "kind": "candidate_sci1_rx_frame", + "channel": "SCI1", + "frame_length": 6, + "capture_buffer_start": 63592, + "capture_buffer_start_hex": "H'F868", + "capture_buffer_end": 63597, + "capture_buffer_end_hex": "H'F86D", + "validation_buffer_start": 63584, + "validation_buffer_start_hex": "H'F860", + "validation_buffer_end": 63589, + "validation_buffer_end_hex": "H'F865", + "checksum_address": 63589, + "checksum_address_hex": "H'F865", + "rx_index_address": 63939, + "rx_index_address_hex": "H'F9C3", + "rdr_address": 65245, + "rdr_address_hex": "H'FEDD", + "interbyte_timeout_address": 63937, + "interbyte_timeout_address_hex": "H'F9C1", + "complete_timer_address": 63941, + "complete_timer_address_hex": "H'F9C5", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "confidence": "high", + "confidence_score": 0.9, + "confidence_reason": "RX count, copy, and checksum-validation evidence were observed; no explicit header/sync byte was identified", + "caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "optional_evidence_count": 2, + "missing_evidence": [], + "evidence_addresses": { + "rx_rdr_read": [ + 47981 + ], + "rx_indexed_store": [ + 48016 + ], + "rx_index_increment_store": [ + 48020, + 48022 + ], + "rx_isr_compare_frame_length": [ + 48026 + ], + "rx_complete_timer": [ + 48030 + ], + "rx_processor_requires_six_bytes": [ + 48043 + ], + "rx_copy_capture_to_frame_buffer": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "rx_checksum_seed": [ + 48086 + ], + "rx_xor_checksum_validation": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "rx_rdrf_clear_before_rdr_read": [ + 47977, + 47981 + ], + "rx_eri_falls_through_to_rxi": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ] + }, + "evidence_addresses_hex": { + "rx_rdr_read": [ + "H'BB6D" + ], + "rx_indexed_store": [ + "H'BB90" + ], + "rx_index_increment_store": [ + "H'BB94", + "H'BB96" + ], + "rx_isr_compare_frame_length": [ + "H'BB9A" + ], + "rx_complete_timer": [ + "H'BB9E" + ], + "rx_processor_requires_six_bytes": [ + "H'BBAB" + ], + "rx_copy_capture_to_frame_buffer": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "rx_checksum_seed": [ + "H'BBD6" + ], + "rx_xor_checksum_validation": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "rx_rdrf_clear_before_rdr_read": [ + "H'BB69", + "H'BB6D" + ], + "rx_eri_falls_through_to_rxi": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ] + }, + "evidence": [ + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + } + ], + "rx_error_handling": { + "kind": "sci1_rx_error_handling_candidate", + "error_latch_address": 64164, + "error_latch_address_hex": "H'FAA4", + "error_latch_bit": 7, + "fallthrough_to_rx_byte_path": true, + "rdrf_clear_before_rdr_read": true, + "summary": "SCI1 ERI appears to mark a physical receive error and continue into the RXI byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order.", + "manual_caveat": "Manual text distinguishes ORER from FER/PER data transfer into RDR and describes the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order.", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "candidate-medium" + }, + "short_comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A" + } + ], + "ram_roles": [ + { + "kind": "candidate_ram_role", + "name": "post_tx_report_delay", + "address": 63936, + "address_hex": "H'F9C0", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "post_tx_report_delay_tick_decrement": [ + 48878, + 48884 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "post_tx_report_delay_tick_decrement": [ + "H'BEEE", + "H'BEF4" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "secondary_tx_report_delay", + "address": 63937, + "address_hex": "H'F9C1", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "secondary_tx_report_delay_tick_decrement": [ + 48888, + 48894 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "secondary_tx_report_delay_tick_decrement": [ + "H'BEF8", + "H'BEFE" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "periodic_report_countdown", + "address": 63942, + "address_hex": "H'F9C6", + "width_bits": 16, + "confidence": "candidate/evidence-supported", + "summary": "periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "periodic_report_countdown_tick_decrement": [ + 48898, + 48904 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "periodic_report_countdown_tick_decrement": [ + "H'BF02", + "H'BF08" + ] + } + } + ], + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + }, + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "required_evidence": { + "tx": [ + "tx_buffer_region", + "tx_checksum_seed", + "checksum_byte", + "xor_checksum_chain", + "initial_send_from_buffer_start", + "tx_index_initialized_to_one", + "tx_isr_indexed_send", + "tx_index_increment", + "tx_index_compare_frame_length" + ], + "rx": [ + "rx_rdr_read", + "rx_indexed_store", + "rx_index_increment_store", + "rx_isr_compare_frame_length", + "rx_complete_timer", + "rx_processor_requires_six_bytes", + "rx_copy_capture_to_frame_buffer", + "rx_checksum_seed", + "rx_xor_checksum_validation" + ] + } + }, + "board_profile": { + "board": "sony_rcp_tx7", + "name": "Sony RCP-TX7", + "summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.", + "manual_references": [ + "Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD", + "Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD", + "Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals", + "Manual/0900766b802125d0.md:11201 P96 is RXD1 input", + "Manual/0900766b802125d0.md:11202 P95 is TXD1 output", + "Manual/0900766b802125d0.md:15725 SCI1 RXD input pin", + "Manual/0900766b802125d0.md:15726 SCI1 TXD output pin", + "Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15794 RDR receive data register", + "Manual/0900766b802125d0.md:15823 TDR transmit data register", + "Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions", + "Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output", + "Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input", + "Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags", + "Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions", + "Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94" + ], + "traces": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "channels": { + "SCI1": { + "traced_to_max202": true, + "path": "RS232/MAX202", + "pins": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + }, + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ] + }, + "SCI2": { + "traced_to_max202": false, + "path": null, + "note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.", + "p9sci2e": false, + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ] + } + }, + "instructions": { + "4148": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "4245": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4250": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "4255": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4260": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4265": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4270": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "17258": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "17274": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "17278": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "47720": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47730": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47739": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47743": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47774": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47797": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47803": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47818": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47963": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47967": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47971": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47977": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47981": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + }, + "state": { + "SYSCR2": { + "value": 180, + "value_hex": "H'B4" + }, + "P9SCI2E": false + } + }, + "peripheral_access": { + "manual_references": [ + "Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access", + "Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte", + "Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP", + "Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP", + "Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte" + ], + "warnings": [] + }, + "indirect_flow": { + "sites": [ + { + "address": 7192, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "unknown", + "summary": "JSR @R0 uses R0; target not resolved" + }, + { + "address": 10403, + "instruction": "JMP @R1", + "kind": "jump", + "target_register": "R1", + "confidence": "table_load", + "table": { + "base": 10406, + "index_register": "R4", + "target_register": "R1", + "load_address": 10399, + "load_instruction": "MOV:G.W @(H'28A6,R4), R1", + "entry_size": 2, + "entry_count": 128, + "decoded_target_count": 103, + "entries": [ + { + "index": 0, + "entry_address": 10406, + "target": 11449, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 10408, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 2, + "entry_address": 10410, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 3, + "entry_address": 10412, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 4, + "entry_address": 10414, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 5, + "entry_address": 10416, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 6, + "entry_address": 10418, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 7, + "entry_address": 10420, + "target": 11715, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 10422, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 9, + "entry_address": 10424, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 10, + "entry_address": 10426, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 11, + "entry_address": 10428, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 12, + "entry_address": 10430, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 13, + "entry_address": 10432, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 14, + "entry_address": 10434, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 15, + "entry_address": 10436, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 16, + "entry_address": 10438, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 17, + "entry_address": 10440, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 18, + "entry_address": 10442, + "target": 11779, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 10444, + "target": 11782, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 10446, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 21, + "entry_address": 10448, + "target": 11833, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 10450, + "target": 11866, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 10452, + "target": 11909, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 10454, + "target": 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"target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 1, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + 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"address": 63216, + "instruction_address": 5640, + "instruction": "BCLR.B #6, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5649, + "instruction": "BCLR.B #5, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5658, + "instruction": "BCLR.B #4, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5662, + "instruction": "BCLR.B #3, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5671, + "instruction": "BCLR.B #2, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": 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"instruction": "BSET.B #5, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15111, + "instruction": "BSET.B #4, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15129, + "instruction": "BSET.B #3, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15147, + "instruction": "BSET.B #2, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15165, + "instruction": "BSET.B #1, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", 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63384, + "instruction_address": 49081, + "instruction": "ADD:Q.B #-1, @H'F798", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F798", + "operand_index": 1 + } + ] + }, + { + "address": 63552, + "name": "ram_F840", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 8, + "read_count": 6, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 49015, + "last_access": 49211, + "accesses": [ + { + "address": 63552, + "instruction_address": 49015, + "instruction": "TST.B @H'F840", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F840", + "operand_index": 0 + }, + { + "address": 63552, + "instruction_address": 49021, + "instruction": "ADD:Q.B #-1, @H'F840", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F840", + "operand_index": 1 + }, + { + "address": 63552, + "instruction_address": 49120, + "instruction": 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"instruction": "MOV:G.B @H'F860, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F860", + "operand_index": 0 + } + ] + }, + { + "address": 63585, + "name": "ram_F861", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 7, + "read_count": 7, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48092, + "last_access": 48722, + "accesses": [ + { + "address": 63585, + "instruction_address": 48092, + "instruction": "XOR.B @H'F861, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + }, + { + "address": 63585, + "instruction_address": 48119, + "instruction": "MOV:G.B @H'F861, R5", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + }, + { + "address": 63585, + "instruction_address": 48153, + "instruction": "BTST.B #7, @H'F861", + "mnemonic": "BTST.B", + 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"region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 5, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48063, + "last_access": 48730, + "accesses": [ + { + "address": 63586, + "instruction_address": 48063, + "instruction": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F862", + "operand_index": 1 + }, + { + "address": 63586, + "instruction_address": 48096, + "instruction": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48125, + "instruction": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48317, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48356, + "instruction": "MOV:G.B @H'F862, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48730, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + } + ] + }, + { + "address": 63587, + "name": "ram_F863", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 6, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48100, + "last_access": 48603, + "accesses": [ + { + "address": 63587, + "instruction_address": 48100, + "instruction": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48237, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48267, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48402, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48427, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48603, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + } + ] + }, + { + "address": 63588, + "name": "ram_F864", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 8, + "read_count": 6, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48071, + "last_access": 48738, + "accesses": [ + { + "address": 63588, + "instruction_address": 48071, + "instruction": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48104, + "instruction": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48253, + "instruction": "MOV:G.B #H'80, @H'F864", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48273, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48325, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48433, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48609, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48738, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + } + ] + }, + { + "address": 63589, + "name": "ram_F865", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48108, + "last_access": 48108, + "accesses": [ + { + "address": 63589, + "instruction_address": 48108, + "instruction": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F865", + "operand_index": 0 + } + ] + }, + { + "address": 63592, + "name": "ram_F868", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48051, + "last_access": 48051, + "accesses": [ + { + "address": 63592, + "instruction_address": 48051, + "instruction": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F868", + "operand_index": 0 + } + ] + }, + { + "address": 63594, + "name": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48059, + "last_access": 48059, + "accesses": [ + { + "address": 63594, + "instruction_address": 48059, + "instruction": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86A", + "operand_index": 0 + } + ] + }, + { + "address": 63596, + "name": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48067, + "last_access": 48067, + "accesses": [ + { + "address": 63596, + "instruction_address": 48067, + "instruction": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86C", + "operand_index": 0 + } + ] + }, + { + "address": 63920, + "name": "ram_F9B0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 9, + "read_count": 8, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15968, + "last_access": 47864, + "accesses": [ + { + "address": 63920, + "instruction_address": 15968, + "instruction": "MOV:G.B @H'F9B0, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 15994, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 15998, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16002, + "instruction": "MOV:G.B @H'F9B0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16377, + "instruction": "CLR.B @H'F9B0", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16473, + "instruction": "MOV:G.B @H'F9B0, R2", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16492, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16496, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 47864, + "instruction": "CMP:G.B @H'F9B0, R1", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + } + ] + }, + { + "address": 63924, + "name": "ram_F9B4", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 7, + "read_count": 7, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10252, + "last_access": 48793, + "accesses": [ + { + "address": 63924, + "instruction_address": 10252, + "instruction": "CMP:G.B @H'F9B4, R1", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 16038, + "instruction": "MOV:G.B @H'F9B4, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 16067, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 16071, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48760, + "instruction": "MOV:G.B @H'F9B4, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 48789, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48793, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + } + ] + }, + { + "address": 63925, + "name": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 10, + "write_count": 7, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15960, + "last_access": 48631, + "accesses": [ + { + "address": 63925, + "instruction_address": 15960, + "instruction": "MOV:G.B @H'F9B5, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16011, + "instruction": "CMP:G.B @H'F9B5, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16373, + "instruction": "CLR.B @H'F9B5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16479, + "instruction": "CMP:G.B @H'F9B5, R2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 47858, + "instruction": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 48493, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48497, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48584, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48588, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48627, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48631, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + } + ] + }, + { + "address": 63929, + "name": "ram_F9B9", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10246, + "last_access": 48752, + "accesses": [ + { + "address": 63929, + "instruction_address": 10246, + "instruction": "MOV:G.B @H'F9B9, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 10274, + "instruction": "MOV:G.B R1, @H'F9B9", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 1 + }, + { + "address": 63929, + "instruction_address": 16030, + "instruction": "MOV:G.B @H'F9B9, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 48752, + "instruction": "MOV:G.B @H'F9B9, R3", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + } + ] + }, + { + "address": 63936, + "name": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 4, + "write_count": 8, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16357, + "last_access": 48884, + "accesses": [ + { + "address": 63936, + "instruction_address": 16357, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47654, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47660, + "instruction": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47778, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47834, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47841, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47848, + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48669, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48702, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48878, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 48884, + "instruction": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + } + ] + }, + { + "address": 63937, + "name": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47853, + "last_access": 48894, + "accesses": [ + { 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"operand": "@H'F9C1", + "operand_index": 1 + } + ] + }, + { + "address": 63938, + "name": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47734, + "last_access": 47811, + "accesses": [ + { + "address": 63938, + "instruction_address": 47734, + "instruction": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47787, + "instruction": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 0 + }, + { + "address": 63938, + "instruction_address": 47807, + "instruction": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47811, + "instruction": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + } + ] + }, + { + "address": 63939, + "name": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 10, + "read_count": 6, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16351, + "last_access": 48849, + "accesses": [ + { + "address": 63939, + "instruction_address": 16351, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 16466, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47760, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47991, + "instruction": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47997, + "instruction": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 1 + }, + { + "address": 63939, + "instruction_address": 48010, + "instruction": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 48022, + "instruction": "MOV:G.B R1, @H'F9C3", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 1 + }, + { + "address": 63939, + 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63941, + "name": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16367, + "last_access": 48951, + "accesses": [ + { + "address": 63941, + "instruction_address": 16367, + "instruction": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48030, + "instruction": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 1 + }, + { + "address": 63941, + "instruction_address": 48868, + "instruction": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48945, + "instruction": "TST.B @H'F9C5", + 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"address": 27231, + "kind": "raw_mov_iw", + "target": 27215, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'6A4F, R0", + "following_bsr": { + "address": 27234, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 27278, + "length": 18, + "text": " A.IRIS MODE Xj", + "trimmed": "A.IRIS MODE Xj", + "kind": "printable_run", + "score": 1.041, + "confidence": "medium", + "xrefs": [ + { + "address": 27294, + "kind": "raw_mov_iw", + "target": 27278, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'6A8E, R0", + "following_bsr": { + "address": 27297, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 27309, + "length": 17, + "text": "AI BACK.L~Xj", + "trimmed": "AI BACK.L~Xj", + "kind": "printable_run", + "score": 0.965, + "confidence": "medium", + "xrefs": [ + { + "address": 27324, + "kind": "raw_mov_iw", + "target": 27308, + "delta": -1, + "register": "R0", + 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"RESET REQ~Xl4", + "trimmed": "RESET REQ~Xl4", + "kind": "printable_run", + "score": 0.992, + "confidence": "medium", + "xrefs": [ + { + "address": 27716, + "kind": "raw_mov_iw", + "target": 27700, + "delta": -1, + "register": "R0", + "instruction": "MOV:I.W #H'6C34, R0", + "following_bsr": { + "address": 27719, + "target": 23697, + "instruction": "BSR H'5C91" + } + } + ], + "xref_count": 1 + }, + { + "address": 28548, + "length": 18, + "text": " OTHERS Xo", + "trimmed": "OTHERS Xo", + "kind": "printable_run", + "score": 1.018, + "confidence": "medium", + "xrefs": [ + { + "address": 28564, + "kind": "raw_mov_iw", + "target": 28548, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'6F84, R0", + "following_bsr": { + "address": 28567, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 28590, + "length": 18, + "text": " SHUTTER Xo", + "trimmed": "SHUTTER Xo", + "kind": "printable_run", + "score": 1.032, + "confidence": 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"address": 29219, + "kind": "raw_mov_iw", + "target": 29203, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'7213, R0", + "following_bsr": { + "address": 29222, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 29349, + "length": 18, + "text": " OTHERS Xr", + "trimmed": "OTHERS Xr", + "kind": "printable_run", + "score": 1.018, + "confidence": "medium", + "xrefs": [ + { + "address": 29365, + "kind": "raw_mov_iw", + "target": 29349, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'72A5, R0", + "following_bsr": { + "address": 29368, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 29383, + "length": 17, + "text": "CAM BARS~Xr", + "trimmed": "CAM BARS~Xr", + "kind": "printable_run", + "score": 0.971, + "confidence": "medium", + "xrefs": [ + { + "address": 29398, + "kind": "raw_mov_iw", + "target": 29382, + "delta": -1, + "register": "R0", + "instruction": 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H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 29587, + "length": 18, + "text": " CENTER MARKER Xs", + "trimmed": "CENTER MARKER Xs", + "kind": "printable_run", + "score": 1.076, + "confidence": "high", + "xrefs": [ + { + "address": 29603, + "kind": "raw_mov_iw", + "target": 29587, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'7393, R0", + "following_bsr": { + "address": 29606, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 29733, + "length": 19, + "text": " OTHERS Xt%", + "trimmed": "OTHERS Xt%", + "kind": "printable_run", + "score": 1.007, + "confidence": "medium", + "xrefs": [ + { + "address": 29749, + "kind": "raw_mov_iw", + "target": 29733, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'7425, R0", + "following_bsr": { + "address": 29752, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 29796, + "length": 19, + "text": " SAFETY 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"address": 38414, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 38437, + "length": 14, + "text": " AUTO ", + "trimmed": "AUTO", + "kind": "printable_run", + "score": 1.0, + "confidence": "medium", + "xrefs": [ + { + "address": 38452, + "kind": "raw_mov_iw", + "target": 38436, + "delta": -1, + "register": "R0", + "instruction": "MOV:I.W #H'9624, R0" + } + ], + "xref_count": 1 + }, + { + "address": 38460, + "length": 14, + "text": " PRESET ", + "trimmed": "PRESET", + "kind": "printable_run", + "score": 1.0, + "confidence": "medium", + "xrefs": [ + { + "address": 38475, + "kind": "raw_mov_iw", + "target": 38459, + "delta": -1, + "register": "R0", + "instruction": "MOV:I.W #H'963B, R0" + } + ], + "xref_count": 1 + }, + { + "address": 38483, + "length": 14, + "text": " DL ", + "trimmed": "DL", + "kind": "printable_run", + "score": 1.0, + "confidence": "medium", + "xrefs": [ + { + "address": 38498, + "kind": "raw_mov_iw", + "target": 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STORE~X", + "score": 0.421 + }, + { + "address": 29733, + "text": " OTHERS Xt%", + "trimmed": "OTHERS Xt%", + "score": 0.4 + }, + { + "address": 29796, + "text": " SAFETY ZONE Xtd", + "trimmed": "SAFETY ZONE Xtd", + "score": 0.4 + }, + { + "address": 46424, + "text": "SCENE F. RECALL~X", + "trimmed": "SCENE F. RECALL~X", + "score": 0.4 + }, + { + "address": 26243, + "text": "POINT1 POINT2Xf", + "trimmed": "POINT1 POINT2Xf", + "score": 0.381 + } + ], + "status": "not_found" + } + ], + "notes": [ + "LCD text scan is byte-oriented and conservative; strings may be inline script fields.", + "Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes." + ] + }, + "lcd_driver": { + "addresses": [ + { + "address": 61952, + "name": "lcd_status_control", + "role": "status/control register inferred from busy polling and command writes" + }, + { + "address": 61953, + "name": "lcd_data", + "role": "data register inferred from paired data reads/writes" + } + ], + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "polling_loops": [ + { + "read_address": 16202, + "test_address": 16207, + "branch_address": 16209, + "register": "R0", + "bit": 7, + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear" + } + ], + "routines": [ + { + "start": 16192, + "end": 16244, + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "roles": [ + "lcd_command_or_address_write", + "lcd_data_read", + "lcd_data_write", + "lcd_status_read" + ], + "role_hint": "lcd_wait_and_transfer" + } + ], + "instructions": { + "16202": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16219": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ], + "16226": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ], + "16237": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "16207": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16209": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + } + }, + "instructions": [ + { + "address": 4096, + "address_region": "program_or_external", + "bytes": "5FFE80", + "text": "MOV:I.W #H'FE80, R7", + "mnemonic": "MOV:I.W", + "operands": "#H'FE80, R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R7 = 0xFE80" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + } + } + } + }, + { + "address": 4099, + "address_region": "program_or_external", + "bytes": "0C070088", + "text": "LDC.W #H'0700, SR", + "mnemonic": "LDC.W", + "operands": "#H'0700, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + ], + "notes": [ + "SR = 0x0700" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4103, + "address_region": "program_or_external", + "bytes": "15FE8006FF", + "text": "MOV:G.B #H'FF, @P1DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @P1DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65152, + "name": "P1DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DDR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4108, + "address_region": "program_or_external", + "bytes": "15FE820600", + "text": "MOV:G.B #H'00, @P1DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4113, + "address_region": "program_or_external", + "bytes": "15FE8906F9", + "text": "MOV:G.B #H'F9, @P6DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'F9, @P6DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65161, + "name": "P6DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DDR = H'F9", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4118, + "address_region": "program_or_external", + "bytes": "15FE8B06F1", + "text": "MOV:G.B #H'F1, @P6DR", + "mnemonic": "MOV:G.B", + "operands": "#H'F1, @P6DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65163, + "name": "P6DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DR = H'F1", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4123, + "address_region": "program_or_external", + "bytes": "15FE8C0600", + "text": "MOV:G.B #H'00, @P7DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65164, + "name": "P7DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DDR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4128, + "address_region": "program_or_external", + "bytes": "15FE8E0600", + "text": "MOV:G.B #H'00, @P7DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4133, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'93", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4138, + "address_region": "program_or_external", + "bytes": "15FEFF0600", + "text": "MOV:G.B #H'00, @P9DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4143, + "address_region": "program_or_external", + "bytes": "15FEFC0687", + "text": "MOV:G.B #H'87, @SYSCR1", + "mnemonic": "MOV:G.B", + "operands": "#H'87, @SYSCR1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65276, + "name": "SYSCR1", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4148, + "address_region": "program_or_external", + "bytes": "15FEFD0684", + "text": "MOV:G.B #H'84, @SYSCR2", + "mnemonic": "MOV:G.B", + "operands": "#H'84, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM)", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4153, + "address_region": "program_or_external", + "bytes": "15FE900602", + "text": "MOV:G.B #H'02, @FRT1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4158, + "address_region": "program_or_external", + "bytes": "15FE910601", + "text": "MOV:G.B #H'01, @FRT1_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4163, + "address_region": "program_or_external", + "bytes": "1DFE920600", + "text": "MOV:G.W #H'00, @FRT1_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT1_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65170, + "name": "FRT1_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4163, + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "register": "FRT1_FRC", + "high_address": 65170, + "low_address": 65171, + "referenced_address": 65170, + "referenced_address_hex": "H'FE92", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4168, + "address_region": "program_or_external", + "bytes": "1DFE9407009C", + "text": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'009C, @FRT1_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65172, + "name": "FRT1_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_OCRA_H = H'9C", + "valid": true, + "peripheral_access": [ + { + "address": 4168, + "instruction": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "register": "FRT1_OCRA", + "high_address": 65172, + "low_address": 65173, + "referenced_address": 65172, + "referenced_address_hex": "H'FE94", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4174, + "address_region": "program_or_external", + "bytes": "15FEA00602", + "text": "MOV:G.B #H'02, @FRT2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4179, + "address_region": "program_or_external", + "bytes": "15FEA10601", + "text": "MOV:G.B #H'01, @FRT2_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT2_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65185, + "name": "FRT2_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4184, + "address_region": "program_or_external", + "bytes": "1DFEA20600", + "text": "MOV:G.W #H'00, @FRT2_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT2_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65186, + "name": "FRT2_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4184, + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "register": "FRT2_FRC", + "high_address": 65186, + "low_address": 65187, + "referenced_address": 65186, + "referenced_address_hex": "H'FEA2", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4189, + "address_region": "program_or_external", + "bytes": "1DFEA4077A12", + "text": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'7A12, @FRT2_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65188, + "name": "FRT2_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_OCRA_H = H'7A12", + "valid": true, + "peripheral_access": [ + { + "address": 4189, + "instruction": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "register": "FRT2_OCRA", + "high_address": 65188, + "low_address": 65189, + "referenced_address": 65188, + "referenced_address_hex": "H'FEA4", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4195, + "address_region": "program_or_external", + "bytes": "15FEB00600", + "text": "MOV:G.B #H'00, @FRT3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65200, + "name": "FRT3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4200, + "address_region": "program_or_external", + "bytes": "15FEB10600", + "text": "MOV:G.B #H'00, @FRT3_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65201, + "name": "FRT3_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4205, + "address_region": "program_or_external", + "bytes": "15FED00600", + "text": "MOV:G.B #H'00, @TMR_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @TMR_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65232, + "name": "TMR_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4210, + "address_region": "program_or_external", + "bytes": "15FED10610", + "text": "MOV:G.B #H'10, @TMR_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'10, @TMR_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65233, + "name": "TMR_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4215, + "address_region": "program_or_external", + "bytes": "15FEC00638", + "text": "MOV:G.B #H'38, @PWM1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65216, + "name": "PWM1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4220, + "address_region": "program_or_external", + "bytes": "15FEC106FF", + "text": "MOV:G.B #H'FF, @PWM1_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM1_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65217, + "name": "PWM1_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4225, + "address_region": "program_or_external", + "bytes": "15FEC40638", + "text": "MOV:G.B #H'38, @PWM2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65220, + "name": "PWM2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4230, + "address_region": "program_or_external", + "bytes": "15FEC506FF", + "text": "MOV:G.B #H'FF, @PWM2_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM2_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65221, + "name": "PWM2_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4235, + "address_region": "program_or_external", + "bytes": "15FEC8063B", + "text": "MOV:G.B #H'3B, @PWM3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3B, @PWM3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65224, + "name": "PWM3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4240, + "address_region": "program_or_external", + "bytes": "15FEC9067D", + "text": "MOV:G.B #H'7D, @PWM3_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'7D, @PWM3_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65225, + "name": "PWM3_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_DTR = H'7D", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4245, + "address_region": "program_or_external", + "bytes": "15FED80624", + "text": "MOV:G.B #H'24, @SCI1_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI1_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65240, + "name": "SCI1_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4250, + "address_region": "program_or_external", + "bytes": "15FEDA063C", + "text": "MOV:G.B #H'3C, @SCI1_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3C, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + } + ] + }, + "sci_protocol": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4255, + "address_region": "program_or_external", + "bytes": "15FED90607", + "text": "MOV:G.B #H'07, @SCI1_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI1_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65241, + "name": "SCI1_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4260, + "address_region": "program_or_external", + "bytes": "15FEF00624", + "text": "MOV:G.B #H'24, @SCI2_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI2_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65264, + "name": "SCI2_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4265, + "address_region": "program_or_external", + "bytes": "15FEF2060C", + "text": "MOV:G.B #H'0C, @SCI2_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'0C, @SCI2_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65266, + "name": "SCI2_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + } + ] + }, + "sci_protocol": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4270, + "address_region": "program_or_external", + "bytes": "15FEF10607", + "text": "MOV:G.B #H'07, @SCI2_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI2_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65265, + "name": "SCI2_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4275, + "address_region": "program_or_external", + "bytes": "15FEE80619", + "text": "MOV:G.B #H'19, @ADCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'19, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4280, + "address_region": "program_or_external", + "bytes": "15FEE9067F", + "text": "MOV:G.B #H'7F, @H'FEE9", + "mnemonic": "MOV:G.B", + "operands": "#H'7F, @H'FEE9", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65257, + "name": null, + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4285, + "address_region": "program_or_external", + "bytes": "15FF1006F0", + "text": "MOV:G.B #H'F0, @WCR", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @WCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65296, + "name": "WCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4290, + "address_region": "program_or_external", + "bytes": "15FF1106FF", + "text": "MOV:G.B #H'FF, @RAMCR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @RAMCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65297, + "name": "RAMCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "RAMCR = H'FF (RAME=1; on-chip RAM enabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4295, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4299, + "address_region": "program_or_external", + "bytes": "302EA8", + "text": "BRA loc_3F76", + "mnemonic": "BRA", + "operands": "loc_3F76", + "kind": "jump", + "targets": [ + 16246 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4302, + "address_region": "program_or_external", + "bytes": "5C0040", + "text": "MOV:I.W #H'0040, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0040, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0040" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + } + } + } + }, + { + "address": 4305, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 4308, + "address_region": "program_or_external", + "bytes": "1E2DF5", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 4311, + "address_region": "program_or_external", + "bytes": "5C0200", + "text": "MOV:I.W #H'0200, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0200, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": 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"cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6627, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 6633, + "address_region": "program_or_external", + "bytes": "A982", + "text": "MOV:G.W R1, R2", + "mnemonic": "MOV:G.W", + "operands": "R1, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6627, + "changes": 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"assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6642, + "address_region": "program_or_external", + "bytes": "230F", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6644, + "address_region": "program_or_external", + "bytes": "590000", + "text": "MOV:I.W #H'0000, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6644, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R1" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 = 0x0000" + ], + "known_after": { + "registers": { + "R1": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R1" + } + } + } + } + }, + { + "address": 6647, + "address_region": "program_or_external", + "bytes": "200A", + "text": "BRA loc_1A03", + "mnemonic": "BRA", + "operands": "loc_1A03", + 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"address_region": "program_or_external", + "bytes": "2303", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6649, + "changes": [], + "notes": [] + } + }, + { + "address": 6656, + "address_region": "program_or_external", + "bytes": "59FFFF", + "text": "MOV:I.W #H'FFFF, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'FFFF, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6656, + "changes": [ + { + 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"name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": 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"address_region": "program_or_external", + "bytes": "01B9F9", + "text": "SCB/F R1, loc_1A90", + "mnemonic": "SCB/F", + "operands": "R1, loc_1A90", + "kind": "branch", + "targets": [ + 6800 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6804, + "changes": [], + "notes": [] + } + }, + { + "address": 6807, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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"text": "BSR loc_1C0E", + "mnemonic": "BSR", + "operands": "loc_1C0E", + "kind": "call", + "targets": [ + 7182 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 7072, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + 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"bytes": "15F6E494", + "text": "MOV:G.B R4, @H'F6E4", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F6E4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63204, + "name": null, + "symbol": "ram_F6E4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 7072, + "changes": [], + "notes": [] + } + }, + { + "address": 7093, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, 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"base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63377, + "name": null, + "symbol": "ram_F791", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 9873, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R2": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "R3": { + "known": true, + "value": 146, + "hex": "0x0092", + "width": 16, + "source": "MOV:I.W #H'0092, R3" + } + } + } + } + }, + { + "address": 9886, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_26A8", + "mnemonic": "BEQ", + "operands": "loc_26A8", + "kind": "branch", + "targets": [ + 9896 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix 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"symbol": "mem_F404", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 9888, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 9892, + "address_region": "program_or_external", + "bytes": "2702", + "text": "BEQ loc_26A8", + "mnemonic": "BEQ", + "operands": "loc_26A8", + "kind": "branch", + "targets": [ + 9896 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 9888, + "changes": [], + "notes": [] + } + }, + { + "address": 9894, + "address_region": "program_or_external", + "bytes": "ABCE", + "text": "BSET.W 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"program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + "dataflow": { + "block": 10399, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + } + ], + "notes": [ + "indirect jump ends known register state" + ] + } + }, + { + "address": 11430, + "address_region": "program_or_external", + "bytes": "15F769D7", + "text": "BCLR.B #7, @H'F769", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11434, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [], + "notes": [] + } + }, + { + "address": 11435, + "address_region": "program_or_external", + "bytes": "1231", + "text": "STM.W {R0,R4,R5}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R4,R5}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 15, + "note": "6+3n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 11437, + "address_region": "program_or_external", + "bytes": "1E1C4A", + "text": "BSR loc_48FA", + "mnemonic": "BSR", + "operands": "loc_48FA", + "kind": "call", + "targets": [ + 18682 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 11440, + "address_region": "program_or_external", + "bytes": "0231", + "text": "LDM.W @SP+, {R0,R4,R5}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R4,R5}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 18, + "note": "6+4n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R4, R5" + ] + } + }, + { + "address": 11442, + "address_region": "program_or_external", + "bytes": "15F769C7", + "text": "BSET.B #7, @H'F769", + "mnemonic": "BSET.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11446, + "address_region": "program_or_external", + "bytes": "30FBE6", + "text": "BRA loc_289F", + "mnemonic": "BRA", + "operands": "loc_289F", + "kind": "jump", + "targets": [ + 10399 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 14640, + "address_region": "program_or_external", + "bytes": "580007", + "text": "MOV:I.W #H'0007, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14640, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x0007" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + } + } + } + }, + { + "address": 14643, + "address_region": "program_or_external", + "bytes": "15FE8E78", + "text": "BTST.B R0, @P7DR", + "mnemonic": "BTST.B", + "operands": "R0, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 14643, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14647, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_3943", + "mnemonic": "BEQ", + "operands": "loc_3943", + "kind": "branch", + "targets": [ + 14659 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14643, + "changes": [], + "notes": [] + } + }, + { + "address": 14649, + "address_region": "program_or_external", + "bytes": "F0F6801A", + "text": "SHLL.B @(-H'0980,R0)", + "mnemonic": "SHLL.B", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14653, + "address_region": "program_or_external", + "bytes": "F0F680C0", + "text": "BSET.B #0, @(-H'0980,R0)", + "mnemonic": "BSET.B", + "operands": "#0, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [], + "notes": [] + } + }, + { + "address": 14657, + "address_region": "program_or_external", + "bytes": "2004", + "text": "BRA loc_3947", + "mnemonic": "BRA", + "operands": "loc_3947", + "kind": "jump", + "targets": [ + 14663 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [], + "notes": [] + } + }, + { + "address": 14659, + "address_region": "program_or_external", + "bytes": "F0F6801A", + "text": "SHLL.B @(-H'0980,R0)", + "mnemonic": "SHLL.B", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14659, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14663, + "address_region": "program_or_external", + "bytes": "F0F68004FF", + "text": "CMP:G.B #H'FF, @(-H'0980,R0)", + "mnemonic": "CMP:G.B", + "operands": "#H'FF, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14663, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14668, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_3954", + "mnemonic": "BNE", + "operands": "loc_3954", + "kind": "branch", + "targets": [ + 14676 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14663, + "changes": [], + "notes": [] + } + }, + { + "address": 14670, + "address_region": "program_or_external", + "bytes": "15F68848", + "text": "BSET.B R0, @H'F688", + "mnemonic": "BSET.B", + "operands": "R0, @H'F688", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63112, + "name": null, + "symbol": "ram_F688", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 14670, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } 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"base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63115, + "name": null, + "symbol": "ram_F68B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 15906, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 15910, + "address_region": "program_or_external", + "bytes": "2725", + "text": "BEQ loc_3E4D", + "mnemonic": "BEQ", + "operands": "loc_3E4D", + "kind": "branch", + "targets": [ + 15949 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"address_region": "program_or_external", + "bytes": "15FE8EF4", + "text": "BTST.B #4, @P7DR", + "mnemonic": "BTST.B", + "operands": "#4, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 15912, + "changes": [], + "notes": [] + } + }, + { + "address": 15941, + "address_region": "program_or_external", + "bytes": "2602", + "text": "BNE loc_3E49", + "mnemonic": "BNE", + "operands": "loc_3E49", + "kind": "branch", + "targets": [ + 15945 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip 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"address_region": "program_or_external", + "bytes": "270B", + "text": "BEQ loc_3EEE", + "mnemonic": "BEQ", + "operands": "loc_3EEE", + "kind": "branch", + "targets": [ + 16110 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16095, + "changes": [], + "notes": [] + } + }, + { + "address": 16099, + "address_region": "program_or_external", + "bytes": "4502", + "text": "CMP:E #H'02, R5", + "mnemonic": "CMP:E", + "operands": "#H'02, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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"notes": [], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 128, + "hex": "0x0080", + "width": 16, + "source": "MOV:I.W #H'0080, R5" + } + } + } + } + }, + { + "address": 16110, + "address_region": "program_or_external", + "bytes": "5D00C0", + "text": "MOV:I.W #H'00C0, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'00C0, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16110, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x00C0" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + } + } + } + }, + { + "address": 16113, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA loc_3EFB", + "mnemonic": "BRA", + "operands": "loc_3EFB", + "kind": "jump", + "targets": [ + 16123 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16110, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + } + 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"normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16120, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 208, + "hex": "0x00D0", + "width": 16, + "source": "MOV:I.W #H'00D0, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x00D0" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 208, + "hex": "0x00D0", + "width": 16, + "source": "MOV:I.W #H'00D0, R5" + } + } + } + } + }, + { + "address": 16123, + "address_region": "program_or_external", + "bytes": "0410AB", + "text": "MULXU.B #H'10, R3", + "mnemonic": "MULXU.B", + "operands": "#H'10, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16123, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:MULXU.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 16126, + "address_region": "program_or_external", + "bytes": "0CFAB023", + "text": "ADD:G.W #H'FAB0, R3", + "mnemonic": "ADD:G.W", + "operands": "#H'FAB0, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16123, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unsupported:MULXU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R3 unknown after arithmetic" + ] + } + }, + { + "address": 16130, + "address_region": "program_or_external", + "bytes": "A913", + "text": "CLR.W R1", + "mnemonic": "CLR.W", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": 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"changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after memory load" + ] + } + }, + { + "address": 16136, + "address_region": "program_or_external", + "bytes": "D372", + "text": "CMP:G.B @R3, R2", + "mnemonic": "CMP:G.B", + "operands": "@R3, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16138, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_3F10", + "mnemonic": "BEQ", + "operands": "loc_3F10", + "kind": "branch", + "targets": [ + 16144 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16140, + "address_region": "program_or_external", + "bytes": "D392", + "text": "MOV:G.B R2, @R3", + "mnemonic": "MOV:G.B", + "operands": "R2, @R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16140, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16142, + "address_region": "program_or_external", + "bytes": "0E18", + "text": "BSR loc_3F28", + "mnemonic": "BSR", + "operands": "loc_3F28", + "kind": "call", + "targets": [ + 16168 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16140, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": 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"cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [], + "notes": [] + } + }, + { + "address": 16150, + "address_region": "program_or_external", + "bytes": "2702", + "text": "BEQ loc_3F1A", + "mnemonic": "BEQ", + "operands": "loc_3F1A", + "kind": "branch", + "targets": [ + 16154 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [], + "notes": [] + } + }, + { + "address": 16152, + "address_region": "program_or_external", + "bytes": "20EA", + "text": "BRA loc_3F04", + "mnemonic": "BRA", + "operands": "loc_3F04", + "kind": "jump", + "targets": [ + 16132 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16152, + "changes": [], + "notes": [] + } + }, + { + "address": 16154, + "address_region": "program_or_external", + "bytes": "1DFB000700E0", + "text": "MOV:G.W #H'00E0, @H'FB00", + "mnemonic": "MOV:G.W", + "operands": "#H'00E0, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": 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"bytes": "1DFB0094", + "text": "MOV:G.W R4, @H'FB00", + "mnemonic": "MOV:G.W", + "operands": "R4, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16178, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16182, + "address_region": "program_or_external", + "bytes": "0E08", + "text": "BSR loc_3F40", + "mnemonic": "BSR", + "operands": "loc_3F40", + "kind": "call", + "targets": [ + 16192 + ], + "cycles": { + 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"kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16191, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16184, + "changes": [], + "notes": [] + } + }, + { + "address": 16192, + "address_region": "program_or_external", + "bytes": "BF98", + "text": "STC.W SR, @-R7", + "mnemonic": "STC.W", + "operands": "SR, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 7, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + } + ], + "notes": [] + } + }, + { + "address": 16194, + "address_region": "program_or_external", + "bytes": "0C00FF58", + "text": "ANDC.W #H'00FF, SR", + "mnemonic": "ANDC.W", + "operands": "#H'00FF, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "SR unknown after ANDC" + ] + } + }, + { + "address": 16198, + "address_region": "program_or_external", + "bytes": "0C060048", + "text": "ORC.W #H'0600, SR", + "mnemonic": "ORC.W", + "operands": "#H'0600, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [], + "notes": [ + "SR unknown after ORC" + ] + } + }, + { + "address": 16202, + "address_region": "program_or_external", + "bytes": "15F2000080", + "text": "MOVFPE.B @H'F200, R0", + "mnemonic": "MOVFPE.B", + "operands": "@H'F200, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16207, + "address_region": "program_or_external", + "bytes": "A0F7", + "text": "BTST.B #7, R0", + "mnemonic": "BTST.B", + "operands": "#7, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16209, + "address_region": "program_or_external", + "bytes": "26F7", + "text": "BNE loc_3F4A", + "mnemonic": "BNE", + "operands": "loc_3F4A", + "kind": "branch", + "targets": [ + 16202 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16211, + "address_region": "program_or_external", + "bytes": "ACF8", + "text": "BTST.W #8, R4", + "mnemonic": "BTST.W", + "operands": "#8, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16213, + "address_region": "program_or_external", + "bytes": "2616", + "text": "BNE loc_3F6D", + "mnemonic": "BNE", + "operands": "loc_3F6D", + "kind": "branch", + "targets": [ + 16237 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [], + "notes": [] + } + }, + { + "address": 16215, + "address_region": "program_or_external", + "bytes": "ACF9", + "text": "BTST.W #9, R4", + "mnemonic": "BTST.W", + "operands": "#9, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16217, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_3F62", + "mnemonic": "BNE", + "operands": "loc_3F62", + "kind": "branch", + "targets": [ + 16226 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [], + "notes": [] + } + }, + { + "address": 16219, + "address_region": "program_or_external", + "bytes": "15F2000094", + "text": "MOVTPE.B R4, @H'F200", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F200", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ] + }, + { + "address": 16224, + "address_region": "program_or_external", + "bytes": "2010", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [], + "notes": [] + } + }, + { + "address": 16226, + "address_region": "program_or_external", + "bytes": "15F2010094", + "text": "MOVTPE.B R4, @H'F201", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F201", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ] + }, + { + "address": 16231, + "address_region": "program_or_external", + "bytes": "1DFB0008", + "text": "ADD:Q.W #1, @H'FB00", + "mnemonic": "ADD:Q.W", + "operands": "#1, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16235, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16237, + "address_region": "program_or_external", + "bytes": "15F2010084", + "text": "MOVFPE.B @H'F201, R4", + "mnemonic": "MOVFPE.B", + "operands": "@H'F201, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16237, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ] + }, + { + "address": 16242, + "address_region": "program_or_external", + "bytes": "CF88", + "text": "LDC.W @R7+, SR", + "mnemonic": "LDC.W", + "operands": "@R7+, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "SR unknown after memory load" + ] + } + }, + { + "address": 16244, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [], + "notes": [] + } + }, + { + "address": 16246, + "address_region": "program_or_external", + "bytes": "582710", + "text": "MOV:I.W #H'2710, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'2710, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x2710" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + } + } + } + }, + { + "address": 16249, + "address_region": "program_or_external", + "bytes": "59C350", + "text": "MOV:I.W #H'C350, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'C350, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + ], + "notes": [ + "R1 = 0xC350" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + }, + "R1": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + } + } + }, + { + "address": 16252, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 16252, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16256, + "address_region": "program_or_external", + "bytes": "01B8F9", + "text": "SCB/F R0, loc_3F7C", + "mnemonic": "SCB/F", + "operands": "R0, loc_3F7C", + "kind": "branch", + "targets": [ + 16252 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16252, + "changes": [], + "notes": [] + } + }, + { + "address": 16259, + "address_region": "program_or_external", + "bytes": "15FE82C7", + "text": "BSET.B #7, @P1DR", + "mnemonic": "BSET.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16263, + "address_region": "program_or_external", + "bytes": "01B9F9", + "text": "SCB/F R1, loc_3F83", + "mnemonic": "SCB/F", + "operands": "R1, loc_3F83", + "kind": "branch", + "targets": [ + 16259 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [], + "notes": [] + } + }, + { + "address": 16266, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16266, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 cleared" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + } + } + } + }, + { + "address": 16268, + "address_region": "program_or_external", + "bytes": "F8E00013", + "text": "CLR.W @(-H'2000,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'2000,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16272, + "address_region": "program_or_external", + "bytes": "F8E80013", + "text": "CLR.W @(-H'1800,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'1800,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16276, + "address_region": "program_or_external", + "bytes": "F8F68013", + "text": "CLR.W @(-H'0980,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16280, + "address_region": "program_or_external", + "bytes": "A809", + "text": "ADD:Q.W #2, R0", + "mnemonic": "ADD:Q.W", + "operands": "#2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R0 unknown after arithmetic" + ] + } + }, + { + "address": 16282, + "address_region": "program_or_external", + "bytes": "480800", + "text": "CMP:I #H'0800, R0", + "mnemonic": "CMP:I", + "operands": "#H'0800, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16285, + "address_region": "program_or_external", + "bytes": "26ED", + "text": "BNE loc_3F8C", + "mnemonic": "BNE", + "operands": "loc_3F8C", + "kind": "branch", + "targets": [ + 16268 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + 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"address_region": "program_or_external", + "bytes": "1E037F", + "text": "BSR loc_4324", + "mnemonic": "BSR", + "operands": "loc_4324", + "kind": "call", + "targets": [ + 17188 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16293, + "address_region": "program_or_external", + "bytes": "1E00EE", + "text": "BSR loc_4096", + "mnemonic": "BSR", + "operands": "loc_4096", + "kind": "call", + "targets": [ + 16534 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16296, + "address_region": "program_or_external", + "bytes": "1E0110", + "text": "BSR loc_40BB", + "mnemonic": "BSR", + "operands": "loc_40BB", + "kind": "call", + "targets": [ + 16571 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16299, + "address_region": "program_or_external", + "bytes": "1E0269", + "text": "BSR loc_4217", + "mnemonic": "BSR", + "operands": "loc_4217", + "kind": "call", + "targets": [ + 16919 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16302, + "address_region": "program_or_external", + "bytes": "1E039B", + "text": "BSR loc_434C", + "mnemonic": "BSR", + "operands": "loc_434C", + "kind": "call", + "targets": [ + 17228 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16311, + "address_region": "program_or_external", + "bytes": "15F79413", + "text": "CLR.B @H'F794", + "mnemonic": "CLR.B", + "operands": "@H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16305, + "changes": [], + "notes": [] + } + }, + { + "address": 16315, + "address_region": "program_or_external", + "bytes": "0E16", + "text": "BSR loc_3FD3", + "mnemonic": "BSR", + "operands": "loc_3FD3", + "kind": "call", + "targets": [ + 16339 + ], + "cycles": { + "cycles": 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"kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16317, + "address_region": "program_or_external", + "bytes": "1E7BEB", + "text": "BSR loc_BBAB", + "mnemonic": "BSR", + "operands": "loc_BBAB", + "kind": "call", + "targets": [ + 48043 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 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"control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17197, + "address_region": "program_or_external", + "bytes": "5C0001", + "text": "MOV:I.W #H'0001, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0001, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0001" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + } + } + }, + { + "address": 17200, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17203, + "address_region": "program_or_external", + "bytes": "1EFB96", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17206, + "address_region": "program_or_external", + "bytes": "5C000E", + "text": "MOV:I.W #H'000E, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'000E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x000E" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + } + } + } + } + }, + { + "address": 17209, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17212, + "address_region": "program_or_external", + "bytes": "1EFB8D", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17215, + "address_region": "program_or_external", + "bytes": "5C0006", + "text": "MOV:I.W #H'0006, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0006, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0006" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + } + } + } + } + }, + { + "address": 17218, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17221, + "address_region": "program_or_external", + "bytes": "1EFB84", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17224, + "address_region": "program_or_external", + "bytes": "1ECD83", + "text": "BSR loc_10CE", + "mnemonic": "BSR", + "operands": "loc_10CE", + "kind": "call", + "targets": [ + 4302 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17227, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [] + } + }, + { + "address": 17228, + "address_region": "program_or_external", + "bytes": "15FF000670", + "text": "MOV:G.B #H'70, @IPRA", + "mnemonic": "MOV:G.B", + "operands": "#H'70, @IPRA", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65280, + "name": "IPRA", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRA = H'70 (irq0 priority=7; irq1 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17233, + "address_region": "program_or_external", + "bytes": "15FF010644", + "text": "MOV:G.B #H'44, @IPRB", + "mnemonic": "MOV:G.B", + "operands": "#H'44, @IPRB", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65281, + "name": "IPRB", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17238, + "address_region": "program_or_external", + "bytes": "15FF020666", + "text": "MOV:G.B #H'66, @IPRC", + "mnemonic": "MOV:G.B", + "operands": "#H'66, @IPRC", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65282, + "name": "IPRC", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRC = H'66 (FRT1 priority=6; FRT2 priority=6)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17243, + "address_region": "program_or_external", + "bytes": "15FF030600", + "text": "MOV:G.B #H'00, @IPRD", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @IPRD", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65283, + "name": "IPRD", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17248, + "address_region": "program_or_external", + "bytes": "15FF040650", + "text": "MOV:G.B #H'50, @IPRE", + "mnemonic": "MOV:G.B", + "operands": "#H'50, @IPRE", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65284, + "name": "IPRE", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRE = H'50 (SCI1 priority=5; SCI2 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17253, + "address_region": "program_or_external", + "bytes": "15FF050640", + "text": "MOV:G.B #H'40, @IPRF", + "mnemonic": "MOV:G.B", + "operands": "#H'40, @IPRF", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65285, + "name": "IPRF", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRF = H'40 (A/D priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17258, + "address_region": "program_or_external", + "bytes": "15FEDAC6", + "text": "BSET.B #6, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#6, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set RIE (bit 6) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17262, + "address_region": "program_or_external", + "bytes": "15FE90C5", + "text": "BSET.B #5, @FRT1_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT1_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17266, + "address_region": "program_or_external", + "bytes": "15FEA0C5", + "text": "BSET.B #5, @FRT2_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT2_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17270, + "address_region": "program_or_external", + "bytes": "15FEE8C6", + "text": "BSET.B #6, @ADCSR", + "mnemonic": "BSET.B", + "operands": "#6, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set ADIE (bit 6) of ADCSR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17274, + "address_region": "program_or_external", + "bytes": "15FEFDC4", + "text": "BSET.B #4, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#4, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ3E (bit 4) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17278, + "address_region": "program_or_external", + "bytes": "15FEFDC5", + "text": "BSET.B #5, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#5, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ4E (bit 5) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17282, + "address_region": "program_or_external", + "bytes": "15FE8EF6", + "text": "BTST.B #6, @P7DR", + "mnemonic": "BTST.B", + "operands": "#6, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17286, + "address_region": "program_or_external", + "bytes": "2706", + "text": "BEQ loc_438E", + "mnemonic": "BEQ", + "operands": "loc_438E", + "kind": "branch", + "targets": [ + 17294 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17288, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 17288, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17294, + "address_region": "program_or_external", + "bytes": "0C030088", + "text": "LDC.W #H'0300, SR", + "mnemonic": "LDC.W", + "operands": "#H'0300, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + ], + "notes": [ + "SR = 0x0300" + ], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17298, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [], + "notes": [], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17299, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17299, + "changes": [], + "notes": [] + } + }, + { + "address": 17300, + "address_region": "program_or_external", + "bytes": "15F7310401", + "text": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "operands": "#H'01, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17305, + "address_region": "program_or_external", + "bytes": "320086", + "text": "BHI loc_4422", + "mnemonic": "BHI", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [], + "notes": [] + } + }, + { + "address": 17308, + "address_region": "program_or_external", + "bytes": "15FB03F7", + "text": "BTST.B #7, @H'FB03", + "mnemonic": "BTST.B", + "operands": "#7, @H'FB03", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64259, + "name": null, + "symbol": "ram_FB03", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17308, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17312, + "address_region": "program_or_external", + "bytes": "36007F", + "text": "BNE loc_4422", + "mnemonic": "BNE", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17308, + "changes": [], + "notes": [] + } + }, + { + "address": 17315, + "address_region": "program_or_external", + "bytes": "1DF73683", + "text": "MOV:G.W @H'F736, R3", + "mnemonic": "MOV:G.W", + "operands": "@H'F736, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63286, + "name": null, + "symbol": "ram_F736", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17315, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 unknown after memory load" + ] + } + }, + { + "address": 17319, + "address_region": "program_or_external", + "bytes": "370078", + "text": "BEQ loc_4422", + "mnemonic": "BEQ", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17315, + "changes": [], + "notes": [] + } + }, + { + "address": 17322, + "address_region": "program_or_external", + "bytes": "1DF69E84", + "text": "MOV:G.W @H'F69E, R4", + "mnemonic": "MOV:G.W", + "operands": "@H'F69E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63134, + "name": null, + "symbol": "ram_F69E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 17326, + "address_region": "program_or_external", + "bytes": "1DF6BE34", + "text": "SUB.W @H'F6BE, R4", + "mnemonic": "SUB.W", + "operands": "@H'F6BE, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63166, + "name": null, + "symbol": "ram_F6BE", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 17330, + "address_region": "program_or_external", + "bytes": "ABDF", + "text": "BCLR.W #15, R3", + "mnemonic": "BCLR.W", + "operands": "#15, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17332, + "address_region": "program_or_external", + "bytes": "2619", + "text": "BNE loc_43CF", + "mnemonic": "BNE", + "operands": "loc_43CF", + "kind": "branch", + "targets": [ + 17359 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [], + "notes": [] + } + }, + { + "address": 17334, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17334, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17336, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_43DB", + "mnemonic": "BNE", + "operands": "loc_43DB", + "kind": "branch", + "targets": [ + 17371 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17334, + "changes": [], + "notes": [] + } + }, + { + "address": 17338, + "address_region": "program_or_external", + "bytes": "ABDD", + "text": "BCLR.W #13, R3", + "mnemonic": "BCLR.W", + "operands": "#13, R3", + "kind": "normal", + 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"block": 17467, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17471, + "address_region": "program_or_external", + "bytes": "5C0002", + "text": "MOV:I.W #H'0002, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0002, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17467, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R4" + } + } + ], + "notes": [ + "R4 = 0x0002" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R4" + } + } + } + } + }, + { + "address": 17474, + "address_region": "program_or_external", + "bytes": "2012", + "text": "BRA loc_4456", + "mnemonic": "BRA", + "operands": "loc_4456", + "kind": "jump", + "targets": [ + 17494 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17467, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R4" + } + } + } + } + }, + { + "address": 17476, + "address_region": "program_or_external", + "bytes": "15F6F70680", + "text": "MOV:G.B #H'80, @H'F6F7", + "mnemonic": "MOV:G.B", + "operands": "#H'80, @H'F6F7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63223, + "name": null, + "symbol": "ram_F6F7", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17476, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17481, + "address_region": "program_or_external", + "bytes": "5C0000", + "text": "MOV:I.W #H'0000, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17476, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R4" + } + } + ], + "notes": [ + "R4 = 0x0000" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R4" + } + } + } + } + }, + { + "address": 17484, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA loc_4456", + "mnemonic": "BRA", + "operands": "loc_4456", + "kind": "jump", + "targets": [ + 17494 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction 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"kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17491, + "address_region": "program_or_external", + "bytes": "5C0001", + "text": "MOV:I.W #H'0001, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0001, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17486, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + ], + "notes": [ + "R4 = 0x0001" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + } + } + }, + { + "address": 17494, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17494, + "changes": [], + "notes": [] + } + }, + { + "address": 17495, + "address_region": "program_or_external", + "bytes": "15F7310401", + "text": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "operands": "#H'01, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17495, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17500, + "address_region": "program_or_external", + "bytes": "320086", + "text": "BHI loc_44E5", + "mnemonic": "BHI", + "operands": "loc_44E5", + "kind": "branch", + "targets": [ + 17637 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17495, + "changes": [], + "notes": [] + } + }, + { + "address": 17503, + "address_region": "program_or_external", + "bytes": "15FB03F7", + "text": "BTST.B #7, @H'FB03", + "mnemonic": "BTST.B", + "operands": "#7, @H'FB03", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64259, + "name": null, + "symbol": "ram_FB03", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17503, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17507, + "address_region": "program_or_external", + "bytes": "36007F", + "text": "BNE loc_44E5", + "mnemonic": "BNE", + "operands": "loc_44E5", + "kind": "branch", + "targets": [ + 17637 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17503, + "changes": [], + "notes": [] + } + }, + { + "address": 17510, + "address_region": "program_or_external", + "bytes": "1DF73883", + "text": "MOV:G.W @H'F738, R3", + "mnemonic": "MOV:G.W", + "operands": "@H'F738, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63288, + "name": null, + "symbol": "ram_F738", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17510, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 unknown after memory load" + ] + } + }, + { + "address": 17514, + "address_region": "program_or_external", + "bytes": "370078", + "text": "BEQ loc_44E5", + "mnemonic": "BEQ", + "operands": "loc_44E5", + "kind": "branch", + "targets": [ + 17637 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17510, + "changes": [], + "notes": [] + } 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memory load" + ] + } + }, + { + "address": 17521, + "address_region": "program_or_external", + "bytes": "1DF6BC34", + "text": "SUB.W @H'F6BC, R4", + "mnemonic": "SUB.W", + "operands": "@H'F6BC, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63164, + "name": null, + "symbol": "ram_F6BC", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17517, + "changes": [], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 17525, + "address_region": "program_or_external", + "bytes": "ABDF", + "text": "BCLR.W #15, R3", + "mnemonic": "BCLR.W", + "operands": "#15, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17517, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17527, + "address_region": "program_or_external", + "bytes": "2619", + "text": "BNE loc_4492", + "mnemonic": "BNE", + "operands": "loc_4492", + "kind": "branch", + "targets": [ + 17554 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17517, + "changes": [], + "notes": [] + } + }, + { + "address": 17529, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17531, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_449E", + "mnemonic": "BNE", + "operands": "loc_449E", + "kind": "branch", + "targets": [ + 17566 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [], + "notes": [] + } + }, + { + "address": 17533, + "address_region": "program_or_external", + "bytes": "ABDD", + "text": "BCLR.W #13, R3", + "mnemonic": "BCLR.W", + "operands": "#13, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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@H'E9EC", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 59884, + "name": null, + "symbol": "mem_E9EC", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [], + "notes": [] + } + }, + { + "address": 18721, + "address_region": "program_or_external", + "bytes": "5280", + "text": "MOV:E.B #H'80, R2", + "mnemonic": "MOV:E.B", + "operands": "#H'80, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + } + } + ], + "notes": [ + "R2 = 0x80" + ], + "known_after": { + "registers": { + "R2": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + } + } + } + } + }, + { + "address": 18723, + "address_region": "program_or_external", + "bytes": "5B00F6", + "text": "MOV:I.W #H'00F6, R3", + "mnemonic": "MOV:I.W", + "operands": "#H'00F6, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 246, + "hex": "0x00F6", + "width": 16, + "source": "MOV:I.W #H'00F6, R3" + } + } + ], + "notes": [ + "R3 = 0x00F6" + ], + "known_after": { + "registers": { + "R2": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "R3": { + "known": true, + "value": 246, + "hex": "0x00F6", + "width": 16, + "source": "MOV:I.W #H'00F6, R3" + } + } + } + } + }, + { + "address": 18726, + "address_region": "program_or_external", + "bytes": "1EF52B", + "text": "BSR loc_3E54", + "mnemonic": "BSR", + "operands": "loc_3E54", + "kind": "call", + "targets": [ + 15956 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:AND.W" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": true, + "value": 246, + "hex": "0x00F6", + "width": 16, + "source": "MOV:I.W #H'00F6, R3" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 18729, + "address_region": "program_or_external", + "bytes": "15F76EF6", + "text": "BTST.B #6, @H'F76E", + "mnemonic": "BTST.B", + "operands": "#6, @H'F76E", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63342, + "name": null, + "symbol": "ram_F76E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18729, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 18733, + "address_region": "program_or_external", + "bytes": "260E", + "text": "BNE loc_493D", + "mnemonic": "BNE", + "operands": "loc_493D", + "kind": "branch", + "targets": [ + 18749 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18729, + "changes": [], + "notes": [] + } + }, + { + "address": 18735, + "address_region": "program_or_external", + "bytes": "15F73280", + "text": "MOV:G.B @H'F732, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F732, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63282, + "name": null, + "symbol": "ram_F732", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 18739, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 18741, + "address_region": "program_or_external", + "bytes": "A01A", + "text": "SHLL.B R0", + "mnemonic": "SHLL.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 18743, + "address_region": "program_or_external", + "bytes": "F8493E80", + "text": "MOV:G.W @(H'493E,R0), R0", + "mnemonic": "MOV:G.W", + "operands": "@(H'493E,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 18747, + "address_region": "program_or_external", + "bytes": "11D8", + "text": "JSR @R0", + "mnemonic": "JSR", + "operands": "@R0", + "kind": "call", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 1, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 3, + "entry_address": 18756, + "target": 25292, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 4, + "entry_address": 18758, + "target": 25268, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 5, + "entry_address": 18760, + "target": 25248, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 6, + "entry_address": 18762, + "target": 25224, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 7, + "entry_address": 18764, + "target": 25205, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 18766, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 9, + "entry_address": 18768, + "target": 33086, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 10, + "entry_address": 18770, + "target": 33062, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 11, + "entry_address": 18772, + "target": 33042, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 12, + "entry_address": 18774, + "target": 33022, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (1/52 decoded targets)" + }, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 18749, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": 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"base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22775, + "changes": [], + "notes": [] + } + }, + { + "address": 22890, + "address_region": "program_or_external", + "bytes": "4000", + "text": "CMP:E #H'00, R0", + "mnemonic": "CMP:E", + "operands": "#H'00, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22890, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 22892, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_5978", + "mnemonic": "BEQ", + "operands": "loc_5978", + "kind": "branch", + "targets": [ + 22904 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22890, + "changes": [], + "notes": [] + } + }, + { + "address": 22894, + "address_region": "program_or_external", + "bytes": "4001", + "text": "CMP:E #H'01, R0", + "mnemonic": "CMP:E", + "operands": "#H'01, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22894, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 22896, + "address_region": "program_or_external", + "bytes": "270B", + "text": "BEQ loc_597D", + "mnemonic": "BEQ", + "operands": "loc_597D", + "kind": "branch", + "targets": [ + 22909 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22894, + "changes": [], + "notes": [] + } + }, + { + "address": 22898, + "address_region": "program_or_external", + "bytes": "4002", + "text": "CMP:E #H'02, R0", + "mnemonic": "CMP:E", + "operands": "#H'02, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22898, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 22900, + "address_region": "program_or_external", + "bytes": "270C", + "text": "BEQ loc_5982", + "mnemonic": "BEQ", + "operands": "loc_5982", + "kind": "branch", + "targets": [ + 22914 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22898, + "changes": [], + "notes": [] + } + }, + { + "address": 22902, + "address_region": "program_or_external", + "bytes": "200F", + "text": "BRA loc_5987", + "mnemonic": "BRA", + "operands": "loc_5987", + "kind": "jump", + "targets": [ + 22919 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22902, + "changes": [], + "notes": [] + } + }, + { + "address": 22904, + "address_region": "program_or_external", + "bytes": "5C0083", + "text": "MOV:I.W #H'0083, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0083, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + 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tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22904, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 131, + "hex": "0x0083", + "width": 16, + "source": "MOV:I.W #H'0083, R4" + } + } + } + } + }, + { + "address": 22909, + "address_region": "program_or_external", + "bytes": "5C00C3", + "text": "MOV:I.W #H'00C3, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'00C3, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22909, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + 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"changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 195, + "hex": "0x00C3", + "width": 16, + "source": "MOV:I.W #H'00C3, R4" + } + } + } + } + }, + { + "address": 22914, + "address_region": "program_or_external", + "bytes": "5C0093", + "text": "MOV:I.W #H'0093, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0093, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22914, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0093" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + } + } + } + }, + { + "address": 22917, + "address_region": "program_or_external", + "bytes": "2003", + "text": "BRA loc_598A", + "mnemonic": "BRA", + "operands": "loc_598A", + "kind": "jump", + "targets": [ + 22922 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22914, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + } + } + } + }, + { + "address": 22919, + "address_region": "program_or_external", + "bytes": "5C00D3", + "text": "MOV:I.W #H'00D3, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'00D3, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22919, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 211, + "hex": "0x00D3", + "width": 16, + "source": "MOV:I.W #H'00D3, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x00D3" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 211, + "hex": "0x00D3", + "width": 16, + "source": "MOV:I.W #H'00D3, R4" + } + } + } + } + }, + { + "address": 22922, + "address_region": "program_or_external", + "bytes": "15F75B24", + "text": "ADD:G.B @H'F75B, R4", + "mnemonic": "ADD:G.B", + "operands": "@H'F75B, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63323, + "name": null, + "symbol": "ram_F75B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 22926, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 22929, + "address_region": "program_or_external", + "bytes": "1EE538", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" 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"known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 22932, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [], + "notes": [] + } + }, + { + "address": 23162, + "address_region": "program_or_external", + "bytes": "15F72616", + "text": "TST.B @H'F726", + "mnemonic": "TST.B", + "operands": "@H'F726", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables 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"base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 29013, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 29033, + "address_region": "program_or_external", + "bytes": "5D0002", + "text": "MOV:I.W #H'0002, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0002, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 29013, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": 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29013, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 29039, + "address_region": "program_or_external", + "bytes": "1EF063", + "text": "BSR loc_61D5", + "mnemonic": "BSR", + "operands": "loc_61D5", + "kind": "call", + "targets": [ + 25045 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 29013, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 29042, + "address_region": "program_or_external", + "bytes": "5D0003", + "text": "MOV:I.W #H'0003, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0003, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 29013, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 3, + "hex": "0x0003", + "width": 16, + "source": "MOV:I.W #H'0003, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + 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"address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 29013, + "changes": [], + "notes": [] + } + }, + { + "address": 37642, + "address_region": "program_or_external", + "bytes": "5B931C", + "text": "MOV:I.W #H'931C, R3", + "mnemonic": "MOV:I.W", + "operands": "#H'931C, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + 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"control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47658, + "address_region": "program_or_external", + "bytes": "26FA", + "text": "BNE loc_BA26", + "mnemonic": "BNE", + "operands": "loc_BA26", + "kind": "branch", + "targets": [ + 47654 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47654, + "changes": [], + "notes": [] + } + }, + { + "address": 47660, + "address_region": "program_or_external", + "bytes": "15F9C00664", + "text": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'64, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47665, + "address_region": "program_or_external", + "bytes": "15F9C40607", + "text": "MOV:G.B #H'07, @H'F9C4", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @H'F9C4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63940, + "name": null, + "symbol": "ram_F9C4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47670, + "address_region": "program_or_external", + "bytes": "1DF85080", + "text": "MOV:G.W @H'F850, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F850, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47674, + "address_region": "program_or_external", + "bytes": "1DF85890", + "text": "MOV:G.W R0, @H'F858", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F858", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47674, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47678, + "address_region": "program_or_external", + "bytes": "1DF85280", + "text": "MOV:G.W @H'F852, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F852, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47682, + "address_region": "program_or_external", + "bytes": "1DF85A90", + "text": "MOV:G.W R0, @H'F85A", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F85A", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47682, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47686, + "address_region": "program_or_external", + "bytes": "15F85480", + "text": "MOV:G.B @H'F854, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F854, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47690, + "address_region": "program_or_external", + "bytes": "15F85C90", + "text": "MOV:G.B R0, @H'F85C", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85C", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47690, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47694, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47694, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_checksum_seed", + "evidence_summary": "candidate TX checksum starts from seed H'005A", + "evidence_addresses": [ + 47694 + ], + "evidence_addresses_hex": [ + "H'BA4E" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 47696, + "address_region": "program_or_external", + "bytes": "15F85860", + "text": "XOR.B @H'F858, R0", + "mnemonic": "XOR.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47700, + "address_region": "program_or_external", + "bytes": "15F85960", + "text": "XOR.B @H'F859, R0", + "mnemonic": "XOR.B", + "operands": "@H'F859, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63577, + "name": null, + "symbol": "ram_F859", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47704, + "address_region": "program_or_external", + "bytes": "15F85A60", + "text": "XOR.B @H'F85A, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47708, + "address_region": "program_or_external", + "bytes": "15F85B60", + "text": "XOR.B @H'F85B, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85B, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63579, + "name": null, + "symbol": "ram_F85B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47712, + "address_region": "program_or_external", + "bytes": "15F85C60", + "text": "XOR.B @H'F85C, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47716, + "address_region": "program_or_external", + "bytes": "15F85D90", + "text": "MOV:G.B R0, @H'F85D", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85D", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63581, + "name": null, + "symbol": "ram_F85D", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "checksum_byte", + "evidence_summary": "candidate checksum byte write targets H'F85D", + "evidence_addresses": [ + 47716 + ], + "evidence_addresses_hex": [ + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47720, + "address_region": "program_or_external", + "bytes": "15FEDCF7", + "text": "BTST.B #7, @SCI1_SSR", + "mnemonic": "BTST.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + } + ], + "board_profile": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47720, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47724, + "address_region": "program_or_external", + "bytes": "27FA", + "text": "BEQ loc_BA68", + "mnemonic": "BEQ", + "operands": "loc_BA68", + "kind": "branch", + "targets": [ + 47720 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + } + ], + "dataflow": { + "block": 47720, + "changes": [], + "notes": [] + } + }, + { + "address": 47726, + "address_region": "program_or_external", + "bytes": "15F85880", + "text": "MOV:G.B @H'F858, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47730, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47730, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47734, + "address_region": "program_or_external", + "bytes": "15F9C20601", + "text": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47734, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_initialized_to_one", + "evidence_summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "evidence_addresses": [ + 47734 + ], + "evidence_addresses_hex": [ + "H'BA76" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47739, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47743, + "address_region": "program_or_external", + "bytes": "15FEDAC7", + "text": "BSET.B #7, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + } + ] + }, + "sci_protocol": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47747, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47748, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47752, + "address_region": "program_or_external", + "bytes": "271F", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [], + "notes": [] + } + }, + { + "address": 47754, + "address_region": "program_or_external", + "bytes": "15FAA5F7", + "text": "BTST.B #7, @H'FAA5", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64165, + "name": null, + "symbol": "ram_FAA5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47758, + "address_region": "program_or_external", + "bytes": "2719", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [], + "notes": [] + } + }, + { + "address": 47760, + "address_region": "program_or_external", + "bytes": "15F9C316", + "text": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47764, + "address_region": "program_or_external", + "bytes": "2713", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [], + "notes": [] + } + }, + { + "address": 47766, + "address_region": "program_or_external", + "bytes": "15FAA2D3", + "text": "BCLR.B #3, @H'FAA2", + "mnemonic": "BCLR.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47770, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47774, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47778, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47783, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BAF1", + "mnemonic": "BRA", + "operands": "loc_BAF1", + "kind": "jump", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47785, + "address_region": "program_or_external", + "bytes": "BF90", + "text": "MOV:G.W R0, @-R7", + "mnemonic": "MOV:G.W", + "operands": "R0, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47787, + "address_region": "program_or_external", + "bytes": "15F9C280", + "text": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47787, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47791, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47793, + "address_region": "program_or_external", + "bytes": "F0F85880", + "text": "MOV:G.B @(-H'07A8,R0), R0", + "mnemonic": "MOV:G.B", + "operands": "@(-H'07A8,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47793, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47797, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47797, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47801, + "address_region": "program_or_external", + "bytes": "CF80", + "text": "MOV:G.W @R7+, R0", + "mnemonic": "MOV:G.W", + "operands": "@R7+, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47803, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47807, + "address_region": "program_or_external", + "bytes": "15F9C208", + "text": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47807, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_increment", + "evidence_summary": "candidate TX ISR increments TX index H'F9C2", + "evidence_addresses": [ + 47807 + ], + "evidence_addresses_hex": [ + "H'BABF" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47811, + "address_region": "program_or_external", + "bytes": "15F9C20406", + "text": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47811, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_compare_frame_length", + "evidence_summary": "candidate TX ISR compares TX index to frame length 6", + "evidence_addresses": [ + 47811 + ], + "evidence_addresses_hex": [ + "H'BAC3" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47816, + "address_region": "program_or_external", + "bytes": "2627", + "text": "BNE loc_BAF1", + "mnemonic": "BNE", + "operands": "loc_BAF1", + "kind": "branch", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47818, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47818, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47822, + "address_region": "program_or_external", + "bytes": "15F795F6", + "text": "BTST.B #6, @H'F795", + "mnemonic": "BTST.B", + "operands": "#6, @H'F795", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63381, + "name": null, + "symbol": "ram_F795", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47826, + "address_region": "program_or_external", + "bytes": "2614", + "text": "BNE loc_BAE8", + "mnemonic": "BNE", + "operands": "loc_BAE8", + "kind": "branch", + "targets": [ + 47848 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47828, + "address_region": "program_or_external", + "bytes": "15F791F7", + "text": "BTST.B #7, @H'F791", + "mnemonic": "BTST.B", + "operands": "#7, @H'F791", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63377, + "name": null, + "symbol": "ram_F791", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47832, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_BAE1", + "mnemonic": "BNE", + "operands": "loc_BAE1", + "kind": "branch", + "targets": [ + 47841 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [], + "notes": [] + } + }, + { + "address": 47834, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47839, + "address_region": "program_or_external", + "bytes": "200C", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [], + "notes": [] + } + }, + { + "address": 47841, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47846, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [], + "notes": [] + } + }, + { + "address": 47848, + "address_region": "program_or_external", + "bytes": "15F9C006F0", + "text": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47848, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47853, + "address_region": "program_or_external", + "bytes": "15F9C113", + "text": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47853, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47857, + "address_region": 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"R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "unsupported:OR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 47915, + "address_region": "program_or_external", + "bytes": "15F85195", + "text": "MOV:G.B R5, @H'F851", + "mnemonic": "MOV:G.B", + "operands": "R5, @H'F851", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63569, + "name": null, + "symbol": "ram_F851", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47919, + "address_region": "program_or_external", + "bytes": "0C01FF50", + "text": "AND.W #H'01FF, R0", + "mnemonic": "AND.W", + "operands": "#H'01FF, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:AND.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47923, + "address_region": "program_or_external", + "bytes": "A81A", + "text": "SHLL.W R0", + "mnemonic": "SHLL.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:AND.W" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47925, + "address_region": "program_or_external", + "bytes": "F8E80084", + "text": "MOV:G.W @(-H'1800,R0), R4", + "mnemonic": "MOV:G.W", + "operands": "@(-H'1800,R0), R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 47929, + "address_region": "program_or_external", + "bytes": "15F85494", + "text": "MOV:G.B R4, @H'F854", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47933, + "address_region": "program_or_external", + "bytes": "A410", + "text": "SWAP.B R4", + "mnemonic": "SWAP.B", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 47935, + "address_region": "program_or_external", + "bytes": "15F85394", + "text": "MOV:G.B R4, @H'F853", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F853", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63571, + "name": null, + "symbol": "ram_F853", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47939, + "address_region": "program_or_external", + "bytes": "1EFEE0", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.W" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:OR.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 47942, + "address_region": "program_or_external", + "bytes": "1DF9C60701F4", + "text": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "operands": "#H'01F4, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47948, + "address_region": "program_or_external", + "bytes": "15F9C80614", + "text": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47953, + "address_region": "program_or_external", + "bytes": "15FAA30680", + "text": "MOV:G.B #H'80, @H'FAA3", + "mnemonic": "MOV:G.B", + "operands": "#H'80, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47958, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47958, + "changes": [], + "notes": [] + } + }, + { + "address": 47959, + "address_region": "program_or_external", + "bytes": "15FAA4C7", + "text": "BSET.B #7, @H'FAA4", + "mnemonic": "BSET.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47959, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "dataflow": { + "block": 47959, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47963, + "address_region": "program_or_external", + "bytes": "15FEDCD5", + "text": "BCLR.B #5, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#5, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear ORER (bit 5) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + } + ], + "serial_reconstruction": [ + { + "address": 47963, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47967, + "address_region": "program_or_external", + "bytes": "15FEDCD4", + "text": "BCLR.B #4, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#4, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear FER (bit 4) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + } + ], + "serial_reconstruction": [ + { + "address": 47967, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47971, + "address_region": "program_or_external", + "bytes": "15FEDCD3", + "text": "BCLR.B #3, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#3, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear PER (bit 3) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + } + ], + "serial_reconstruction": [ + { + "address": 47971, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47975, + "address_region": "program_or_external", + "bytes": "1203", + "text": "STM.W {R0,R1}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R1}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47977, + "address_region": "program_or_external", + "bytes": "15FEDCD6", + "text": "BCLR.B #6, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#6, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear RDRF (bit 6) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + } + ], + "serial_reconstruction": [ + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47981, + "address_region": "program_or_external", + "bytes": "15FEDD80", + "text": "MOV:G.B @SCI1_RDR, R0", + "mnemonic": "MOV:G.B", + "operands": "@SCI1_RDR, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65245, + "name": "SCI1_RDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdr_read", + "evidence_summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "evidence_addresses": [ + 47981 + ], + "evidence_addresses_hex": [ + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47985, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47989, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BB7D", + "mnemonic": "BNE", + "operands": "loc_BB7D", + "kind": "branch", + "targets": [ + 47997 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47991, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47995, + "address_region": "program_or_external", + "bytes": "200D", + "text": "BRA loc_BB8A", + "mnemonic": "BRA", + "operands": "loc_BB8A", + "kind": "jump", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [], + "notes": [] + } + }, + { + "address": 47997, + "address_region": "program_or_external", + "bytes": "15F9C30405", + "text": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'05, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48002, + "address_region": "program_or_external", + "bytes": "2306", + "text": "BLS loc_BB8A", + "mnemonic": "BLS", + "operands": "loc_BB8A", + "kind": "branch", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [], + "notes": [] + } + }, + { + "address": 48004, + "address_region": "program_or_external", + "bytes": "15FAA413", + "text": "CLR.B @H'FAA4", + "mnemonic": "CLR.B", + "operands": "@H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48008, + "address_region": "program_or_external", + "bytes": "2019", + "text": "BRA loc_BBA3", + "mnemonic": "BRA", + "operands": "loc_BBA3", + "kind": "jump", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [], + "notes": [] + } + }, + { + "address": 48010, + "address_region": "program_or_external", + "bytes": "15F9C381", + "text": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C3, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 48014, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 48016, + "address_region": "program_or_external", + "bytes": "F1F86890", + "text": "MOV:G.B R0, @(-H'0798,R1)", + "mnemonic": "MOV:G.B", + "operands": "R0, @(-H'0798,R1)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48016, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_indexed_store", + "evidence_summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "evidence_addresses": [ + 48016 + ], + "evidence_addresses_hex": [ + "H'BB90" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48020, + "address_region": "program_or_external", + "bytes": "A108", + "text": "ADD:Q.B #1, R1", + "mnemonic": "ADD:Q.B", + "operands": "#1, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48020, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 48022, + "address_region": "program_or_external", + "bytes": "15F9C391", + "text": "MOV:G.B R1, @H'F9C3", + "mnemonic": "MOV:G.B", + "operands": "R1, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48022, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48026, + "address_region": "program_or_external", + "bytes": "4106", + "text": "CMP:E #H'06, R1", + "mnemonic": "CMP:E", + "operands": "#H'06, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48026, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_isr_compare_frame_length", + "evidence_summary": "RX ISR compares incremented count to candidate frame length 6", + "evidence_addresses": [ + 48026 + ], + "evidence_addresses_hex": [ + "H'BB9A" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48028, + "address_region": "program_or_external", + "bytes": "2605", + "text": "BNE loc_BBA3", + "mnemonic": "BNE", + "operands": "loc_BBA3", + "kind": "branch", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48030, + "address_region": "program_or_external", + "bytes": "15F9C50614", + "text": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48030, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_complete_timer", + "evidence_summary": "RX ISR sets H'F9C5 after count reaches 6", + "evidence_addresses": [ + 48030 + ], + "evidence_addresses_hex": [ + "H'BB9E" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high" + } + ], + "dataflow": { + "block": 48030, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48035, + "address_region": "program_or_external", + "bytes": "15F9C10605", + "text": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "operands": "#H'05, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48040, + "address_region": "program_or_external", + "bytes": "0203", + "text": "LDM.W @SP+, {R0,R1}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R1}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R1" + ] + } + }, + { + "address": 48042, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [], + "notes": [] + } + }, + { + "address": 48043, + "address_region": "program_or_external", + "bytes": "15F9C30406", + "text": "CMP:G.B #H'06, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48043, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_processor_requires_six_bytes", + "evidence_summary": "RX processing path requires H'F9C3 to equal 6", + "evidence_addresses": [ + 48043 + ], + "evidence_addresses_hex": [ + "H'BBAB" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high" + } + ], + "dataflow": { + "block": 48043, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48048, + "address_region": "program_or_external", + "bytes": "3602BC", + "text": "BNE loc_BE6F", + "mnemonic": "BNE", + "operands": "loc_BE6F", + "kind": "branch", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48043, + "changes": [], + "notes": [] + } + }, + { + "address": 48051, + "address_region": "program_or_external", + "bytes": "1DF86880", + "text": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F868, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63592, + "name": null, + "symbol": "ram_F868", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48051, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48055, + "address_region": "program_or_external", + "bytes": "1DF86090", + "text": "MOV:G.W R0, @H'F860", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F860", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48055, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48059, + "address_region": "program_or_external", + "bytes": "1DF86A80", + "text": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63594, + "name": null, + "symbol": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48059, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48063, + "address_region": "program_or_external", + "bytes": "1DF86290", + "text": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F862", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48063, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48067, + "address_region": "program_or_external", + "bytes": "1DF86C80", + "text": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63596, + "name": null, + "symbol": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48067, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48071, + "address_region": "program_or_external", + "bytes": "1DF86490", + "text": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F864", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48071, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48075, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48079, + "address_region": "program_or_external", + "bytes": "15FAA4F7", + "text": "BTST.B #7, @H'FAA4", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48083, + "address_region": "program_or_external", + "bytes": "360253", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48086, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_checksum_seed", + "evidence_summary": "candidate RX checksum validation starts from seed H'005A", + "evidence_addresses": [ + 48086 + ], + "evidence_addresses_hex": [ + "H'BBD6" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high" + }, + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 48088, + "address_region": "program_or_external", + "bytes": "15F86060", + "text": "XOR.B @H'F860, R0", + "mnemonic": "XOR.B", + "operands": "@H'F860, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48088, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48092, + "address_region": "program_or_external", + "bytes": "15F86160", + "text": "XOR.B @H'F861, R0", + "mnemonic": "XOR.B", + "operands": "@H'F861, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48092, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48096, + "address_region": "program_or_external", + "bytes": "15F86260", + "text": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "operands": "@H'F862, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48096, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48100, + "address_region": "program_or_external", + "bytes": "15F86360", + "text": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "operands": "@H'F863, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63587, + "name": null, + "symbol": "ram_F863", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48100, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48104, + "address_region": "program_or_external", + "bytes": "15F86460", + "text": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "operands": "@H'F864, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48104, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48108, + "address_region": "program_or_external", + "bytes": "15F86570", + "text": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "operands": "@H'F865, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63589, + "name": null, + "symbol": "ram_F865", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48108, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48112, + "address_region": "program_or_external", + "bytes": "360236", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48115, + "address_region": "program_or_external", + "bytes": "15FAA613", + "text": "CLR.B @H'FAA6", + "mnemonic": "CLR.B", + "operands": "@H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48119, + "address_region": "program_or_external", + "bytes": "15F86185", + "text": "MOV:G.B @H'F861, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F861, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48123, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 48125, + "address_region": "program_or_external", + "bytes": "15F86285", + "text": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F862, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48129, + "address_region": "program_or_external", + "bytes": "1EA627", + "text": "BSR loc_622B", + "mnemonic": "BSR", + "operands": "loc_622B", + "kind": "call", + "targets": [ + 25131 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + 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+ "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48578, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48578, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48582, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_BDD0", + "mnemonic": "BEQ", + "operands": "loc_BDD0", + "kind": "branch", + "targets": [ + 48592 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48578, + "changes": [], + "notes": [] + } + }, + { + "address": 48584, + "address_region": "program_or_external", + "bytes": "15F9B508", + "text": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48584, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48588, + "address_region": "program_or_external", + "bytes": "15F9B5D7", + "text": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48584, + "changes": [], + "notes": [] + } + }, + { + "address": 48592, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48592, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48596, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48592, + "changes": [], + "notes": [] + } + }, + { + "address": 48600, + "address_region": "program_or_external", + "bytes": "300094", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48592, + "changes": [], + "notes": [] + } + }, + { + "address": 48603, + "address_region": "program_or_external", + "bytes": "15F86380", + "text": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F863, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63587, + "name": null, + "symbol": "ram_F863", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48607, + "address_region": "program_or_external", + "bytes": "A010", + "text": "SWAP.B R0", + "mnemonic": "SWAP.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48609, + "address_region": "program_or_external", + "bytes": "15F86480", + "text": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F864, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48613, + "address_region": "program_or_external", + "bytes": "FCE40090", + "text": "MOV:G.W R0, @(-H'1C00,R4)", + "mnemonic": "MOV:G.W", + "operands": "R0, @(-H'1C00,R4)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48617, + "address_region": "program_or_external", + "bytes": "F5EC00C6", + "text": "BSET.B #6, @(-H'1400,R5)", + "mnemonic": "BSET.B", + "operands": "#6, @(-H'1400,R5)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48621, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48625, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_BDFB", + "mnemonic": "BEQ", + "operands": "loc_BDFB", + "kind": "branch", + "targets": [ + 48635 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48627, + "address_region": "program_or_external", + "bytes": "15F9B508", + "text": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48631, + "address_region": "program_or_external", + "bytes": "15F9B5D7", + "text": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [], + "notes": [] + } + }, + { + "address": 48635, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48639, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48643, + "address_region": "program_or_external", + "bytes": "206A", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48645, + "address_region": "program_or_external", + "bytes": "1DF85880", + "text": "MOV:G.W @H'F858, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48645, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48649, + "address_region": "program_or_external", + "bytes": "1DF85090", + "text": "MOV:G.W R0, @H'F850", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48653, + "address_region": "program_or_external", + "bytes": "1DF85A80", + "text": "MOV:G.W @H'F85A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48653, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48657, + "address_region": "program_or_external", + "bytes": "1DF85290", + "text": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48661, + "address_region": "program_or_external", + "bytes": "1DF85C80", + "text": "MOV:G.W @H'F85C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48661, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48665, + "address_region": "program_or_external", + "bytes": "1DF85490", + "text": "MOV:G.W R0, @H'F854", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48669, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48674, + "address_region": "program_or_external", + "bytes": "1EFC01", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48677, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48679, + "address_region": "program_or_external", + "bytes": "2046", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48679, + "changes": [], + "notes": [] + } + }, + { + "address": 48681, + "address_region": "program_or_external", + "bytes": "15FAA4D7", + "text": "BCLR.B #7, @H'FAA4", + "mnemonic": "BCLR.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48685, + "address_region": "program_or_external", + "bytes": "15FAA5F7", + "text": "BTST.B #7, @H'FAA5", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64165, + "name": null, + "symbol": "ram_FAA5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [], + "notes": [] + } + }, + { + "address": 48689, + "address_region": "program_or_external", + "bytes": "273A", + "text": "BEQ loc_BE6D", + "mnemonic": "BEQ", + "operands": "loc_BE6D", + "kind": "branch", + "targets": [ + 48749 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [], + "notes": [] + } + }, + { + "address": 48691, + "address_region": "program_or_external", + "bytes": "15FAA608", + "text": "ADD:Q.B #1, @H'FAA6", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48691, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48695, + "address_region": "program_or_external", + "bytes": "15FAA60402", + "text": "CMP:G.B #H'02, @H'FAA6", + "mnemonic": "CMP:G.B", + "operands": "#H'02, @H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48691, + "changes": [], + "notes": [] + } + }, + { + "address": 48700, + "address_region": "program_or_external", + "bytes": "250F", + "text": "BCS loc_BE4D", + "mnemonic": "BCS", + "operands": "loc_BE4D", + "kind": "branch", + "targets": [ + 48717 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48691, + "changes": [], + "notes": [] + } + }, + { + "address": 48702, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48702, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48707, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48702, + "changes": [], + "notes": [] + } + }, + { + "address": 48711, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48702, + "changes": [], + "notes": [] + } + }, + { + "address": 48715, + "address_region": "program_or_external", + "bytes": "2020", + "text": "BRA loc_BE6D", + "mnemonic": "BRA", + "operands": "loc_BE6D", + "kind": "jump", + "targets": [ + 48749 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48702, + "changes": [], + "notes": [] + } + }, + { + "address": 48717, + "address_region": "program_or_external", + "bytes": "15F8500607", + "text": "MOV:G.B #H'07, @H'F850", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48722, + "address_region": "program_or_external", + "bytes": "15F86180", + "text": "MOV:G.B @H'F861, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F861, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48726, + "address_region": "program_or_external", + "bytes": "15F85190", + "text": "MOV:G.B R0, @H'F851", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F851", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, 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invalidated R0" + ] + } + }, + { + "address": 48809, + "address_region": "program_or_external", + "bytes": "15FAA390", + "text": "MOV:G.B R0, @H'FAA3", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48798, + "changes": [], + "notes": [] + } + }, + { + "address": 48813, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BEB5", + "mnemonic": "BNE", + "operands": "loc_BEB5", + "kind": "branch", + "targets": [ + 48821 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48798, + "changes": [], + "notes": [] + } + }, + { + "address": 48815, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48815, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48819, + "address_region": "program_or_external", + "bytes": "2033", + "text": "BRA loc_BEE8", + "mnemonic": "BRA", + "operands": "loc_BEE8", + "kind": "jump", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48815, + "changes": [], + "notes": [] + } + }, + { + "address": 48821, + "address_region": "program_or_external", + "bytes": "1DF9C616", + "text": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "operands": "@H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48821, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48825, + "address_region": "program_or_external", + "bytes": "262D", + "text": "BNE loc_BEE8", + "mnemonic": "BNE", + "operands": "loc_BEE8", + "kind": "branch", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48821, + "changes": [], + "notes": [] + } + }, + { + "address": 48827, + "address_region": "program_or_external", + "bytes": "15F9C816", + "text": "TST.B @H'F9C8", + "mnemonic": "TST.B", + "operands": "@H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48827, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48831, + "address_region": "program_or_external", + "bytes": "2723", + "text": "BEQ loc_BEE4", + "mnemonic": "BEQ", + "operands": "loc_BEE4", + "kind": "branch", + "targets": [ + 48868 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48827, + "changes": [], + "notes": [] + } + }, + { + "address": 48833, + "address_region": "program_or_external", + "bytes": "15F9C80C", + "text": "ADD:Q.B #-1, @H'F9C8", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48837, + "address_region": "program_or_external", + "bytes": "1DF9C60701F4", + "text": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "operands": "#H'01F4, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [], + "notes": [] + } + }, + { + "address": 48843, + "address_region": "program_or_external", + "bytes": "15FAA3F7", + "text": "BTST.B #7, @H'FAA3", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [], + "notes": [] + } + }, + { + "address": 48847, + "address_region": "program_or_external", + "bytes": "2717", + "text": "BEQ loc_BEE8", + "mnemonic": "BEQ", + "operands": "loc_BEE8", + "kind": "branch", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [], + "notes": [] + } + }, + { + "address": 48849, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48853, + "address_region": "program_or_external", + "bytes": "1EFB4E", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48856, + "address_region": "program_or_external", + "bytes": "200E", + "text": "BRA loc_BEE8", + "mnemonic": "BRA", + "operands": "loc_BEE8", + "kind": "jump", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [], + "notes": [] + } + }, + { + "address": 48868, + "address_region": "program_or_external", + "bytes": "15F9C513", + "text": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "operands": "@H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48868, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48872, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48872, + "changes": [], + "notes": [] + } + }, + { + "address": 48874, + "address_region": "program_or_external", + "bytes": "15FE91D5", + "text": "BCLR.B #5, @FRT1_TCSR", + "mnemonic": "BCLR.B", + "operands": "#5, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear OCFA (bit 5) of FRT1_TCSR", + "valid": true, + "serial_reconstruction": [ + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48878, + "address_region": "program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48878, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48882, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BEF8", + "mnemonic": "BEQ", + "operands": "loc_BEF8", + "kind": "branch", + "targets": [ + 48888 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48884, + "address_region": "program_or_external", + "bytes": "15F9C00C", + "text": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48884, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48884, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48888, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48888, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48888, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48892, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF02", + "mnemonic": "BEQ", + "operands": "loc_BF02", + "kind": "branch", + "targets": [ + 48898 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48888, + "changes": [], + "notes": [] + } + }, + { + "address": 48894, + "address_region": "program_or_external", + "bytes": "15F9C10C", + "text": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48894, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48894, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48898, + "address_region": "program_or_external", + "bytes": "1DF9C616", + "text": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "operands": "@H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48898, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48898, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48902, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF0C", + "mnemonic": "BEQ", + "operands": "loc_BF0C", + "kind": "branch", + "targets": [ + 48908 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48898, + "changes": [], + "notes": [] + } + }, + { + "address": 48904, + "address_region": "program_or_external", + "bytes": "1DF9C60C", + "text": "ADD:Q.W #-1, @H'F9C6", + "mnemonic": "ADD:Q.W", + "operands": "#-1, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48904, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48904, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48908, + "address_region": "program_or_external", + "bytes": "15F6F6F7", + "text": "BTST.B #7, @H'F6F6", + "mnemonic": "BTST.B", + "operands": "#7, @H'F6F6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63222, + "name": null, + "symbol": "ram_F6F6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48908, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48912, + "address_region": "program_or_external", + "bytes": "2710", + "text": "BEQ loc_BF22", + "mnemonic": "BEQ", + "operands": "loc_BF22", + "kind": "branch", + "targets": [ + 48930 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48908, + "changes": [], + "notes": [] + } + }, + { + "address": 48914, + "address_region": "program_or_external", + "bytes": "1DF6F416", + "text": "TST.W @H'F6F4", + "mnemonic": "TST.W", + "operands": "@H'F6F4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 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"15F6F6C5", + "text": "BSET.B #5, @H'F6F6", + "mnemonic": "BSET.B", + "operands": "#5, @H'F6F6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63222, + "name": null, + "symbol": "ram_F6F6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48920, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48924, + "address_region": "program_or_external", + "bytes": "2004", + "text": "BRA loc_BF22", + "mnemonic": "BRA", + "operands": "loc_BF22", + "kind": "jump", + "targets": [ + 48930 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48920, + "changes": [], + "notes": [] + } + }, + { + "address": 48926, + "address_region": "program_or_external", + "bytes": "1DF6F40C", + "text": "ADD:Q.W #-1, @H'F6F4", + "mnemonic": "ADD:Q.W", + "operands": "#-1, @H'F6F4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63220, + "name": null, + "symbol": "ram_F6F4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48926, + "changes": [ + { + "kind": "control", + "name": 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instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65185, + "name": "FRT2_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear OCFA (bit 5) of FRT2_TCSR", + "valid": true, + "dataflow": { + "block": 48931, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48935, + "address_region": "program_or_external", + "bytes": "15F9C416", + "text": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "operands": "@H'F9C4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63940, + "name": null, + "symbol": "ram_F9C4", + "region": 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"manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63940, + "name": null, + "symbol": "ram_F9C4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48941, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48945, + "address_region": "program_or_external", + "bytes": "15F9C516", + "text": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "operands": "@H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": 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"not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49031, + "changes": [], + "notes": [] + } + }, + { + "address": 49037, + "address_region": "program_or_external", + "bytes": "15F713D6", + "text": "BCLR.B #6, @H'F713", + "mnemonic": "BCLR.B", + "operands": "#6, @H'F713", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63251, + "name": null, + "symbol": "ram_F713", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49037, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49041, + "address_region": "program_or_external", + "bytes": "2610", + "text": "BNE loc_BFA3", + "mnemonic": "BNE", + "operands": "loc_BFA3", + "kind": "branch", + "targets": [ + 49059 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49037, + "changes": [], + "notes": [] + } + }, + { + "address": 49043, + "address_region": "program_or_external", + "bytes": "15F711D7", + "text": "BCLR.B #7, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49047, + "address_region": "program_or_external", + "bytes": "15F711D6", + "text": "BCLR.B #6, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#6, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [], + "notes": [] + } + }, + { + "address": 49051, + "address_region": "program_or_external", + "bytes": "15F711D5", + "text": "BCLR.B #5, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#5, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [], + "notes": [] + } + }, + { + "address": 49055, + "address_region": "program_or_external", + "bytes": "15F711D4", + "text": "BCLR.B #4, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#4, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [], + "notes": [] + } + }, + { + "address": 49059, + "address_region": "program_or_external", + "bytes": "15F79716", + "text": "TST.B @H'F797", + "mnemonic": "TST.B", + "operands": "@H'F797", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63383, + "name": null, + "symbol": "ram_F797", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49059, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49063, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_BFB3", + "mnemonic": "BEQ", + "operands": "loc_BFB3", + "kind": "branch", + "targets": [ + 49075 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49059, + "changes": [], + "notes": [] + } + }, + { + "address": 49065, + "address_region": "program_or_external", + "bytes": "15F7970C", + "text": "ADD:Q.B #-1, @H'F797", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F797", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63383, + "name": null, + "symbol": "ram_F797", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49065, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49069, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_BFB3", + "mnemonic": "BNE", + "operands": "loc_BFB3", + "kind": "branch", + "targets": [ + 49075 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49065, + "changes": [], + "notes": [] + } + }, + { + "address": 49071, + "address_region": "program_or_external", + "bytes": "15F731D7", + "text": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49071, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49075, + "address_region": "program_or_external", + "bytes": "15F79816", + "text": "TST.B @H'F798", + "mnemonic": "TST.B", + "operands": "@H'F798", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63384, + "name": null, + "symbol": "ram_F798", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49075, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49079, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_BFC3", + "mnemonic": "BEQ", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49075, + "changes": [], + "notes": [] + } + }, + { + "address": 49081, + "address_region": "program_or_external", + "bytes": "15F7980C", + "text": "ADD:Q.B #-1, @H'F798", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F798", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63384, + "name": null, + "symbol": "ram_F798", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49085, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_BFC3", + "mnemonic": "BNE", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [], + "notes": [] + } + }, + { + "address": 49087, + "address_region": "program_or_external", + "bytes": "15F731D7", + "text": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49087, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49091, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49091, + "changes": [], + "notes": [] + } + }, + { + "address": 49092, + "address_region": "program_or_external", + "bytes": "15FEECF7", + "text": "BTST.B #7, @WDT_TCSR_R", + "mnemonic": "BTST.B", + "operands": "#7, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49096, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49102, + "address_region": "program_or_external", + "bytes": "15F79408", + "text": "ADD:Q.B #1, @H'F794", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49106, + "address_region": "program_or_external", + "bytes": "15F794040A", + "text": "CMP:G.B #H'0A, @H'F794", + "mnemonic": "CMP:G.B", + "operands": "#H'0A, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49111, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BFDF", + "mnemonic": "BNE", + "operands": "loc_BFDF", + "kind": "branch", + "targets": [ + 49119 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49113, + "address_region": "program_or_external", + "bytes": "1DFEEC07A57F", + "text": "MOV:G.W #H'A57F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A57F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49113, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49119, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49119, + "changes": [], + "notes": [] + } + }, + { + "address": 49120, + "address_region": "program_or_external", + "bytes": "15F840060A", + "text": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "operands": "#H'0A, @H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49120, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49125, + "address_region": "program_or_external", + "bytes": "AD82", + "text": "MOV:G.W R5, R2", + "mnemonic": "MOV:G.W", + "operands": "R5, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after MOV source" + ] + } + }, + { + "address": 49127, + "address_region": "program_or_external", + "bytes": "0E27", + "text": "BSR loc_C010", + "mnemonic": "BSR", + "operands": "loc_C010", + "kind": "call", + "targets": [ + 49168 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49129, + "address_region": "program_or_external", + "bytes": "0E4E", + "text": "BSR loc_C039", + "mnemonic": "BSR", + "operands": "loc_C039", + "kind": "call", + "targets": [ + 49209 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49131, + "address_region": "program_or_external", + "bytes": "AA75", + "text": "CMP:G.W R2, R5", + "mnemonic": "CMP:G.W", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49133, + "address_region": "program_or_external", + "bytes": "270E", + "text": "BEQ loc_BFFD", + "mnemonic": "BEQ", + "operands": "loc_BFFD", + "kind": "branch", + "targets": [ + 49149 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [], + "notes": [] + } + }, + { + "address": 49135, + "address_region": "program_or_external", + "bytes": "15F84016", + "text": "TST.B @H'F840", + "mnemonic": "TST.B", + "operands": "@H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49135, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49139, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BFF9", + "mnemonic": "BEQ", + "operands": "loc_BFF9", + "kind": "branch", + "targets": [ + 49145 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49135, + "changes": [], + "notes": [] + } + }, + { + "address": 49141, + "address_region": "program_or_external", + "bytes": "AA85", + "text": "MOV:G.W R2, R5", + "mnemonic": "MOV:G.W", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49141, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 unknown after MOV source" + ] + } + }, + { + "address": 49143, + "address_region": "program_or_external", + "bytes": "20EC", + "text": "BRA loc_BFE5", + "mnemonic": "BRA", + "operands": "loc_BFE5", + "kind": "jump", + "targets": [ + 49125 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49141, + "changes": [], + "notes": [] + } + }, + { + "address": 49145, + "address_region": "program_or_external", + "bytes": "15F841C7", + "text": "BSET.B #7, @H'F841", + "mnemonic": "BSET.B", + "operands": "#7, @H'F841", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63553, + "name": null, + "symbol": "ram_F841", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49145, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49149, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49149, + "changes": [], + "notes": [] + } + }, + { + "address": 49150, + "address_region": "program_or_external", + "bytes": "15F840060A", + "text": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "operands": "#H'0A, @H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49150, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49155, + "address_region": "program_or_external", + "bytes": "0E34", + "text": "BSR loc_C039", + "mnemonic": "BSR", + "operands": "loc_C039", + "kind": "call", + "targets": [ + 49209 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49150, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", 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"known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49157, + "address_region": "program_or_external", + "bytes": "15F84016", + "text": "TST.B @H'F840", + "mnemonic": "TST.B", + "operands": "@H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49150, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49161, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_C00F", + "mnemonic": "BNE", + "operands": "loc_C00F", + "kind": "branch", + "targets": [ + 49167 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49150, + "changes": [], + "notes": [] + } + }, + { + "address": 49163, + "address_region": "program_or_external", + "bytes": "15F841C6", + "text": "BSET.B #6, @H'F841", + "mnemonic": "BSET.B", + "operands": "#6, @H'F841", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63553, + "name": null, + "symbol": "ram_F841", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49163, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49167, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49167, + "changes": [], + "notes": [] + } + }, + { + "address": 49168, + "address_region": "program_or_external", + "bytes": "0E58", + "text": "BSR loc_C06A", + "mnemonic": "BSR", + "operands": "loc_C06A", + "kind": "call", + "targets": [ + 49258 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49168, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": 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"address": 49291, + "address_region": "program_or_external", + "bytes": "590007", + "text": "MOV:I.W #H'0007, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49291, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R1" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 = 0x0007" + ], + "known_after": { + "registers": { + "R1": { + "known": true, + "value": 7, + "hex": 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"address_region": "program_or_external", + "bytes": "15FEFE0613", + "text": "MOV:G.B #H'13, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'13, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'13", + "valid": true, + "dataflow": { + "block": 49371, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49376, + "address_region": "program_or_external", + "bytes": "590007", + "text": "MOV:I.W #H'0007, R1", + "mnemonic": "MOV:I.W", + "operands": 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"base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49383, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [], + "notes": [] + } + }, + { + "address": 49387, + "address_region": "program_or_external", + "bytes": "15FEFFF7", + "text": "BTST.B #7, @P9DR", + "mnemonic": "BTST.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [], + "notes": [] + } + }, + { + "address": 49391, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_C0F5", + "mnemonic": "BEQ", + "operands": "loc_C0F5", + "kind": "branch", + "targets": [ + 49397 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [], + "notes": [] + } + }, + { + "address": 49393, + "address_region": "program_or_external", + "bytes": "A549", + "text": "BSET.B R1, R5", + "mnemonic": "BSET.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49393, + "changes": [ + { + "kind": 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"address": 49397, + "address_region": "program_or_external", + "bytes": "A559", + "text": "BCLR.B R1, R5", + "mnemonic": "BCLR.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49397, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 49399, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49403, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": 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"block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49411, + "address_region": "program_or_external", + "bytes": "01B9DD", + "text": "SCB/F R1, loc_C0E3", + "mnemonic": "SCB/F", + "operands": "R1, loc_C0E3", + "kind": "branch", + "targets": [ + 49379 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49414, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": 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"valid": true, + "dataflow": { + "block": 49414, + "changes": [], + "notes": [] + } + }, + { + "address": 49420, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49424, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49428, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": 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"valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49457, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49461, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49465, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49469, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49473, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49474, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49478, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49482, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49486, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49490, + "address_region": "program_or_external", + "bytes": "15FEFFC7", + "text": "BSET.B #7, @P9DR", + "mnemonic": "BSET.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49494, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49498, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49502, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49506, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + } + ], + "decompiler_consistency": { + "kind": "decompiler_pseudocode_consistency", + "summary": "3 byte-immediate-to-word destination case(s) require explicit zero-extension in pseudocode.", + "checks": [ + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4163, + "address_hex": "H'1043", + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4184, + "address_hex": "H'1058", + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 16487, + "address_hex": "H'4067", + "instruction": "MOV:G.W #H'00, @(-H'0790,R2)", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + } + ] + }, + "serial_semantics": { + "kind": "serial_semantics", + "protocol_semantics": [ + { + "kind": "serial_semantics", + "scope": "evidence_supported_sci1_6_byte_frame", + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation.", + "frame_candidate": { + "channel": "SCI1", + "rx_frame_start": 63584, + "rx_frame_start_hex": "H'F860", + "rx_frame_end": 63589, + "rx_frame_end_hex": "H'F865", + "tx_staging_start": 63568, + "tx_staging_start_hex": "H'F850", + "tx_staging_end": 63572, + "tx_staging_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "frame_length": 6, + "tx_staging_length": 5, + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "serial_reconstruction_supported": true, + "rx_reconstruction_candidate_id": "sci1_rx_frame_f868_len6_candidate", + "tx_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + "byte_layout": [ + { + "offset": 0, + "rx_address": 63584, + "tx_staging_address": 63568, + "name_candidate": "op_flags", + "semantic": "low three bits select a command; upper bits are preserved or gated in some paths", + "confidence": "medium-high" + }, + { + "offset": 1, + "rx_address": 63585, + "tx_staging_address": 63569, + "name_candidate": "addr_page_flags", + "semantic": "candidate high/page byte for logical point/index; bit 7 is tested as a control flag", + "confidence": "medium" + }, + { + "offset": 2, + "rx_address": 63586, + "tx_staging_address": 63570, + "name_candidate": "addr_offset", + "semantic": "candidate low/offset byte for logical point/index", + "confidence": "medium" + }, + { + "offset": 3, + "rx_address": 63587, + "tx_staging_address": 63571, + "name_candidate": "value_hi", + "semantic": "candidate high byte of a word value", + "confidence": "medium" + }, + { + "offset": 4, + "rx_address": 63588, + "tx_staging_address": 63572, + "name_candidate": "value_lo", + "semantic": "candidate low byte of a word value", + "confidence": "medium" + }, + { + "offset": 5, + "rx_address": 63589, + "tx_staging_address": null, + "name_candidate": "checksum", + "semantic": "0x5A-seeded XOR of bytes 0..4", + "confidence": "high" + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2588 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2620 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2632 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2716 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2635 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2672 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2704 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2716 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "index_decoder": { + "kind": "logical_index_decoder_candidate", + "label": "loc_622B", + "address": 25131, + "address_hex": "H'622B", + "input_fields": [ + "addr_page_flags", + "addr_offset" + ], + "output_register": "R5", + "post_scale_register": "R4", + "post_scale": "R4 = R5 << 1", + "mapping_candidate": [ + { + "page": 0, + "offset_range": "0x00-0x7F", + "index_range": "0x000-0x07F" + }, + { + "page": 1, + "offset_range": "0x00-0xFF", + "index_range": "0x080-0x17F" + }, + { + "page": 2, + "offset_range": "0x00-0x7F", + "index_range": "0x180-0x1FF" + }, + { + "page": "other/overflow", + "index": "0x1FF" + } + ], + "evidence_addresses": [ + 48129 + ], + "evidence_addresses_hex": [ + "H'BC01" + ], + "confidence": "medium", + "caveat": "Mapping is inferred from loc_622B behavior and the nearby R4 = R5 << 1 table-index use." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47841, + "instruction_address_hex": "H'BAE1", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47848, + "instruction_address_hex": "H'BAE8", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "immediate": 240, + "immediate_hex": "H'F0" + }, + { + "instruction_address": 48669, + "instruction_address_hex": "H'BE1D", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48702, + "instruction_address_hex": "H'BE3E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48878, + "instruction_address_hex": "H'BEEE", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "rx_fields": [ + { + "kind": "rx_field_semantic_candidate", + "offset": 0, + "name": "command_low3", + "address": 63584, + "address_hex": "H'F860", + "confidence": "candidate-high", + "caveat": "RX[0] is masked with 0x07 before command comparisons", + "evidence_addresses": [ + 48088, + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "mask": 7, + "mask_hex": "H'07" + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 1, + "name": "likely_id_or_index", + "address": 63585, + "address_hex": "H'F861", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 2, + "name": "likely_id_or_index", + "address": 63586, + "address_hex": "H'F862", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 3, + "name": "likely_value", + "address": 63587, + "address_hex": "H'F863", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 4, + "name": "likely_value", + "address": 63588, + "address_hex": "H'F864", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 5, + "name": "checksum", + "address": 63589, + "address_hex": "H'F865", + "confidence": "candidate-high", + "caveat": "RX[5] is validated by the serial reconstruction checksum evidence", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ] + } + ], + "response_builders": [ + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 47939, + "call_address_hex": "H'BB43", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48674, + "call_address_hex": "H'BE22", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "evidence": [ + { + "kind": "rx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 RX frame candidate", + "candidate_id": "sci1_rx_frame_f868_len6_candidate" + }, + { + "kind": "tx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 TX frame candidate", + "candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + { + "kind": "rx0_masked_command_dispatch", + "summary": "RX[0] is read, masked with 0x07, and compared against command values", + "addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + { + "kind": "responses_stage_f850_f854_before_send", + "summary": "F850-F854 writes are observed before calls to loc_BA26", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378, + 48649, + 48657, + 48665, + 48674, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "response_count": 5 + }, + { + "kind": "bb43_autonomous_tx_report_path", + "summary": "BB43 stages a candidate device-to-host report before loc_BA26; this is separate from RX command dispatch.", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + { + "kind": "rx_payload_bytes_read", + "summary": "RX[1..4] are read in the command-processing region", + "addresses": [ + 48092, + 48096, + 48100, + 48104, + 48119, + 48125, + 48153, + 48190, + 48237, + 48267, + 48273, + 48309, + 48317, + 48325, + 48348, + 48356, + 48402, + 48427, + 48433, + 48603, + 48609, + 48722, + 48730, + 48738 + ], + "addresses_hex": [ + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBF7", + "H'BBFD", + "H'BC19", + "H'BC3E", + "H'BC6D", + "H'BC8B", + "H'BC91", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCDC", + "H'BCE4", + "H'BD12", + "H'BD2B", + "H'BD31", + "H'BDDB", + "H'BDE1", + "H'BE52", + "H'BE5A", + "H'BE62" + ] + } + ] + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2588 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2620 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2632 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2716 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2635 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2672 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2704 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2716 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47841, + "instruction_address_hex": "H'BAE1", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47848, + "instruction_address_hex": "H'BAE8", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "immediate": 240, + "immediate_hex": "H'F0" + }, + { + "instruction_address": 48669, + "instruction_address_hex": "H'BE1D", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48702, + "instruction_address_hex": "H'BE3E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48878, + "instruction_address_hex": "H'BEEE", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation." + } +} \ No newline at end of file diff --git a/build/rom_others_menu_deep.asm b/build/rom_others_menu_deep.asm new file mode 100644 index 0000000..1c521ad --- /dev/null +++ b/build/rom_others_menu_deep.asm @@ -0,0 +1,4219 @@ +; H8/536 ROM disassembly +; input: ROM\M27C512@DIP28_1.BIN +; bytes: 65536 +; vector mode: min +; analysis: recursive trace from vectors +; +; Notes from the manual: +; - H8/536 uses the H8/500 CPU instruction set. +; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC. +; - The register field is H'FE80-H'FFFF; names below come from appendix B. +; - @aa:8 short absolute operands use BR as the upper address byte. +; - SCI baud inference uses section 14.2.8 BRR formulas when SMR/BRR are known. +; - LCD inference treats E-clock H'F200/H'F201 accesses as status/control and data candidates. +; - Pass --clock-hz to convert SCI BRR settings into numeric baud rates. +; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states. + +; Memory Map +; H'0000-H'009F exception_vectors vectors +; H'00A0-H'00FF dtc_vectors dtc_vectors +; H'0100-H'F67F program_or_external program +; H'F680-H'FE7F on_chip_ram ram +; H'FE80-H'FFFF register_field registers + +; Vectors +; H'0000 reset -> vec_reset_1000 (H'1000) +; H'0004 invalid_instruction -> vec_reset_1000 (H'1000) +; H'0006 zero_divide -> vec_reset_1000 (H'1000) +; H'0008 trap_vs -> vec_reset_1000 (H'1000) +; H'0010 address_error -> vec_reset_1000 (H'1000) +; H'0012 trace -> vec_reset_1000 (H'1000) +; H'0016 nmi -> vec_nmi_4393 (H'4393) +; H'0020 trapa_0 -> vec_reset_1000 (H'1000) +; H'0022 trapa_1 -> vec_reset_1000 (H'1000) +; H'0024 trapa_2 -> vec_reset_1000 (H'1000) +; H'0026 trapa_3 -> vec_reset_1000 (H'1000) +; H'0028 trapa_4 -> vec_reset_1000 (H'1000) +; H'002A trapa_5 -> vec_reset_1000 (H'1000) +; H'002C trapa_6 -> vec_reset_1000 (H'1000) +; H'002E trapa_7 -> vec_reset_1000 (H'1000) +; H'0030 trapa_8 -> vec_reset_1000 (H'1000) +; H'0032 trapa_9 -> vec_reset_1000 (H'1000) +; H'0034 trapa_a -> vec_reset_1000 (H'1000) +; H'0036 trapa_b -> vec_reset_1000 (H'1000) +; H'0038 trapa_c -> vec_reset_1000 (H'1000) +; H'003A trapa_d -> vec_reset_1000 (H'1000) +; H'003C trapa_e -> vec_reset_1000 (H'1000) +; H'003E trapa_f -> vec_reset_1000 (H'1000) +; H'0040 irq0 -> vec_reset_1000 (H'1000) +; H'0042 interval_timer -> vec_interval_timer_BFC4 (H'BFC4) +; H'0048 irq1 -> vec_reset_1000 (H'1000) +; H'0050 irq2 -> vec_reset_1000 (H'1000) +; H'0052 irq3 -> vec_irq3_3C30 (H'3C30) +; H'0058 irq4 -> vec_irq4_3AC7 (H'3AC7) +; H'005A irq5 -> vec_reset_1000 (H'1000) +; H'0062 frt1_ocia -> vec_frt1_ocia_BEEA (H'BEEA) +; H'006A frt2_ocia -> vec_frt2_ocia_BF23 (H'BF23) +; H'0080 sci1_eri -> vec_sci1_eri_BB57 (H'BB57) +; H'0082 sci1_rxi -> vec_sci1_rxi_BB67 (H'BB67) +; H'0084 sci1_txi -> vec_sci1_txi_BA84 (H'BA84) +; H'0090 ad_adi -> vec_ad_adi_3D99 (H'3D99) + +; Unreached Data Candidates +; string H'2A52 len=11 '78785=5=5=,' +; string H'2BBA len=7 '8*8B8Z8' +; string H'41B2 len=32 '01020304050607080910111213141516' +; string H'57A4 len=7 'Z [ ' +; string H'582A len=6 'Z [ ' +; string H'5B55 len=10 '0123456789' +; string H'5B60 len=40 ' 0 1 2 3 4 5 6 7 8 910111213141516171819' +; string H'60F6 len=16 '0123456789ABCDEF' +; string H'630C len=9 'm*mDm^mxm' +; string H'633E len=6 'vpwhx6' +; string H'63D7 len=10 'OPERATION ' +; string H'63F5 len=10 ' PAINT ' +; string H'6410 len=18 ' ADV~Xd' +; string H'6443 len=10 'OPERATION ' +; string H'6461 len=10 'IRIS/M.BLK' +; string H'6490 len=10 'OPERATION ' +; string H'64AE len=10 ' LOCK ' +; string H'652F len=19 ' DYNA LATITUDE Xe/' +; string H'6551 len=18 'HIGH LOW~XeP' +; string H'6578 len=18 'STD OFF~Xew' +; string H'65C9 len=18 ' BLACK STR Xe' +; string H'6644 len=19 ' BLACK STR XfD' +; string H'6665 len=19 ' STRETCH LEVEL Xfe' +; string H'6683 len=18 'POINT1 POINT2Xf' +; string H'6706 len=18 ' BLACK STR Xg' +; string H'6727 len=19 " COMPRESS LEVEL Xg'" +; string H'6745 len=19 'POINT1 POINT2XgE' +; string H'67E0 len=18 ' TLCS Xg' +; string H'6802 len=17 'ON OFF~Xh' +; string H'681F len=18 ' AGC GAIN AE Xh' +; string H'686A len=136 ' CL F16 F11 F8 F5.6F4 F2.8F2 F1.8F1.4 OP DPR HYP HIGHMID LOW 36dB30dB24dB18dB12dB 9dB 6dB 3dB 0dB-3dB' +; string H'693B len=19 ' AUTO FUNC Xi;' +; string H'695C len=19 ' ATW Xi\\' +; string H'6984 len=17 'ON OFF~Xi' +; string H'6A4F len=19 ' AUTO FUNC XjO' +; string H'6A71 len=18 'STD SPOT.L~Xjp' +; string H'6A8E len=18 ' A.IRIS MODE Xj' +; string H'6AAD len=17 'AI BACK.L~Xj' +; string H'6B3D len=19 ' AUTO FUNC Xk=' +; string H'6B5E len=19 ' AUTO FOCUS Xk^' +; ptrtbl H'1A1E count=4 -> H'F6F8, H'FAFC, H'FDFE, H'FF00 +; ptrtbl H'1EB0 count=4 -> H'F730, H'F727, H'2815, H'F731 +; ptrtbl H'28A8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28B6 count=10 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'28DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28F2 count=29 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'292E count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'293C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2944 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'294C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2954 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'295C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2964 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'296C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2974 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2982 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'29AE count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29B8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29FA count=13 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A20 count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2A34 count=15 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A62 count=24 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A98 count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2AA2 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2AC8 count=115 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2BC4 count=113 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'33A0 count=3 -> H'FF26, H'11A9, H'F726 +; ptrtbl H'3478 count=3 -> H'F790, H'F727, H'441D +; ptrtbl H'35DC count=3 -> H'FE27, H'1215, H'F717 +; ptrtbl H'4698 count=3 -> H'F750, H'1627, H'10FB +; ptrtbl H'47AE count=3 -> H'F752, H'1627, H'10FB +; ptrtbl H'48AA count=4 -> H'FB03, H'F726, H'1215, H'F6D1 +; ptrtbl H'4966 count=6 -> H'93AA, H'9392, H'937C, H'935A, H'9326, H'930A +; ptrtbl H'505A count=3 -> H'1627, H'5515, H'FB03 +; ptrtbl H'5A22 count=3 -> H'1AF8, H'F74C, H'1627 +; ptrtbl H'62EE count=4 -> H'FCE2, H'FC62, H'FA84, H'11DC +; ptrtbl H'74FC count=3 -> H'F772, H'1627, H'12A8 +; ptrtbl H'80F2 count=3 -> H'FC80, H'FC84, H'11DC +; ptrtbl H'9E10 count=3 -> H'FE1E, H'BC7D, H'5500 + +; Symbols +; mem_1011 H'1011 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_10FB H'10FB program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1161 H'1161 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1170 H'1170 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1179 H'1179 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1188 H'1188 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1197 H'1197 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11A0 H'11A0 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_11A9 H'11A9 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11DC H'11DC program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1206 H'1206 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1215 H'1215 program_or_external memory r=0 w=0 width=unknown xrefs=3 +; mem_12A8 H'12A8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1314 H'1314 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1617 H'1617 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1627 H'1627 program_or_external memory r=0 w=0 width=unknown xrefs=7 +; mem_1630 H'1630 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1647 H'1647 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1664 H'1664 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1682 H'1682 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1700 H'1700 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1819 H'1819 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1A00 H'1A00 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1AF8 H'1AF8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2815 H'2815 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2CA6 H'2CA6 program_or_external memory r=0 w=0 width=unknown xrefs=429 +; mem_441D H'441D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449C H'449C program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449E H'449E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_44A0 H'44A0 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5500 H'5500 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5515 H'5515 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_602E H'602E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6030 H'6030 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6032 H'6032 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_930A H'930A program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_9326 H'9326 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_935A H'935A program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_937C H'937C program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_9392 H'9392 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_93AA H'93AA program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_BC7D H'BC7D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_E000 H'E000 program_or_external memory r=0 w=1 width=word +; mem_E004 H'E004 program_or_external memory r=1 w=0 width=word +; mem_E006 H'E006 program_or_external memory r=0 w=1 width=word +; mem_E046 H'E046 program_or_external memory r=0 w=1 width=word +; mem_E080 H'E080 program_or_external memory r=0 w=1 width=word +; mem_E102 H'E102 program_or_external memory r=2 w=0 width=word +; mem_E11E H'E11E program_or_external memory r=2 w=0 width=word +; mem_E124 H'E124 program_or_external memory r=2 w=0 width=word +; mem_E126 H'E126 program_or_external memory r=5 w=0 width=word +; mem_E14E H'E14E program_or_external memory r=1 w=0 width=word +; mem_E16E H'E16E program_or_external memory r=1 w=0 width=word +; mem_E172 H'E172 program_or_external memory r=1 w=0 width=word +; mem_E1EC H'E1EC program_or_external memory r=2 w=0 width=word +; mem_E220 H'E220 program_or_external memory r=1 w=0 width=word +; mem_E800 H'E800 program_or_external memory r=0 w=1 width=word +; mem_E806 H'E806 program_or_external memory r=0 w=1 width=word +; mem_E880 H'E880 program_or_external memory r=0 w=1 width=word +; mem_E902 H'E902 program_or_external memory r=0 w=1 width=word +; mem_E924 H'E924 program_or_external memory r=0 w=1 width=word +; mem_E9EC H'E9EC program_or_external memory r=0 w=1 width=word +; mem_F000 H'F000 program_or_external memory r=2 w=0 width=byte +; mem_F001 H'F001 program_or_external memory r=2 w=1 width=byte +; mem_F002 H'F002 program_or_external memory r=2 w=1 width=mixed +; mem_F003 H'F003 program_or_external memory r=1 w=1 width=byte +; mem_F004 H'F004 program_or_external memory r=2 w=1 width=mixed +; mem_F005 H'F005 program_or_external memory r=1 w=1 width=byte +; mem_F006 H'F006 program_or_external memory r=2 w=0 width=mixed +; mem_F007 H'F007 program_or_external memory r=1 w=0 width=byte +; mem_F008 H'F008 program_or_external memory r=2 w=0 width=mixed +; mem_F009 H'F009 program_or_external memory r=1 w=1 width=byte +; mem_F00A H'F00A program_or_external memory r=2 w=1 width=mixed +; mem_F00B H'F00B program_or_external memory r=0 w=1 width=byte +; mem_F00C H'F00C program_or_external memory r=2 w=1 width=mixed +; mem_F00D H'F00D program_or_external memory r=0 w=1 width=byte +; mem_F00E H'F00E program_or_external memory r=0 w=1 width=byte +; mem_F00F H'F00F program_or_external memory r=1 w=1 width=byte +; mem_F100 H'F100 program_or_external memory r=2 w=0 width=byte +; mem_F101 H'F101 program_or_external memory r=2 w=1 width=byte +; ... 243 more symbols omitted from listing header + +; Board Profile +; Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver. +; H8 pin 66 P95/TXD (TXD) -> MAX202 pin 11 +; H8 pin 67 P96/RXD (RXD) -> MAX202 pin 12 +; SCI2 pin routing is disabled by SYSCR2.P9SCI2E=0 in the observed setup. + +; Serial Protocol Reconstruction +; TX candidate: 6 bytes H'F858-H'F85D, checksum H'F85D seeded by H'005A (confidence high 0.95) +; TX path: initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted +; RX candidate: 6 bytes capture H'F868-H'F86D, validate H'F860-H'F865 checksum H'F865 seeded by H'005A (confidence high 0.9) +; caveat: candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet +; Serial RAM role candidates +; H'F9C0: post_tx_report_delay - post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C1: secondary_tx_report_delay - secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C6: periodic_report_countdown - periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it + +; LCD/Text Scan +; search 'CONNECT': not literal, hits=0 +; near: H'A025 'COMPLETED', H'8E79 'ON CONT1 OFF~X', H'8F55 'ON CONT2 OFF~X', H'94A9 'ON' +; LCD text regions +; region H'63D7-H'6758 count=15 'OPERATION', 'PAINT', 'OPERATION', 'IRIS/M.BLK' +; region H'67E0-H'6831 count=2 'TLCS Xg', 'AGC GAIN AE Xh' +; region H'6A4F-H'6C47 count=8 'AUTO FUNC XjO', 'A.IRIS MODE Xj', 'AI BACK.L~Xj', 'AUTO FUNC Xk=' +; region H'6F84-H'6FC0 count=2 'OTHERS Xo', 'SHUTTER Xo' +; region H'7052-H'7477 count=15 'SET RCP', 'MASTER', 'OTHERS Xp', 'COPY TO SLAVES~Xp' +; region H'757A-H'7824 count=14 'BARS TYPE Xuz', 'SMPTE Xu', 'SPLIT Xu', 'FULLFIELD 75% Xu' +; region H'78B5-H'792F count=4 'OTHERS Xx', 'WHITE BLACK~Xx', 'COMM LINK ITEM-2Xx', 'FLARE Xy' +; region H'819C-H'87A9 count=28 'SHADING X', 'WHITE~X', 'SHADING AUTO SETX', 'BLACK~X' +; region H'883D-H'8959 count=7 'MATRIX X', 'STD FL~X', 'PRESET MATRIX X', 'H.SAT SPCL~X' +; region H'8A0C-H'8BAC count=7 'MATRIX X', 'ON SKIN OFF~X', 'SAT HUE X', 'MATRIX X' +; region H'8CB7-H'8CFD count=2 'FILTER X', '1 2 3 4 X' +; region H'8E57-H'8EA7 count=3 'LENS X', 'ON CONT1 OFF~X', 'FOCUS ZOOM X' +; ... 23 more LCD text regions +; LCD text candidates +; text H'41B0 len=35 medium '01020304050607080910111213141516X' +; text H'5B55 len=10 high '0123456789' xrefs=2 +; text H'60F6 len=16 high '0123456789ABCDEF' +; text H'63D7 len=10 high 'OPERATION' xrefs=1 +; text H'63F5 len=10 high 'PAINT' xrefs=1 +; text H'6443 len=10 high 'OPERATION' xrefs=1 +; text H'6461 len=10 high 'IRIS/M.BLK' xrefs=1 +; text H'6490 len=10 high 'OPERATION' xrefs=1 +; text H'64AE len=10 high 'LOCK' xrefs=1 +; text H'652F len=19 high 'DYNA LATITUDE Xe/' xrefs=1 +; text H'6551 len=18 medium 'HIGH LOW~XeP' xrefs=1 +; text H'65C9 len=18 medium 'BLACK STR Xe' xrefs=1 +; text H'6644 len=19 medium 'BLACK STR XfD' xrefs=1 +; text H'6665 len=19 medium 'STRETCH LEVEL Xfe' xrefs=1 +; text H'6683 len=18 high 'POINT1 POINT2Xf' xrefs=1 +; text H'6706 len=18 medium 'BLACK STR Xg' xrefs=1 +; text H'6727 len=19 medium "COMPRESS LEVEL Xg'" xrefs=1 +; text H'6745 len=19 high 'POINT1 POINT2XgE' xrefs=1 +; text H'67E0 len=18 medium 'TLCS Xg' xrefs=1 +; text H'681F len=18 medium 'AGC GAIN AE Xh' xrefs=1 +; text H'693B len=19 medium 'AUTO FUNC Xi;' xrefs=1 +; text H'6A4F len=19 medium 'AUTO FUNC XjO' xrefs=1 +; text H'6A8E len=18 medium 'A.IRIS MODE Xj' xrefs=1 +; text H'6AAD len=17 medium 'AI BACK.L~Xj' xrefs=1 +; text H'6B3D len=19 medium 'AUTO FUNC Xk=' xrefs=1 +; text H'6B5E len=19 medium 'AUTO FOCUS Xk^' xrefs=1 +; text H'6BEF len=18 medium 'DIAG Xk' xrefs=1 +; text H'6C16 len=18 medium 'DIAG DATA Xl' xrefs=2 +; text H'6C35 len=18 medium 'RESET REQ~Xl4' xrefs=1 +; text H'6F84 len=18 medium 'OTHERS Xo' xrefs=2 +; text H'6FAE len=18 medium 'SHUTTER Xo' xrefs=2 +; text H'7052 len=14 medium 'SET RCP' xrefs=1 +; text H'706F len=14 medium 'MASTER' xrefs=1 +; text H'709F len=18 medium 'OTHERS Xp' xrefs=2 +; text H'70C0 len=18 medium 'COPY TO SLAVES~Xp' xrefs=2 +; text H'7144 len=19 medium 'CAM ID SET~XqD' xrefs=1 +; text H'71C9 len=18 medium 'OTHERS Xq' xrefs=1 +; text H'71F9 len=18 medium 'CAM ID IND Xq' xrefs=1 +; text H'7213 len=18 medium 'TITLE IND Xr' xrefs=1 +; text H'72A5 len=18 medium 'OTHERS Xr' xrefs=1 +; text H'72C7 len=17 medium 'CAM BARS~Xr' xrefs=1 +; text H'72E4 len=18 medium 'CLOCK IND Xr' xrefs=1 +; text H'7369 len=19 medium 'OTHERS Xsi' xrefs=1 +; text H'7393 len=18 high 'CENTER MARKER Xs' xrefs=1 +; text H'7425 len=19 medium 'OTHERS Xt%' xrefs=1 +; text H'7464 len=19 medium 'SAFETY ZONE Xtd' xrefs=1 +; text H'757A len=19 medium 'BARS TYPE Xuz' xrefs=1 +; text H'75A4 len=18 medium 'SMPTE Xu' xrefs=1 +; ... 192 more LCD text candidates + +; LCD Driver Candidates +; H'F200 lcd_status_control status/control register inferred from busy polling and command writes +; H'F201 lcd_data data register inferred from paired data reads/writes +; LCD routines +; routine H'3F40-H'3F74 lcd_wait_and_transfer lcd_command_or_address_write, lcd_data_read, lcd_data_write, lcd_status_read +; LCD busy loops +; loop H'3F4A->H'3F51 LCD busy-flag poll: read H'F200, test bit 7, branch until clear + + +vec_reset_1000: +1000: 5F FE 80 MOV:I.W #H'FE80, R7 ; dataflow R7=H'FE80; cycles=3 +1003: 0C 07 00 88 LDC.W #H'0700, SR ; dataflow SR=H'0700; cycles=6 +1007: 15 FE 80 06 FF MOV:G.B #H'FF, @P1DDR ; P1DDR = H'FF; cycles=9 +100C: 15 FE 82 06 00 MOV:G.B #H'00, @P1DR ; P1DR = H'00; cycles=9 +1011: 15 FE 89 06 F9 MOV:G.B #H'F9, @P6DDR ; P6DDR = H'F9; cycles=9 +1016: 15 FE 8B 06 F1 MOV:G.B #H'F1, @P6DR ; P6DR = H'F1; cycles=9 +101B: 15 FE 8C 06 00 MOV:G.B #H'00, @P7DDR ; P7DDR = H'00; cycles=9 +1020: 15 FE 8E 06 00 MOV:G.B #H'00, @P7DR ; P7DR = H'00; cycles=9 +1025: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +102A: 15 FE FF 06 00 MOV:G.B #H'00, @P9DR ; P9DR = H'00; cycles=9 +102F: 15 FE FC 06 87 MOV:G.B #H'87, @SYSCR1 ; SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled); cycles=9 +1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; FRT1_FRC word write; TEMP byte-order hazard avoided; cycles=9 +1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_H ; FRT1_OCRA_H = H'9C; FRT1_OCRA word write; TEMP byte-order hazard avoided; cycles=11 +104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; FRT2_FRC word write; TEMP byte-order hazard avoided; cycles=11 +105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; FRT2_OCRA word write; TEMP byte-order hazard avoided; cycles=9 +1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 +1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 +106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1072: 15 FE D1 06 10 MOV:G.B #H'10, @TMR_TCSR ; TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0); cycles=9 +1077: 15 FE C0 06 38 MOV:G.B #H'38, @PWM1_TCR ; PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +107C: 15 FE C1 06 FF MOV:G.B #H'FF, @PWM1_DTR ; PWM1_DTR = H'FF; cycles=9 +1081: 15 FE C4 06 38 MOV:G.B #H'38, @PWM2_TCR ; PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1086: 15 FE C5 06 FF MOV:G.B #H'FF, @PWM2_DTR ; PWM2_DTR = H'FF; cycles=9 +108B: 15 FE C8 06 3B MOV:G.B #H'3B, @PWM3_TCR ; PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1); cycles=9 +1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D; cycles=9 +1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI1 receive and receive-error interrupts (RIE); enable SCI1 transmitter (TE); enable SCI1 receiver (RE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI2 receive and receive-error interrupts (RIE); disable SCI2 transmitter (TE); disable SCI2 receiver (RE); SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 +10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field; cycles=9 +10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 +10C2: 15 FF 11 06 FF MOV:G.B #H'FF, @RAMCR ; RAMCR = H'FF (RAME=1; on-chip RAM enabled); cycles=9 +10C7: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=8 +10CB: 30 2E A8 BRA loc_3F76 ; cycles=8 + +loc_10CE: +10CE: 5C 00 40 MOV:I.W #H'0040, R4 ; dataflow R4=H'0040; cycles=3 +10D1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10D4: 1E 2D F5 BSR loc_3ECC ; cycles=13 +10D7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10DA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10DD: 1E 2D EC BSR loc_3ECC ; cycles=14 +10E0: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10E3: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10E6: 1E 2D E3 BSR loc_3ECC ; cycles=13 +10E9: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10EC: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10EF: 1E 2D DA BSR loc_3ECC ; cycles=14 +10F2: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +10F5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10F8: 1E 2D D1 BSR loc_3ECC ; cycles=13 +10FB: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +10FE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1101: 1E 2D C8 BSR loc_3ECC ; cycles=14 +1104: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1107: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +110A: 1E 2D BF BSR loc_3ECC ; cycles=13 +110D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1110: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1113: 1E 2D B6 BSR loc_3ECC ; cycles=14 +1116: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1119: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +111C: 1E 2D AD BSR loc_3ECC ; cycles=13 +111F: 5C 00 48 MOV:I.W #H'0048, R4 ; dataflow R4=H'0048; cycles=3 +1122: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1125: 1E 2D A4 BSR loc_3ECC ; cycles=14 +1128: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +112B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +112E: 1E 2D 9B BSR loc_3ECC ; cycles=13 +1131: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1134: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1137: 1E 2D 92 BSR loc_3ECC ; cycles=14 +113A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +113D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1140: 1E 2D 89 BSR loc_3ECC ; cycles=13 +1143: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1146: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1149: 1E 2D 80 BSR loc_3ECC ; cycles=14 +114C: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +114F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1152: 1E 2D 77 BSR loc_3ECC ; cycles=13 +1155: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1158: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +115B: 1E 2D 6E BSR loc_3ECC ; cycles=14 +115E: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1161: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1164: 1E 2D 65 BSR loc_3ECC ; cycles=13 +1167: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +116A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +116D: 1E 2D 5C BSR loc_3ECC ; cycles=14 +1170: 5C 00 50 MOV:I.W #H'0050, R4 ; dataflow R4=H'0050; cycles=3 +1173: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1176: 1E 2D 53 BSR loc_3ECC ; cycles=13 +1179: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +117C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +117F: 1E 2D 4A BSR loc_3ECC ; cycles=14 +1182: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1185: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1188: 1E 2D 41 BSR loc_3ECC ; cycles=13 +118B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +118E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1191: 1E 2D 38 BSR loc_3ECC ; cycles=14 +1194: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +1197: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +119A: 1E 2D 2F BSR loc_3ECC ; cycles=13 +119D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11A3: 1E 2D 26 BSR loc_3ECC ; cycles=14 +11A6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11AC: 1E 2D 1D BSR loc_3ECC ; cycles=13 +11AF: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11B2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11B5: 1E 2D 14 BSR loc_3ECC ; cycles=14 +11B8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11BB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11BE: 1E 2D 0B BSR loc_3ECC ; cycles=13 +11C1: 5C 00 58 MOV:I.W #H'0058, R4 ; dataflow R4=H'0058; cycles=3 +11C4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11C7: 1E 2D 02 BSR loc_3ECC ; cycles=14 +11CA: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11CD: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D0: 1E 2C F9 BSR loc_3ECC ; cycles=13 +11D3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11D6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D9: 1E 2C F0 BSR loc_3ECC ; cycles=14 +11DC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11DF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11E2: 1E 2C E7 BSR loc_3ECC ; cycles=13 +11E5: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +11E8: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11EB: 1E 2C DE BSR loc_3ECC ; cycles=14 +11EE: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11F1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11F4: 1E 2C D5 BSR loc_3ECC ; cycles=13 +11F7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11FA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11FD: 1E 2C CC BSR loc_3ECC ; cycles=14 +1200: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1203: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1206: 1E 2C C3 BSR loc_3ECC ; cycles=13 +1209: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +120C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +120F: 1E 2C BA BSR loc_3ECC ; cycles=14 +1212: 5C 00 60 MOV:I.W #H'0060, R4 ; dataflow R4=H'0060; cycles=3 +1215: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1218: 1E 2C B1 BSR loc_3ECC ; cycles=13 +121B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +121E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1221: 1E 2C A8 BSR loc_3ECC ; cycles=14 +1224: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1227: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +122A: 1E 2C 9F BSR loc_3ECC ; cycles=13 +122D: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1230: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1233: 1E 2C 96 BSR loc_3ECC ; cycles=14 +1236: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1239: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +123C: 1E 2C 8D BSR loc_3ECC ; cycles=13 +123F: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1242: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1245: 1E 2C 84 BSR loc_3ECC ; cycles=14 +1248: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +124B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +124E: 1E 2C 7B BSR loc_3ECC ; cycles=13 +1251: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1254: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1257: 1E 2C 72 BSR loc_3ECC ; cycles=14 +125A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +125D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1260: 1E 2C 69 BSR loc_3ECC ; cycles=13 +1263: 5C 00 68 MOV:I.W #H'0068, R4 ; dataflow R4=H'0068; cycles=3 +1266: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1269: 1E 2C 60 BSR loc_3ECC ; cycles=14 +126C: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +126F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1272: 1E 2C 57 BSR loc_3ECC ; cycles=13 +1275: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1278: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +127B: 1E 2C 4E BSR loc_3ECC ; cycles=14 +127E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1281: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1284: 1E 2C 45 BSR loc_3ECC ; cycles=13 +1287: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +128A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +128D: 1E 2C 3C BSR loc_3ECC ; cycles=14 +1290: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1293: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1296: 1E 2C 33 BSR loc_3ECC ; cycles=13 +1299: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +129C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +129F: 1E 2C 2A BSR loc_3ECC ; cycles=14 +12A2: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12A5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12A8: 1E 2C 21 BSR loc_3ECC ; cycles=13 +12AB: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12AE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12B1: 1E 2C 18 BSR loc_3ECC ; cycles=14 +12B4: 5C 00 70 MOV:I.W #H'0070, R4 ; dataflow R4=H'0070; cycles=3 +12B7: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12BA: 1E 2C 0F BSR loc_3ECC ; cycles=13 +12BD: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12C3: 1E 2C 06 BSR loc_3ECC ; cycles=14 +12C6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12CC: 1E 2B FD BSR loc_3ECC ; cycles=13 +12CF: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12D2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12D5: 1E 2B F4 BSR loc_3ECC ; cycles=14 +12D8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12DB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12DE: 1E 2B EB BSR loc_3ECC ; cycles=13 +12E1: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12E4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12E7: 1E 2B E2 BSR loc_3ECC ; cycles=14 +12EA: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12ED: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F0: 1E 2B D9 BSR loc_3ECC ; cycles=13 +12F3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12F6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F9: 1E 2B D0 BSR loc_3ECC ; cycles=14 +12FC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12FF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1302: 1E 2B C7 BSR loc_3ECC ; cycles=13 +1305: 5C 00 78 MOV:I.W #H'0078, R4 ; dataflow R4=H'0078; cycles=3 +1308: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +130B: 1E 2B BE BSR loc_3ECC ; cycles=14 +130E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1311: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1314: 1E 2B B5 BSR loc_3ECC ; cycles=13 +1317: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +131A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +131D: 1E 2B AC BSR loc_3ECC ; cycles=14 +1320: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1323: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1326: 1E 2B A3 BSR loc_3ECC ; cycles=13 +1329: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +132C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +132F: 1E 2B 9A BSR loc_3ECC ; cycles=14 +1332: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1335: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1338: 1E 2B 91 BSR loc_3ECC ; cycles=13 +133B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +133E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1341: 1E 2B 88 BSR loc_3ECC ; cycles=14 +1344: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1347: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +134A: 1E 2B 7F BSR loc_3ECC ; cycles=13 +134D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1350: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1353: 1E 2B 76 BSR loc_3ECC ; cycles=14 +1356: 19 RTS ; cycles=12 + +loc_15E0: +15E0: 1E 10 6D BSR loc_2650 ; cycles=13 +15E3: 15 F6 89 D7 BCLR.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=8 +15E7: 27 10 BEQ loc_15F9 ; cycles=3/8 nt/t +15E9: 1D F6 8E 81 MOV:G.W @H'F68E, R1 ; refs ram_F68E in on_chip_ram; cycles=6 +15ED: 1D E9 02 91 MOV:G.W R1, @H'E902 ; refs mem_E902 in program_or_external; cycles=6 +15F1: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +15F3: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +15F6: 1E 28 5B BSR loc_3E54 ; cycles=13 + +loc_15F9: +15F9: 15 F6 F0 16 TST.B @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +15FD: 27 3E BEQ loc_163D ; cycles=3/8 nt/t +15FF: 15 F6 F0 D7 BCLR.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1603: 27 03 BEQ loc_1608 ; cycles=3/8 nt/t +1605: 18 43 94 JSR @loc_4394 ; cycles=14 + +loc_1608: +1608: 15 F6 F0 D6 BCLR.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +160C: 27 03 BEQ loc_1611 ; cycles=3/7 nt/t +160E: 18 44 57 JSR @loc_4457 ; cycles=13 + +loc_1611: +1611: 15 F6 F0 D5 BCLR.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1615: 27 03 BEQ loc_161A ; cycles=3/8 nt/t +1617: 18 45 1A JSR @loc_451A ; cycles=14 + +loc_161A: +161A: 15 F6 F0 D4 BCLR.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +161E: 15 F6 F0 D3 BCLR.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1622: 27 03 BEQ loc_1627 ; cycles=3/7 nt/t +1624: 18 17 05 JSR @loc_1705 ; cycles=13 + +loc_1627: +1627: 15 F6 F0 D2 BCLR.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +162B: 27 03 BEQ loc_1630 ; cycles=3/8 nt/t +162D: 18 17 4D JSR @loc_174D ; cycles=14 + +loc_1630: +1630: 15 F6 F0 D1 BCLR.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1634: 27 03 BEQ loc_1639 ; cycles=3/7 nt/t +1636: 18 17 95 JSR @loc_1795 ; cycles=13 + +loc_1639: +1639: 15 F6 F0 D0 BCLR.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 + +loc_163D: +163D: 15 F6 F1 16 TST.B @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=6 +1641: 27 43 BEQ loc_1686 ; cycles=3/8 nt/t +1643: 15 F6 F1 D7 BCLR.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1647: 27 03 BEQ loc_164C ; cycles=3/8 nt/t +1649: 18 17 C9 JSR @loc_17C9 ; cycles=14 + +loc_164C: +164C: 15 F6 F1 D6 BCLR.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1650: 27 03 BEQ loc_1655 ; cycles=3/7 nt/t +1652: 18 17 FB JSR @loc_17FB ; cycles=13 + +loc_1655: +1655: 15 F6 F1 D5 BCLR.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1659: 27 03 BEQ loc_165E ; cycles=3/8 nt/t +165B: 18 18 2D JSR @loc_182D ; cycles=14 + +loc_165E: +165E: 15 F6 F1 D4 BCLR.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1662: 27 03 BEQ loc_1667 ; cycles=3/7 nt/t +1664: 18 18 91 JSR @loc_1891 ; cycles=13 + +loc_1667: +1667: 15 F6 F1 D3 BCLR.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +166B: 27 03 BEQ loc_1670 ; cycles=3/8 nt/t +166D: 18 18 E7 JSR @loc_18E7 ; cycles=14 + +loc_1670: +1670: 15 F6 F1 D2 BCLR.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1674: 27 03 BEQ loc_1679 ; cycles=3/7 nt/t +1676: 18 19 4A JSR @loc_194A ; cycles=13 + +loc_1679: +1679: 15 F6 F1 D1 BCLR.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +167D: 27 03 BEQ loc_1682 ; cycles=3/8 nt/t +167F: 18 19 79 JSR @loc_1979 ; cycles=14 + +loc_1682: +1682: 15 F6 F1 D0 BCLR.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 + +loc_1686: +1686: 15 F6 F2 16 TST.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=7 +168A: 27 48 BEQ loc_16D4 ; cycles=3/7 nt/t +168C: 15 F6 F2 D7 BCLR.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +1690: 27 03 BEQ loc_1695 ; cycles=3/7 nt/t +1692: 18 1B 2D JSR @loc_1B2D ; cycles=13 + +loc_1695: +1695: 15 F6 F2 D6 BCLR.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +1699: 27 03 BEQ loc_169E ; cycles=3/8 nt/t +169B: 18 1B 44 JSR @loc_1B44 ; cycles=14 + +loc_169E: +169E: 15 F6 F2 D5 BCLR.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16A2: 27 03 BEQ loc_16A7 ; cycles=3/7 nt/t +16A4: 18 1B 5B JSR @loc_1B5B ; cycles=13 + +loc_16A7: +16A7: 15 F6 F2 D4 BCLR.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16AB: 27 03 BEQ loc_16B0 ; cycles=3/8 nt/t +16AD: 18 1B A0 JSR @loc_1BA0 ; cycles=14 + +loc_16B0: +16B0: 15 F6 F2 D3 BCLR.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16B4: 27 03 BEQ loc_16B9 ; cycles=3/7 nt/t +16B6: 18 1B B6 JSR @loc_1BB6 ; cycles=13 + +loc_16B9: +16B9: 15 F6 F2 D2 BCLR.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16BD: 27 03 BEQ loc_16C2 ; cycles=3/8 nt/t +16BF: 18 1B CC JSR @loc_1BCC ; cycles=14 + +loc_16C2: +16C2: 15 F6 F2 D1 BCLR.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16C6: 27 03 BEQ loc_16CB ; cycles=3/7 nt/t +16C8: 18 1B 72 JSR @loc_1B72 ; cycles=13 + +loc_16CB: +16CB: 15 F6 F2 D0 BCLR.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16CF: 27 03 BEQ loc_16D4 ; cycles=3/8 nt/t +16D1: 18 1B 89 JSR @loc_1B89 ; cycles=14 + +loc_16D4: +16D4: 15 F6 F3 16 TST.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=7 +16D8: 27 2A BEQ loc_1704 ; cycles=3/7 nt/t +16DA: 15 F6 F3 D7 BCLR.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16DE: 15 F6 F3 D6 BCLR.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E2: 15 F6 F3 D5 BCLR.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E6: 15 F6 F3 D4 BCLR.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16EA: 27 03 BEQ loc_16EF ; cycles=3/7 nt/t +16EC: 18 1B E2 JSR @loc_1BE2 ; cycles=13 + +loc_16EF: +16EF: 15 F6 F3 D3 BCLR.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=8 +16F3: 27 03 BEQ loc_16F8 ; cycles=3/8 nt/t +16F5: 18 1B F8 JSR @loc_1BF8 ; cycles=14 + +loc_16F8: +16F8: 15 F6 F3 D2 BCLR.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16FC: 15 F6 F3 D1 BCLR.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +1700: 15 F6 F3 D0 BCLR.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 + +loc_1704: +1704: 19 RTS ; cycles=12 + +loc_1705: +1705: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +170A: 22 38 BHI loc_1744 ; cycles=3/7 nt/t +170C: 1D E1 4E FF BTST.W #15, @H'E14E ; refs mem_E14E in program_or_external; cycles=7 +1710: 26 24 BNE loc_1736 ; cycles=3/7 nt/t +1712: 15 F7 30 F6 BTST.B #6, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1716: 26 1E BNE loc_1736 ; cycles=3/7 nt/t +1718: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +171C: 26 08 BNE loc_1726 ; cycles=3/7 nt/t +171E: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +1722: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_1726: +1726: 1D F7 32 07 1C 07 MOV:G.W #H'1C07, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +172C: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1731: 1E 31 C6 BSR loc_48FA ; cycles=14 +1734: 20 0E BRA loc_1744 ; cycles=7 + +loc_1736: +1736: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +173A: 1D F6 B6 34 SUB.W @H'F6B6, R4 ; refs ram_F6B6 in on_chip_ram; cycles=7 +173E: 5B 00 A9 MOV:I.W #H'00A9, R3 ; dataflow R3=H'00A9; cycles=3 +1741: 1E 02 5E BSR loc_19A2 ; cycles=14 + +loc_1744: +1744: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +1748: 1D F6 B6 94 MOV:G.W R4, @H'F6B6 ; refs ram_F6B6 in on_chip_ram; cycles=7 +174C: 19 RTS ; cycles=12 + +loc_174D: +174D: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1752: 22 38 BHI loc_178C ; cycles=3/7 nt/t +1754: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1758: 27 32 BEQ loc_178C ; cycles=3/7 nt/t +175A: 1D E1 6E FD BTST.W #13, @H'E16E ; refs mem_E16E in program_or_external; cycles=7 +175E: 26 1E BNE loc_177E ; cycles=3/7 nt/t +1760: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +1764: 26 08 BNE loc_176E ; cycles=3/7 nt/t +1766: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +176A: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_176E: +176E: 1D F7 32 07 1C 06 MOV:G.W #H'1C06, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +1774: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1779: 1E 31 7E BSR loc_48FA ; cycles=14 +177C: 20 0E BRA loc_178C ; cycles=7 + +loc_177E: +177E: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1782: 1D F6 B4 34 SUB.W @H'F6B4, R4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1786: 5B 00 C5 MOV:I.W #H'00C5, R3 ; dataflow R3=H'00C5; cycles=3 +1789: 1E 02 16 BSR loc_19A2 ; cycles=14 + +loc_178C: +178C: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1790: 1D F6 B4 94 MOV:G.W R4, @H'F6B4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1794: 19 RTS ; cycles=12 + +loc_1795: +1795: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +179A: 22 24 BHI loc_17C0 ; cycles=3/7 nt/t +179C: 1D E1 72 FD BTST.W #13, @H'E172 ; refs mem_E172 in program_or_external; cycles=7 +17A0: 26 05 BNE loc_17A7 ; cycles=3/7 nt/t +17A2: 1E 09 82 BSR loc_2127 ; cycles=13 +17A5: 20 19 BRA loc_17C0 ; cycles=8 + +loc_17A7: +17A7: 1D E2 20 FF BTST.W #15, @H'E220 ; refs mem_E220 in program_or_external; cycles=6 +17AB: 27 05 BEQ loc_17B2 ; cycles=3/8 nt/t +17AD: 1E 09 77 BSR loc_2127 ; cycles=14 +17B0: 20 0E BRA loc_17C0 ; cycles=7 + +loc_17B2: +17B2: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17B6: 1D F6 B2 34 SUB.W @H'F6B2, R4 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17BA: 5B 00 BC MOV:I.W #H'00BC, R3 ; dataflow R3=H'00BC; cycles=3 +17BD: 1E 01 E2 BSR loc_19A2 ; cycles=14 + +loc_17C0: +17C0: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17C4: 1D F6 B2 94 MOV:G.W R4, @H'F6B2 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17C8: 19 RTS ; cycles=12 + +loc_17C9: +17C9: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +17CE: 22 22 BHI loc_17F2 ; cycles=3/7 nt/t +17D0: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +17D4: 27 1C BEQ loc_17F2 ; cycles=3/7 nt/t +17D6: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17DA: 1D F6 CE 34 SUB.W @H'F6CE, R4 ; refs ram_F6CE in on_chip_ram; cycles=7 +17DE: 5B 00 A3 MOV:I.W #H'00A3, R3 ; dataflow R3=H'00A3; cycles=3 +17E1: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +17E5: 27 08 BEQ loc_17EF ; cycles=3/8 nt/t +17E7: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +17EB: 27 02 BEQ loc_17EF ; cycles=3/8 nt/t +17ED: AB CE BSET.W #14, R3 ; cycles=3 + +loc_17EF: +17EF: 1E 01 B0 BSR loc_19A2 ; cycles=14 + +loc_17F2: +17F2: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17F6: 1D F6 CE 94 MOV:G.W R4, @H'F6CE ; refs ram_F6CE in on_chip_ram; cycles=7 +17FA: 19 RTS ; cycles=12 + +loc_17FB: +17FB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1800: 22 22 BHI loc_1824 ; cycles=3/7 nt/t +1802: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +1806: 27 1C BEQ loc_1824 ; cycles=3/7 nt/t +1808: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +180C: 1D F6 CC 34 SUB.W @H'F6CC, R4 ; refs ram_F6CC in on_chip_ram; cycles=7 +1810: 5B 00 A4 MOV:I.W #H'00A4, R3 ; dataflow R3=H'00A4; cycles=3 +1813: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1817: 27 08 BEQ loc_1821 ; cycles=3/8 nt/t +1819: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +181D: 27 02 BEQ loc_1821 ; cycles=3/8 nt/t +181F: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1821: +1821: 1E 01 7E BSR loc_19A2 ; cycles=14 + +loc_1824: +1824: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +1828: 1D F6 CC 94 MOV:G.W R4, @H'F6CC ; refs ram_F6CC in on_chip_ram; cycles=7 +182C: 19 RTS ; cycles=12 + +loc_182D: +182D: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1831: 26 32 BNE loc_1865 ; cycles=3/8 nt/t +1833: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1838: 22 22 BHI loc_185C ; cycles=3/7 nt/t +183A: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +183E: 27 1C BEQ loc_185C ; cycles=3/7 nt/t +1840: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1844: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1848: 5B 00 A5 MOV:I.W #H'00A5, R3 ; dataflow R3=H'00A5; cycles=3 +184B: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +184F: 27 08 BEQ loc_1859 ; cycles=3/8 nt/t +1851: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1855: 27 02 BEQ loc_1859 ; cycles=3/8 nt/t +1857: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1859: +1859: 1E 01 46 BSR loc_19A2 ; cycles=14 + +loc_185C: +185C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1860: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1864: 19 RTS ; cycles=12 + +loc_1865: +1865: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +186A: 22 1C BHI loc_1888 ; cycles=3/7 nt/t +186C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1870: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1874: 5B 00 D8 MOV:I.W #H'00D8, R3 ; dataflow R3=H'00D8; cycles=3 +1877: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +187B: 27 08 BEQ loc_1885 ; cycles=3/8 nt/t +187D: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1881: 27 02 BEQ loc_1885 ; cycles=3/8 nt/t +1883: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1885: +1885: 1E 01 1A BSR loc_19A2 ; cycles=14 + +loc_1888: +1888: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +188C: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1890: 19 RTS ; cycles=12 + +loc_1891: +1891: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1895: 26 24 BNE loc_18BB ; cycles=3/8 nt/t +1897: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +189C: 22 14 BHI loc_18B2 ; cycles=3/7 nt/t +189E: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18A2: 27 0E BEQ loc_18B2 ; cycles=3/7 nt/t +18A4: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18A8: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18AC: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +18AF: 1E 00 F0 BSR loc_19A2 ; cycles=14 + +loc_18B2: +18B2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18B6: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18BA: 19 RTS ; cycles=12 + +loc_18BB: +18BB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18C0: 22 1C BHI loc_18DE ; cycles=3/7 nt/t +18C2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18C6: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18CA: 5B 00 D9 MOV:I.W #H'00D9, R3 ; dataflow R3=H'00D9; cycles=3 +18CD: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +18D1: 27 08 BEQ loc_18DB ; cycles=3/8 nt/t +18D3: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +18D7: 27 02 BEQ loc_18DB ; cycles=3/8 nt/t +18D9: AB CE BSET.W #14, R3 ; cycles=3 + +loc_18DB: +18DB: 1E 00 C4 BSR loc_19A2 ; cycles=14 + +loc_18DE: +18DE: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18E2: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18E6: 19 RTS ; cycles=12 + +loc_18E7: +18E7: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +18EB: 26 32 BNE loc_191F ; cycles=3/8 nt/t +18ED: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18F2: 22 22 BHI loc_1916 ; cycles=3/7 nt/t +18F4: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18F8: 27 1C BEQ loc_1916 ; cycles=3/7 nt/t +18FA: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +18FE: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +1902: 5B 00 A6 MOV:I.W #H'00A6, R3 ; dataflow R3=H'00A6; cycles=3 +1905: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1909: 27 08 BEQ loc_1913 ; cycles=3/8 nt/t +190B: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +190F: 27 02 BEQ loc_1913 ; cycles=3/8 nt/t +1911: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1913: +1913: 1E 00 8C BSR loc_19A2 ; cycles=14 + +loc_1916: +1916: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +191A: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=7 +191E: 19 RTS ; cycles=12 + +loc_191F: +191F: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1924: 22 1B BHI loc_1941 ; cycles=3/7 nt/t +1926: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +192A: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +192E: 5B 00 DA MOV:I.W #H'00DA, R3 ; dataflow R3=H'00DA; cycles=3 +1931: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1935: 27 08 BEQ loc_193F ; cycles=3/8 nt/t +1937: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +193B: 27 02 BEQ loc_193F ; cycles=3/8 nt/t +193D: AB CE BSET.W #14, R3 ; cycles=3 + +loc_193F: +193F: 0E 61 BSR loc_19A2 ; cycles=14 + +loc_1941: +1941: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=6 +1945: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=6 +1949: 19 RTS ; cycles=13 + +loc_194A: +194A: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +194F: 22 1F BHI loc_1970 ; cycles=3/8 nt/t +1951: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=6 +1955: 1D F6 C4 34 SUB.W @H'F6C4, R4 ; refs ram_F6C4 in on_chip_ram; cycles=6 +1959: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +195D: 26 00 BNE loc_195F ; cycles=3/8 nt/t + +loc_195F: +195F: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +1962: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +1966: 27 02 BEQ loc_196A ; cycles=3/7 nt/t +1968: AB CE BSET.W #14, R3 ; cycles=3 + +loc_196A: +196A: 0E 36 BSR loc_19A2 ; cycles=13 +196C: 15 F7 6D C7 BSET.B #7, @H'F76D ; refs ram_F76D in on_chip_ram; cycles=9 + +loc_1970: +1970: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=7 +1974: 1D F6 C4 94 MOV:G.W R4, @H'F6C4 ; refs ram_F6C4 in on_chip_ram; cycles=7 +1978: 19 RTS ; cycles=12 + +loc_1979: +1979: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +197E: 22 19 BHI loc_1999 ; cycles=3/7 nt/t +1980: 1D F6 A2 80 MOV:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +1984: 1D F6 C2 30 SUB.W @H'F6C2, R0 ; refs ram_F6C2 in on_chip_ram; cycles=7 +1988: 1D F6 8C A8 MULXU.W @H'F68C, R0 ; refs ram_F68C in on_chip_ram; cycles=26 +198C: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +198F: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1993: 27 02 BEQ loc_1997 ; cycles=3/8 nt/t +1995: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1997: +1997: 0E 42 BSR loc_19DB ; cycles=14 + +loc_1999: +1999: 1D F6 A2 84 MOV:G.W @H'F6A2, R4 ; refs ram_F6A2 in on_chip_ram; cycles=6 +199D: 1D F6 C2 94 MOV:G.W R4, @H'F6C2 ; refs ram_F6C2 in on_chip_ram; cycles=6 +19A1: 19 RTS ; cycles=13 + +loc_19A2: +19A2: AB 85 MOV:G.W R3, R5 ; cycles=3 +19A4: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19A8: AB 1A SHLL.W R3 ; cycles=3 +19AA: FB E4 00 80 MOV:G.W @(-H'1C00,R3), R0 ; cycles=7 +19AE: 48 FC 00 CMP:I #H'FC00, R0 ; cycles=3 +19B1: 22 03 BHI loc_19B6 ; cycles=3/8 nt/t +19B3: 58 FE 00 MOV:I.W #H'FE00, R0 ; dataflow R0=H'FE00; cycles=3 + +loc_19B6: +19B6: A8 15 NOT.W R0 ; cycles=3 +19B8: A8 08 ADD:Q.W #1, R0 ; cycles=4 +19BA: 4C 00 0F CMP:I #H'000F, R4 ; cycles=3 +19BD: 23 14 BLS loc_19D3 ; cycles=3/8 nt/t +19BF: 4C FF F0 CMP:I #H'FFF0, R4 ; cycles=3 +19C2: 24 0F BCC loc_19D3 ; cycles=3/7 nt/t +19C4: 4C 80 00 CMP:I #H'8000, R4 ; cycles=3 +19C7: 24 05 BCC loc_19CE ; cycles=3/8 nt/t +19C9: 5C 00 1A MOV:I.W #H'001A, R4 ; dataflow R4=H'001A; cycles=3 +19CC: 20 09 BRA loc_19D7 ; cycles=7 + +loc_19CE: +19CE: 5C FF 1C MOV:I.W #H'FF1C, R4 ; dataflow R4=H'FF1C; cycles=3 +19D1: 20 04 BRA loc_19D7 ; cycles=8 + +loc_19D3: +19D3: F4 1A 25 84 MOV:G.B @(H'1A25,R4), R4 ; cycles=6 + +loc_19D7: +19D7: AC A8 MULXU.W R4, R0 ; cycles=25 +19D9: 20 08 BRA loc_19E3 ; cycles=8 + +loc_19DB: +19DB: AB 85 MOV:G.W R3, R5 ; cycles=3 +19DD: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19E1: AB 1A SHLL.W R3 ; cycles=3 + +loc_19E3: +19E3: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +19E7: A8 21 ADD:G.W R0, R1 ; cycles=3 +19E9: A9 82 MOV:G.W R1, R2 ; cycles=3 +19EB: 25 0C BCS loc_19F9 ; cycles=3/8 nt/t +19ED: A8 32 SUB.W R0, R2 ; cycles=3 +19EF: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +19F2: 23 0F BLS loc_1A03 ; cycles=3/7 nt/t +19F4: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +19F7: 20 0A BRA loc_1A03 ; cycles=8 + +loc_19F9: +19F9: AA 30 SUB.W R2, R0 ; cycles=3 +19FB: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +19FE: 23 03 BLS loc_1A03 ; cycles=3/7 nt/t +1A00: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_1A03: +1A03: FB E0 00 71 CMP:G.W @(-H'2000,R3), R1 ; cycles=6 +1A07: 27 0B BEQ loc_1A14 ; cycles=3/8 nt/t +1A09: FB E8 00 91 MOV:G.W R1, @(-H'1800,R3) ; cycles=6 +1A0D: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A0F: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A11: 1E 24 40 BSR loc_3E54 ; cycles=14 + +loc_1A14: +1A14: 19 RTS ; cycles=12 + +loc_1A35: +1A35: AB 85 MOV:G.W R3, R5 ; cycles=3 +1A37: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +1A3B: AB 1A SHLL.W R3 ; cycles=3 +1A3D: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +1A41: 27 3A BEQ loc_1A7D ; cycles=3/8 nt/t +1A43: 0E 48 BSR loc_1A8D ; cycles=14 + +loc_1A45: +1A45: AC 16 TST.W R4 ; cycles=3 +1A47: 26 10 BNE loc_1A59 ; cycles=3/8 nt/t +1A49: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A4B: +1A4B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A4F: A8 1B SHLR.W R0 ; cycles=3 +1A51: 27 16 BEQ loc_1A69 ; cycles=3/8 nt/t +1A53: A8 51 AND.W R0, R1 ; cycles=3 +1A55: 27 F4 BEQ loc_1A4B ; cycles=3/8 nt/t +1A57: 20 12 BRA loc_1A6B ; cycles=8 + +loc_1A59: +1A59: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A5B: +1A5B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A5F: A8 1A SHLL.W R0 ; cycles=3 +1A61: 27 06 BEQ loc_1A69 ; cycles=3/8 nt/t +1A63: A8 51 AND.W R0, R1 ; cycles=3 +1A65: 27 F4 BEQ loc_1A5B ; cycles=3/8 nt/t +1A67: 20 02 BRA loc_1A6B ; cycles=8 + +loc_1A69: +1A69: AA 80 MOV:G.W R2, R0 ; cycles=3 + +loc_1A6B: +1A6B: FB E0 00 70 CMP:G.W @(-H'2000,R3), R0 ; cycles=6 +1A6F: 27 0B BEQ loc_1A7C ; cycles=3/8 nt/t +1A71: FB E8 00 90 MOV:G.W R0, @(-H'1800,R3) ; cycles=6 +1A75: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A77: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A79: 1E 23 D8 BSR loc_3E54 ; cycles=14 + +loc_1A7C: +1A7C: 19 RTS ; cycles=12 + +loc_1A7D: +1A7D: A8 CF BSET.W #15, R0 ; cycles=3 + +loc_1A7F: +1A7F: A8 81 MOV:G.W R0, R1 ; cycles=3 +1A81: FB E4 00 51 AND.W @(-H'1C00,R3), R1 ; cycles=6 +1A85: 26 04 BNE loc_1A8B ; cycles=3/8 nt/t +1A87: A8 1B SHLR.W R0 ; cycles=3 +1A89: 20 F4 BRA loc_1A7F ; cycles=8 + +loc_1A8B: +1A8B: 20 B8 BRA loc_1A45 ; cycles=8 + +loc_1A8D: +1A8D: 59 00 0F MOV:I.W #H'000F, R1 ; dataflow R1=H'000F; cycles=3 + +loc_1A90: +1A90: A8 79 BTST.W R1, R0 ; cycles=3 +1A92: 26 03 BNE loc_1A97 ; cycles=3/7 nt/t +1A94: 01 B9 F9 SCB/F R1, loc_1A90 ; cycles=3/4/8 false/-1/t + +loc_1A97: +1A97: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +1A99: A8 49 BSET.W R1, R0 ; cycles=3 +1A9B: 19 RTS ; cycles=13 + +loc_1A9C: +1A9C: AB 16 TST.W R3 ; cycles=3 +1A9E: 27 32 BEQ loc_1AD2 ; cycles=3/7 nt/t +1AA0: AB 1A SHLL.W R3 ; cycles=3 +1AA2: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +1AA6: A0 15 NOT.B R0 ; cycles=2 +1AA8: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AAB: AC 16 TST.W R4 ; cycles=3 +1AAD: 26 0D BNE loc_1ABC ; cycles=3/8 nt/t + +loc_1AAF: +1AAF: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1AB1: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AB4: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=7 +1AB8: 27 F5 BEQ loc_1AAF ; cycles=3/7 nt/t +1ABA: 20 0B BRA loc_1AC7 ; cycles=7 + +loc_1ABC: +1ABC: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1ABE: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AC1: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=6 +1AC5: 27 F5 BEQ loc_1ABC ; cycles=3/8 nt/t + +loc_1AC7: +1AC7: A0 15 NOT.B R0 ; cycles=2 +1AC9: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1ACC: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +1AD0: 20 0E BRA loc_1AE0 ; cycles=7 + +loc_1AD2: +1AD2: AC 16 TST.W R4 ; cycles=3 +1AD4: 26 06 BNE loc_1ADC ; cycles=3/7 nt/t +1AD6: 15 F7 33 08 ADD:Q.B #1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +1ADA: 20 04 BRA loc_1AE0 ; cycles=7 + +loc_1ADC: +1ADC: 15 F7 33 0C ADD:Q.B #-1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 + +loc_1AE0: +1AE0: 1E 2E 17 BSR loc_48FA ; cycles=13 +1AE3: 19 RTS ; cycles=13 + +loc_1AE4: +1AE4: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=7 +1AE8: A0 12 EXTU.B R0 ; cycles=3 +1AEA: F0 F7 5D 81 MOV:G.B @(-H'08A3,R0), R1 ; cycles=7 +1AEE: AC 16 TST.W R4 ; cycles=3 +1AF0: 26 0A BNE loc_1AFC ; cycles=3/7 nt/t +1AF2: A1 08 ADD:Q.B #1, R1 ; cycles=4 +1AF4: 41 2E CMP:E #H'2E, R1 ; cycles=2 +1AF6: 23 0B BLS loc_1B03 ; cycles=3/7 nt/t +1AF8: 51 00 MOV:E.B #H'00, R1 ; dataflow R1=H'00; cycles=2 +1AFA: 20 07 BRA loc_1B03 ; cycles=7 + +loc_1AFC: +1AFC: 04 01 31 SUB.B #H'01, R1 ; cycles=3 +1AFF: 24 02 BCC loc_1B03 ; cycles=3/8 nt/t +1B01: 51 2E MOV:E.B #H'2E, R1 ; dataflow R1=H'2E; cycles=2 + +loc_1B03: +1B03: F0 F7 5D 91 MOV:G.B R1, @(-H'08A3,R0) ; cycles=6 +1B07: 1E 2D F0 BSR loc_48FA ; cycles=14 +1B0A: 19 RTS ; cycles=12 + +loc_1B0B: +1B0B: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=6 +1B0F: AC 16 TST.W R4 ; cycles=3 +1B11: 26 0A BNE loc_1B1D ; cycles=3/8 nt/t +1B13: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1B15: 40 08 CMP:E #H'08, R0 ; cycles=2 +1B17: 23 0C BLS loc_1B25 ; cycles=3/8 nt/t +1B19: 50 08 MOV:E.B #H'08, R0 ; dataflow R0=H'08; cycles=2 +1B1B: 20 08 BRA loc_1B25 ; cycles=8 + +loc_1B1D: +1B1D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1B1F: 40 01 CMP:E #H'01, R0 ; cycles=2 +1B21: 24 02 BCC loc_1B25 ; cycles=3/8 nt/t +1B23: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_1B25: +1B25: 15 F7 5B 90 MOV:G.B R0, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=6 +1B29: 1E 2D CE BSR loc_48FA ; cycles=14 +1B2C: 19 RTS ; cycles=12 + +loc_1B2D: +1B2D: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B31: 15 F6 E7 64 XOR.B @H'F6E7, R4 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B35: 5D 00 7E MOV:I.W #H'007E, R5 ; dataflow R5=H'007E; cycles=3 +1B38: 1E 00 D3 BSR loc_1C0E ; cycles=13 +1B3B: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B3F: 15 F6 E7 94 MOV:G.B R4, @H'F6E7 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B43: 19 RTS ; cycles=13 + +loc_1B44: +1B44: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B48: 15 F6 E6 64 XOR.B @H'F6E6, R4 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B4C: 5D 00 6E MOV:I.W #H'006E, R5 ; dataflow R5=H'006E; cycles=3 +1B4F: 1E 00 BC BSR loc_1C0E ; cycles=14 +1B52: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B56: 15 F6 E6 94 MOV:G.B R4, @H'F6E6 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B5A: 19 RTS ; cycles=12 + +loc_1B5B: +1B5B: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B5F: 15 F6 E5 64 XOR.B @H'F6E5, R4 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B63: 5D 00 5E MOV:I.W #H'005E, R5 ; dataflow R5=H'005E; cycles=3 +1B66: 1E 00 A5 BSR loc_1C0E ; cycles=13 +1B69: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B6D: 15 F6 E5 94 MOV:G.B R4, @H'F6E5 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B71: 19 RTS ; cycles=13 + +loc_1B72: +1B72: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B76: 15 F6 E1 64 XOR.B @H'F6E1, R4 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B7A: 5D 00 1E MOV:I.W #H'001E, R5 ; dataflow R5=H'001E; cycles=3 +1B7D: 1E 00 8E BSR loc_1C0E ; cycles=14 +1B80: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B84: 15 F6 E1 94 MOV:G.B R4, @H'F6E1 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B88: 19 RTS ; cycles=12 + +loc_1B89: +1B89: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B8D: 15 F6 E0 64 XOR.B @H'F6E0, R4 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B91: 5D 00 0E MOV:I.W #H'000E, R5 ; dataflow R5=H'000E; cycles=3 +1B94: 1E 00 77 BSR loc_1C0E ; cycles=13 +1B97: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B9B: 15 F6 E0 94 MOV:G.B R4, @H'F6E0 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B9F: 19 RTS ; cycles=13 + +loc_1BA0: +1BA0: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=7 +1BA4: 15 F6 E4 64 XOR.B @H'F6E4, R4 ; refs ram_F6E4 in on_chip_ram; cycles=7 +1BA8: 5D 00 4E MOV:I.W #H'004E, R5 ; dataflow R5=H'004E; cycles=3 +1BAB: 0E 61 BSR loc_1C0E ; cycles=14 +1BAD: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=6 +1BB1: 15 F6 E4 94 MOV:G.B R4, @H'F6E4 ; refs ram_F6E4 in on_chip_ram; cycles=6 +1BB5: 19 RTS ; cycles=13 + +loc_1BB6: +1BB6: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=7 +1BBA: 15 F6 E3 64 XOR.B @H'F6E3, R4 ; refs ram_F6E3 in on_chip_ram; cycles=7 +1BBE: 5D 00 3E MOV:I.W #H'003E, R5 ; dataflow R5=H'003E; cycles=3 +1BC1: 0E 4B BSR loc_1C0E ; cycles=14 +1BC3: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=6 +1BC7: 15 F6 E3 94 MOV:G.B R4, @H'F6E3 ; refs ram_F6E3 in on_chip_ram; cycles=6 +1BCB: 19 RTS ; cycles=13 + +loc_1BCC: +1BCC: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=7 +1BD0: 15 F6 E2 64 XOR.B @H'F6E2, R4 ; refs ram_F6E2 in on_chip_ram; cycles=7 +1BD4: 5D 00 2E MOV:I.W #H'002E, R5 ; dataflow R5=H'002E; cycles=3 +1BD7: 0E 35 BSR loc_1C0E ; cycles=14 +1BD9: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=6 +1BDD: 15 F6 E2 94 MOV:G.B R4, @H'F6E2 ; refs ram_F6E2 in on_chip_ram; cycles=6 +1BE1: 19 RTS ; cycles=13 + +loc_1BE2: +1BE2: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=7 +1BE6: 15 F6 EC 64 XOR.B @H'F6EC, R4 ; refs ram_F6EC in on_chip_ram; cycles=7 +1BEA: 5D 00 CE MOV:I.W #H'00CE, R5 ; dataflow R5=H'00CE; cycles=3 +1BED: 0E 1F BSR loc_1C0E ; cycles=14 +1BEF: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=6 +1BF3: 15 F6 EC 94 MOV:G.B R4, @H'F6EC ; refs ram_F6EC in on_chip_ram; cycles=6 +1BF7: 19 RTS ; cycles=13 + +loc_1BF8: +1BF8: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=7 +1BFC: 15 F6 EB 64 XOR.B @H'F6EB, R4 ; refs ram_F6EB in on_chip_ram; cycles=7 +1C00: 5D 00 BE MOV:I.W #H'00BE, R5 ; dataflow R5=H'00BE; cycles=3 +1C03: 0E 09 BSR loc_1C0E ; cycles=14 +1C05: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=6 +1C09: 15 F6 EB 94 MOV:G.B R4, @H'F6EB ; refs ram_F6EB in on_chip_ram; cycles=6 +1C0D: 19 RTS ; cycles=13 + +loc_1C0E: +1C0E: A4 1A SHLL.B R4 ; cycles=2 +1C10: 24 0A BCC loc_1C1C ; cycles=3/7 nt/t +1C12: FD 27 06 80 MOV:G.W @(H'2706,R5), R0 ; cycles=7 +1C16: 12 30 STM.W {R4,R5}, @-SP ; cycles=12 +1C18: 11 D8 JSR @R0 ; JSR @R0 uses R0; target not resolved; cycles=13 +1C1A: 02 30 LDM.W @SP+, {R4,R5} ; cycles=14 + +loc_1C1C: +1C1C: A4 16 TST.B R4 ; cycles=2 +1C1E: 27 04 BEQ loc_1C24 ; cycles=3/7 nt/t +1C20: AD 0D ADD:Q.W #-2, R5 ; cycles=4 +1C22: 20 EA BRA loc_1C0E ; cycles=7 + +loc_1C24: +1C24: 19 RTS ; cycles=12 + +loc_2127: +2127: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=8 +212B: 26 08 BNE loc_2135 ; cycles=3/8 nt/t +212D: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=6 +2131: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=6 + +loc_2135: +2135: 1D F7 32 07 1C 03 MOV:G.W #H'1C03, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +213B: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +2140: 1E 27 B7 BSR loc_48FA ; cycles=13 +2143: 19 RTS ; cycles=13 + +loc_2650: +2650: 15 F6 F6 D5 BCLR.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +2654: 37 00 68 BEQ loc_26BF ; cycles=3/7 nt/t +2657: 1D E1 24 80 MOV:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +265B: A8 1A SHLL.W R0 ; cycles=3 +265D: A0 10 SWAP.B R0 ; cycles=3 +265F: 15 F6 F6 F6 BTST.B #6, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=6 +2663: 26 08 BNE loc_266D ; cycles=3/8 nt/t +2665: A0 08 ADD:Q.B #1, R0 ; cycles=4 +2667: 24 1A BCC loc_2683 ; cycles=3/8 nt/t +2669: 50 FF MOV:E.B #H'FF, R0 ; dataflow R0=H'FF; cycles=2 +266B: 20 16 BRA loc_2683 ; cycles=8 + +loc_266D: +266D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +266F: 1D E0 04 FD BTST.W #13, @H'E004 ; refs mem_E004 in program_or_external; cycles=6 +2673: 26 08 BNE loc_267D ; cycles=3/8 nt/t +2675: 40 49 CMP:E #H'49, R0 ; cycles=2 +2677: 24 0A BCC loc_2683 ; cycles=3/8 nt/t +2679: 50 49 MOV:E.B #H'49, R0 ; dataflow R0=H'49; cycles=2 +267B: 20 06 BRA loc_2683 ; cycles=8 + +loc_267D: +267D: 40 16 CMP:E #H'16, R0 ; cycles=2 +267F: 24 02 BCC loc_2683 ; cycles=3/8 nt/t +2681: 50 16 MOV:E.B #H'16, R0 ; dataflow R0=H'16; cycles=2 + +loc_2683: +2683: A0 12 EXTU.B R0 ; cycles=3 +2685: A0 10 SWAP.B R0 ; cycles=3 +2687: A8 1B SHLR.W R0 ; cycles=3 +2689: A8 CF BSET.W #15, R0 ; cycles=3 +268B: 1D E1 24 70 CMP:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +268F: 27 2E BEQ loc_26BF ; cycles=3/8 nt/t +2691: 1D E9 24 90 MOV:G.W R0, @H'E924 ; refs mem_E924 in program_or_external; cycles=6 +2695: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +2697: 5B 00 92 MOV:I.W #H'0092, R3 ; dataflow R3=H'0092; cycles=3 +269A: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +269E: 27 08 BEQ loc_26A8 ; cycles=3/7 nt/t +26A0: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs mem_F404 in program_or_external; cycles=7 +26A4: 27 02 BEQ loc_26A8 ; cycles=3/7 nt/t +26A6: AB CE BSET.W #14, R3 ; cycles=3 + +loc_26A8: +26A8: 1E 17 A9 BSR loc_3E54 ; cycles=13 +26AB: 15 F6 F6 C0 BSET.B #0, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=8 +26AF: 26 08 BNE loc_26B9 ; cycles=3/8 nt/t +26B1: 1D F6 F4 07 07 D0 MOV:G.W #H'07D0, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 +26B7: 20 06 BRA loc_26BF ; cycles=8 + +loc_26B9: +26B9: 1D F6 F4 07 00 C8 MOV:G.W #H'00C8, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_26BF: +26BF: 19 RTS ; cycles=13 + +loc_2806: +2806: 15 F9 B9 81 MOV:G.B @H'F9B9, R1 ; refs ram_F9B9 in on_chip_ram; cycles=7 +280A: A1 12 EXTU.B R1 ; cycles=3 +280C: 15 F9 B4 71 CMP:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +2810: 26 03 BNE loc_2815 ; cycles=3/7 nt/t +2812: 30 04 91 BRA loc_2CA6 ; cycles=7 + +loc_2815: +2815: A9 80 MOV:G.W R1, R0 ; cycles=3 +2817: A8 1A SHLL.W R0 ; cycles=3 +2819: F8 F9 70 80 MOV:G.W @(-H'0690,R0), R0 ; cycles=6 +281D: A1 08 ADD:Q.B #1, R1 ; cycles=4 +281F: 04 1F 51 AND.B #H'1F, R1 ; cycles=3 +2822: 15 F9 B9 91 MOV:G.B R1, @H'F9B9 ; refs ram_F9B9 in on_chip_ram; cycles=7 +2826: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +282A: A8 85 MOV:G.W R0, R5 ; cycles=3 +282C: 1E 39 D7 BSR loc_6206 ; cycles=13 +282F: A8 84 MOV:G.W R0, R4 ; cycles=3 +2831: AC 1A SHLL.W R4 ; cycles=3 +2833: A8 16 TST.W R0 ; cycles=3 +2835: 27 68 BEQ loc_289F ; cycles=3/8 nt/t +2837: 1D F7 36 81 MOV:G.W @H'F736, R1 ; refs ram_F736 in on_chip_ram; cycles=6 +283B: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +283F: A9 70 CMP:G.W R1, R0 ; cycles=3 +2841: 37 04 67 BEQ loc_2CAB ; cycles=3/8 nt/t +2844: 1D F7 38 81 MOV:G.W @H'F738, R1 ; refs ram_F738 in on_chip_ram; cycles=7 +2848: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +284C: A9 70 CMP:G.W R1, R0 ; cycles=3 +284E: 37 04 5A BEQ loc_2CAB ; cycles=3/7 nt/t +2851: 1D F7 3A 81 MOV:G.W @H'F73A, R1 ; refs ram_F73A in on_chip_ram; cycles=6 +2855: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2859: A9 70 CMP:G.W R1, R0 ; cycles=3 +285B: 37 04 4D BEQ loc_2CAB ; cycles=3/8 nt/t +285E: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs ram_F73C in on_chip_ram; cycles=7 +2862: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2866: A9 70 CMP:G.W R1, R0 ; cycles=3 +2868: 37 04 40 BEQ loc_2CAB ; cycles=3/7 nt/t +286B: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +286F: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2873: A9 70 CMP:G.W R1, R0 ; cycles=3 +2875: 37 04 33 BEQ loc_2CAB ; cycles=3/8 nt/t +2878: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs ram_F740 in on_chip_ram; cycles=7 +287C: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2880: A9 70 CMP:G.W R1, R0 ; cycles=3 +2882: 37 04 26 BEQ loc_2CAB ; cycles=3/7 nt/t +2885: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +2889: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +288D: A9 70 CMP:G.W R1, R0 ; cycles=3 +288F: 37 04 19 BEQ loc_2CAB ; cycles=3/8 nt/t +2892: 1D F7 54 81 MOV:G.W @H'F754, R1 ; refs ram_F754 in on_chip_ram; cycles=7 +2896: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +289A: A9 70 CMP:G.W R1, R0 ; cycles=3 +289C: 37 04 0C BEQ loc_2CAB ; cycles=3/7 nt/t + +loc_289F: +289F: FC 28 A6 81 MOV:G.W @(H'28A6,R4), R1 ; cycles=6 +28A3: 11 D1 JMP @R1 ; JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets); cycles=7 + +loc_2CA6: +2CA6: 15 F7 69 D7 BCLR.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CAA: 19 RTS ; cycles=12 + +loc_2CAB: +2CAB: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +2CAD: 1E 1C 4A BSR loc_48FA ; cycles=14 +2CB0: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 +2CB2: 15 F7 69 C7 BSET.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CB6: 30 FB E6 BRA loc_289F ; cycles=7 + +loc_3930: +3930: 58 00 07 MOV:I.W #H'0007, R0 ; dataflow R0=H'0007; cycles=3 + +loc_3933: +3933: 15 FE 8E 78 BTST.B R0, @P7DR ; refs P7DR in register_field; cycles=6 +3937: 27 0A BEQ loc_3943 ; cycles=3/8 nt/t +3939: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 +393D: F0 F6 80 C0 BSET.B #0, @(-H'0980,R0) ; cycles=8 +3941: 20 04 BRA loc_3947 ; cycles=8 + +loc_3943: +3943: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 + +loc_3947: +3947: F0 F6 80 04 FF CMP:G.B #H'FF, @(-H'0980,R0) ; cycles=6 +394C: 26 06 BNE loc_3954 ; cycles=3/7 nt/t +394E: 15 F6 88 48 BSET.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=9 +3952: 20 0B BRA loc_395F ; cycles=7 + +loc_3954: +3954: F0 F6 80 04 00 CMP:G.B #H'00, @(-H'0980,R0) ; cycles=7 +3959: 26 04 BNE loc_395F ; cycles=3/8 nt/t +395B: 15 F6 88 58 BCLR.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=8 + +loc_395F: +395F: 01 B8 D1 SCB/F R0, loc_3933 ; cycles=3/4/9 false/-1/t +3962: 15 F7 22 08 ADD:Q.B #1, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=9 +3966: 15 F7 22 04 3C CMP:G.B #H'3C, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +396B: 27 0F BEQ loc_397C ; cycles=3/8 nt/t +396D: 15 F7 22 04 78 CMP:G.B #H'78, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=6 +3972: 27 0B BEQ loc_397F ; cycles=3/7 nt/t +3974: 15 F7 22 04 B4 CMP:G.B #H'B4, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +3979: 27 08 BEQ loc_3983 ; cycles=3/8 nt/t +397B: 19 RTS ; cycles=13 + +loc_397C: +397C: 0E 17 BSR loc_3995 ; cycles=13 +397E: 19 RTS ; cycles=12 + +loc_397F: +397F: 1E 00 AC BSR loc_3A2E ; cycles=14 +3982: 19 RTS ; cycles=12 + +loc_3983: +3983: 0E 05 BSR loc_398A ; cycles=14 +3985: 15 F7 22 13 CLR.B @H'F722 ; refs ram_F722 in on_chip_ram; cycles=8 +3989: 19 RTS ; cycles=13 + +loc_398A: +398A: 15 FE E8 F7 BTST.B #7, @ADCSR ; refs ADCSR in register_field; cycles=7 +398E: 26 04 BNE loc_3994 ; cycles=3/7 nt/t +3990: 15 FE E8 C5 BSET.B #5, @ADCSR ; set ADST (bit 5) of ADCSR; cycles=9 + +loc_3994: +3994: 19 RTS ; cycles=12 + +loc_3995: +3995: 15 F7 20 16 TST.B @H'F720 ; refs ram_F720 in on_chip_ram; cycles=6 +3999: 36 00 91 BNE loc_3A2D ; cycles=3/8 nt/t +399C: 15 F1 01 06 A0 MOV:G.B #H'A0, @H'F101 ; refs mem_F101 in program_or_external; cycles=9 +39A1: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +39A5: 37 00 85 BEQ loc_3A2D ; cycles=3/8 nt/t +39A8: 15 F7 1B 80 MOV:G.B @H'F71B, R0 ; refs ram_F71B in on_chip_ram; cycles=7 +39AC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39B0: 15 F7 13 50 AND.B @H'F713, R0 ; refs ram_F713 in on_chip_ram; cycles=7 +39B4: 15 F1 02 90 MOV:G.B R0, @H'F102 ; refs mem_F102 in program_or_external; cycles=7 +39B8: 15 F7 1A 80 MOV:G.B @H'F71A, R0 ; refs ram_F71A in on_chip_ram; cycles=7 +39BC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39C0: 15 F7 12 50 AND.B @H'F712, R0 ; refs ram_F712 in on_chip_ram; cycles=7 +39C4: 15 F1 03 90 MOV:G.B R0, @H'F103 ; refs mem_F103 in program_or_external; cycles=7 +39C8: 15 F7 19 80 MOV:G.B @H'F719, R0 ; refs ram_F719 in on_chip_ram; cycles=7 +39CC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39D0: 15 F7 11 50 AND.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=7 +39D4: 15 F1 04 90 MOV:G.B R0, @H'F104 ; refs mem_F104 in program_or_external; cycles=7 +39D8: 15 F7 18 80 MOV:G.B @H'F718, R0 ; refs ram_F718 in on_chip_ram; cycles=7 +39DC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39E0: 15 F7 10 50 AND.B @H'F710, R0 ; refs ram_F710 in on_chip_ram; cycles=7 +39E4: 15 F1 05 90 MOV:G.B R0, @H'F105 ; refs mem_F105 in program_or_external; cycles=7 +39E8: 15 F7 02 80 MOV:G.B @H'F702, R0 ; refs ram_F702 in on_chip_ram; cycles=7 +39EC: 15 F1 09 90 MOV:G.B R0, @H'F109 ; refs mem_F109 in program_or_external; cycles=7 +39F0: 15 F7 03 80 MOV:G.B @H'F703, R0 ; refs ram_F703 in on_chip_ram; cycles=7 +39F4: 15 F1 0A 90 MOV:G.B R0, @H'F10A ; refs mem_F10A in program_or_external; cycles=7 +39F8: 15 F7 04 80 MOV:G.B @H'F704, R0 ; refs ram_F704 in on_chip_ram; cycles=7 +39FC: 15 F1 0B 90 MOV:G.B R0, @H'F10B ; refs mem_F10B in program_or_external; cycles=7 +3A00: 15 F7 05 80 MOV:G.B @H'F705, R0 ; refs ram_F705 in on_chip_ram; cycles=7 +3A04: 15 F1 0C 90 MOV:G.B R0, @H'F10C ; refs mem_F10C in program_or_external; cycles=7 +3A08: 15 F7 00 80 MOV:G.B @H'F700, R0 ; refs ram_F700 in on_chip_ram; cycles=7 +3A0C: 15 F1 0D 90 MOV:G.B R0, @H'F10D ; refs mem_F10D in program_or_external; cycles=7 +3A10: 15 F7 01 80 MOV:G.B @H'F701, R0 ; refs ram_F701 in on_chip_ram; cycles=7 +3A14: 15 F1 0E 90 MOV:G.B R0, @H'F10E ; refs mem_F10E in program_or_external; cycles=7 +3A18: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=7 +3A1C: A0 15 NOT.B R0 ; cycles=2 +3A1E: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3A21: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3A24: 15 F1 0F 90 MOV:G.B R0, @H'F10F ; refs mem_F10F in program_or_external; cycles=7 +3A28: 15 F7 20 06 03 MOV:G.B #H'03, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=9 + +loc_3A2D: +3A2D: 19 RTS ; cycles=13 + +loc_3A2E: +3A2E: 15 F7 21 16 TST.B @H'F721 ; refs ram_F721 in on_chip_ram; cycles=7 +3A32: 36 00 91 BNE loc_3AC6 ; cycles=3/7 nt/t +3A35: 15 F0 01 06 A0 MOV:G.B #H'A0, @H'F001 ; refs mem_F001 in program_or_external; cycles=9 +3A3A: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3A3E: 37 00 85 BEQ loc_3AC6 ; cycles=3/7 nt/t +3A41: 15 F7 1F 80 MOV:G.B @H'F71F, R0 ; refs ram_F71F in on_chip_ram; cycles=6 +3A45: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A49: 15 F7 17 50 AND.B @H'F717, R0 ; refs ram_F717 in on_chip_ram; cycles=6 +3A4D: 15 F0 02 90 MOV:G.B R0, @H'F002 ; refs mem_F002 in program_or_external; cycles=6 +3A51: 15 F7 1E 80 MOV:G.B @H'F71E, R0 ; refs ram_F71E in on_chip_ram; cycles=6 +3A55: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A59: 15 F7 16 50 AND.B @H'F716, R0 ; refs ram_F716 in on_chip_ram; cycles=6 +3A5D: 15 F0 03 90 MOV:G.B R0, @H'F003 ; refs mem_F003 in program_or_external; cycles=6 +3A61: 15 F7 1D 80 MOV:G.B @H'F71D, R0 ; refs ram_F71D in on_chip_ram; cycles=6 +3A65: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A69: 15 F7 15 50 AND.B @H'F715, R0 ; refs ram_F715 in on_chip_ram; cycles=6 +3A6D: 15 F0 04 90 MOV:G.B R0, @H'F004 ; refs mem_F004 in program_or_external; cycles=6 +3A71: 15 F7 1C 80 MOV:G.B @H'F71C, R0 ; refs ram_F71C in on_chip_ram; cycles=6 +3A75: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A79: 15 F7 14 50 AND.B @H'F714, R0 ; refs ram_F714 in on_chip_ram; cycles=6 +3A7D: 15 F0 05 90 MOV:G.B R0, @H'F005 ; refs mem_F005 in program_or_external; cycles=6 +3A81: 15 F7 08 80 MOV:G.B @H'F708, R0 ; refs ram_F708 in on_chip_ram; cycles=6 +3A85: 15 F0 09 90 MOV:G.B R0, @H'F009 ; refs mem_F009 in program_or_external; cycles=6 +3A89: 15 F7 09 80 MOV:G.B @H'F709, R0 ; refs ram_F709 in on_chip_ram; cycles=6 +3A8D: 15 F0 0A 90 MOV:G.B R0, @H'F00A ; refs mem_F00A in program_or_external; cycles=6 +3A91: 15 F7 0A 80 MOV:G.B @H'F70A, R0 ; refs ram_F70A in on_chip_ram; cycles=6 +3A95: 15 F0 0B 90 MOV:G.B R0, @H'F00B ; refs mem_F00B in program_or_external; cycles=6 +3A99: 15 F7 0B 80 MOV:G.B @H'F70B, R0 ; refs ram_F70B in on_chip_ram; cycles=6 +3A9D: 15 F0 0C 90 MOV:G.B R0, @H'F00C ; refs mem_F00C in program_or_external; cycles=6 +3AA1: 15 F7 06 80 MOV:G.B @H'F706, R0 ; refs ram_F706 in on_chip_ram; cycles=6 +3AA5: 15 F0 0D 90 MOV:G.B R0, @H'F00D ; refs mem_F00D in program_or_external; cycles=6 +3AA9: 15 F7 07 80 MOV:G.B @H'F707, R0 ; refs ram_F707 in on_chip_ram; cycles=6 +3AAD: 15 F0 0E 90 MOV:G.B R0, @H'F00E ; refs mem_F00E in program_or_external; cycles=6 +3AB1: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=6 +3AB5: A0 15 NOT.B R0 ; cycles=2 +3AB7: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3ABA: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3ABD: 15 F0 0F 90 MOV:G.B R0, @H'F00F ; refs mem_F00F in program_or_external; cycles=6 +3AC1: 15 F7 21 06 03 MOV:G.B #H'03, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3AC6: +3AC6: 19 RTS ; cycles=12 + +vec_irq4_3AC7: +3AC7: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +3AC9: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +3ACD: 36 01 5D BNE loc_3C2D ; cycles=3/8 nt/t +3AD0: 15 F1 0F 80 MOV:G.B @H'F10F, R0 ; refs mem_F10F in program_or_external; cycles=7 +3AD4: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3AD6: 27 08 BEQ loc_3AE0 ; cycles=3/7 nt/t +3AD8: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3ADA: 37 00 85 BEQ loc_3B62 ; cycles=3/7 nt/t +3ADD: 30 01 4D BRA loc_3C2D ; cycles=8 + +loc_3AE0: +3AE0: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3AE4: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3AE7: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3AEB: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3AEF: 1D F6 9A 70 CMP:G.W @H'F69A, R0 ; refs ram_F69A in on_chip_ram; cycles=6 +3AF3: 27 08 BEQ loc_3AFD ; cycles=3/8 nt/t +3AF5: 15 F6 F0 C5 BSET.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3AF9: 1D F6 9A 90 MOV:G.W R0, @H'F69A ; refs ram_F69A in on_chip_ram; cycles=6 + +loc_3AFD: +3AFD: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B01: 1D F6 98 70 CMP:G.W @H'F698, R0 ; refs ram_F698 in on_chip_ram; cycles=6 +3B05: 27 08 BEQ loc_3B0F ; cycles=3/8 nt/t +3B07: 15 F6 F0 C4 BSET.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B0B: 1D F6 98 90 MOV:G.W R0, @H'F698 ; refs ram_F698 in on_chip_ram; cycles=6 + +loc_3B0F: +3B0F: 1D F1 08 80 MOV:G.W @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3B13: 1D F6 96 70 CMP:G.W @H'F696, R0 ; refs ram_F696 in on_chip_ram; cycles=6 +3B17: 27 08 BEQ loc_3B21 ; cycles=3/8 nt/t +3B19: 15 F6 F0 C3 BSET.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B1D: 1D F6 96 90 MOV:G.W R0, @H'F696 ; refs ram_F696 in on_chip_ram; cycles=6 + +loc_3B21: +3B21: 1D F1 06 80 MOV:G.W @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3B25: 1D F6 94 70 CMP:G.W @H'F694, R0 ; refs ram_F694 in on_chip_ram; cycles=6 +3B29: 27 08 BEQ loc_3B33 ; cycles=3/8 nt/t +3B2B: 15 F6 F0 C2 BSET.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B2F: 1D F6 94 90 MOV:G.W R0, @H'F694 ; refs ram_F694 in on_chip_ram; cycles=6 + +loc_3B33: +3B33: 1D F1 04 80 MOV:G.W @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3B37: 1D F6 92 70 CMP:G.W @H'F692, R0 ; refs ram_F692 in on_chip_ram; cycles=6 +3B3B: 27 08 BEQ loc_3B45 ; cycles=3/8 nt/t +3B3D: 15 F6 F0 C1 BSET.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B41: 1D F6 92 90 MOV:G.W R0, @H'F692 ; refs ram_F692 in on_chip_ram; cycles=6 + +loc_3B45: +3B45: 1D F1 02 80 MOV:G.W @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3B49: 1D F6 90 70 CMP:G.W @H'F690, R0 ; refs ram_F690 in on_chip_ram; cycles=6 +3B4D: 27 08 BEQ loc_3B57 ; cycles=3/8 nt/t +3B4F: 15 F6 F0 C0 BSET.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B53: 1D F6 90 90 MOV:G.W R0, @H'F690 ; refs ram_F690 in on_chip_ram; cycles=6 + +loc_3B57: +3B57: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3B5B: 15 F7 20 D0 BCLR.B #0, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 +3B5F: 30 00 CB BRA loc_3C2D ; cycles=8 + +loc_3B62: +3B62: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3B66: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3B69: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3B6D: 15 F6 F2 13 CLR.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3B71: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3B75: 1D F6 9E 70 CMP:G.W @H'F69E, R0 ; refs ram_F69E in on_chip_ram; cycles=6 +3B79: 27 08 BEQ loc_3B83 ; cycles=3/8 nt/t +3B7B: 15 F6 F0 C7 BSET.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B7F: 1D F6 9E 90 MOV:G.W R0, @H'F69E ; refs ram_F69E in on_chip_ram; cycles=6 + +loc_3B83: +3B83: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B87: 1D F6 9C 70 CMP:G.W @H'F69C, R0 ; refs ram_F69C in on_chip_ram; cycles=6 +3B8B: 27 08 BEQ loc_3B95 ; cycles=3/8 nt/t +3B8D: 15 F6 F0 C6 BSET.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B91: 1D F6 9C 90 MOV:G.W R0, @H'F69C ; refs ram_F69C in on_chip_ram; cycles=6 + +loc_3B95: +3B95: 15 F1 09 80 MOV:G.B @H'F109, R0 ; refs mem_F109 in program_or_external; cycles=6 +3B99: 15 F6 D0 70 CMP:G.B @H'F6D0, R0 ; refs ram_F6D0 in on_chip_ram; cycles=6 +3B9D: 27 08 BEQ loc_3BA7 ; cycles=3/8 nt/t +3B9F: 15 F6 F2 C0 BSET.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BA3: 15 F6 D0 90 MOV:G.B R0, @H'F6D0 ; refs ram_F6D0 in on_chip_ram; cycles=6 + +loc_3BA7: +3BA7: 15 F1 08 80 MOV:G.B @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3BAB: 15 F6 D1 70 CMP:G.B @H'F6D1, R0 ; refs ram_F6D1 in on_chip_ram; cycles=6 +3BAF: 27 08 BEQ loc_3BB9 ; cycles=3/8 nt/t +3BB1: 15 F6 F2 C1 BSET.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BB5: 15 F6 D1 90 MOV:G.B R0, @H'F6D1 ; refs ram_F6D1 in on_chip_ram; cycles=6 + +loc_3BB9: +3BB9: 15 F1 07 80 MOV:G.B @H'F107, R0 ; refs mem_F107 in program_or_external; cycles=6 +3BBD: 15 F6 D2 70 CMP:G.B @H'F6D2, R0 ; refs ram_F6D2 in on_chip_ram; cycles=6 +3BC1: 27 08 BEQ loc_3BCB ; cycles=3/8 nt/t +3BC3: 15 F6 F2 C2 BSET.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BC7: 15 F6 D2 90 MOV:G.B R0, @H'F6D2 ; refs ram_F6D2 in on_chip_ram; cycles=6 + +loc_3BCB: +3BCB: 15 F1 06 80 MOV:G.B @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3BCF: 15 F6 D3 70 CMP:G.B @H'F6D3, R0 ; refs ram_F6D3 in on_chip_ram; cycles=6 +3BD3: 27 08 BEQ loc_3BDD ; cycles=3/8 nt/t +3BD5: 15 F6 F2 C3 BSET.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BD9: 15 F6 D3 90 MOV:G.B R0, @H'F6D3 ; refs ram_F6D3 in on_chip_ram; cycles=6 + +loc_3BDD: +3BDD: 15 F1 05 80 MOV:G.B @H'F105, R0 ; refs mem_F105 in program_or_external; cycles=6 +3BE1: 15 F6 D4 70 CMP:G.B @H'F6D4, R0 ; refs ram_F6D4 in on_chip_ram; cycles=6 +3BE5: 27 08 BEQ loc_3BEF ; cycles=3/8 nt/t +3BE7: 15 F6 F2 C4 BSET.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BEB: 15 F6 D4 90 MOV:G.B R0, @H'F6D4 ; refs ram_F6D4 in on_chip_ram; cycles=6 + +loc_3BEF: +3BEF: 15 F1 04 80 MOV:G.B @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3BF3: 15 F6 D5 70 CMP:G.B @H'F6D5, R0 ; refs ram_F6D5 in on_chip_ram; cycles=6 +3BF7: 27 08 BEQ loc_3C01 ; cycles=3/8 nt/t +3BF9: 15 F6 F2 C5 BSET.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BFD: 15 F6 D5 90 MOV:G.B R0, @H'F6D5 ; refs ram_F6D5 in on_chip_ram; cycles=6 + +loc_3C01: +3C01: 15 F1 03 80 MOV:G.B @H'F103, R0 ; refs mem_F103 in program_or_external; cycles=6 +3C05: 15 F6 D6 70 CMP:G.B @H'F6D6, R0 ; refs ram_F6D6 in on_chip_ram; cycles=6 +3C09: 27 08 BEQ loc_3C13 ; cycles=3/8 nt/t +3C0B: 15 F6 F2 C6 BSET.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C0F: 15 F6 D6 90 MOV:G.B R0, @H'F6D6 ; refs ram_F6D6 in on_chip_ram; cycles=6 + +loc_3C13: +3C13: 15 F1 02 80 MOV:G.B @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3C17: 15 F6 D7 70 CMP:G.B @H'F6D7, R0 ; refs ram_F6D7 in on_chip_ram; cycles=6 +3C1B: 27 08 BEQ loc_3C25 ; cycles=3/8 nt/t +3C1D: 15 F6 F2 C7 BSET.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C21: 15 F6 D7 90 MOV:G.B R0, @H'F6D7 ; refs ram_F6D7 in on_chip_ram; cycles=6 + +loc_3C25: +3C25: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3C29: 15 F7 20 D1 BCLR.B #1, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 + +loc_3C2D: +3C2D: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +3C2F: 0A RTE ; cycles=14 + +vec_irq3_3C30: +3C30: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +3C32: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3C36: 36 01 5D BNE loc_3D96 ; cycles=3/7 nt/t +3C39: 15 F0 0F 80 MOV:G.B @H'F00F, R0 ; refs mem_F00F in program_or_external; cycles=6 +3C3D: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3C3F: 27 08 BEQ loc_3C49 ; cycles=3/8 nt/t +3C41: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3C43: 37 00 85 BEQ loc_3CCB ; cycles=3/8 nt/t +3C46: 30 01 4D BRA loc_3D96 ; cycles=7 + +loc_3C49: +3C49: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3C4D: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3C50: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3C54: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3C58: 1D F6 AA 70 CMP:G.W @H'F6AA, R0 ; refs ram_F6AA in on_chip_ram; cycles=7 +3C5C: 27 08 BEQ loc_3C66 ; cycles=3/7 nt/t +3C5E: 15 F6 F1 C5 BSET.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C62: 1D F6 AA 90 MOV:G.W R0, @H'F6AA ; refs ram_F6AA in on_chip_ram; cycles=7 + +loc_3C66: +3C66: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3C6A: 1D F6 A8 70 CMP:G.W @H'F6A8, R0 ; refs ram_F6A8 in on_chip_ram; cycles=7 +3C6E: 27 08 BEQ loc_3C78 ; cycles=3/7 nt/t +3C70: 15 F6 F1 C4 BSET.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C74: 1D F6 A8 90 MOV:G.W R0, @H'F6A8 ; refs ram_F6A8 in on_chip_ram; cycles=7 + +loc_3C78: +3C78: 1D F0 08 80 MOV:G.W @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3C7C: 1D F6 A6 70 CMP:G.W @H'F6A6, R0 ; refs ram_F6A6 in on_chip_ram; cycles=7 +3C80: 27 08 BEQ loc_3C8A ; cycles=3/7 nt/t +3C82: 15 F6 F1 C3 BSET.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C86: 1D F6 A6 90 MOV:G.W R0, @H'F6A6 ; refs ram_F6A6 in on_chip_ram; cycles=7 + +loc_3C8A: +3C8A: 1D F0 06 80 MOV:G.W @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3C8E: 1D F6 A4 70 CMP:G.W @H'F6A4, R0 ; refs ram_F6A4 in on_chip_ram; cycles=7 +3C92: 27 08 BEQ loc_3C9C ; cycles=3/7 nt/t +3C94: 15 F6 F1 C2 BSET.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C98: 1D F6 A4 90 MOV:G.W R0, @H'F6A4 ; refs ram_F6A4 in on_chip_ram; cycles=7 + +loc_3C9C: +3C9C: 1D F0 04 80 MOV:G.W @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3CA0: 1D F6 A2 70 CMP:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +3CA4: 27 08 BEQ loc_3CAE ; cycles=3/7 nt/t +3CA6: 15 F6 F1 C1 BSET.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CAA: 1D F6 A2 90 MOV:G.W R0, @H'F6A2 ; refs ram_F6A2 in on_chip_ram; cycles=7 + +loc_3CAE: +3CAE: 1D F0 02 80 MOV:G.W @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3CB2: 1D F6 A0 70 CMP:G.W @H'F6A0, R0 ; refs ram_F6A0 in on_chip_ram; cycles=7 +3CB6: 27 08 BEQ loc_3CC0 ; cycles=3/7 nt/t +3CB8: 15 F6 F1 C0 BSET.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CBC: 1D F6 A0 90 MOV:G.W R0, @H'F6A0 ; refs ram_F6A0 in on_chip_ram; cycles=7 + +loc_3CC0: +3CC0: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3CC4: 15 F7 21 D0 BCLR.B #0, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 +3CC8: 30 00 CB BRA loc_3D96 ; cycles=7 + +loc_3CCB: +3CCB: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3CCF: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3CD2: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3CD6: 15 F6 F3 13 CLR.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3CDA: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3CDE: 1D F6 AE 70 CMP:G.W @H'F6AE, R0 ; refs ram_F6AE in on_chip_ram; cycles=7 +3CE2: 27 08 BEQ loc_3CEC ; cycles=3/7 nt/t +3CE4: 15 F6 F1 C7 BSET.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CE8: 1D F6 AE 90 MOV:G.W R0, @H'F6AE ; refs ram_F6AE in on_chip_ram; cycles=7 + +loc_3CEC: +3CEC: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3CF0: 1D F6 AC 70 CMP:G.W @H'F6AC, R0 ; refs ram_F6AC in on_chip_ram; cycles=7 +3CF4: 27 08 BEQ loc_3CFE ; cycles=3/7 nt/t +3CF6: 15 F6 F1 C6 BSET.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CFA: 1D F6 AC 90 MOV:G.W R0, @H'F6AC ; refs ram_F6AC in on_chip_ram; cycles=7 + +loc_3CFE: +3CFE: 15 F0 09 80 MOV:G.B @H'F009, R0 ; refs mem_F009 in program_or_external; cycles=7 +3D02: 15 F6 D8 70 CMP:G.B @H'F6D8, R0 ; refs ram_F6D8 in on_chip_ram; cycles=7 +3D06: 27 08 BEQ loc_3D10 ; cycles=3/7 nt/t +3D08: 15 F6 F3 C0 BSET.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D0C: 15 F6 D8 90 MOV:G.B R0, @H'F6D8 ; refs ram_F6D8 in on_chip_ram; cycles=7 + +loc_3D10: +3D10: 15 F0 08 80 MOV:G.B @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3D14: 15 F6 D9 70 CMP:G.B @H'F6D9, R0 ; refs ram_F6D9 in on_chip_ram; cycles=7 +3D18: 27 08 BEQ loc_3D22 ; cycles=3/7 nt/t +3D1A: 15 F6 F3 C1 BSET.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D1E: 15 F6 D9 90 MOV:G.B R0, @H'F6D9 ; refs ram_F6D9 in on_chip_ram; cycles=7 + +loc_3D22: +3D22: 15 F0 07 80 MOV:G.B @H'F007, R0 ; refs mem_F007 in program_or_external; cycles=7 +3D26: 15 F6 DA 70 CMP:G.B @H'F6DA, R0 ; refs ram_F6DA in on_chip_ram; cycles=7 +3D2A: 27 08 BEQ loc_3D34 ; cycles=3/7 nt/t +3D2C: 15 F6 F3 C2 BSET.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D30: 15 F6 DA 90 MOV:G.B R0, @H'F6DA ; refs ram_F6DA in on_chip_ram; cycles=7 + +loc_3D34: +3D34: 15 F0 06 80 MOV:G.B @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3D38: 15 F6 DB 70 CMP:G.B @H'F6DB, R0 ; refs ram_F6DB in on_chip_ram; cycles=7 +3D3C: 27 08 BEQ loc_3D46 ; cycles=3/7 nt/t +3D3E: 15 F6 F3 C3 BSET.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D42: 15 F6 DB 90 MOV:G.B R0, @H'F6DB ; refs ram_F6DB in on_chip_ram; cycles=7 + +loc_3D46: +3D46: 15 F0 05 80 MOV:G.B @H'F005, R0 ; refs mem_F005 in program_or_external; cycles=7 +3D4A: 15 F6 DC 70 CMP:G.B @H'F6DC, R0 ; refs ram_F6DC in on_chip_ram; cycles=7 +3D4E: 27 08 BEQ loc_3D58 ; cycles=3/7 nt/t +3D50: 15 F6 F3 C4 BSET.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D54: 15 F6 DC 90 MOV:G.B R0, @H'F6DC ; refs ram_F6DC in on_chip_ram; cycles=7 + +loc_3D58: +3D58: 15 F0 04 80 MOV:G.B @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3D5C: 15 F6 DD 70 CMP:G.B @H'F6DD, R0 ; refs ram_F6DD in on_chip_ram; cycles=7 +3D60: 27 08 BEQ loc_3D6A ; cycles=3/7 nt/t +3D62: 15 F6 F3 C5 BSET.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D66: 15 F6 DD 90 MOV:G.B R0, @H'F6DD ; refs ram_F6DD in on_chip_ram; cycles=7 + +loc_3D6A: +3D6A: 15 F0 03 80 MOV:G.B @H'F003, R0 ; refs mem_F003 in program_or_external; cycles=7 +3D6E: 15 F6 DE 70 CMP:G.B @H'F6DE, R0 ; refs ram_F6DE in on_chip_ram; cycles=7 +3D72: 27 08 BEQ loc_3D7C ; cycles=3/7 nt/t +3D74: 15 F6 F3 C6 BSET.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D78: 15 F6 DE 90 MOV:G.B R0, @H'F6DE ; refs ram_F6DE in on_chip_ram; cycles=7 + +loc_3D7C: +3D7C: 15 F0 02 80 MOV:G.B @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3D80: 15 F6 DF 70 CMP:G.B @H'F6DF, R0 ; refs ram_F6DF in on_chip_ram; cycles=7 +3D84: 27 08 BEQ loc_3D8E ; cycles=3/7 nt/t +3D86: 15 F6 F3 C7 BSET.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D8A: 15 F6 DF 90 MOV:G.B R0, @H'F6DF ; refs ram_F6DF in on_chip_ram; cycles=7 + +loc_3D8E: +3D8E: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3D92: 15 F7 21 D1 BCLR.B #1, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3D96: +3D96: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +3D98: 0A RTE ; cycles=13 + +vec_ad_adi_3D99: +3D99: 15 FE E8 D5 BCLR.B #5, @ADCSR ; clear ADST (bit 5) of ADCSR; cycles=8 +3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DA3: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; ADDRA word read; TEMP byte-order hazard avoided; refs ADDRA_H in register_field; cycles=7 +3DAA: A1 10 SWAP.B R1 ; cycles=3 +3DAC: A1 12 EXTU.B R1 ; cycles=3 +3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 ; cycles=7 +3DB2: A9 20 ADD:G.W R1, R0 ; cycles=3 +3DB4: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3DB7: 15 F6 8A 70 CMP:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DBB: 27 4B BEQ loc_3E08 ; cycles=3/8 nt/t +3DBD: 15 F6 8A 82 MOV:G.B @H'F68A, R2 ; refs ram_F68A in on_chip_ram; cycles=6 +3DC1: 15 F6 8A 90 MOV:G.B R0, @H'F68A ; refs ram_F68A in on_chip_ram; cycles=6 +3DC5: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +3DCA: 22 3C BHI loc_3E08 ; cycles=3/7 nt/t +3DCC: A0 12 EXTU.B R0 ; cycles=3 +3DCE: A2 12 EXTU.B R2 ; cycles=3 +3DD0: 0C 01 01 A8 MULXU.W #H'0101, R0 ; cycles=25 +3DD4: 0C 01 01 AA MULXU.W #H'0101, R2 ; cycles=25 +3DD8: AB 31 SUB.W R3, R1 ; cycles=3 +3DDA: 1D E1 02 80 MOV:G.W @H'E102, R0 ; refs mem_E102 in program_or_external; cycles=7 +3DDE: A8 21 ADD:G.W R0, R1 ; cycles=3 +3DE0: A9 82 MOV:G.W R1, R2 ; cycles=3 +3DE2: 25 0C BCS loc_3DF0 ; cycles=3/7 nt/t +3DE4: A8 32 SUB.W R0, R2 ; cycles=3 +3DE6: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +3DE9: 23 0F BLS loc_3DFA ; cycles=3/8 nt/t +3DEB: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +3DEE: 20 0A BRA loc_3DFA ; cycles=7 + +loc_3DF0: +3DF0: AA 30 SUB.W R2, R0 ; cycles=3 +3DF2: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +3DF5: 23 03 BLS loc_3DFA ; cycles=3/8 nt/t +3DF7: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_3DFA: +3DFA: 1D E1 02 71 CMP:G.W @H'E102, R1 ; refs mem_E102 in program_or_external; cycles=7 +3DFE: 27 08 BEQ loc_3E08 ; cycles=3/7 nt/t +3E00: 1D F6 8E 91 MOV:G.W R1, @H'F68E ; refs ram_F68E in on_chip_ram; cycles=7 +3E04: 15 F6 89 C7 BSET.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=9 + +loc_3E08: +3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E0C: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; ADDRB word read; TEMP byte-order hazard avoided; refs ADDRB_H in register_field; cycles=6 +3E13: A1 10 SWAP.B R1 ; cycles=3 +3E15: A1 12 EXTU.B R1 ; cycles=3 +3E17: A9 20 ADD:G.W R1, R0 ; cycles=3 +3E19: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3E1C: 1D F6 8C 16 TST.W @H'F68C ; refs ram_F68C in on_chip_ram; cycles=7 +3E20: 27 06 BEQ loc_3E28 ; cycles=3/7 nt/t +3E22: 15 F6 8B 70 CMP:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E26: 27 25 BEQ loc_3E4D ; cycles=3/7 nt/t + +loc_3E28: +3E28: 15 F6 8B 90 MOV:G.B R0, @H'F68B ; refs ram_F68B in on_chip_ram; cycles=7 +3E2C: A0 12 EXTU.B R0 ; cycles=3 +3E2E: A8 83 MOV:G.W R0, R3 ; cycles=3 +3E30: A3 AB MULXU.B R3, R3 ; cycles=18 +3E32: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +3E34: 0C 00 C8 BA DIVXU.W #H'00C8, R2 ; cycles=29 +3E38: 04 04 A8 MULXU.B #H'04, R0 ; cycles=19 +3E3B: 0C 00 AB 20 ADD:G.W #H'00AB, R0 ; cycles=4 +3E3F: AB 20 ADD:G.W R3, R0 ; cycles=3 +3E41: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +3E45: 26 02 BNE loc_3E49 ; cycles=3/8 nt/t +3E47: A8 1B SHLR.W R0 ; cycles=3 + +loc_3E49: +3E49: 1D F6 8C 90 MOV:G.W R0, @H'F68C ; refs ram_F68C in on_chip_ram; cycles=6 + +loc_3E4D: +3E4D: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 +3E4F: 15 FE E8 D7 BCLR.B #7, @ADCSR ; clear ADF (bit 7) of ADCSR; cycles=8 +3E53: 0A RTE ; cycles=14 + +loc_3E54: +3E54: A2 F7 BTST.B #7, R2 ; cycles=2 +3E56: 27 42 BEQ loc_3E9A ; cycles=3/7 nt/t +3E58: 15 F9 B5 80 MOV:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=7 +3E5C: A0 12 EXTU.B R0 ; cycles=3 +3E5E: A8 1A SHLL.W R0 ; cycles=3 +3E60: 15 F9 B0 81 MOV:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E64: A1 12 EXTU.B R1 ; cycles=3 +3E66: A9 1A SHLL.W R1 ; cycles=3 + +loc_3E68: +3E68: A0 71 CMP:G.B R0, R1 ; cycles=2 +3E6A: 27 0A BEQ loc_3E76 ; cycles=3/7 nt/t +3E6C: F8 F8 70 73 CMP:G.W @(-H'0790,R0), R3 ; cycles=7 +3E70: 27 28 BEQ loc_3E9A ; cycles=3/7 nt/t +3E72: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3E74: 20 F2 BRA loc_3E68 ; cycles=7 + +loc_3E76: +3E76: F9 F8 70 93 MOV:G.W R3, @(-H'0790,R1) ; cycles=7 +3E7A: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +3E7E: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_3E82: +3E82: 15 F9 B0 80 MOV:G.B @H'F9B0, R0 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E86: A0 08 ADD:Q.B #1, R0 ; cycles=4 +3E88: 04 7F 50 AND.B #H'7F, R0 ; cycles=3 +3E8B: 15 F9 B5 70 CMP:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=6 +3E8F: 26 09 BNE loc_3E9A ; cycles=3/8 nt/t +3E91: 12 0C STM.W {R2,R3}, @-SP ; cycles=12 +3E93: 1E 01 3D BSR loc_3FD3 ; cycles=14 +3E96: 02 0C LDM.W @SP+, {R2,R3} ; cycles=14 +3E98: 20 E8 BRA loc_3E82 ; cycles=7 + +loc_3E9A: +3E9A: A2 F6 BTST.B #6, R2 ; cycles=2 +3E9C: 27 2D BEQ loc_3ECB ; cycles=3/7 nt/t +3E9E: 15 F9 B9 80 MOV:G.B @H'F9B9, R0 ; refs ram_F9B9 in on_chip_ram; cycles=7 +3EA2: A0 12 EXTU.B R0 ; cycles=3 +3EA4: A8 1A SHLL.W R0 ; cycles=3 +3EA6: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +3EAA: A1 12 EXTU.B R1 ; cycles=3 +3EAC: A9 1A SHLL.W R1 ; cycles=3 + +loc_3EAE: +3EAE: A0 71 CMP:G.B R0, R1 ; cycles=2 +3EB0: 27 0D BEQ loc_3EBF ; cycles=3/7 nt/t +3EB2: F8 F9 70 73 CMP:G.W @(-H'0690,R0), R3 ; cycles=7 +3EB6: 27 13 BEQ loc_3ECB ; cycles=3/7 nt/t +3EB8: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3EBA: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3EBD: 20 EF BRA loc_3EAE ; cycles=8 + +loc_3EBF: +3EBF: F9 F9 70 93 MOV:G.W R3, @(-H'0690,R1) ; cycles=6 +3EC3: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +3EC7: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_3ECB: +3ECB: 19 RTS ; cycles=13 + +loc_3ECC: +3ECC: 12 1F STM.W {R0,R1,R2,R3,R4}, @-SP ; cycles=21 +3ECE: A5 12 EXTU.B R5 ; cycles=3 +3ED0: 45 03 CMP:E #H'03, R5 ; cycles=2 +3ED2: 23 05 BLS loc_3ED9 ; cycles=3/7 nt/t +3ED4: 1E 00 69 BSR loc_3F40 ; cycles=13 +3ED7: 20 4C BRA loc_3F25 ; cycles=8 + +loc_3ED9: +3ED9: A5 83 MOV:G.B R5, R3 ; cycles=2 +3EDB: 45 00 CMP:E #H'00, R5 ; cycles=2 +3EDD: 27 0A BEQ loc_3EE9 ; cycles=3/8 nt/t +3EDF: 45 01 CMP:E #H'01, R5 ; cycles=2 +3EE1: 27 0B BEQ loc_3EEE ; cycles=3/8 nt/t +3EE3: 45 02 CMP:E #H'02, R5 ; cycles=2 +3EE5: 27 0C BEQ loc_3EF3 ; cycles=3/8 nt/t +3EE7: 20 0F BRA loc_3EF8 ; cycles=8 + +loc_3EE9: +3EE9: 5D 00 80 MOV:I.W #H'0080, R5 ; dataflow R5=H'0080; cycles=3 +3EEC: 20 0D BRA loc_3EFB ; cycles=7 + +loc_3EEE: +3EEE: 5D 00 C0 MOV:I.W #H'00C0, R5 ; dataflow R5=H'00C0; cycles=3 +3EF1: 20 08 BRA loc_3EFB ; cycles=8 + +loc_3EF3: +3EF3: 5D 00 90 MOV:I.W #H'0090, R5 ; dataflow R5=H'0090; cycles=3 +3EF6: 20 03 BRA loc_3EFB ; cycles=7 + +loc_3EF8: +3EF8: 5D 00 D0 MOV:I.W #H'00D0, R5 ; dataflow R5=H'00D0; cycles=3 + +loc_3EFB: +3EFB: 04 10 AB MULXU.B #H'10, R3 ; cycles=19 +3EFE: 0C FA B0 23 ADD:G.W #H'FAB0, R3 ; cycles=4 +3F02: A9 13 CLR.W R1 ; dataflow R1=H'0000; cycles=3 + +loc_3F04: +3F04: F1 FA F0 82 MOV:G.B @(-H'0510,R1), R2 ; cycles=7 +3F08: D3 72 CMP:G.B @R3, R2 ; cycles=6 +3F0A: 27 04 BEQ loc_3F10 ; cycles=3/7 nt/t +3F0C: D3 92 MOV:G.B R2, @R3 ; cycles=6 +3F0E: 0E 18 BSR loc_3F28 ; cycles=13 + +loc_3F10: +3F10: A1 08 ADD:Q.B #1, R1 ; cycles=4 +3F12: A3 08 ADD:Q.B #1, R3 ; cycles=4 +3F14: 41 10 CMP:E #H'10, R1 ; cycles=2 +3F16: 27 02 BEQ loc_3F1A ; cycles=3/7 nt/t +3F18: 20 EA BRA loc_3F04 ; cycles=7 + +loc_3F1A: +3F1A: 1D FB 00 07 00 E0 MOV:G.W #H'00E0, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=11 +3F20: 5C 00 E0 MOV:I.W #H'00E0, R4 ; dataflow R4=H'00E0; cycles=3 +3F23: 0E 1B BSR loc_3F40 ; cycles=14 + +loc_3F25: +3F25: 02 1F LDM.W @SP+, {R0,R1,R2,R3,R4} ; cycles=26 +3F27: 19 RTS ; cycles=13 + +loc_3F28: +3F28: AD 84 MOV:G.W R5, R4 ; cycles=3 +3F2A: A1 24 ADD:G.B R1, R4 ; cycles=2 +3F2C: 1D FB 00 74 CMP:G.W @H'FB00, R4 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F30: 27 06 BEQ loc_3F38 ; cycles=3/7 nt/t +3F32: 1D FB 00 94 MOV:G.W R4, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F36: 0E 08 BSR loc_3F40 ; cycles=13 + +loc_3F38: +3F38: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +3F3B: A2 24 ADD:G.B R2, R4 ; cycles=2 +3F3D: 0E 01 BSR loc_3F40 ; cycles=14 +3F3F: 19 RTS ; cycles=13 + +loc_3F40: +3F40: BF 98 STC.W SR, @-R7 ; cycles=8 +3F42: 0C 00 FF 58 ANDC.W #H'00FF, SR ; cycles=4 +3F46: 0C 06 00 48 ORC.W #H'0600, SR ; cycles=4 + +loc_3F4A: +3F4A: 15 F2 00 00 80 MOVFPE.B @H'F200, R0 ; LCD status read from E-clock H'F200; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; refs mem_F200 in program_or_external; cycles=13 +3F4F: A0 F7 BTST.B #7, R0 ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=2 +3F51: 26 F7 BNE loc_3F4A ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=3/8 nt/t +3F53: AC F8 BTST.W #8, R4 ; cycles=3 +3F55: 26 16 BNE loc_3F6D ; cycles=3/8 nt/t +3F57: AC F9 BTST.W #9, R4 ; cycles=3 +3F59: 26 07 BNE loc_3F62 ; cycles=3/8 nt/t +3F5B: 15 F2 00 00 94 MOVTPE.B R4, @H'F200 ; LCD command/address write to E-clock H'F200; refs mem_F200 in program_or_external; cycles=13 +3F60: 20 10 BRA loc_3F72 ; cycles=7 + +loc_3F62: +3F62: 15 F2 01 00 94 MOVTPE.B R4, @H'F201 ; LCD data write to E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 +3F67: 1D FB 00 08 ADD:Q.W #1, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=8 +3F6B: 20 05 BRA loc_3F72 ; cycles=8 + +loc_3F6D: +3F6D: 15 F2 01 00 84 MOVFPE.B @H'F201, R4 ; LCD data read from E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 + +loc_3F72: +3F72: CF 88 LDC.W @R7+, SR ; cycles=7 +3F74: 19 RTS ; cycles=12 + +loc_3F76: +3F76: 58 27 10 MOV:I.W #H'2710, R0 ; dataflow R0=H'2710; cycles=3 +3F79: 59 C3 50 MOV:I.W #H'C350, R1 ; dataflow R1=H'C350; cycles=3 + +loc_3F7C: +3F7C: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=9 +3F80: 01 B8 F9 SCB/F R0, loc_3F7C ; cycles=3/4/8 false/-1/t + +loc_3F83: +3F83: 15 FE 82 C7 BSET.B #7, @P1DR ; set bit 7 of P1DR; cycles=8 +3F87: 01 B9 F9 SCB/F R1, loc_3F83 ; cycles=3/4/9 false/-1/t +3F8A: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_3F8C: +3F8C: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=9 +3F90: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=9 +3F94: F8 F6 80 13 CLR.W @(-H'0980,R0) ; cycles=9 +3F98: A8 09 ADD:Q.W #2, R0 ; cycles=4 +3F9A: 48 08 00 CMP:I #H'0800, R0 ; cycles=3 +3F9D: 26 ED BNE loc_3F8C ; cycles=3/8 nt/t +3F9F: 1E 03 6A BSR loc_430C ; cycles=14 +3FA2: 1E 03 7F BSR loc_4324 ; cycles=13 +3FA5: 1E 00 EE BSR loc_4096 ; cycles=14 +3FA8: 1E 01 10 BSR loc_40BB ; cycles=13 +3FAB: 1E 02 69 BSR loc_4217 ; cycles=14 +3FAE: 1E 03 9B BSR loc_434C ; cycles=13 + +loc_3FB1: +3FB1: 1D FE EC 07 5A 00 MOV:G.W #H'5A00, @WDT_TCSR_R ; WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00); cycles=9 +3FB7: 15 F7 94 13 CLR.B @H'F794 ; refs ram_F794 in on_chip_ram; cycles=8 +3FBB: 0E 16 BSR loc_3FD3 ; cycles=14 +3FBD: 1E 7B EB BSR loc_BBAB ; cycles=14 +3FC0: 0E 2D BSR loc_3FEF ; cycles=13 +3FC2: 1E 00 81 BSR loc_4046 ; cycles=13 +3FC5: 1E 7E D6 BSR loc_BE9E ; cycles=14 +3FC8: 1E E8 3B BSR loc_2806 ; cycles=13 +3FCB: 1E F9 62 BSR loc_3930 ; cycles=14 +3FCE: 1E D6 0F BSR loc_15E0 ; cycles=13 +3FD1: 20 DE BRA loc_3FB1 ; cycles=8 + +loc_3FD3: +3FD3: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +3FD7: 26 15 BNE loc_3FEE ; cycles=3/8 nt/t +3FD9: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +3FDD: 27 06 BEQ loc_3FE5 ; cycles=3/8 nt/t +3FDF: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +3FE3: 26 09 BNE loc_3FEE ; cycles=3/8 nt/t + +loc_3FE5: +3FE5: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=6 +3FE9: 26 03 BNE loc_3FEE ; cycles=3/8 nt/t +3FEB: 1E 7B 04 BSR loc_BAF2 ; cycles=14 + +loc_3FEE: +3FEE: 19 RTS ; cycles=12 + +loc_3FEF: +3FEF: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +3FF3: 26 12 BNE loc_4007 ; cycles=3/8 nt/t +3FF5: 15 F9 B5 13 CLR.B @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +3FF9: 15 F9 B0 13 CLR.B @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=8 +3FFD: 15 FA A5 D7 BCLR.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 +4001: 27 08 BEQ loc_400B ; cycles=3/8 nt/t +4003: 0E 07 BSR loc_400C ; cycles=14 +4005: 20 04 BRA loc_400B ; cycles=8 + +loc_4007: +4007: 15 FA A5 C7 BSET.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 + +loc_400B: +400B: 19 RTS ; cycles=13 + +loc_400C: +400C: 15 F7 30 13 CLR.B @H'F730 ; refs ram_F730 in on_chip_ram; cycles=9 +4010: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=9 +4014: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=9 +4018: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=9 +401C: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=9 +4020: 1D F7 32 13 CLR.W @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +4024: 1D F7 5C 13 CLR.W @H'F75C ; refs ram_F75C in on_chip_ram; cycles=9 +4028: 15 FB 03 13 CLR.B @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +402C: 1D E0 46 13 CLR.W @H'E046 ; refs mem_E046 in program_or_external; cycles=9 +4030: 1D F7 6A 13 CLR.W @H'F76A ; refs ram_F76A in on_chip_ram; cycles=9 +4034: 15 F7 91 13 CLR.B @H'F791 ; refs ram_F791 in on_chip_ram; cycles=9 +4038: 15 F7 95 13 CLR.B @H'F795 ; refs ram_F795 in on_chip_ram; cycles=9 +403C: 15 F7 6E 13 CLR.B @H'F76E ; refs ram_F76E in on_chip_ram; cycles=9 +4040: 0E 33 BSR loc_4075 ; cycles=13 +4042: 1E 01 D2 BSR loc_4217 ; cycles=13 +4045: 19 RTS ; cycles=13 + +loc_4046: +4046: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=7 +404A: 26 0C BNE loc_4058 ; cycles=3/7 nt/t +404C: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +4050: 27 07 BEQ loc_4059 ; cycles=3/7 nt/t +4052: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +4056: 27 01 BEQ loc_4059 ; cycles=3/7 nt/t + +loc_4058: +4058: 19 RTS ; cycles=12 + +loc_4059: +4059: 15 F9 B0 82 MOV:G.B @H'F9B0, R2 ; refs ram_F9B0 in on_chip_ram; cycles=6 +405D: A2 12 EXTU.B R2 ; cycles=3 +405F: 15 F9 B5 72 CMP:G.B @H'F9B5, R2 ; refs ram_F9B5 in on_chip_ram; cycles=6 +4063: 26 0F BNE loc_4074 ; cycles=3/8 nt/t +4065: A2 1A SHLL.B R2 ; cycles=2 +4067: FA F8 70 06 00 MOV:G.W #H'00, @(-H'0790,R2) ; cycles=11 +406C: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +4070: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_4074: +4074: 19 RTS ; cycles=12 + +loc_4075: +4075: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_4077: +4077: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=8 +407B: F8 E4 00 13 CLR.W @(-H'1C00,R0) ; cycles=8 +407F: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=8 +4083: 48 02 00 CMP:I #H'0200, R0 ; cycles=3 +4086: 24 04 BCC loc_408C ; cycles=3/7 nt/t +4088: F8 EC 00 13 CLR.W @(-H'1400,R0) ; cycles=9 + +loc_408C: +408C: A8 09 ADD:Q.W #2, R0 ; cycles=4 +408E: 48 04 00 CMP:I #H'0400, R0 ; cycles=3 +4091: 26 E4 BNE loc_4077 ; cycles=3/8 nt/t +4093: 0E 01 BSR loc_4096 ; cycles=14 +4095: 19 RTS ; cycles=13 + +loc_4096: +4096: 1D E0 00 07 00 80 MOV:G.W #H'0080, @H'E000 ; refs mem_E000 in program_or_external; cycles=11 +409C: 1D E0 06 07 80 00 MOV:G.W #H'8000, @H'E006 ; refs mem_E006 in program_or_external; cycles=11 +40A2: 1D E0 80 07 FF FF MOV:G.W #H'FFFF, @H'E080 ; refs mem_E080 in program_or_external; cycles=11 +40A8: 1D E8 00 07 00 80 MOV:G.W #H'0080, @H'E800 ; refs mem_E800 in program_or_external; cycles=11 +40AE: 1D E8 06 07 80 00 MOV:G.W #H'8000, @H'E806 ; refs mem_E806 in program_or_external; cycles=11 +40B4: 1D E8 80 07 FF FF MOV:G.W #H'FFFF, @H'E880 ; refs mem_E880 in program_or_external; cycles=11 +40BA: 19 RTS ; cycles=12 + +loc_40BB: +40BB: 58 00 40 MOV:I.W #H'0040, R0 ; dataflow R0=H'0040; cycles=3 + +loc_40BE: +40BE: F8 F8 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0792,R0) ; cycles=9 +40C4: F8 F8 AE 07 FF FF MOV:G.W #H'FFFF, @(-H'0752,R0) ; cycles=9 +40CA: F8 F8 EE 07 FF FF MOV:G.W #H'FFFF, @(-H'0712,R0) ; cycles=9 +40D0: F8 F9 2E 07 FF FF MOV:G.W #H'FFFF, @(-H'06D2,R0) ; cycles=9 +40D6: F8 F9 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0692,R0) ; cycles=9 +40DC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +40DE: 26 DE BNE loc_40BE ; cycles=3/7 nt/t +40E0: 15 F9 C4 06 14 MOV:G.B #H'14, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +40E5: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +40EA: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +40EF: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +40F4: 15 FE 8E F7 BTST.B #7, @P7DR ; refs P7DR in register_field; cycles=7 +40F8: 27 09 BEQ loc_4103 ; cycles=3/7 nt/t +40FA: 1D F4 02 05 6B 6F CMP:G.W #H'6B6F, @H'F402 ; refs mem_F402 in program_or_external; cycles=7 +4100: 37 00 AD BEQ loc_41B0 ; cycles=3/7 nt/t + +loc_4103: +4103: 58 01 00 MOV:I.W #H'0100, R0 ; dataflow R0=H'0100; cycles=3 + +loc_4106: +4106: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +4108: F8 C9 64 85 MOV:G.W @(-H'369C,R0), R5 ; cycles=7 +410C: F8 F4 00 95 MOV:G.W R5, @(-H'0C00,R0) ; cycles=7 +4110: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +4112: A8 84 MOV:G.W R0, R4 ; cycles=3 +4114: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4117: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +411B: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +411E: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4122: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4125: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4129: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +412C: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4130: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4133: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4137: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +413A: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +413E: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4141: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4145: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4148: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +414C: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +414F: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4153: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4156: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +415A: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +415D: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4161: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4164: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4168: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +416B: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +416F: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4172: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4176: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4179: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +417D: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4180: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +4182: 26 82 BNE loc_4106 ; cycles=3/7 nt/t +4184: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_4187: +4187: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +4189: A8 84 MOV:G.W R0, R4 ; cycles=3 +418B: A4 10 SWAP.B R4 ; cycles=3 +418D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4190: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4193: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4195: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4198: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +419B: AC 09 ADD:Q.W #2, R4 ; cycles=4 +419D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A0: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41A3: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41A5: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A8: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41AB: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +41AD: 01 B8 D7 SCB/F R0, loc_4187 ; cycles=3/4/9 false/-1/t + +loc_41B0: +41B0: 20 20 BRA loc_41D2 ; cycles=7 + +loc_41D2: +41D2: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_41D5: +41D5: A8 81 MOV:G.W R0, R1 ; cycles=3 +41D7: A1 1A SHLL.B R1 ; cycles=2 +41D9: A1 1A SHLL.B R1 ; cycles=2 +41DB: A1 1A SHLL.B R1 ; cycles=2 +41DD: A8 84 MOV:G.W R0, R4 ; cycles=3 +41DF: A4 10 SWAP.B R4 ; cycles=3 +41E1: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41E3: 18 BF FE JSR @loc_BFFE ; cycles=14 +41E6: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41E8: F9 F7 B0 95 MOV:G.W R5, @(-H'0850,R1) ; cycles=7 +41EC: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41EE: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41F0: 18 BF FE JSR @loc_BFFE ; cycles=13 +41F3: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41F5: F9 F7 B2 95 MOV:G.W R5, @(-H'084E,R1) ; cycles=6 +41F9: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41FB: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41FD: 18 BF FE JSR @loc_BFFE ; cycles=14 +4200: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +4202: F9 F7 B4 95 MOV:G.W R5, @(-H'084C,R1) ; cycles=7 +4206: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4208: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +420A: 18 BF FE JSR @loc_BFFE ; cycles=13 +420D: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +420F: F9 F7 B6 95 MOV:G.W R5, @(-H'084A,R1) ; cycles=6 +4213: 01 B8 BF SCB/F R0, loc_41D5 ; cycles=3/4/9 false/-1/t +4216: 19 RTS ; cycles=12 + +loc_4217: +4217: 15 F7 98 13 CLR.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +421B: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +421F: 15 FE 82 D2 BCLR.B #2, @P1DR ; clear bit 2 of P1DR; cycles=8 +4223: 1D F7 00 07 24 24 MOV:G.W #H'2424, @H'F700 ; refs ram_F700 in on_chip_ram; cycles=9 +4229: 1D F7 02 07 24 24 MOV:G.W #H'2424, @H'F702 ; refs ram_F702 in on_chip_ram; cycles=9 +422F: 1D F7 04 07 24 24 MOV:G.W #H'2424, @H'F704 ; refs ram_F704 in on_chip_ram; cycles=9 +4235: 1D F7 06 07 24 24 MOV:G.W #H'2424, @H'F706 ; refs ram_F706 in on_chip_ram; cycles=9 +423B: 15 F7 08 06 7F MOV:G.B #H'7F, @H'F708 ; refs ram_F708 in on_chip_ram; cycles=9 +4240: 15 F7 09 06 24 MOV:G.B #H'24, @H'F709 ; refs ram_F709 in on_chip_ram; cycles=9 +4245: 1D F7 0A 07 24 24 MOV:G.W #H'2424, @H'F70A ; refs ram_F70A in on_chip_ram; cycles=9 +424B: 15 F7 10 13 CLR.B @H'F710 ; refs ram_F710 in on_chip_ram; cycles=8 +424F: 15 F7 11 13 CLR.B @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +4253: 15 F7 12 13 CLR.B @H'F712 ; refs ram_F712 in on_chip_ram; cycles=8 +4257: 15 F7 13 13 CLR.B @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +425B: 15 F7 14 13 CLR.B @H'F714 ; refs ram_F714 in on_chip_ram; cycles=8 +425F: 15 F7 15 13 CLR.B @H'F715 ; refs ram_F715 in on_chip_ram; cycles=8 +4263: 15 F7 16 13 CLR.B @H'F716 ; refs ram_F716 in on_chip_ram; cycles=8 +4267: 15 F7 17 13 CLR.B @H'F717 ; refs ram_F717 in on_chip_ram; cycles=8 +426B: 15 F7 18 06 FF MOV:G.B #H'FF, @H'F718 ; refs ram_F718 in on_chip_ram; cycles=9 +4270: 15 F7 19 06 FF MOV:G.B #H'FF, @H'F719 ; refs ram_F719 in on_chip_ram; cycles=9 +4275: 15 F7 1A 06 FF MOV:G.B #H'FF, @H'F71A ; refs ram_F71A in on_chip_ram; cycles=9 +427A: 15 F7 1B 06 FF MOV:G.B #H'FF, @H'F71B ; refs ram_F71B in on_chip_ram; cycles=9 +427F: 15 F7 1C 06 FF MOV:G.B #H'FF, @H'F71C ; refs ram_F71C in on_chip_ram; cycles=9 +4284: 15 F7 1D 06 FF MOV:G.B #H'FF, @H'F71D ; refs ram_F71D in on_chip_ram; cycles=9 +4289: 15 F7 1E 06 FF MOV:G.B #H'FF, @H'F71E ; refs ram_F71E in on_chip_ram; cycles=9 +428E: 15 F7 1F 06 FF MOV:G.B #H'FF, @H'F71F ; refs ram_F71F in on_chip_ram; cycles=9 +4293: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +4299: 1D FA F2 07 4F 4E MOV:G.W #H'4F4E, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +429F: 1D FA F4 07 4E 45 MOV:G.W #H'4E45, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42A5: 1D FA F6 07 43 54 MOV:G.W #H'4354, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42AB: 1D FA F8 07 3A 4E MOV:G.W #H'3A4E, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42B1: 1D FA FA 07 4F 54 MOV:G.W #H'4F54, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42B7: 1D FA FC 07 20 41 MOV:G.W #H'2041, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42BD: 1D FA FE 07 43 54 MOV:G.W #H'4354, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42C3: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +42C6: 1E FC 03 BSR loc_3ECC ; cycles=13 +42C9: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +42CF: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +42D5: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42DB: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42E1: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42E7: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42ED: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42F3: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42F9: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +42FC: 1E FB CD BSR loc_3ECC ; cycles=13 +42FF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +4302: 1E FB C7 BSR loc_3ECC ; cycles=13 +4305: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +4308: 1E FB C1 BSR loc_3ECC ; cycles=13 +430B: 19 RTS ; cycles=13 + +loc_430C: +430C: 15 FE 8B D0 BCLR.B #0, @P6DR ; clear bit 0 of P6DR; cycles=9 +4310: 15 F5 55 06 AA MOV:G.B #H'AA, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +4315: 15 F4 AA 06 55 MOV:G.B #H'55, @H'F4AA ; refs mem_F4AA in program_or_external; cycles=9 +431A: 15 F5 55 06 CC MOV:G.B #H'CC, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +431F: 15 FE 8B C0 BSET.B #0, @P6DR ; set bit 0 of P6DR; cycles=8 +4323: 19 RTS ; cycles=13 + +loc_4324: +4324: 5C 00 38 MOV:I.W #H'0038, R4 ; dataflow R4=H'0038; cycles=3 +4327: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +432A: 1E FB 9F BSR loc_3ECC ; cycles=13 +432D: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 +4330: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4333: 1E FB 96 BSR loc_3ECC ; cycles=14 +4336: 5C 00 0E MOV:I.W #H'000E, R4 ; dataflow R4=H'000E; cycles=3 +4339: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +433C: 1E FB 8D BSR loc_3ECC ; cycles=13 +433F: 5C 00 06 MOV:I.W #H'0006, R4 ; dataflow R4=H'0006; cycles=3 +4342: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4345: 1E FB 84 BSR loc_3ECC ; cycles=14 +4348: 1E CD 83 BSR loc_10CE ; cycles=13 +434B: 19 RTS ; cycles=13 + +loc_434C: +434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9 +4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9 +4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9 +435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9 +4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9 +4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40 (A/D priority=4); cycles=9 +436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR; enable SCI1 receive and receive-error interrupts (RIE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR; cycles=9 +4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR; cycles=9 +4376: 15 FE E8 C6 BSET.B #6, @ADCSR ; set ADIE (bit 6) of ADCSR; cycles=9 +437A: 15 FE FD C4 BSET.B #4, @SYSCR2 ; set IRQ3E (bit 4) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +437E: 15 FE FD C5 BSET.B #5, @SYSCR2 ; set IRQ4E (bit 5) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +4382: 15 FE 8E F6 BTST.B #6, @P7DR ; refs P7DR in register_field; cycles=7 +4386: 27 06 BEQ loc_438E ; cycles=3/7 nt/t +4388: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 + +loc_438E: +438E: 0C 03 00 88 LDC.W #H'0300, SR ; dataflow SR=H'0300; cycles=6 +4392: 19 RTS ; cycles=12 + +vec_nmi_4393: +4393: 0A RTE ; cycles=14 + +loc_4394: +4394: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +4399: 32 00 86 BHI loc_4422 ; cycles=3/8 nt/t +439C: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +43A0: 36 00 7F BNE loc_4422 ; cycles=3/7 nt/t +43A3: 1D F7 36 83 MOV:G.W @H'F736, R3 ; refs ram_F736 in on_chip_ram; cycles=6 +43A7: 37 00 78 BEQ loc_4422 ; cycles=3/8 nt/t +43AA: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +43AE: 1D F6 BE 34 SUB.W @H'F6BE, R4 ; refs ram_F6BE in on_chip_ram; cycles=7 +43B2: AB DF BCLR.W #15, R3 ; cycles=3 +43B4: 26 19 BNE loc_43CF ; cycles=3/7 nt/t +43B6: AB DE BCLR.W #14, R3 ; cycles=3 +43B8: 26 21 BNE loc_43DB ; cycles=3/7 nt/t +43BA: AB DD BCLR.W #13, R3 ; cycles=3 +43BC: 26 29 BNE loc_43E7 ; cycles=3/7 nt/t +43BE: AB DC BCLR.W #12, R3 ; cycles=3 +43C0: 26 31 BNE loc_43F3 ; cycles=3/7 nt/t +43C2: AB DB BCLR.W #11, R3 ; cycles=3 +43C4: 26 39 BNE loc_43FF ; cycles=3/7 nt/t +43C6: AB DA BCLR.W #10, R3 ; cycles=3 +43C8: 26 43 BNE loc_440D ; cycles=3/7 nt/t +43CA: 1E D5 D5 BSR loc_19A2 ; cycles=13 +43CD: 20 53 BRA loc_4422 ; cycles=8 + +loc_43CF: +43CF: 0E 5E BSR loc_442F ; cycles=14 +43D1: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43D4: 27 03 BEQ loc_43D9 ; cycles=3/7 nt/t +43D6: 1E D6 5C BSR loc_1A35 ; cycles=13 + +loc_43D9: +43D9: 20 47 BRA loc_4422 ; cycles=8 + +loc_43DB: +43DB: 0E 52 BSR loc_442F ; cycles=14 +43DD: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43E0: 27 03 BEQ loc_43E5 ; cycles=3/7 nt/t +43E2: 1E D6 B7 BSR loc_1A9C ; cycles=13 + +loc_43E5: +43E5: 20 3B BRA loc_4422 ; cycles=8 + +loc_43E7: +43E7: 0E 46 BSR loc_442F ; cycles=14 +43E9: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43EC: 27 03 BEQ loc_43F1 ; cycles=3/7 nt/t +43EE: 1E D6 F3 BSR loc_1AE4 ; cycles=13 + +loc_43F1: +43F1: 20 2F BRA loc_4422 ; cycles=8 + +loc_43F3: +43F3: 0E 3A BSR loc_442F ; cycles=14 +43F5: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43F8: 27 03 BEQ loc_43FD ; cycles=3/7 nt/t +43FA: 1E D7 0E BSR loc_1B0B ; cycles=13 + +loc_43FD: +43FD: 20 23 BRA loc_4422 ; cycles=8 + +loc_43FF: +43FF: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4404: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +4408: 1E 04 EF BSR loc_48FA ; cycles=13 +440B: 20 15 BRA loc_4422 ; cycles=8 + +loc_440D: +440D: 0E 20 BSR loc_442F ; cycles=14 +440F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4412: 27 0C BEQ loc_4420 ; cycles=3/7 nt/t +4414: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4419: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +441D: 1E 04 DA BSR loc_48FA ; cycles=14 + +loc_4420: +4420: 20 00 BRA loc_4422 ; cycles=7 + +loc_4422: +4422: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +4426: 1D F6 BE 94 MOV:G.W R4, @H'F6BE ; refs ram_F6BE in on_chip_ram; cycles=7 +442A: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +442E: 19 RTS ; cycles=12 + +loc_442F: +442F: 15 F6 F7 24 ADD:G.B @H'F6F7, R4 ; refs ram_F6F7 in on_chip_ram; cycles=6 +4433: 44 88 CMP:E #H'88, R4 ; cycles=2 +4435: 24 0D BCC loc_4444 ; cycles=3/8 nt/t +4437: 44 78 CMP:E #H'78, R4 ; cycles=2 +4439: 23 13 BLS loc_444E ; cycles=3/8 nt/t +443B: 15 F6 F7 94 MOV:G.B R4, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=6 +443F: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4442: 20 12 BRA loc_4456 ; cycles=7 + +loc_4444: +4444: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4449: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +444C: 20 08 BRA loc_4456 ; cycles=7 + +loc_444E: +444E: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4453: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4456: +4456: 19 RTS ; cycles=12 + +loc_4457: +4457: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +445C: 32 00 86 BHI loc_44E5 ; cycles=3/7 nt/t +445F: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=6 +4463: 36 00 7F BNE loc_44E5 ; cycles=3/8 nt/t +4466: 1D F7 38 83 MOV:G.W @H'F738, R3 ; refs ram_F738 in on_chip_ram; cycles=7 +446A: 37 00 78 BEQ loc_44E5 ; cycles=3/7 nt/t +446D: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +4471: 1D F6 BC 34 SUB.W @H'F6BC, R4 ; refs ram_F6BC in on_chip_ram; cycles=6 +4475: AB DF BCLR.W #15, R3 ; cycles=3 +4477: 26 19 BNE loc_4492 ; cycles=3/8 nt/t +4479: AB DE BCLR.W #14, R3 ; cycles=3 +447B: 26 21 BNE loc_449E ; cycles=3/8 nt/t +447D: AB DD BCLR.W #13, R3 ; cycles=3 +447F: 26 29 BNE loc_44AA ; cycles=3/8 nt/t +4481: AB DC BCLR.W #12, R3 ; cycles=3 +4483: 26 31 BNE loc_44B6 ; cycles=3/8 nt/t +4485: AB DB BCLR.W #11, R3 ; cycles=3 +4487: 26 39 BNE loc_44C2 ; cycles=3/8 nt/t +4489: AB DA BCLR.W #10, R3 ; cycles=3 +448B: 26 43 BNE loc_44D0 ; cycles=3/8 nt/t +448D: 1E D5 12 BSR loc_19A2 ; cycles=14 +4490: 20 53 BRA loc_44E5 ; cycles=7 + +loc_4492: +4492: 0E 5E BSR loc_44F2 ; cycles=13 +4494: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4497: 27 03 BEQ loc_449C ; cycles=3/8 nt/t +4499: 1E D5 99 BSR loc_1A35 ; cycles=14 + +loc_449C: +449C: 20 47 BRA loc_44E5 ; cycles=7 + +loc_449E: +449E: 0E 52 BSR loc_44F2 ; cycles=13 +44A0: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44A3: 27 03 BEQ loc_44A8 ; cycles=3/8 nt/t +44A5: 1E D5 F4 BSR loc_1A9C ; cycles=14 + +loc_44A8: +44A8: 20 3B BRA loc_44E5 ; cycles=7 + +loc_44AA: +44AA: 0E 46 BSR loc_44F2 ; cycles=13 +44AC: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44AF: 27 03 BEQ loc_44B4 ; cycles=3/8 nt/t +44B1: 1E D6 30 BSR loc_1AE4 ; cycles=14 + +loc_44B4: +44B4: 20 2F BRA loc_44E5 ; cycles=7 + +loc_44B6: +44B6: 0E 3A BSR loc_44F2 ; cycles=13 +44B8: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44BB: 27 03 BEQ loc_44C0 ; cycles=3/8 nt/t +44BD: 1E D6 4B BSR loc_1B0B ; cycles=14 + +loc_44C0: +44C0: 20 23 BRA loc_44E5 ; cycles=7 + +loc_44C2: +44C2: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44C7: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +44CB: 1E 04 2C BSR loc_48FA ; cycles=14 +44CE: 20 15 BRA loc_44E5 ; cycles=7 + +loc_44D0: +44D0: 0E 20 BSR loc_44F2 ; cycles=13 +44D2: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44D5: 27 0C BEQ loc_44E3 ; cycles=3/8 nt/t +44D7: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44DC: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +44E0: 1E 04 17 BSR loc_48FA ; cycles=13 + +loc_44E3: +44E3: 20 00 BRA loc_44E5 ; cycles=8 + +loc_44E5: +44E5: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +44E9: 1D F6 BC 94 MOV:G.W R4, @H'F6BC ; refs ram_F6BC in on_chip_ram; cycles=6 +44ED: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=8 +44F1: 19 RTS ; cycles=13 + +loc_44F2: +44F2: 15 F6 F8 24 ADD:G.B @H'F6F8, R4 ; refs ram_F6F8 in on_chip_ram; cycles=7 +44F6: 44 88 CMP:E #H'88, R4 ; cycles=2 +44F8: 24 0D BCC loc_4507 ; cycles=3/7 nt/t +44FA: 44 78 CMP:E #H'78, R4 ; cycles=2 +44FC: 23 13 BLS loc_4511 ; cycles=3/7 nt/t +44FE: 15 F6 F8 94 MOV:G.B R4, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=7 +4502: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4505: 20 12 BRA loc_4519 ; cycles=8 + +loc_4507: +4507: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +450C: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +450F: 20 08 BRA loc_4519 ; cycles=8 + +loc_4511: +4511: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +4516: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4519: +4519: 19 RTS ; cycles=13 + +loc_451A: +451A: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +451F: 32 00 86 BHI loc_45A8 ; cycles=3/8 nt/t +4522: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +4526: 36 00 7F BNE loc_45A8 ; cycles=3/7 nt/t +4529: 1D F7 3A 83 MOV:G.W @H'F73A, R3 ; refs ram_F73A in on_chip_ram; cycles=6 +452D: 37 00 78 BEQ loc_45A8 ; cycles=3/8 nt/t +4530: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +4534: 1D F6 BA 34 SUB.W @H'F6BA, R4 ; refs ram_F6BA in on_chip_ram; cycles=7 +4538: AB DF BCLR.W #15, R3 ; cycles=3 +453A: 26 19 BNE loc_4555 ; cycles=3/7 nt/t +453C: AB DE BCLR.W #14, R3 ; cycles=3 +453E: 26 21 BNE loc_4561 ; cycles=3/7 nt/t +4540: AB DD BCLR.W #13, R3 ; cycles=3 +4542: 26 29 BNE loc_456D ; cycles=3/7 nt/t +4544: AB DC BCLR.W #12, R3 ; cycles=3 +4546: 26 31 BNE loc_4579 ; cycles=3/7 nt/t +4548: AB DB BCLR.W #11, R3 ; cycles=3 +454A: 26 39 BNE loc_4585 ; cycles=3/7 nt/t +454C: AB DA BCLR.W #10, R3 ; cycles=3 +454E: 26 43 BNE loc_4593 ; cycles=3/7 nt/t +4550: 1E D4 4F BSR loc_19A2 ; cycles=13 +4553: 20 53 BRA loc_45A8 ; cycles=8 + +loc_4555: +4555: 0E 5E BSR loc_45B5 ; cycles=14 +4557: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +455A: 27 03 BEQ loc_455F ; cycles=3/7 nt/t +455C: 1E D4 D6 BSR loc_1A35 ; cycles=13 + +loc_455F: +455F: 20 47 BRA loc_45A8 ; cycles=8 + +loc_4561: +4561: 0E 52 BSR loc_45B5 ; cycles=14 +4563: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4566: 27 03 BEQ loc_456B ; cycles=3/7 nt/t +4568: 1E D5 31 BSR loc_1A9C ; cycles=13 + +loc_456B: +456B: 20 3B BRA loc_45A8 ; cycles=8 + +loc_456D: +456D: 0E 46 BSR loc_45B5 ; cycles=14 +456F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4572: 27 03 BEQ loc_4577 ; cycles=3/7 nt/t +4574: 1E D5 6D BSR loc_1AE4 ; cycles=13 + +loc_4577: +4577: 20 2F BRA loc_45A8 ; cycles=8 + +loc_4579: +4579: 0E 3A BSR loc_45B5 ; cycles=14 +457B: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +457E: 27 03 BEQ loc_4583 ; cycles=3/7 nt/t +4580: 1E D5 88 BSR loc_1B0B ; cycles=13 + +loc_4583: +4583: 20 23 BRA loc_45A8 ; cycles=8 + +loc_4585: +4585: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +458A: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +458E: 1E 03 69 BSR loc_48FA ; cycles=13 +4591: 20 15 BRA loc_45A8 ; cycles=8 + +loc_4593: +4593: 0E 20 BSR loc_45B5 ; cycles=14 +4595: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4598: 27 0C BEQ loc_45A6 ; cycles=3/7 nt/t +459A: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +459F: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +45A3: 1E 03 54 BSR loc_48FA ; cycles=14 + +loc_45A6: +45A6: 20 00 BRA loc_45A8 ; cycles=7 + +loc_45A8: +45A8: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +45AC: 1D F6 BA 94 MOV:G.W R4, @H'F6BA ; refs ram_F6BA in on_chip_ram; cycles=7 +45B0: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +45B4: 19 RTS ; cycles=12 + +loc_45B5: +45B5: 15 F6 F9 24 ADD:G.B @H'F6F9, R4 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45B9: 44 88 CMP:E #H'88, R4 ; cycles=2 +45BB: 24 0D BCC loc_45CA ; cycles=3/8 nt/t +45BD: 44 78 CMP:E #H'78, R4 ; cycles=2 +45BF: 23 13 BLS loc_45D4 ; cycles=3/8 nt/t +45C1: 15 F6 F9 94 MOV:G.B R4, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45C5: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +45C8: 20 12 BRA loc_45DC ; cycles=7 + +loc_45CA: +45CA: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45CF: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +45D2: 20 08 BRA loc_45DC ; cycles=7 + +loc_45D4: +45D4: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45D9: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_45DC: +45DC: 19 RTS ; cycles=12 + +loc_48EF: +48EF: 1D F7 34 80 MOV:G.W @H'F734, R0 ; refs ram_F734 in on_chip_ram; cycles=6 +48F3: 1D F7 32 90 MOV:G.W R0, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +48F7: 0E 01 BSR loc_48FA ; cycles=14 +48F9: 19 RTS ; cycles=13 + +loc_48FA: +48FA: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +48FE: 26 29 BNE loc_4929 ; cycles=3/7 nt/t +4900: 15 F7 32 04 1A CMP:G.B #H'1A, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=7 +4905: 27 22 BEQ loc_4929 ; cycles=3/8 nt/t +4907: 1D F7 32 05 19 00 CMP:G.W #H'1900, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +490D: 27 1A BEQ loc_4929 ; cycles=3/8 nt/t +490F: 1D E1 EC FD BTST.W #13, @H'E1EC ; refs mem_E1EC in program_or_external; cycles=6 +4913: 27 14 BEQ loc_4929 ; cycles=3/8 nt/t +4915: 1D E1 EC 80 MOV:G.W @H'E1EC, R0 ; refs mem_E1EC in program_or_external; cycles=6 +4919: 0C 9F FF 50 AND.W #H'9FFF, R0 ; cycles=4 +491D: 1D E9 EC 90 MOV:G.W R0, @H'E9EC ; refs mem_E9EC in program_or_external; cycles=6 +4921: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +4923: 5B 00 F6 MOV:I.W #H'00F6, R3 ; dataflow R3=H'00F6; cycles=3 +4926: 1E F5 2B BSR loc_3E54 ; cycles=13 + +loc_4929: +4929: 15 F7 6E F6 BTST.B #6, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +492D: 26 0E BNE loc_493D ; cycles=3/8 nt/t +492F: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +4933: A0 12 EXTU.B R0 ; cycles=3 +4935: A0 1A SHLL.B R0 ; cycles=2 +4937: F8 49 3E 80 MOV:G.W @(H'493E,R0), R0 ; cycles=6 +493B: 11 D8 JSR @R0 ; JSR @R0 uses R0 loaded from pointer table H'493E via R0 (8/52 decoded targets); cycles=14 + +loc_493D: +493D: 19 RTS ; cycles=13 + +loc_5500: +5500: 15 F7 95 F7 BTST.B #7, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +5504: 36 00 A6 BNE loc_55AD ; cycles=3/7 nt/t +5507: 15 F7 6E 82 MOV:G.B @H'F76E, R2 ; refs ram_F76E in on_chip_ram; cycles=6 +550B: 0C 00 0F 52 AND.W #H'000F, R2 ; cycles=4 +550F: AA 83 MOV:G.W R2, R3 ; cycles=3 +5511: A3 1A SHLL.B R3 ; cycles=2 +5513: A3 1A SHLL.B R3 ; cycles=2 +5515: A3 1A SHLL.B R3 ; cycles=2 +5517: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5519: 15 F7 5E 84 MOV:G.B @H'F75E, R4 ; refs ram_F75E in on_chip_ram; cycles=6 +551D: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5521: A5 10 SWAP.B R5 ; cycles=3 +5523: 15 F7 5F 84 MOV:G.B @H'F75F, R4 ; refs ram_F75F in on_chip_ram; cycles=6 +5527: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +552B: FB F7 B0 95 MOV:G.W R5, @(-H'0850,R3) ; cycles=6 +552F: AA 84 MOV:G.W R2, R4 ; cycles=3 +5531: A4 10 SWAP.B R4 ; cycles=3 +5533: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5535: 1E 6A A8 BSR loc_BFE0 ; cycles=14 +5538: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +553A: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +553C: 15 F7 60 84 MOV:G.B @H'F760, R4 ; refs ram_F760 in on_chip_ram; cycles=7 +5540: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5544: A5 10 SWAP.B R5 ; cycles=3 +5546: 15 F7 61 84 MOV:G.B @H'F761, R4 ; refs ram_F761 in on_chip_ram; cycles=7 +554A: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +554E: FB F7 B2 95 MOV:G.W R5, @(-H'084E,R3) ; cycles=7 +5552: AA 84 MOV:G.W R2, R4 ; cycles=3 +5554: A4 10 SWAP.B R4 ; cycles=3 +5556: AC 09 ADD:Q.W #2, R4 ; cycles=4 +5558: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +555A: 1E 6A 83 BSR loc_BFE0 ; cycles=13 +555D: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +555F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5561: 15 F7 62 84 MOV:G.B @H'F762, R4 ; refs ram_F762 in on_chip_ram; cycles=6 +5565: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5569: A5 10 SWAP.B R5 ; cycles=3 +556B: 15 F7 63 84 MOV:G.B @H'F763, R4 ; refs ram_F763 in on_chip_ram; cycles=6 +556F: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5573: FB F7 B4 95 MOV:G.W R5, @(-H'084C,R3) ; cycles=6 +5577: AA 84 MOV:G.W R2, R4 ; cycles=3 +5579: A4 10 SWAP.B R4 ; cycles=3 +557B: 0C 00 04 24 ADD:G.W #H'0004, R4 ; cycles=4 +557F: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5581: 1E 6A 5C BSR loc_BFE0 ; cycles=14 +5584: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +5586: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5588: 15 F7 64 84 MOV:G.B @H'F764, R4 ; refs ram_F764 in on_chip_ram; cycles=7 +558C: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5590: A5 10 SWAP.B R5 ; cycles=3 +5592: 15 F7 65 84 MOV:G.B @H'F765, R4 ; refs ram_F765 in on_chip_ram; cycles=7 +5596: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +559A: FB F7 B6 95 MOV:G.W R5, @(-H'084A,R3) ; cycles=7 +559E: AA 84 MOV:G.W R2, R4 ; cycles=3 +55A0: A4 10 SWAP.B R4 ; cycles=3 +55A2: 0C 00 06 24 ADD:G.W #H'0006, R4 ; cycles=4 +55A6: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +55A8: 1E 6A 35 BSR loc_BFE0 ; cycles=13 +55AB: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 + +loc_55AD: +55AD: AD 13 CLR.W R5 ; dataflow R5=H'0000; cycles=3 + +loc_55AF: +55AF: FD C5 64 84 MOV:G.W @(-H'3A9C,R5), R4 ; cycles=6 +55B3: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=6 +55B7: 27 06 BEQ loc_55BF ; cycles=3/8 nt/t +55B9: AC FE BTST.W #14, R4 ; cycles=3 +55BB: 27 13 BEQ loc_55D0 ; cycles=3/8 nt/t +55BD: 20 04 BRA loc_55C3 ; cycles=8 + +loc_55BF: +55BF: AC FD BTST.W #13, R4 ; cycles=3 +55C1: 27 0D BEQ loc_55D0 ; cycles=3/8 nt/t + +loc_55C3: +55C3: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55C5: AD 83 MOV:G.W R5, R3 ; cycles=3 +55C7: AB 1B SHLR.W R3 ; cycles=3 +55C9: 0C 02 00 43 OR.W #H'0200, R3 ; cycles=4 +55CD: 1E E8 84 BSR loc_3E54 ; cycles=14 + +loc_55D0: +55D0: AD 09 ADD:Q.W #2, R5 ; cycles=4 +55D2: 4D 04 00 CMP:I #H'0400, R5 ; cycles=3 +55D5: 25 D8 BCS loc_55AF ; cycles=3/8 nt/t +55D7: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55D9: 5B 00 6C MOV:I.W #H'006C, R3 ; dataflow R3=H'006C; cycles=3 +55DC: 1E E8 75 BSR loc_3E54 ; cycles=13 +55DF: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=8 +55E3: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=8 +55E7: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=8 +55EB: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=8 +55EF: 19 RTS ; cycles=13 + +loc_5A7A: +5A7A: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=7 +5A7E: 26 10 BNE loc_5A90 ; cycles=3/7 nt/t +5A80: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A84: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A88: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A8C: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 + +loc_5A90: +5A90: 19 RTS ; cycles=12 + +loc_5A91: +5A91: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5A94: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5A98: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5A9B: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5A9F: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5AA2: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5AA6: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5AA9: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5AAD: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5AB0: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5AB4: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5AB7: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5ABB: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5ABE: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5AC2: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5AC5: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5AC9: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5ACC: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5AD0: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5AD3: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5AD7: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5ADA: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5ADE: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5AE1: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5AE5: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5AE8: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5AEC: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5AEF: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5AF3: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5AF6: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5AFA: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5AFD: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5B01: 19 RTS ; cycles=13 + +loc_5B02: +5B02: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=7 +5B06: A0 12 EXTU.B R0 ; cycles=3 +5B08: 40 01 CMP:E #H'01, R0 ; cycles=2 +5B0A: 23 48 BLS loc_5B54 ; cycles=3/7 nt/t +5B0C: 40 09 CMP:E #H'09, R0 ; cycles=2 +5B0E: 22 1D BHI loc_5B2D ; cycles=3/7 nt/t +5B10: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=7 +5B14: 15 FA FF 90 MOV:G.B R0, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=7 +5B18: 15 FA FE 06 2F MOV:G.B #H'2F, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5B1D: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=6 +5B21: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B23: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=6 +5B27: 15 FA FD 90 MOV:G.B R0, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5B2B: 20 27 BRA loc_5B54 ; cycles=8 + +loc_5B2D: +5B2D: A0 1A SHLL.B R0 ; cycles=2 +5B2F: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=6 +5B33: 1D FA FE 90 MOV:G.W R0, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=6 +5B37: 15 FA FD 06 2F MOV:G.B #H'2F, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=9 +5B3C: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +5B40: A0 12 EXTU.B R0 ; cycles=3 +5B42: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B44: A0 1A SHLL.B R0 ; cycles=2 +5B46: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=7 +5B4A: 15 FA FC 90 MOV:G.B R0, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5B4E: A0 10 SWAP.B R0 ; cycles=3 +5B50: 15 FA FB 90 MOV:G.B R0, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=7 + +loc_5B54: +5B54: 19 RTS ; cycles=12 + +loc_5C91: +5C91: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +5C95: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5C99: 27 62 BEQ loc_5CFD ; cycles=3/8 nt/t +5C9B: A9 1A SHLL.W R1 ; cycles=3 +5C9D: 1D F7 4E 16 TST.W @H'F74E ; refs ram_F74E in on_chip_ram; cycles=6 +5CA1: 27 10 BEQ loc_5CB3 ; cycles=3/8 nt/t +5CA3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CA7: 1D F7 4E 52 AND.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAB: 1D F7 4E 72 CMP:G.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAF: 27 12 BEQ loc_5CC3 ; cycles=3/8 nt/t +5CB1: 20 4A BRA loc_5CFD ; cycles=8 + +loc_5CB3: +5CB3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CB7: 1D F7 46 52 AND.W @H'F746, R2 ; refs ram_F746 in on_chip_ram; cycles=6 +5CBB: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CBF: 27 3C BEQ loc_5CFD ; cycles=3/8 nt/t +5CC1: 20 00 BRA loc_5CC3 ; cycles=8 + +loc_5CC3: +5CC3: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5CC6: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5CCA: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5CCD: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5CD1: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5CD4: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5CD8: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5CDB: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5CDF: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5CE2: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5CE6: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5CE9: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5CED: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5CF0: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5CF4: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5CF7: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5CFB: 20 18 BRA loc_5D15 ; cycles=8 + +loc_5CFD: +5CFD: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +5D03: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5D09: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +5D0F: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 + +loc_5D15: +5D15: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +5D19: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5D1D: 27 62 BEQ loc_5D81 ; cycles=3/8 nt/t +5D1F: A9 1A SHLL.W R1 ; cycles=3 +5D21: 1D F7 52 16 TST.W @H'F752 ; refs ram_F752 in on_chip_ram; cycles=6 +5D25: 27 10 BEQ loc_5D37 ; cycles=3/8 nt/t +5D27: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D2B: 1D F7 52 52 AND.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D2F: 1D F7 52 72 CMP:G.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D33: 27 12 BEQ loc_5D47 ; cycles=3/8 nt/t +5D35: 20 4A BRA loc_5D81 ; cycles=8 + +loc_5D37: +5D37: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D3B: 1D F7 4A 52 AND.W @H'F74A, R2 ; refs ram_F74A in on_chip_ram; cycles=6 +5D3F: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D43: 27 3C BEQ loc_5D81 ; cycles=3/8 nt/t +5D45: 20 00 BRA loc_5D47 ; cycles=8 + +loc_5D47: +5D47: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5D4A: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5D4E: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5D51: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5D55: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5D58: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5D5C: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5D5F: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5D63: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5D66: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5D6A: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5D6D: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5D71: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5D74: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5D78: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5D7B: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5D7F: 20 18 BRA loc_5D99 ; cycles=8 + +loc_5D81: +5D81: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +5D87: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +5D8D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5D93: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 + +loc_5D99: +5D99: 19 RTS ; cycles=13 + +loc_5FD2: +5FD2: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=7 +5FD6: 15 F7 2F 70 CMP:G.B @H'F72F, R0 ; refs ram_F72F in on_chip_ram; cycles=7 +5FDA: 27 41 BEQ loc_601D ; cycles=3/7 nt/t +5FDC: 1D F7 2C 13 CLR.W @H'F72C ; refs ram_F72C in on_chip_ram; cycles=9 +5FE0: 15 F7 2E 13 CLR.B @H'F72E ; refs ram_F72E in on_chip_ram; cycles=9 +5FE4: 15 F7 2F 90 MOV:G.B R0, @H'F72F ; refs ram_F72F in on_chip_ram; cycles=7 +5FE8: A4 12 EXTU.B R4 ; cycles=3 + +loc_5FEA: +5FEA: AC 80 MOV:G.W R4, R0 ; cycles=3 +5FEC: A0 1A SHLL.B R0 ; cycles=2 +5FEE: AB 20 ADD:G.W R3, R0 ; cycles=3 +5FF0: D8 80 MOV:G.W @R0, R0 ; cycles=6 +5FF2: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +5FF4: D8 81 MOV:G.W @R0, R1 ; cycles=6 +5FF6: 15 F7 31 71 CMP:G.B @H'F731, R1 ; refs ram_F731 in on_chip_ram; cycles=7 +5FFA: 25 1E BCS loc_601A ; cycles=3/7 nt/t +5FFC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +5FFE: D8 16 TST.W @R0 ; cycles=6 +6000: 27 10 BEQ loc_6012 ; cycles=3/7 nt/t + +loc_6002: +6002: D8 81 MOV:G.W @R0, R1 ; cycles=6 +6004: 27 14 BEQ loc_601A ; cycles=3/7 nt/t +6006: A9 1A SHLL.W R1 ; cycles=3 +6008: F9 E4 00 16 TST.W @(-H'1C00,R1) ; cycles=7 +600C: 26 04 BNE loc_6012 ; cycles=3/7 nt/t +600E: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +6010: 20 F0 BRA loc_6002 ; cycles=7 + +loc_6012: +6012: 1D F7 2C 4C BSET.W R4, @H'F72C ; refs ram_F72C in on_chip_ram; cycles=9 +6016: 15 F7 2E 08 ADD:Q.B #1, @H'F72E ; refs ram_F72E in on_chip_ram; cycles=9 + +loc_601A: +601A: 01 BC CD SCB/F R4, loc_5FEA ; cycles=3/4/8 false/-1/t + +loc_601D: +601D: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=6 +6021: 27 1D BEQ loc_6040 ; cycles=3/8 nt/t +6023: 15 F7 33 04 FF CMP:G.B #H'FF, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=6 +6028: 27 08 BEQ loc_6032 ; cycles=3/7 nt/t +602A: 15 F7 33 70 CMP:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +602E: 23 0A BLS loc_603A ; cycles=3/7 nt/t +6030: 20 20 BRA loc_6052 ; cycles=7 + +loc_6032: +6032: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +6034: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +6038: 20 18 BRA loc_6052 ; cycles=7 + +loc_603A: +603A: 15 F7 33 13 CLR.B @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +603E: 20 12 BRA loc_6052 ; cycles=7 + +loc_6040: +6040: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +6044: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +6049: 15 F7 2F 13 CLR.B @H'F72F ; refs ram_F72F in on_chip_ram; cycles=8 +604D: 5C FF FE MOV:I.W #H'FFFE, R4 ; dataflow R4=H'FFFE; cycles=3 +6050: 20 18 BRA loc_606A ; cycles=7 + +loc_6052: +6052: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +6056: A0 12 EXTU.B R0 ; cycles=3 +6058: 1D F7 2C 81 MOV:G.W @H'F72C, R1 ; refs ram_F72C in on_chip_ram; cycles=7 +605C: 5C 00 FF MOV:I.W #H'00FF, R4 ; dataflow R4=H'00FF; cycles=3 + +loc_605F: +605F: A4 08 ADD:Q.B #1, R4 ; cycles=4 +6061: A9 1B SHLR.W R1 ; cycles=3 +6063: 24 FA BCC loc_605F ; cycles=3/8 nt/t +6065: 01 B8 F7 SCB/F R0, loc_605F ; cycles=3/4/9 false/-1/t +6068: A4 1A SHLL.B R4 ; cycles=2 + +loc_606A: +606A: 19 RTS ; cycles=12 + +loc_6173: +6173: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +6179: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +617F: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +6185: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +618B: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +6191: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +6197: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +619D: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +61A3: 19 RTS ; cycles=13 + +loc_6206: +6206: 0C 01 FF 55 AND.W #H'01FF, R5 ; cycles=4 +620A: 4D 00 7F CMP:I #H'007F, R5 ; cycles=3 +620D: 23 07 BLS loc_6216 ; cycles=3/8 nt/t +620F: 4D 01 7F CMP:I #H'017F, R5 ; cycles=3 +6212: 23 04 BLS loc_6218 ; cycles=3/7 nt/t +6214: 20 0C BRA loc_6222 ; cycles=7 + +loc_6216: +6216: 20 12 BRA loc_622A ; cycles=7 + +loc_6218: +6218: 0C 00 80 35 SUB.W #H'0080, R5 ; cycles=4 +621C: 0C 01 00 25 ADD:G.W #H'0100, R5 ; cycles=4 +6220: 20 08 BRA loc_622A ; cycles=7 + +loc_6222: +6222: 0C 01 80 35 SUB.W #H'0180, R5 ; cycles=4 +6226: 0C 02 00 25 ADD:G.W #H'0200, R5 ; cycles=4 + +loc_622A: +622A: 19 RTS ; cycles=12 + +loc_622B: +622B: AD 84 MOV:G.W R5, R4 ; cycles=3 +622D: A5 12 EXTU.B R5 ; cycles=3 +622F: A4 10 SWAP.B R4 ; cycles=3 +6231: 04 07 54 AND.B #H'07, R4 ; cycles=3 +6234: 44 00 CMP:E #H'00, R4 ; cycles=2 +6236: 27 0C BEQ loc_6244 ; cycles=3/7 nt/t +6238: 44 01 CMP:E #H'01, R4 ; cycles=2 +623A: 27 11 BEQ loc_624D ; cycles=3/7 nt/t +623C: 44 02 CMP:E #H'02, R4 ; cycles=2 +623E: 27 16 BEQ loc_6256 ; cycles=3/7 nt/t +6240: 44 03 CMP:E #H'03, R4 ; cycles=2 +6242: 27 1B BEQ loc_625F ; cycles=3/7 nt/t + +loc_6244: +6244: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6246: 22 17 BHI loc_625F ; cycles=3/7 nt/t +6248: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +624B: 20 17 BRA loc_6264 ; cycles=8 + +loc_624D: +624D: 45 FF CMP:E #H'FF, R5 ; cycles=2 +624F: 22 0E BHI loc_625F ; cycles=3/8 nt/t +6251: 5C 00 80 MOV:I.W #H'0080, R4 ; dataflow R4=H'0080; cycles=3 +6254: 20 0E BRA loc_6264 ; cycles=7 + +loc_6256: +6256: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6258: 22 05 BHI loc_625F ; cycles=3/7 nt/t +625A: 5C 01 80 MOV:I.W #H'0180, R4 ; dataflow R4=H'0180; cycles=3 +625D: 20 05 BRA loc_6264 ; cycles=8 + +loc_625F: +625F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +6261: 5D 01 FF MOV:I.W #H'01FF, R5 ; dataflow R5=H'01FF; cycles=3 + +loc_6264: +6264: AC 25 ADD:G.W R4, R5 ; cycles=3 +6266: 19 RTS ; cycles=12 +6F60: 27 02 BEQ loc_6F64 ; cycles=3/7 nt/t +6F62: AB CE BSET.W #14, R3 ; cycles=3 + +loc_6F64: +6F64: 1E CE ED BSR loc_3E54 ; cycles=13 +6F67: 15 F7 11 80 MOV:G.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=6 +6F6B: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +6F6E: 1D E1 1E FB BTST.W #11, @H'E11E ; refs mem_E11E in program_or_external; cycles=7 +6F72: 27 02 BEQ loc_6F76 ; cycles=3/7 nt/t +6F74: A0 C6 BSET.B #6, R0 ; cycles=2 + +loc_6F76: +6F76: 1D E1 1E FC BTST.W #12, @H'E11E ; refs mem_E11E in program_or_external; cycles=7 +6F7A: 27 02 BEQ loc_6F7E ; cycles=3/7 nt/t +6F7C: A0 C4 BSET.B #4, R0 ; cycles=2 + +loc_6F7E: +6F7E: 15 F7 11 90 MOV:G.B R0, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=7 +6F82: 20 10 BRA loc_6F94 ; cycles=7 +6F84: 20 20 BRA loc_6FA6 ; cycles=7 + +loc_6F94: +6F94: 58 6F 84 MOV:I.W #H'6F84, R0 ; LCD text xref H'6F84 'OTHERS Xo'; dataflow R0=H'6F84; cycles=3 +6F97: 1E EA F7 BSR loc_5A91 ; cycles=14 +6F9A: 1E EB 65 BSR loc_5B02 ; cycles=13 +6F9D: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +6FA0: 1E CF 29 BSR loc_3ECC ; cycles=13 +6FA3: 1E F1 CD BSR loc_6173 ; cycles=14 + +loc_6FA6: +6FA6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +6FA9: 1E CF 20 BSR loc_3ECC ; cycles=14 +6FAC: 20 10 BRA loc_6FBE ; cycles=7 + +loc_6FBE: +6FBE: 58 6F AE MOV:I.W #H'6FAE, R0 ; LCD text xref H'6FAE 'SHUTTER Xo'; dataflow R0=H'6FAE; cycles=3 +6FC1: 1E EA CD BSR loc_5A91 ; cycles=14 +6FC4: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +6FC7: 1E CF 02 BSR loc_3ECC ; cycles=14 +6FCA: 20 10 BRA loc_6FDC ; cycles=7 + +loc_6FDC: +6FDC: 58 6F CC MOV:I.W #H'6FCC, R0 ; dataflow R0=H'6FCC; cycles=3 +6FDF: 1E EC AF BSR loc_5C91 ; cycles=14 +6FE2: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +6FE5: 1E CE E4 BSR loc_3ECC ; cycles=14 +6FE8: 19 RTS ; cycles=12 +7000: F7 .db H'F7 +7040: 11 C7 PJMP @R7 ; PJMP @R7 uses R7; target not resolved; cycles=8 +7047: 1E E4 B6 BSR loc_5500 ; cycles=14 +704A: 20 51 BRA loc_709D ; cycles=7 + +loc_709D: +709D: 20 10 BRA loc_70AF ; cycles=8 + +loc_70AF: +70AF: 58 70 9F MOV:I.W #H'709F, R0 ; LCD text xref H'709F 'OTHERS Xp'; dataflow R0=H'709F; cycles=3 +70B2: 1E E9 DC BSR loc_5A91 ; cycles=13 +70B5: 1E EA 4A BSR loc_5B02 ; cycles=14 +70B8: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +70BB: 1E CE 0E BSR loc_3ECC ; cycles=14 +70BE: 20 10 BRA loc_70D0 ; cycles=7 + +loc_70D0: +70D0: 58 70 C0 MOV:I.W #H'70C0, R0 ; LCD text xref H'70C0 'COPY TO SLAVES~Xp'; dataflow R0=H'70C0; cycles=3 +70D3: 1E E9 BB BSR loc_5A91 ; cycles=14 +70D6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +70D9: 1E CD F0 BSR loc_3ECC ; cycles=14 +70DC: 1E F0 94 BSR loc_6173 ; cycles=13 +70DF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +70E2: 1E CD E7 BSR loc_3ECC ; cycles=13 +70E5: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +70E8: 1E CD E1 BSR loc_3ECC ; cycles=13 +70EB: 1E E9 8C BSR loc_5A7A ; cycles=14 +70EE: 19 RTS ; cycles=12 +70F1: 00 NOP ; cycles=2 +70F2: 00 NOP ; cycles=2 +70F3: 43 00 CMP:E #H'00, R3 ; cycles=2 +70F5: 01 .db H'01 +930A: 5B 93 1C MOV:I.W #H'931C, R3 ; dataflow R3=H'931C; cycles=3 +930D: 54 04 MOV:E.B #H'04, R4 ; dataflow R4=H'04; cycles=2 +930F: 1E CC C0 BSR loc_5FD2 ; cycles=14 +9312: FC 93 1C 84 MOV:G.W @(-H'6CE4,R4), R4 ; cycles=7 +9316: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +9318: 19 RTS ; cycles=12 +9326: 5B 93 4E MOV:I.W #H'934E, R3 ; dataflow R3=H'934E; cycles=3 +9329: 54 03 MOV:E.B #H'03, R4 ; dataflow R4=H'03; cycles=2 +932B: 15 F7 96 F7 BTST.B #7, @H'F796 ; refs ram_F796 in on_chip_ram; cycles=6 +932F: 26 06 BNE loc_9337 ; cycles=3/8 nt/t +9331: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +9335: 27 02 BEQ loc_9339 ; cycles=3/8 nt/t + +loc_9337: +9337: 54 04 MOV:E.B #H'04, R4 ; dataflow R4=H'04; cycles=2 + +loc_9339: +9339: 15 F6 D1 F1 BTST.B #1, @H'F6D1 ; refs ram_F6D1 in on_chip_ram; cycles=6 +933D: 27 02 BEQ loc_9341 ; cycles=3/8 nt/t +933F: 54 05 MOV:E.B #H'05, R4 ; dataflow R4=H'05; cycles=2 + +loc_9341: +9341: 1E CC 8E BSR loc_5FD2 ; cycles=14 +9344: FC 93 4E 84 MOV:G.W @(-H'6CB2,R4), R4 ; cycles=7 +9348: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +934A: 19 RTS ; cycles=12 +935A: 5B 93 6C MOV:I.W #H'936C, R3 ; dataflow R3=H'936C; cycles=3 +935D: 54 07 MOV:E.B #H'07, R4 ; dataflow R4=H'07; cycles=2 +935F: 1E CC 70 BSR loc_5FD2 ; cycles=14 +9362: FC 93 6C 84 MOV:G.W @(-H'6C94,R4), R4 ; cycles=7 +9366: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +9368: 19 RTS ; cycles=12 +937C: 5B 93 8E MOV:I.W #H'938E, R3 ; dataflow R3=H'938E; cycles=3 +937F: 54 01 MOV:E.B #H'01, R4 ; dataflow R4=H'01; cycles=2 +9381: 1E CC 4E BSR loc_5FD2 ; cycles=14 +9384: FC 93 8E 84 MOV:G.W @(-H'6C72,R4), R4 ; cycles=7 +9388: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +938A: 19 RTS ; cycles=12 +9392: 5B 93 A4 MOV:I.W #H'93A4, R3 ; dataflow R3=H'93A4; cycles=3 +9395: 54 02 MOV:E.B #H'02, R4 ; dataflow R4=H'02; cycles=2 +9397: 1E CC 38 BSR loc_5FD2 ; cycles=14 +939A: FC 93 A4 84 MOV:G.W @(-H'6C5C,R4), R4 ; cycles=7 +939E: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +93A0: 19 RTS ; cycles=12 +93AA: 5B 93 BC MOV:I.W #H'93BC, R3 ; dataflow R3=H'93BC; cycles=3 +93AD: 54 00 MOV:E.B #H'00, R4 ; dataflow R4=H'00; cycles=2 +93AF: 1E CC 20 BSR loc_5FD2 ; cycles=14 +93B2: FC 93 BC 84 MOV:G.W @(-H'6C44,R4), R4 ; cycles=7 +93B6: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +93B8: 19 RTS ; cycles=12 +93BE: 5B 93 D0 MOV:I.W #H'93D0, R3 ; dataflow R3=H'93D0; cycles=3 +93C1: 54 01 MOV:E.B #H'01, R4 ; dataflow R4=H'01; cycles=2 +93C3: 1E CC 0C BSR loc_5FD2 ; cycles=14 +93C6: FC 93 D0 84 MOV:G.W @(-H'6C30,R4), R4 ; cycles=7 +93CA: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +93CC: 19 RTS ; cycles=12 +93D4: 5B 93 E6 MOV:I.W #H'93E6, R3 ; dataflow R3=H'93E6; cycles=3 +93D7: 54 01 MOV:E.B #H'01, R4 ; dataflow R4=H'01; cycles=2 +93D9: 1E CB F6 BSR loc_5FD2 ; cycles=14 +93DC: FC 93 E6 84 MOV:G.W @(-H'6C1A,R4), R4 ; LCD text xref H'6C16 'DIAG DATA Xl'; cycles=7 +93E0: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +93E2: 19 RTS ; cycles=12 + +loc_BA26: +BA26: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=7 +BA2A: 26 FA BNE loc_BA26 ; cycles=3/7 nt/t +BA2C: 15 F9 C0 06 64 MOV:G.B #H'64, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BA31: 15 F9 C4 06 07 MOV:G.B #H'07, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +BA36: 1D F8 50 80 MOV:G.W @H'F850, R0 ; refs ram_F850 in on_chip_ram; cycles=7 +BA3A: 1D F8 58 90 MOV:G.W R0, @H'F858 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA3E: 1D F8 52 80 MOV:G.W @H'F852, R0 ; refs ram_F852 in on_chip_ram; cycles=7 +BA42: 1D F8 5A 90 MOV:G.W R0, @H'F85A ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA46: 15 F8 54 80 MOV:G.B @H'F854, R0 ; refs ram_F854 in on_chip_ram; cycles=7 +BA4A: 15 F8 5C 90 MOV:G.B R0, @H'F85C ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA4E: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high; dataflow R0=H'5A; cycles=2 +BA50: 15 F8 58 60 XOR.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA54: 15 F8 59 60 XOR.B @H'F859, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F859 in on_chip_ram; cycles=7 +BA58: 15 F8 5A 60 XOR.B @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA5C: 15 F8 5B 60 XOR.B @H'F85B, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85B in on_chip_ram; cycles=7 +BA60: 15 F8 5C 60 XOR.B @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA64: 15 F8 5D 90 MOV:G.B R0, @H'F85D ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85D in on_chip_ram; cycles=7 + +loc_BA68: +BA68: 15 FE DC F7 BTST.B #7, @SCI1_SSR ; wait for SCI1 transmit data register empty (TDRE=1); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR in register_field; cycles=7 +BA6C: 27 FA BEQ loc_BA68 ; repeat SCI1 transmit-empty wait while TDRE=0; cycles=3/7 nt/t +BA6E: 15 F8 58 80 MOV:G.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA72: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=7 +BA76: 15 F9 C2 06 01 MOV:G.B #H'01, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high; refs ram_F9C2 in on_chip_ram; cycles=9 +BA7B: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BA7F: 15 FE DA C7 BSET.B #7, @SCI1_SCR ; set TIE (bit 7) of SCI1_SCR; enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=8 +BA83: 19 RTS ; cycles=13 + +vec_sci1_txi_BA84: +BA84: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BA88: 27 1F BEQ loc_BAA9 ; cycles=3/7 nt/t +BA8A: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BA8E: 27 19 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA90: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BA94: 27 13 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA96: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BA9A: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BA9E: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BAA2: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAA7: 20 48 BRA loc_BAF1 ; cycles=8 + +loc_BAA9: +BAA9: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +BAAB: 15 F9 C2 80 MOV:G.B @H'F9C2, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAAF: A0 12 EXTU.B R0 ; cycles=3 +BAB1: F0 F8 58 80 MOV:G.B @(-H'07A8,R0), R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; cycles=6 +BAB5: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=6 +BAB9: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +BABB: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BABF: 15 F9 C2 08 ADD:Q.B #1, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high; refs ram_F9C2 in on_chip_ram; cycles=8 +BAC3: 15 F9 C2 04 06 CMP:G.B #H'06, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAC8: 26 27 BNE loc_BAF1 ; cycles=3/7 nt/t +BACA: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BACE: 15 F7 95 F6 BTST.B #6, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +BAD2: 26 14 BNE loc_BAE8 ; cycles=3/7 nt/t +BAD4: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +BAD8: 26 07 BNE loc_BAE1 ; cycles=3/7 nt/t +BADA: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BADF: 20 0C BRA loc_BAED ; cycles=8 + +loc_BAE1: +BAE1: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAE6: 20 05 BRA loc_BAED ; cycles=7 + +loc_BAE8: +BAE8: 15 F9 C0 06 F0 MOV:G.B #H'F0, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BAED: +BAED: 15 F9 C1 13 CLR.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=8 + +loc_BAF1: +BAF1: 0A RTE ; cycles=14 + +loc_BAF2: +BAF2: 15 F9 B5 81 MOV:G.B @H'F9B5, R1 ; refs ram_F9B5 in on_chip_ram; cycles=7 +BAF6: A1 12 EXTU.B R1 ; cycles=3 +BAF8: 15 F9 B0 71 CMP:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +BAFC: 26 02 BNE loc_BB00 ; cycles=3/7 nt/t +BAFE: 20 56 BRA loc_BB56 ; cycles=7 + +loc_BB00: +BB00: 15 FA A2 C3 BSET.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BB04: A9 80 MOV:G.W R1, R0 ; cycles=3 +BB06: A8 1A SHLL.W R0 ; cycles=3 +BB08: F8 F8 70 80 MOV:G.W @(-H'0790,R0), R0 ; cycles=7 +BB0C: A8 85 MOV:G.W R0, R5 ; cycles=3 +BB0E: 1E A6 F5 BSR loc_6206 ; cycles=13 +BB11: A8 81 MOV:G.W R0, R1 ; cycles=3 +BB13: A1 10 SWAP.B R1 ; cycles=3 +BB15: A1 1B SHLR.B R1 ; cycles=2 +BB17: A1 82 MOV:G.B R1, R2 ; cycles=2 +BB19: 04 07 51 AND.B #H'07, R1 ; cycles=3 +BB1C: 15 F8 50 91 MOV:G.B R1, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=7 +BB20: 15 F8 52 95 MOV:G.B R5, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BB24: A5 10 SWAP.B R5 ; cycles=3 +BB26: 04 78 52 AND.B #H'78, R2 ; cycles=3 +BB29: A2 45 OR.B R2, R5 ; cycles=2 +BB2B: 15 F8 51 95 MOV:G.B R5, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BB2F: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +BB33: A8 1A SHLL.W R0 ; cycles=3 +BB35: F8 E8 00 84 MOV:G.W @(-H'1800,R0), R4 ; cycles=6 +BB39: 15 F8 54 94 MOV:G.B R4, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BB3D: A4 10 SWAP.B R4 ; cycles=3 +BB3F: 15 F8 53 94 MOV:G.B R4, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=6 +BB43: 1E FE E0 BSR loc_BA26 ; cycles=14 +BB46: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=11 +BB4C: 15 F9 C8 06 14 MOV:G.B #H'14, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=9 +BB51: 15 FA A3 06 80 MOV:G.B #H'80, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 + +loc_BB56: +BB56: 19 RTS ; cycles=12 + +vec_sci1_eri_BB57: +BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; refs ram_FAA4 in on_chip_ram; cycles=8 +BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 + +vec_sci1_rxi_BB67: +BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR in register_field; cycles=6 +BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=6 +BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t +BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BB7B: 20 0D BRA loc_BB8A ; cycles=8 + +loc_BB7D: +BB7D: 15 F9 C3 04 05 CMP:G.B #H'05, @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +BB82: 23 06 BLS loc_BB8A ; cycles=3/7 nt/t +BB84: 15 FA A4 13 CLR.B @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=9 +BB88: 20 19 BRA loc_BBA3 ; cycles=7 + +loc_BB8A: +BB8A: 15 F9 C3 81 MOV:G.B @H'F9C3, R1 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BB8E: A1 12 EXTU.B R1 ; cycles=3 +BB90: F1 F8 68 90 MOV:G.B R0, @(-H'0798,R1) ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high; cycles=7 +BB94: A1 08 ADD:Q.B #1, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; cycles=4 +BB96: 15 F9 C3 91 MOV:G.B R1, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; refs ram_F9C3 in on_chip_ram; cycles=7 +BB9A: 41 06 CMP:E #H'06, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high; cycles=2 +BB9C: 26 05 BNE loc_BBA3 ; cycles=3/7 nt/t +BB9E: 15 F9 C5 06 14 MOV:G.B #H'14, @H'F9C5 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BBA3: +BBA3: 15 F9 C1 06 05 MOV:G.B #H'05, @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=9 +BBA8: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +BBAA: 0A RTE ; cycles=13 + +loc_BBAB: +BBAB: 15 F9 C3 04 06 CMP:G.B #H'06, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high; refs ram_F9C3 in on_chip_ram; cycles=6 +BBB0: 36 02 BC BNE loc_BE6F ; cycles=3/7 nt/t +BBB3: 1D F8 68 80 MOV:G.W @H'F868, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F868 in on_chip_ram; cycles=6 +BBB7: 1D F8 60 90 MOV:G.W R0, @H'F860 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=6 +BBBB: 1D F8 6A 80 MOV:G.W @H'F86A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86A in on_chip_ram; cycles=6 +BBBF: 1D F8 62 90 MOV:G.W R0, @H'F862 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=6 +BBC3: 1D F8 6C 80 MOV:G.W @H'F86C, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86C in on_chip_ram; cycles=6 +BBC7: 1D F8 64 90 MOV:G.W R0, @H'F864 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=6 +BBCB: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BBCF: 15 FA A4 F7 BTST.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=6 +BBD3: 36 02 53 BNE loc_BE29 ; cycles=3/8 nt/t +BBD6: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; dataflow R0=H'5A; cycles=2 +BBD8: 15 F8 60 60 XOR.B @H'F860, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=7 +BBDC: 15 F8 61 60 XOR.B @H'F861, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F861 in on_chip_ram; cycles=7 +BBE0: 15 F8 62 60 XOR.B @H'F862, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=7 +BBE4: 15 F8 63 60 XOR.B @H'F863, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F863 in on_chip_ram; cycles=7 +BBE8: 15 F8 64 60 XOR.B @H'F864, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=7 +BBEC: 15 F8 65 70 CMP:G.B @H'F865, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F865 in on_chip_ram; cycles=7 +BBF0: 36 02 36 BNE loc_BE29 ; cycles=3/7 nt/t +BBF3: 15 FA A6 13 CLR.B @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BBF7: 15 F8 61 85 MOV:G.B @H'F861, R5 ; refs ram_F861 in on_chip_ram; cycles=6 +BBFB: A5 10 SWAP.B R5 ; cycles=3 +BBFD: 15 F8 62 85 MOV:G.B @H'F862, R5 ; refs ram_F862 in on_chip_ram; cycles=6 +BC01: 1E A6 27 BSR loc_622B ; cycles=14 +BC04: AD 84 MOV:G.W R5, R4 ; cycles=3 +BC06: AC 1A SHLL.W R4 ; cycles=3 +BC08: 15 F8 60 80 MOV:G.B @H'F860, R0 ; refs ram_F860 in on_chip_ram; cycles=7 +BC0C: 04 07 50 AND.B #H'07, R0 ; cycles=3 +BC0F: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BC13: 26 25 BNE loc_BC3A ; cycles=3/8 nt/t + +loc_BC15: +BC15: 15 FA A2 C7 BSET.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC19: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=6 +BC1D: 36 00 EB BNE loc_BD0B ; cycles=3/8 nt/t +BC20: 40 00 CMP:E #H'00, R0 ; cycles=2 +BC22: 27 45 BEQ loc_BC69 ; cycles=3/7 nt/t +BC24: 40 01 CMP:E #H'01, R0 ; cycles=2 +BC26: 37 00 AE BEQ loc_BCD7 ; cycles=3/7 nt/t +BC29: 40 02 CMP:E #H'02, R0 ; cycles=2 +BC2B: 37 00 D6 BEQ loc_BD04 ; cycles=3/8 nt/t +BC2E: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC30: 37 01 D2 BEQ loc_BE05 ; cycles=3/7 nt/t +BC33: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC37: 30 02 35 BRA loc_BE6F ; cycles=8 + +loc_BC3A: +BC3A: A0 F2 BTST.B #2, R0 ; cycles=2 +BC3C: 27 1E BEQ loc_BC5C ; cycles=3/7 nt/t +BC3E: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=7 +BC42: 36 01 E2 BNE loc_BE27 ; cycles=3/7 nt/t +BC45: 40 04 CMP:E #H'04, R0 ; cycles=2 +BC47: 37 00 C4 BEQ loc_BD0E ; cycles=3/8 nt/t +BC4A: 40 05 CMP:E #H'05, R0 ; cycles=2 +BC4C: 37 01 31 BEQ loc_BD80 ; cycles=3/7 nt/t +BC4F: 40 06 CMP:E #H'06, R0 ; cycles=2 +BC51: 37 01 87 BEQ loc_BDDB ; cycles=3/8 nt/t +BC54: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC56: 37 01 AC BEQ loc_BE05 ; cycles=3/7 nt/t +BC59: 30 02 13 BRA loc_BE6F ; cycles=8 + +loc_BC5C: +BC5C: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BC60: 37 02 0C BEQ loc_BE6F ; cycles=3/7 nt/t +BC63: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BC67: 20 AC BRA loc_BC15 ; cycles=8 + +loc_BC69: +BC69: AD 16 TST.W R5 ; cycles=3 +BC6B: 26 1E BNE loc_BC8B ; cycles=3/8 nt/t +BC6D: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC71: A0 10 SWAP.B R0 ; cycles=3 +BC73: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BC75: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC79: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC7D: 15 F8 64 06 80 MOV:G.B #H'80, @H'F864 ; refs ram_F864 in on_chip_ram; cycles=9 +BC82: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BC86: 1E 01 E7 BSR loc_BE70 ; cycles=13 +BC89: 20 25 BRA loc_BCB0 ; cycles=8 + +loc_BC8B: +BC8B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC8F: A0 10 SWAP.B R0 ; cycles=3 +BC91: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BC95: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC99: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC9D: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BCA1: FC C5 64 81 MOV:G.W @(-H'3A9C,R4), R1 ; cycles=6 +BCA5: A1 12 EXTU.B R1 ; cycles=3 +BCA7: 27 04 BEQ loc_BCAD ; cycles=3/8 nt/t +BCA9: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 + +loc_BCAD: +BCAD: 1E 01 C0 BSR loc_BE70 ; cycles=14 + +loc_BCB0: +BCB0: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCB5: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=6 +BCB9: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BCBD: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=6 +BCC1: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BCC5: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BCC9: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BCCD: 1E FD 56 BSR loc_BA26 ; cycles=14 +BCD0: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BCD4: 30 01 98 BRA loc_BE6F ; cycles=7 + +loc_BCD7: +BCD7: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCDC: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BCE0: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCE4: 15 F8 62 80 MOV:G.B @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BCE8: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCEC: FC E0 00 80 MOV:G.W @(-H'2000,R4), R0 ; cycles=7 +BCF0: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BCF4: A0 10 SWAP.B R0 ; cycles=3 +BCF6: 15 F8 53 90 MOV:G.B R0, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=7 +BCFA: 1E FD 29 BSR loc_BA26 ; cycles=13 +BCFD: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD01: 30 01 6B BRA loc_BE6F ; cycles=8 + +loc_BD04: +BD04: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BD08: 30 01 64 BRA loc_BE6F ; cycles=7 + +loc_BD0B: +BD0B: 30 01 61 BRA loc_BE6F ; cycles=8 + +loc_BD0E: +BD0E: AD 16 TST.W R5 ; cycles=3 +BD10: 26 19 BNE loc_BD2B ; cycles=3/7 nt/t +BD12: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=7 +BD16: A0 10 SWAP.B R0 ; cycles=3 +BD18: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BD1A: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=7 +BD1E: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=7 +BD22: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BD26: 1E 01 47 BSR loc_BE70 ; cycles=13 +BD29: 20 3C BRA loc_BD67 ; cycles=8 + +loc_BD2B: +BD2B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BD2F: A0 10 SWAP.B R0 ; cycles=3 +BD31: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BD35: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BD39: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BD3D: F4 C5 65 81 MOV:G.B @(-H'3A9B,R4), R1 ; cycles=6 +BD41: A1 12 EXTU.B R1 ; cycles=3 +BD43: 27 1F BEQ loc_BD64 ; cycles=3/8 nt/t +BD45: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 +BD49: 15 F7 6E F7 BTST.B #7, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +BD4D: 27 15 BEQ loc_BD64 ; cycles=3/8 nt/t +BD4F: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +BD51: 15 F7 6E 84 MOV:G.B @H'F76E, R4 ; refs ram_F76E in on_chip_ram; cycles=6 +BD55: A4 10 SWAP.B R4 ; cycles=3 +BD57: A1 84 MOV:G.B R1, R4 ; cycles=2 +BD59: 0C 0F FE 54 AND.W #H'0FFE, R4 ; cycles=4 +BD5D: A8 85 MOV:G.W R0, R5 ; cycles=3 +BD5F: 1E 02 7E BSR loc_BFE0 ; cycles=14 +BD62: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 + +loc_BD64: +BD64: 1E 01 09 BSR loc_BE70 ; cycles=13 + +loc_BD67: +BD67: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BD6B: 27 08 BEQ loc_BD75 ; cycles=3/8 nt/t +BD6D: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BD71: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BD75: +BD75: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BD79: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD7D: 30 00 EF BRA loc_BE6F ; cycles=8 + +loc_BD80: +BD80: 4D 00 6C CMP:I #H'006C, R5 ; cycles=3 +BD83: 27 3A BEQ loc_BDBF ; cycles=3/8 nt/t +BD85: 4D 00 6D CMP:I #H'006D, R5 ; cycles=3 +BD88: 27 35 BEQ loc_BDBF ; cycles=3/7 nt/t +BD8A: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD8D: 27 30 BEQ loc_BDBF ; cycles=3/8 nt/t +BD8F: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD92: 27 2B BEQ loc_BDBF ; cycles=3/7 nt/t +BD94: 15 F7 31 F7 BTST.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +BD98: 27 28 BEQ loc_BDC2 ; cycles=3/7 nt/t +BD9A: 4D 00 6B CMP:I #H'006B, R5 ; cycles=3 +BD9D: 27 16 BEQ loc_BDB5 ; cycles=3/8 nt/t +BD9F: 4D 00 96 CMP:I #H'0096, R5 ; cycles=3 +BDA2: 27 11 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDA4: 4D 00 97 CMP:I #H'0097, R5 ; cycles=3 +BDA7: 27 0C BEQ loc_BDB5 ; cycles=3/8 nt/t +BDA9: 4D 00 C6 CMP:I #H'00C6, R5 ; cycles=3 +BDAC: 27 07 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDAE: 4D 00 F8 CMP:I #H'00F8, R5 ; cycles=3 +BDB1: 27 02 BEQ loc_BDB5 ; cycles=3/8 nt/t +BDB3: 20 0D BRA loc_BDC2 ; cycles=8 + +loc_BDB5: +BDB5: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +BDB9: 15 F7 90 D7 BCLR.B #7, @H'F790 ; refs ram_F790 in on_chip_ram; cycles=8 +BDBD: 20 03 BRA loc_BDC2 ; cycles=8 + +loc_BDBF: +BDBF: 1E 00 AE BSR loc_BE70 ; cycles=14 + +loc_BDC2: +BDC2: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BDC6: 27 08 BEQ loc_BDD0 ; cycles=3/7 nt/t +BDC8: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 +BDCC: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 + +loc_BDD0: +BDD0: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BDD4: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BDD8: 30 00 94 BRA loc_BE6F ; cycles=7 + +loc_BDDB: +BDDB: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BDDF: A0 10 SWAP.B R0 ; cycles=3 +BDE1: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BDE5: FC E4 00 90 MOV:G.W R0, @(-H'1C00,R4) ; cycles=6 +BDE9: F5 EC 00 C6 BSET.B #6, @(-H'1400,R5) ; cycles=8 +BDED: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BDF1: 27 08 BEQ loc_BDFB ; cycles=3/8 nt/t +BDF3: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BDF7: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BDFB: +BDFB: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BDFF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE03: 20 6A BRA loc_BE6F ; cycles=8 + +loc_BE05: +BE05: 1D F8 58 80 MOV:G.W @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=6 +BE09: 1D F8 50 90 MOV:G.W R0, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=6 +BE0D: 1D F8 5A 80 MOV:G.W @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=6 +BE11: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BE15: 1D F8 5C 80 MOV:G.W @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=6 +BE19: 1D F8 54 90 MOV:G.W R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BE1D: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE22: 1E FC 01 BSR loc_BA26 ; cycles=13 +BE25: 20 48 BRA loc_BE6F ; cycles=8 + +loc_BE27: +BE27: 20 46 BRA loc_BE6F ; cycles=8 + +loc_BE29: +BE29: 15 FA A4 D7 BCLR.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=8 +BE2D: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +BE31: 27 3A BEQ loc_BE6D ; cycles=3/8 nt/t +BE33: 15 FA A6 08 ADD:Q.B #1, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BE37: 15 FA A6 04 02 CMP:G.B #H'02, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=6 +BE3C: 25 0F BCS loc_BE4D ; cycles=3/7 nt/t +BE3E: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE43: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BE47: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE4B: 20 20 BRA loc_BE6D ; cycles=8 + +loc_BE4D: +BE4D: 15 F8 50 06 07 MOV:G.B #H'07, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BE52: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BE56: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BE5A: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BE5E: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BE62: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=7 +BE66: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BE6A: 1E FB B9 BSR loc_BA26 ; cycles=13 + +loc_BE6D: +BE6D: 20 00 BRA loc_BE6F ; cycles=8 + +loc_BE6F: +BE6F: 19 RTS ; cycles=13 + +loc_BE70: +BE70: 15 F9 B9 83 MOV:G.B @H'F9B9, R3 ; refs ram_F9B9 in on_chip_ram; cycles=7 +BE74: A3 12 EXTU.B R3 ; cycles=3 +BE76: AB 1A SHLL.W R3 ; cycles=3 +BE78: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +BE7C: A1 12 EXTU.B R1 ; cycles=3 +BE7E: A9 1A SHLL.W R1 ; cycles=3 + +loc_BE80: +BE80: A3 71 CMP:G.B R3, R1 ; cycles=2 +BE82: 27 0D BEQ loc_BE91 ; cycles=3/7 nt/t +BE84: FB F9 70 75 CMP:G.W @(-H'0690,R3), R5 ; cycles=7 +BE88: 27 13 BEQ loc_BE9D ; cycles=3/7 nt/t +BE8A: A3 09 ADD:Q.B #2, R3 ; cycles=4 +BE8C: 04 3F 53 AND.B #H'3F, R3 ; cycles=3 +BE8F: 20 EF BRA loc_BE80 ; cycles=8 + +loc_BE91: +BE91: F9 F9 70 95 MOV:G.W R5, @(-H'0690,R1) ; cycles=6 +BE95: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +BE99: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_BE9D: +BE9D: 19 RTS ; cycles=13 + +loc_BE9E: +BE9E: 15 FA A5 80 MOV:G.B @H'FAA5, R0 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BEA2: 04 80 50 AND.B #H'80, R0 ; cycles=3 +BEA5: 15 FA A3 50 AND.B @H'FAA3, R0 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEA9: 15 FA A3 90 MOV:G.B R0, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEAD: 26 06 BNE loc_BEB5 ; cycles=3/8 nt/t +BEAF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BEB3: 20 33 BRA loc_BEE8 ; cycles=8 + +loc_BEB5: +BEB5: 1D F9 C6 16 TST.W @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=6 +BEB9: 26 2D BNE loc_BEE8 ; cycles=3/8 nt/t +BEBB: 15 F9 C8 16 TST.B @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=6 +BEBF: 27 23 BEQ loc_BEE4 ; cycles=3/8 nt/t +BEC1: 15 F9 C8 0C ADD:Q.B #-1, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=8 +BEC5: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=9 +BECB: 15 FA A3 F7 BTST.B #7, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BECF: 27 17 BEQ loc_BEE8 ; cycles=3/8 nt/t +BED1: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BED5: 1E FB 4E BSR loc_BA26 ; cycles=14 +BED8: 20 0E BRA loc_BEE8 ; cycles=7 + +loc_BEE4: +BEE4: 15 F9 C5 13 CLR.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BEE8: +BEE8: 19 RTS ; cycles=12 + +vec_frt1_ocia_BEEA: +BEEA: 15 FE 91 D5 BCLR.B #5, @FRT1_TCSR ; clear OCFA (bit 5) of FRT1_TCSR; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; cycles=9 +BEEE: 15 F9 C0 16 TST.B @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=7 +BEF2: 27 04 BEQ loc_BEF8 ; cycles=3/7 nt/t +BEF4: 15 F9 C0 0C ADD:Q.B #-1, @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BEF8: +BEF8: 15 F9 C1 16 TST.B @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=7 +BEFC: 27 04 BEQ loc_BF02 ; cycles=3/7 nt/t +BEFE: 15 F9 C1 0C ADD:Q.B #-1, @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=9 + +loc_BF02: +BF02: 1D F9 C6 16 TST.W @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=7 +BF06: 27 04 BEQ loc_BF0C ; cycles=3/7 nt/t +BF08: 1D F9 C6 0C ADD:Q.W #-1, @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=9 + +loc_BF0C: +BF0C: 15 F6 F6 F7 BTST.B #7, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=7 +BF10: 27 10 BEQ loc_BF22 ; cycles=3/7 nt/t +BF12: 1D F6 F4 16 TST.W @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=7 +BF16: 26 06 BNE loc_BF1E ; cycles=3/7 nt/t +BF18: 15 F6 F6 C5 BSET.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +BF1C: 20 04 BRA loc_BF22 ; cycles=7 + +loc_BF1E: +BF1E: 1D F6 F4 0C ADD:Q.W #-1, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_BF22: +BF22: 0A RTE ; cycles=13 + +vec_frt2_ocia_BF23: +BF23: 15 FE A1 D5 BCLR.B #5, @FRT2_TCSR ; clear OCFA (bit 5) of FRT2_TCSR; cycles=8 +BF27: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=6 +BF2B: 27 04 BEQ loc_BF31 ; cycles=3/8 nt/t +BF2D: 15 F9 C4 0C ADD:Q.B #-1, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=8 + +loc_BF31: +BF31: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +BF35: 27 04 BEQ loc_BF3B ; cycles=3/8 nt/t +BF37: 15 F9 C5 0C ADD:Q.B #-1, @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=8 + +loc_BF3B: +BF3B: 15 F7 24 16 TST.B @H'F724 ; refs ram_F724 in on_chip_ram; cycles=6 +BF3F: 27 06 BEQ loc_BF47 ; cycles=3/8 nt/t +BF41: 15 F7 24 0C ADD:Q.B #-1, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=8 +BF45: 20 09 BRA loc_BF50 ; cycles=8 + +loc_BF47: +BF47: 15 F7 24 06 03 MOV:G.B #H'03, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=9 +BF4C: 15 F7 23 15 NOT.B @H'F723 ; refs ram_F723 in on_chip_ram; cycles=9 + +loc_BF50: +BF50: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +BF54: 27 17 BEQ loc_BF6D ; cycles=3/7 nt/t +BF56: 15 FB 02 16 TST.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=7 +BF5A: 27 06 BEQ loc_BF62 ; cycles=3/7 nt/t +BF5C: 15 FB 02 0C ADD:Q.B #-1, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +BF60: 20 0B BRA loc_BF6D ; cycles=7 + +loc_BF62: +BF62: 15 FB 03 D7 BCLR.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +BF66: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +BF68: 1E 89 84 BSR loc_48EF ; cycles=13 +BF6B: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 + +loc_BF6D: +BF6D: 15 F7 6C 16 TST.B @H'F76C ; refs ram_F76C in on_chip_ram; cycles=6 +BF71: 27 04 BEQ loc_BF77 ; cycles=3/8 nt/t +BF73: 15 F7 6C 0C ADD:Q.B #-1, @H'F76C ; refs ram_F76C in on_chip_ram; cycles=8 + +loc_BF77: +BF77: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BF7B: 27 04 BEQ loc_BF81 ; cycles=3/8 nt/t +BF7D: 15 F8 40 0C ADD:Q.B #-1, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=8 + +loc_BF81: +BF81: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=6 +BF85: 27 1C BEQ loc_BFA3 ; cycles=3/8 nt/t +BF87: 15 F7 26 0C ADD:Q.B #-1, @H'F726 ; refs ram_F726 in on_chip_ram; cycles=8 +BF8B: 26 16 BNE loc_BFA3 ; cycles=3/8 nt/t +BF8D: 15 F7 13 D6 BCLR.B #6, @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +BF91: 26 10 BNE loc_BFA3 ; cycles=3/8 nt/t +BF93: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF97: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9B: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9F: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 + +loc_BFA3: +BFA3: 15 F7 97 16 TST.B @H'F797 ; refs ram_F797 in on_chip_ram; cycles=6 +BFA7: 27 0A BEQ loc_BFB3 ; cycles=3/8 nt/t +BFA9: 15 F7 97 0C ADD:Q.B #-1, @H'F797 ; refs ram_F797 in on_chip_ram; cycles=8 +BFAD: 26 04 BNE loc_BFB3 ; cycles=3/8 nt/t +BFAF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFB3: +BFB3: 15 F7 98 16 TST.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=6 +BFB7: 27 0A BEQ loc_BFC3 ; cycles=3/8 nt/t +BFB9: 15 F7 98 0C ADD:Q.B #-1, @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +BFBD: 26 04 BNE loc_BFC3 ; cycles=3/8 nt/t +BFBF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFC3: +BFC3: 0A RTE ; cycles=14 + +vec_interval_timer_BFC4: +BFC4: 15 FE EC F7 BTST.B #7, @WDT_TCSR_R ; refs WDT_TCSR_R in register_field; cycles=7 +BFC8: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 +BFCE: 15 F7 94 08 ADD:Q.B #1, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=9 +BFD2: 15 F7 94 04 0A CMP:G.B #H'0A, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=7 +BFD7: 26 06 BNE loc_BFDF ; cycles=3/8 nt/t +BFD9: 1D FE EC 07 A5 7F MOV:G.W #H'A57F, @WDT_TCSR_R ; WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096); cycles=9 + +loc_BFDF: +BFDF: 0A RTE ; cycles=14 + +loc_BFE0: +BFE0: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 + +loc_BFE5: +BFE5: AD 82 MOV:G.W R5, R2 ; cycles=3 +BFE7: 0E 27 BSR loc_C010 ; cycles=14 +BFE9: 0E 4E BSR loc_C039 ; cycles=14 +BFEB: AA 75 CMP:G.W R2, R5 ; cycles=3 +BFED: 27 0E BEQ loc_BFFD ; cycles=3/8 nt/t +BFEF: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BFF3: 27 04 BEQ loc_BFF9 ; cycles=3/8 nt/t +BFF5: AA 85 MOV:G.W R2, R5 ; cycles=3 +BFF7: 20 EC BRA loc_BFE5 ; cycles=8 + +loc_BFF9: +BFF9: 15 F8 41 C7 BSET.B #7, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_BFFD: +BFFD: 19 RTS ; cycles=13 + +loc_BFFE: +BFFE: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 +C003: 0E 34 BSR loc_C039 ; cycles=14 +C005: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C009: 26 04 BNE loc_C00F ; cycles=3/8 nt/t +C00B: 15 F8 41 C6 BSET.B #6, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_C00F: +C00F: 19 RTS ; cycles=13 + +loc_C010: +C010: 0E 58 BSR loc_C06A ; cycles=13 + +loc_C012: +C012: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=7 +C016: 27 20 BEQ loc_C038 ; cycles=3/7 nt/t +C018: 1E 01 06 BSR loc_C121 ; cycles=13 +C01B: A3 80 MOV:G.B R3, R0 ; cycles=2 +C01D: 0E 6C BSR loc_C08B ; cycles=14 +C01F: 27 F1 BEQ loc_C012 ; cycles=3/8 nt/t +C021: A4 80 MOV:G.B R4, R0 ; cycles=2 +C023: 0E 66 BSR loc_C08B ; cycles=14 +C025: 27 EB BEQ loc_C012 ; cycles=3/8 nt/t +C027: AD 80 MOV:G.W R5, R0 ; cycles=3 +C029: A0 10 SWAP.B R0 ; cycles=3 +C02B: 0E 5E BSR loc_C08B ; cycles=14 +C02D: 27 E3 BEQ loc_C012 ; cycles=3/8 nt/t +C02F: A5 80 MOV:G.B R5, R0 ; cycles=2 +C031: 0E 58 BSR loc_C08B ; cycles=14 +C033: 27 DD BEQ loc_C012 ; cycles=3/8 nt/t +C035: 1E 01 0A BSR loc_C142 ; cycles=14 + +loc_C038: +C038: 19 RTS ; cycles=12 + +loc_C039: +C039: 0E 2F BSR loc_C06A ; cycles=14 + +loc_C03B: +C03B: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C03F: 27 28 BEQ loc_C069 ; cycles=3/8 nt/t +C041: 1E 00 DD BSR loc_C121 ; cycles=14 +C044: A3 80 MOV:G.B R3, R0 ; cycles=2 +C046: 0E 43 BSR loc_C08B ; cycles=13 +C048: 27 F1 BEQ loc_C03B ; cycles=3/7 nt/t +C04A: A4 80 MOV:G.B R4, R0 ; cycles=2 +C04C: 0E 3D BSR loc_C08B ; cycles=13 +C04E: 27 EB BEQ loc_C03B ; cycles=3/7 nt/t +C050: 1E 00 CE BSR loc_C121 ; cycles=13 +C053: A3 80 MOV:G.B R3, R0 ; cycles=2 +C055: A0 C0 BSET.B #0, R0 ; cycles=2 +C057: 0E 32 BSR loc_C08B ; cycles=14 +C059: 27 E0 BEQ loc_C03B ; cycles=3/8 nt/t +C05B: 1E 00 7D BSR loc_C0DB ; cycles=14 +C05E: A5 10 SWAP.B R5 ; cycles=3 +C060: 1E 00 A9 BSR loc_C10C ; cycles=13 +C063: 1E 00 75 BSR loc_C0DB ; cycles=14 +C066: 1E 00 D9 BSR loc_C142 ; cycles=13 + +loc_C069: +C069: 19 RTS ; cycles=13 + +loc_C06A: +C06A: 0C 0F FF 54 AND.W #H'0FFF, R4 ; cycles=4 +C06E: 4C 08 00 CMP:I #H'0800, R4 ; cycles=3 +C071: 24 0B BCC loc_C07E ; cycles=3/8 nt/t +C073: AC 83 MOV:G.W R4, R3 ; cycles=3 +C075: A3 10 SWAP.B R3 ; cycles=3 +C077: A3 1A SHLL.B R3 ; cycles=2 +C079: 04 A0 43 OR.B #H'A0, R3 ; cycles=3 +C07C: 20 0C BRA loc_C08A ; cycles=7 + +loc_C07E: +C07E: AC 83 MOV:G.W R4, R3 ; cycles=3 +C080: A3 10 SWAP.B R3 ; cycles=3 +C082: A3 1A SHLL.B R3 ; cycles=2 +C084: 04 0E 53 AND.B #H'0E, R3 ; cycles=3 +C087: 04 E0 43 OR.B #H'E0, R3 ; cycles=3 + +loc_C08A: +C08A: 19 RTS ; cycles=12 + +loc_C08B: +C08B: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C08E: +C08E: A0 1A SHLL.B R0 ; cycles=2 +C090: 24 06 BCC loc_C098 ; cycles=3/7 nt/t +C092: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C096: 20 04 BRA loc_C09C ; cycles=7 + +loc_C098: +C098: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 + +loc_C09C: +C09C: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A0: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A8: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0AC: 01 B9 DF SCB/F R1, loc_C08E ; cycles=3/4/8 false/-1/t +C0AF: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0B4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0B8: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0BC: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=7 +C0C0: 27 0D BEQ loc_C0CF ; cycles=3/7 nt/t +C0C2: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0C6: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0CB: 50 00 MOV:E.B #H'00, R0 ; dataflow R0=H'00; cycles=2 +C0CD: 20 0B BRA loc_C0DA ; cycles=8 + +loc_C0CF: +C0CF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0D3: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0D8: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_C0DA: +C0DA: 19 RTS ; cycles=12 + +loc_C0DB: +C0DB: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0E0: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C0E3: +C0E3: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0E7: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0EB: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=6 +C0EF: 27 04 BEQ loc_C0F5 ; cycles=3/8 nt/t +C0F1: A5 49 BSET.B R1, R5 ; cycles=2 +C0F3: 20 02 BRA loc_C0F7 ; cycles=8 + +loc_C0F5: +C0F5: A5 59 BCLR.B R1, R5 ; cycles=2 + +loc_C0F7: +C0F7: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FB: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C103: 01 B9 DD SCB/F R1, loc_C0E3 ; cycles=3/4/9 false/-1/t +C106: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C10B: 19 RTS ; cycles=13 + +loc_C10C: +C10C: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C110: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C114: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C118: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C11C: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C120: 19 RTS ; cycles=12 + +loc_C121: +C121: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=8 +C125: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C129: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C12D: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C131: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=8 +C135: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C139: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C13D: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C141: 19 RTS ; cycles=13 + +loc_C142: +C142: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C146: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14E: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C152: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C156: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15E: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C162: 19 RTS ; cycles=12 diff --git a/build/rom_others_menu_deep.json b/build/rom_others_menu_deep.json new file mode 100644 index 0000000..9be0ecf --- /dev/null +++ b/build/rom_others_menu_deep.json @@ -0,0 +1,220100 @@ +{ + "vectors": [ + { + "address": 0, + "name": "reset", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 4, + "name": "invalid_instruction", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 6, + "name": "zero_divide", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 8, + "name": "trap_vs", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 16, + "name": "address_error", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 18, + "name": "trace", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 22, + "name": "nmi", + "target": 17299, + "target_label": "vec_nmi_4393" + }, + { + "address": 32, + "name": "trapa_0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 34, + "name": "trapa_1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 36, + "name": "trapa_2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 38, + "name": "trapa_3", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 40, + "name": "trapa_4", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 42, + "name": "trapa_5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 44, + "name": "trapa_6", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 46, + "name": "trapa_7", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 48, + "name": "trapa_8", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 50, + "name": "trapa_9", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 52, + "name": "trapa_a", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 54, + "name": "trapa_b", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 56, + "name": "trapa_c", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 58, + "name": "trapa_d", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 60, + "name": "trapa_e", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 62, + "name": "trapa_f", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 64, + "name": "irq0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 66, + "name": "interval_timer", + "target": 49092, + "target_label": "vec_interval_timer_BFC4" + }, + { + "address": 72, + "name": "irq1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 80, + "name": "irq2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 82, + "name": "irq3", + "target": 15408, + "target_label": "vec_irq3_3C30" + }, + { + "address": 88, + "name": "irq4", + "target": 15047, + "target_label": "vec_irq4_3AC7" + }, + { + "address": 90, + "name": "irq5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 98, + "name": "frt1_ocia", + "target": 48874, + "target_label": "vec_frt1_ocia_BEEA" + }, + { + "address": 106, + "name": "frt2_ocia", + "target": 48931, + "target_label": "vec_frt2_ocia_BF23" + }, + { + "address": 128, + "name": "sci1_eri", + "target": 47959, + "target_label": "vec_sci1_eri_BB57" + }, + { + "address": 130, + "name": "sci1_rxi", + "target": 47975, + "target_label": "vec_sci1_rxi_BB67" + }, + { + "address": 132, + "name": "sci1_txi", + "target": 47748, + "target_label": "vec_sci1_txi_BA84" + }, + { + "address": 144, + "name": "ad_adi", + "target": 15769, + "target_label": "vec_ad_adi_3D99" + } + ], + "dtc_vectors": [], + "memory_regions": [ + { + "name": "exception_vectors", + "start": 0, + "end": 159, + "kind": "vectors", + "manual": "section 2 address space" + }, + { + "name": "dtc_vectors", + "start": 160, + "end": 255, + "kind": "dtc_vectors", + "manual": "section 2 address space" + }, + { + "name": "program_or_external", + "start": 256, + "end": 63103, + "kind": "program", + "manual": "section 2/17 mode-dependent ROM or external space" + }, + { + "name": "on_chip_ram", + "start": 63104, + "end": 65151, + "kind": "ram", + "manual": "section 16 RAM" + }, + { + "name": "register_field", + "start": 65152, + "end": 65535, + "kind": "registers", + "manual": "appendix B register map" + } + ], + "data_candidates": { + "strings": [ + { + "address": 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48853 + }, + { + "from": 48931, + "from_label": "vec_frt2_ocia_BF23", + "to": 18671, + "to_label": "loc_48EF", + "call_site": 49000 + }, + { + "from": 49120, + "from_label": "loc_BFE0", + "to": 49168, + "to_label": "loc_C010", + "call_site": 49127 + }, + { + "from": 49120, + "from_label": "loc_BFE0", + "to": 49209, + "to_label": "loc_C039", + "call_site": 49129 + }, + { + "from": 49150, + "from_label": "loc_BFFE", + "to": 49209, + "to_label": "loc_C039", + "call_site": 49155 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49258, + "to_label": "loc_C06A", + "call_site": 49168 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49291, + "to_label": "loc_C08B", + "call_site": 49181 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49441, + "to_label": "loc_C121", + "call_site": 49176 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49474, + "to_label": "loc_C142", + "call_site": 49205 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49258, + "to_label": "loc_C06A", + "call_site": 49209 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49291, + "to_label": "loc_C08B", + "call_site": 49222 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49371, + "to_label": "loc_C0DB", + "call_site": 49243 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49420, + "to_label": "loc_C10C", + "call_site": 49248 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49441, + "to_label": "loc_C121", + "call_site": 49217 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49474, + "to_label": "loc_C142", + "call_site": 49254 + } + ] + }, + "timing_summary": { + "blocks": [], + "loops": [] + }, + "sci": { + "clock_hz": null, + "formulas": { + "async": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))" + }, + "manual_references": [ + "Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source", + "Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source", + "Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator", + "Manual/0900766b802125d0.md:16303 asynchronous BRR formula", + "Manual/0900766b802125d0.md:16379 synchronous BRR formula", + "Manual/0900766b802125d0.md:16410 SCI clock source selection tables" + ], + "channels": { + "SCI1": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ], + "configurations": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "SCI2": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "configurations": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + } + } + }, + "sci_protocol": { + "manual_references": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "channels": { + "SCI1": { + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "SCI2": { + "events": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ] + } + }, + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "serial_reconstruction": { + "kind": "serial_reconstruction", + "candidates": [ + { + "id": "sci1_tx_frame_f858_len6_candidate", + "kind": "candidate_sci1_tx_frame", + "channel": "SCI1", + "frame_length": 6, + "buffer_start": 63576, + "buffer_start_hex": "H'F858", + "buffer_end": 63581, + "buffer_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "tx_index_address": 63938, + "tx_index_address_hex": "H'F9C2", + "tdr_address": 65243, + "tdr_address_hex": "H'FEDB", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "roles": [ + { + "name": "tx_frame", + "address": 63576, + "address_hex": "H'F858", + "end_address": 63581, + "end_address_hex": "H'F85D", + "summary": "evidence-supported candidate SCI1 TX frame buffer" + }, + { + "name": "tx_checksum", + "address": 63581, + "address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "summary": "evidence-supported candidate SCI1 TX XOR checksum byte" + }, + { + "name": "tx_index", + "address": 63938, + "address_hex": "H'F9C2", + "summary": "evidence-supported candidate SCI1 TX frame index" + } + ], + "tx_path": { + "kind": "interrupt_driven_txi", + "initial_tdr_write_address": 47730, + "initial_tdr_write_address_hex": "H'BA72", + "txi_indexed_tdr_write_address": 47797, + "txi_indexed_tdr_write_address_hex": "H'BAB5", + "summary": "initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted", + "tdre_caveat": "TDRE reassertion is hardware/emulator timing context; static evidence is the indexed TXI send path." + }, + "confidence": "high", + "confidence_score": 0.95, + "confidence_reason": "all required independent evidence groups were observed", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "missing_evidence": [], + "evidence_addresses": { + "tx_buffer_region": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "tx_checksum_seed": [ + 47694 + ], + "checksum_byte": [ + 47716 + ], + "xor_checksum_chain": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "initial_send_from_buffer_start": [ + 47726, + 47730 + ], + "tx_index_initialized_to_one": [ + 47734 + ], + "tx_isr_indexed_send": [ + 47787, + 47793, + 47797 + ], + "tx_index_increment": [ + 47807 + ], + "tx_index_compare_frame_length": [ + 47811 + ] + }, + "evidence_addresses_hex": { + "tx_buffer_region": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "tx_checksum_seed": [ + "H'BA4E" + ], + "checksum_byte": [ + "H'BA64" + ], + "xor_checksum_chain": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "initial_send_from_buffer_start": [ + "H'BA6E", + "H'BA72" + ], + "tx_index_initialized_to_one": [ + "H'BA76" + ], + "tx_isr_indexed_send": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "tx_index_increment": [ + "H'BABF" + ], + "tx_index_compare_frame_length": [ + "H'BAC3" + ] + }, + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + } + ], + "short_comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis using buffer H'F858-H'F85D with checksum byte H'F85D seeded by H'005A" + }, + { + "id": "sci1_rx_frame_f868_len6_candidate", + "kind": "candidate_sci1_rx_frame", + "channel": "SCI1", + "frame_length": 6, + "capture_buffer_start": 63592, + "capture_buffer_start_hex": "H'F868", + "capture_buffer_end": 63597, + "capture_buffer_end_hex": "H'F86D", + "validation_buffer_start": 63584, + "validation_buffer_start_hex": "H'F860", + "validation_buffer_end": 63589, + "validation_buffer_end_hex": "H'F865", + "checksum_address": 63589, + "checksum_address_hex": "H'F865", + "rx_index_address": 63939, + "rx_index_address_hex": "H'F9C3", + "rdr_address": 65245, + "rdr_address_hex": "H'FEDD", + "interbyte_timeout_address": 63937, + "interbyte_timeout_address_hex": "H'F9C1", + "complete_timer_address": 63941, + "complete_timer_address_hex": "H'F9C5", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "confidence": "high", + "confidence_score": 0.9, + "confidence_reason": "RX count, copy, and checksum-validation evidence were observed; no explicit header/sync byte was identified", + "caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "optional_evidence_count": 2, + "missing_evidence": [], + "evidence_addresses": { + "rx_rdr_read": [ + 47981 + ], + "rx_indexed_store": [ + 48016 + ], + "rx_index_increment_store": [ + 48020, + 48022 + ], + "rx_isr_compare_frame_length": [ + 48026 + ], + "rx_complete_timer": [ + 48030 + ], + "rx_processor_requires_six_bytes": [ + 48043 + ], + "rx_copy_capture_to_frame_buffer": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "rx_checksum_seed": [ + 48086 + ], + "rx_xor_checksum_validation": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "rx_rdrf_clear_before_rdr_read": [ + 47977, + 47981 + ], + "rx_eri_falls_through_to_rxi": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ] + }, + "evidence_addresses_hex": { + "rx_rdr_read": [ + "H'BB6D" + ], + "rx_indexed_store": [ + "H'BB90" + ], + "rx_index_increment_store": [ + "H'BB94", + "H'BB96" + ], + "rx_isr_compare_frame_length": [ + "H'BB9A" + ], + "rx_complete_timer": [ + "H'BB9E" + ], + "rx_processor_requires_six_bytes": [ + "H'BBAB" + ], + "rx_copy_capture_to_frame_buffer": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "rx_checksum_seed": [ + "H'BBD6" + ], + "rx_xor_checksum_validation": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "rx_rdrf_clear_before_rdr_read": [ + "H'BB69", + "H'BB6D" + ], + "rx_eri_falls_through_to_rxi": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ] + }, + "evidence": [ + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + } + ], + "rx_error_handling": { + "kind": "sci1_rx_error_handling_candidate", + "error_latch_address": 64164, + "error_latch_address_hex": "H'FAA4", + "error_latch_bit": 7, + "fallthrough_to_rx_byte_path": true, + "rdrf_clear_before_rdr_read": true, + "summary": "SCI1 ERI appears to mark a physical receive error and continue into the RXI byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order.", + "manual_caveat": "Manual text distinguishes ORER from FER/PER data transfer into RDR and describes the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order.", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "candidate-medium" + }, + "short_comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A" + } + ], + "ram_roles": [ + { + "kind": "candidate_ram_role", + "name": "post_tx_report_delay", + "address": 63936, + "address_hex": "H'F9C0", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "post_tx_report_delay_tick_decrement": [ + 48878, + 48884 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "post_tx_report_delay_tick_decrement": [ + "H'BEEE", + "H'BEF4" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "secondary_tx_report_delay", + "address": 63937, + "address_hex": "H'F9C1", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "secondary_tx_report_delay_tick_decrement": [ + 48888, + 48894 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "secondary_tx_report_delay_tick_decrement": [ + "H'BEF8", + "H'BEFE" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "periodic_report_countdown", + "address": 63942, + "address_hex": "H'F9C6", + "width_bits": 16, + "confidence": "candidate/evidence-supported", + "summary": "periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "periodic_report_countdown_tick_decrement": [ + 48898, + 48904 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "periodic_report_countdown_tick_decrement": [ + "H'BF02", + "H'BF08" + ] + } + } + ], + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + }, + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "required_evidence": { + "tx": [ + "tx_buffer_region", + "tx_checksum_seed", + "checksum_byte", + "xor_checksum_chain", + "initial_send_from_buffer_start", + "tx_index_initialized_to_one", + "tx_isr_indexed_send", + "tx_index_increment", + "tx_index_compare_frame_length" + ], + "rx": [ + "rx_rdr_read", + "rx_indexed_store", + "rx_index_increment_store", + "rx_isr_compare_frame_length", + "rx_complete_timer", + "rx_processor_requires_six_bytes", + "rx_copy_capture_to_frame_buffer", + "rx_checksum_seed", + "rx_xor_checksum_validation" + ] + } + }, + "board_profile": { + "board": "sony_rcp_tx7", + "name": "Sony RCP-TX7", + "summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.", + "manual_references": [ + "Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD", + "Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD", + "Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals", + "Manual/0900766b802125d0.md:11201 P96 is RXD1 input", + "Manual/0900766b802125d0.md:11202 P95 is TXD1 output", + "Manual/0900766b802125d0.md:15725 SCI1 RXD input pin", + "Manual/0900766b802125d0.md:15726 SCI1 TXD output pin", + "Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15794 RDR receive data register", + "Manual/0900766b802125d0.md:15823 TDR transmit data register", + "Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions", + "Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output", + "Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input", + "Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags", + "Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions", + "Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94" + ], + "traces": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "channels": { + "SCI1": { + "traced_to_max202": true, + "path": "RS232/MAX202", + "pins": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + }, + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ] + }, + "SCI2": { + "traced_to_max202": false, + "path": null, + "note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.", + "p9sci2e": false, + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ] + } + }, + "instructions": { + "4148": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "4245": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4250": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "4255": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4260": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4265": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4270": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "17258": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "17274": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "17278": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "47720": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47730": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47739": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47743": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47774": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47797": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47803": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47818": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47963": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47967": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47971": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47977": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47981": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + }, + "state": { + "SYSCR2": { + "value": 180, + "value_hex": "H'B4" + }, + "P9SCI2E": false + } + }, + "peripheral_access": { + "manual_references": [ + "Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access", + "Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte", + "Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP", + "Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP", + "Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte" + ], + "warnings": [] + }, + "indirect_flow": { + "sites": [ + { + "address": 7192, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "unknown", + "summary": "JSR @R0 uses R0; target not resolved" + }, + { + "address": 10403, + "instruction": "JMP @R1", + "kind": "jump", + "target_register": "R1", + "confidence": "table_load", + "table": { + "base": 10406, + "index_register": "R4", + "target_register": "R1", + "load_address": 10399, + "load_instruction": "MOV:G.W @(H'28A6,R4), R1", + "entry_size": 2, + "entry_count": 128, + "decoded_target_count": 103, + "entries": [ + { + "index": 0, + "entry_address": 10406, + "target": 11449, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 10408, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 2, + "entry_address": 10410, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 3, + "entry_address": 10412, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 4, + "entry_address": 10414, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 5, + "entry_address": 10416, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 6, + "entry_address": 10418, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 7, + "entry_address": 10420, + "target": 11715, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 10422, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 9, + "entry_address": 10424, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 10, + "entry_address": 10426, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 11, + "entry_address": 10428, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 12, + "entry_address": 10430, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 13, + "entry_address": 10432, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 14, + "entry_address": 10434, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 15, + "entry_address": 10436, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 16, + "entry_address": 10438, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 17, + "entry_address": 10440, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 18, + "entry_address": 10442, + "target": 11779, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 10444, + "target": 11782, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 10446, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 21, + "entry_address": 10448, + "target": 11833, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 10450, + "target": 11866, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 10452, + "target": 11909, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 10454, + "target": 11887, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 10456, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 10458, + "target": 11972, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 10460, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 28, + "entry_address": 10462, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 29, + "entry_address": 10464, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 30, + "entry_address": 10466, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 31, + "entry_address": 10468, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 32, + "entry_address": 10470, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 33, + "entry_address": 10472, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 34, + "entry_address": 10474, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 35, + "entry_address": 10476, + "target": 12006, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 10478, + "target": 12044, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 10480, + "target": 12060, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 10482, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 39, + "entry_address": 10484, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 40, + "entry_address": 10486, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 41, + "entry_address": 10488, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 42, + "entry_address": 10490, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 43, + "entry_address": 10492, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 44, + "entry_address": 10494, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 45, + "entry_address": 10496, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 46, + "entry_address": 10498, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 47, + "entry_address": 10500, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 48, + "entry_address": 10502, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 49, + "entry_address": 10504, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 50, + "entry_address": 10506, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 51, + "entry_address": 10508, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 52, + "entry_address": 10510, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 53, + "entry_address": 10512, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 54, + "entry_address": 10514, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 55, + "entry_address": 10516, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 56, + "entry_address": 10518, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 57, + "entry_address": 10520, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 58, + "entry_address": 10522, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 59, + "entry_address": 10524, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 60, + "entry_address": 10526, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 61, + "entry_address": 10528, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 62, + "entry_address": 10530, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 63, + "entry_address": 10532, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 64, + "entry_address": 10534, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 65, + "entry_address": 10536, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 66, + "entry_address": 10538, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 67, + "entry_address": 10540, + "target": 12106, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 68, + "entry_address": 10542, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 69, + "entry_address": 10544, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 70, + "entry_address": 10546, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 71, + "entry_address": 10548, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 72, + "entry_address": 10550, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 73, + "entry_address": 10552, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 74, + "entry_address": 10554, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 75, + "entry_address": 10556, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 76, + "entry_address": 10558, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 77, + "entry_address": 10560, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 78, + "entry_address": 10562, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 79, + "entry_address": 10564, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 80, + "entry_address": 10566, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 81, + "entry_address": 10568, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 82, + "entry_address": 10570, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 83, + "entry_address": 10572, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 84, + "entry_address": 10574, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 85, + "entry_address": 10576, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 86, + "entry_address": 10578, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 87, + "entry_address": 10580, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 88, + "entry_address": 10582, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 89, + "entry_address": 10584, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 90, + "entry_address": 10586, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 91, + "entry_address": 10588, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 92, + "entry_address": 10590, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 93, + "entry_address": 10592, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 94, + "entry_address": 10594, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 95, + "entry_address": 10596, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 96, + "entry_address": 10598, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 97, + "entry_address": 10600, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 98, + "entry_address": 10602, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 99, + "entry_address": 10604, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 100, + "entry_address": 10606, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 101, + "entry_address": 10608, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 102, + "entry_address": 10610, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 103, + "entry_address": 10612, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 104, + "entry_address": 10614, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 105, + "entry_address": 10616, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 106, + "entry_address": 10618, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 107, + "entry_address": 10620, + "target": 12146, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 108, + "entry_address": 10622, + "target": 12207, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 109, + "entry_address": 10624, + "target": 12309, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 110, + "entry_address": 10626, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 8, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 3, + "entry_address": 18756, + "target": 25292, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 4, + "entry_address": 18758, + "target": 25268, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 5, + "entry_address": 18760, + "target": 25248, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 6, + "entry_address": 18762, + "target": 25224, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 7, + "entry_address": 18764, + "target": 25205, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 18766, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 9, + "entry_address": 18768, + "target": 33086, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 10, + "entry_address": 18770, + "target": 33062, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 11, + "entry_address": 18772, + "target": 33042, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 12, + "entry_address": 18774, + "target": 33022, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (8/52 decoded targets)" + }, + { + "address": 28736, + "instruction": "PJMP @R7", + "kind": "jump", + "target_register": "R7", + "confidence": "unknown", + "summary": "PJMP @R7 uses R7; target not resolved" + }, + { + "address": 37654, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37704, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37734, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37768, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37790, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37814, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37834, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + { + "address": 37856, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + } + ] + }, + "dataflow": { + "blocks": [ + { + "start": 4096, + "instructions": [ + 4096, + 4099, + 4103, + 4108, + 4113, + 4118, + 4123, + 4128, + 4133, + 4138, + 4143, + 4148, + 4153, + 4158, + 4163, + 4168, + 4174, + 4179, + 4184, + 4189, + 4195, + 4200, + 4205, + 4210, + 4215, + 4220, + 4225, + 4230, + 4235, + 4240, + 4245, + 4250, + 4255, + 4260, + 4265, + 4270, + 4275, + 4280, + 4285, + 4290, + 4295, + 4299 + ], + "end": 4299, + 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"address": 63112, + "instruction_address": 14683, + "instruction": "BCLR.B R0, @H'F688", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F688", + "operand_index": 1 + } + ] + }, + { + "address": 63113, + "name": "ram_F689", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5603, + "last_access": 15876, + "accesses": [ + { + "address": 63113, + "instruction_address": 5603, + "instruction": "BCLR.B #7, @H'F689", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F689", + "operand_index": 1 + }, + { + "address": 63113, + "instruction_address": 15876, + "instruction": "BSET.B #7, @H'F689", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F689", + "operand_index": 1 + } + ] + }, + { + "address": 63114, + "name": "ram_F68A", + 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"operand_index": 1 + } + ] + }, + { + "address": 63193, + "name": "ram_F6D9", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15636, + "last_access": 15646, + "accesses": [ + { + "address": 63193, + "instruction_address": 15636, + "instruction": "CMP:G.B @H'F6D9, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6D9", + "operand_index": 0 + }, + { + "address": 63193, + "instruction_address": 15646, + "instruction": "MOV:G.B R0, @H'F6D9", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6D9", + "operand_index": 1 + } + ] + }, + { + "address": 63194, + "name": "ram_F6DA", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15654, + "last_access": 15664, + "accesses": [ + { + "address": 63194, + "instruction_address": 15654, + "instruction": "CMP:G.B @H'F6DA, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DA", + "operand_index": 0 + }, + { + "address": 63194, + "instruction_address": 15664, + "instruction": "MOV:G.B R0, @H'F6DA", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6DA", + "operand_index": 1 + } + ] + }, + { + "address": 63195, + "name": "ram_F6DB", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7160, + "last_access": 15682, + "accesses": [ + { + "address": 63195, + "instruction_address": 7160, + "instruction": "MOV:G.B @H'F6DB, R4", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DB", + "operand_index": 0 + }, + { + "address": 63195, + "instruction_address": 7173, + "instruction": "MOV:G.B @H'F6DB, R4", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DB", + "operand_index": 0 + }, + { + "address": 63195, + "instruction_address": 15672, + "instruction": "CMP:G.B @H'F6DB, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DB", + "operand_index": 0 + }, + { + "address": 63195, + "instruction_address": 15682, + "instruction": "MOV:G.B R0, @H'F6DB", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6DB", + "operand_index": 1 + } + ] + }, + { + "address": 63196, + "name": "ram_F6DC", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7138, + "last_access": 15700, + "accesses": [ + { + "address": 63196, + "instruction_address": 7138, + "instruction": "MOV:G.B @H'F6DC, R4", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DC", + "operand_index": 0 + }, + { + "address": 63196, + "instruction_address": 7151, + "instruction": "MOV:G.B @H'F6DC, R4", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DC", + "operand_index": 0 + }, + { + "address": 63196, + "instruction_address": 15690, + "instruction": "CMP:G.B @H'F6DC, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DC", + "operand_index": 0 + }, + { + "address": 63196, + "instruction_address": 15700, + "instruction": "MOV:G.B R0, @H'F6DC", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6DC", + "operand_index": 1 + } + ] + }, + { + "address": 63197, + "name": "ram_F6DD", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15708, + "last_access": 15718, + "accesses": [ + { + "address": 63197, + "instruction_address": 15708, + "instruction": "CMP:G.B @H'F6DD, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DD", + "operand_index": 0 + }, + { + "address": 63197, + "instruction_address": 15718, + "instruction": "MOV:G.B R0, @H'F6DD", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6DD", + "operand_index": 1 + } + ] + }, + { + "address": 63198, + "name": "ram_F6DE", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15726, + "last_access": 15736, + "accesses": [ + { + "address": 63198, + "instruction_address": 15726, + "instruction": "CMP:G.B @H'F6DE, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DE", + 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"name": "ram_F6E0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7053, + "last_access": 7067, + "accesses": [ + { + "address": 63200, + "instruction_address": 7053, + "instruction": "XOR.B @H'F6E0, R4", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6E0", + "operand_index": 0 + }, + { + "address": 63200, + "instruction_address": 7067, + "instruction": "MOV:G.B R4, @H'F6E0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6E0", + "operand_index": 1 + } + ] + }, + { + "address": 63201, + "name": "ram_F6E1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7030, + "last_access": 7044, + "accesses": [ + { + "address": 63201, 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"mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6E2", + "operand_index": 1 + } + ] + }, + { + "address": 63203, + "name": "ram_F6E3", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7098, + "last_access": 7111, + "accesses": [ + { + "address": 63203, + "instruction_address": 7098, + "instruction": "XOR.B @H'F6E3, R4", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6E3", + "operand_index": 0 + }, + { + "address": 63203, + "instruction_address": 7111, + "instruction": "MOV:G.B R4, @H'F6E3", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6E3", + "operand_index": 1 + } + ] + }, + { + "address": 63204, + "name": "ram_F6E4", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + 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"address": 63207, + "name": "ram_F6E7", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 6961, + "last_access": 6975, + "accesses": [ + { + "address": 63207, + "instruction_address": 6961, + "instruction": "XOR.B @H'F6E7, R4", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6E7", + "operand_index": 0 + }, + { + "address": 63207, + "instruction_address": 6975, + "instruction": "MOV:G.B R4, @H'F6E7", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6E7", + "operand_index": 1 + } + ] + }, + { + "address": 63211, + "name": "ram_F6EB", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7164, + "last_access": 7177, + "accesses": [ + { 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"instruction": "BCLR.B #1, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5689, + "instruction": "BCLR.B #0, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15072, + "instruction": "MOV:G.B @H'F6F0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 0 + }, + { + "address": 63216, + "instruction_address": 15079, + "instruction": "MOV:G.B R0, @H'F6F0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15093, + "instruction": "BSET.B #5, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + 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"BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15202, + "instruction": "MOV:G.B @H'F6F0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 0 + }, + { + "address": 63216, + "instruction_address": 15209, + "instruction": "MOV:G.B R0, @H'F6F0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15227, + "instruction": "BSET.B #7, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15245, + "instruction": "BSET.B #6, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + } + ] + }, + { + "address": 63217, + "name": "ram_F6F1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 21, + "read_count": 19, + "write_count": 18, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5693, + "last_access": 15606, + "accesses": [ + { + "address": 63217, + "instruction_address": 5693, + "instruction": "TST.B @H'F6F1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 0 + }, + { + "address": 63217, + "instruction_address": 5699, + "instruction": "BCLR.B #7, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5708, + "instruction": "BCLR.B #6, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5717, + "instruction": "BCLR.B #5, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5726, + "instruction": "BCLR.B #4, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5735, + "instruction": "BCLR.B #3, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5744, + "instruction": "BCLR.B #2, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5753, + "instruction": "BCLR.B #1, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5762, + "instruction": "BCLR.B #0, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15433, + "instruction": "MOV:G.B @H'F6F1, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 0 + }, + { + "address": 63217, + "instruction_address": 15440, + "instruction": "MOV:G.B R0, @H'F6F1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15454, + "instruction": "BSET.B #5, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15472, + "instruction": "BSET.B #4, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15490, + "instruction": "BSET.B #3, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15508, + "instruction": "BSET.B #2, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15526, + "instruction": "BSET.B #1, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15544, + "instruction": "BSET.B #0, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15563, + "instruction": "MOV:G.B @H'F6F1, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 0 + }, + { + "address": 63217, + "instruction_address": 15570, + "instruction": "MOV:G.B R0, @H'F6F1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15588, + "instruction": "BSET.B #7, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15606, + "instruction": "BSET.B #6, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + } + ] + }, + { + "address": 63218, + "name": "ram_F6F2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 18, + "read_count": 17, + "write_count": 17, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5766, + "last_access": 15389, + "accesses": [ + { + "address": 63218, + "instruction_address": 5766, + "instruction": "TST.B @H'F6F2", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 0 + }, + { + "address": 63218, + "instruction_address": 5772, + "instruction": "BCLR.B #7, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5781, + "instruction": "BCLR.B #6, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5790, + "instruction": "BCLR.B #5, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5799, + "instruction": "BCLR.B #4, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5808, + "instruction": "BCLR.B #3, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5817, + "instruction": "BCLR.B #2, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5826, + "instruction": "BCLR.B #1, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5835, + "instruction": "BCLR.B #0, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15213, + "instruction": "CLR.B @H'F6F2", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 0 + }, + { + "address": 63218, + "instruction_address": 15263, + "instruction": "BSET.B #0, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15281, + "instruction": "BSET.B #1, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15299, + "instruction": "BSET.B #2, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15317, + "instruction": "BSET.B #3, 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] + }, + { + "address": 63219, + "name": "ram_F6F3", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 18, + "read_count": 17, + "write_count": 17, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5844, + "last_access": 15750, + "accesses": [ + { + "address": 63219, + "instruction_address": 5844, + "instruction": "TST.B @H'F6F3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 0 + }, + { + "address": 63219, + "instruction_address": 5850, + "instruction": "BCLR.B #7, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5854, + "instruction": "BCLR.B #6, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5858, + "instruction": "BCLR.B #5, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5862, + "instruction": "BCLR.B #4, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5871, + "instruction": "BCLR.B #3, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5880, + "instruction": "BCLR.B #2, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5884, + "instruction": "BCLR.B #1, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5888, + "instruction": "BCLR.B #0, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15574, + "instruction": "CLR.B @H'F6F3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 0 + }, + { + "address": 63219, + "instruction_address": 15624, + "instruction": "BSET.B #0, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15642, + "instruction": "BSET.B #1, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15660, + "instruction": "BSET.B #2, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15678, + "instruction": "BSET.B #3, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15696, + "instruction": "BSET.B #4, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15714, + "instruction": "BSET.B #5, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15732, + "instruction": "BSET.B #6, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 15750, + "instruction": "BSET.B #7, @H'F6F3", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + } + ] + }, + { + "address": 63220, + "name": "ram_F6F4", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 2, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 9905, + "last_access": 48926, + "accesses": [ + { + "address": 63220, + "instruction_address": 9905, + "instruction": "MOV:G.W #H'07D0, @H'F6F4", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F6F4", + "operand_index": 1 + }, + { + "address": 63220, + "instruction_address": 9913, + "instruction": "MOV:G.W #H'00C8, @H'F6F4", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F6F4", + "operand_index": 1 + }, + { + "address": 63220, + "instruction_address": 48914, + "instruction": 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"operand_index": 0 + } + ] + }, + { + "address": 63278, + "name": "ram_F72E", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 23298, + "last_access": 24605, + "accesses": [ + { + "address": 63278, + "instruction_address": 23298, + "instruction": "MOV:G.B @H'F72E, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + }, + { + "address": 63278, + "instruction_address": 24544, + "instruction": "CLR.B @H'F72E", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + }, + { + "address": 63278, + "instruction_address": 24598, + "instruction": "ADD:Q.B #1, @H'F72E", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 1 + }, + { + "address": 63278, + "instruction_address": 24605, + "instruction": "MOV:G.B @H'F72E, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + } + ] + }, + { + "address": 63279, + "name": "ram_F72F", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 24534, + "last_access": 24649, + "accesses": [ + { + "address": 63279, + "instruction_address": 24534, + "instruction": "CMP:G.B @H'F72F, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72F", + "operand_index": 0 + }, + { + "address": 63279, + "instruction_address": 24548, + "instruction": "MOV:G.B R0, @H'F72F", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F72F", + "operand_index": 1 + }, + { + "address": 63279, + "instruction_address": 24649, + "instruction": "CLR.B @H'F72F", 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"instruction_address": 48565, + "instruction": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 49071, + "instruction": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 49087, + "instruction": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + } + ], + "xref_count": 1, + "xrefs": [ + { + "source": "pointer_table", + "address": 7856, + "target": 63281 + } + ] + }, + { + "address": 63282, + "name": "ram_F732", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 12, + "read_count": 7, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 5918, + "last_access": 24530, + "accesses": [ + { + "address": 63282, + "instruction_address": 5918, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 5926, + "instruction": "MOV:G.W #H'1C07, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 5990, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 5998, + "instruction": "MOV:G.W #H'1C06, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 8493, + "instruction": "MOV:G.W @H'F732, R1", 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@H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 6860, + "instruction": "MOV:G.B R0, @H'F733", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 6870, + "instruction": "ADD:Q.B #1, @H'F733", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 6876, + "instruction": "ADD:Q.B #-1, @H'F733", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 23325, + "instruction": "MOV:G.B @H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 23356, + "instruction": "MOV:G.B @H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 24611, + "instruction": "CMP:G.B #H'FF, @H'F733", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 24618, + "instruction": "CMP:G.B @H'F733, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 24628, + "instruction": "MOV:G.B R0, @H'F733", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 24634, + "instruction": "CLR.B @H'F733", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 24658, + "instruction": "MOV:G.B @H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + } + ] + }, + { + "address": 63284, + "name": "ram_F734", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 5922, + "last_access": 18671, + "accesses": [ + { + "address": 63284, + "instruction_address": 5922, + "instruction": "MOV:G.W R1, @H'F734", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F734", + "operand_index": 1 + }, + { + "address": 63284, + "instruction_address": 5994, + "instruction": "MOV:G.W R1, @H'F734", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F734", + "operand_index": 1 + }, + { + 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"mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F852", + "operand_index": 1 + }, + { + "address": 63570, + "instruction_address": 48657, + "instruction": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F852", + "operand_index": 1 + }, + { + "address": 63570, + "instruction_address": 48734, + "instruction": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F852", + "operand_index": 1 + } + ] + }, + { + "address": 63571, + "name": "ram_F853", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 0, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47935, + "last_access": 48374, + "accesses": [ + { + "address": 63571, + "instruction_address": 47935, + "instruction": "MOV:G.B R4, @H'F853", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": 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1 + }, + { + "address": 63572, + "instruction_address": 48329, + "instruction": "MOV:G.B R0, @H'F854", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F854", + "operand_index": 1 + }, + { + "address": 63572, + "instruction_address": 48368, + "instruction": "MOV:G.B R0, @H'F854", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F854", + "operand_index": 1 + }, + { + "address": 63572, + "instruction_address": 48665, + "instruction": "MOV:G.W R0, @H'F854", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F854", + "operand_index": 1 + }, + { + "address": 63572, + "instruction_address": 48742, + "instruction": "MOV:G.B R0, @H'F854", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F854", + "operand_index": 1 + } + ] + }, + { + "address": 63576, + "name": "ram_F858", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, 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"operand_index": 0 + } + ] + }, + { + "address": 63577, + "name": "ram_F859", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47700, + "last_access": 47700, + "accesses": [ + { + "address": 63577, + "instruction_address": 47700, + "instruction": "XOR.B @H'F859, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F859", + "operand_index": 0 + } + ] + }, + { + "address": 63578, + "name": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47682, + "last_access": 48653, + "accesses": [ + { + "address": 63578, + "instruction_address": 47682, + "instruction": "MOV:G.W R0, @H'F85A", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": 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"address": 63580, + "name": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47690, + "last_access": 48661, + "accesses": [ + { + "address": 63580, + "instruction_address": 47690, + "instruction": "MOV:G.B R0, @H'F85C", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F85C", + "operand_index": 1 + }, + { + "address": 63580, + "instruction_address": 47712, + "instruction": "XOR.B @H'F85C, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F85C", + "operand_index": 0 + }, + { + "address": 63580, + "instruction_address": 48661, + "instruction": "MOV:G.W @H'F85C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F85C", + "operand_index": 0 + } + ] + }, + { + "address": 63581, + "name": "ram_F85D", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 0, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47716, + "last_access": 47716, + "accesses": [ + { + "address": 63581, + "instruction_address": 47716, + "instruction": "MOV:G.B R0, @H'F85D", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F85D", + "operand_index": 1 + } + ] + }, + { + "address": 63584, + "name": "ram_F860", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48055, + "last_access": 48136, + "accesses": [ + { + "address": 63584, + "instruction_address": 48055, + "instruction": "MOV:G.W R0, @H'F860", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F860", + "operand_index": 1 + }, + { + "address": 63584, + "instruction_address": 48088, + "instruction": "XOR.B @H'F860, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F860", + "operand_index": 0 + }, + { + "address": 63584, + "instruction_address": 48136, + "instruction": "MOV:G.B @H'F860, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F860", + "operand_index": 0 + } + ] + }, + { + "address": 63585, + "name": "ram_F861", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 7, + "read_count": 7, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48092, + "last_access": 48722, + "accesses": [ + { + "address": 63585, + "instruction_address": 48092, + "instruction": "XOR.B @H'F861, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + }, + { + "address": 63585, + "instruction_address": 48119, + "instruction": "MOV:G.B @H'F861, R5", + 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"instruction_address": 48722, + "instruction": "MOV:G.B @H'F861, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + } + ] + }, + { + "address": 63586, + "name": "ram_F862", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 5, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48063, + "last_access": 48730, + "accesses": [ + { + "address": 63586, + "instruction_address": 48063, + "instruction": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F862", + "operand_index": 1 + }, + { + "address": 63586, + "instruction_address": 48096, + "instruction": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48125, + "instruction": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48317, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48356, + "instruction": "MOV:G.B @H'F862, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48730, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + } + ] + }, + { + "address": 63587, + "name": "ram_F863", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 6, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48100, + "last_access": 48603, + "accesses": [ + { + "address": 63587, + "instruction_address": 48100, + "instruction": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48237, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48267, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48402, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48427, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48603, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + } + ] + }, + { + "address": 63588, + "name": "ram_F864", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 8, + "read_count": 6, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48071, + "last_access": 48738, + "accesses": [ + { + "address": 63588, + "instruction_address": 48071, + "instruction": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48104, + "instruction": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48253, + "instruction": "MOV:G.B #H'80, @H'F864", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48273, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48325, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48433, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48609, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48738, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + } + ] + }, + { + "address": 63589, + "name": "ram_F865", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48108, + "last_access": 48108, + "accesses": [ + { + "address": 63589, + "instruction_address": 48108, + "instruction": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F865", + "operand_index": 0 + } + ] + }, + { + "address": 63592, + "name": "ram_F868", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48051, + "last_access": 48051, + "accesses": [ + { + "address": 63592, + "instruction_address": 48051, + "instruction": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F868", + "operand_index": 0 + } + ] + }, + { + "address": 63594, + "name": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48059, + "last_access": 48059, + "accesses": [ + { + "address": 63594, + "instruction_address": 48059, + "instruction": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86A", + "operand_index": 0 + } + ] + }, + { + "address": 63596, + "name": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48067, + "last_access": 48067, + "accesses": [ + { + "address": 63596, + "instruction_address": 48067, + "instruction": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86C", + "operand_index": 0 + } + ] + }, + { + "address": 63920, + "name": "ram_F9B0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 9, + "read_count": 8, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15968, + "last_access": 47864, + "accesses": [ + { + "address": 63920, + "instruction_address": 15968, + "instruction": "MOV:G.B @H'F9B0, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 15994, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 15998, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16002, + "instruction": "MOV:G.B @H'F9B0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16377, + "instruction": "CLR.B @H'F9B0", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16473, + "instruction": "MOV:G.B @H'F9B0, R2", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16492, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16496, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 47864, + "instruction": "CMP:G.B @H'F9B0, R1", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + } + ] + }, + { + "address": 63924, + "name": "ram_F9B4", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 7, + "read_count": 7, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10252, + "last_access": 48793, + "accesses": [ + { + "address": 63924, + "instruction_address": 10252, + "instruction": "CMP:G.B @H'F9B4, R1", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 16038, + "instruction": "MOV:G.B @H'F9B4, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 16067, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 16071, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48760, + "instruction": "MOV:G.B @H'F9B4, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 48789, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48793, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + } + ] + }, + { + "address": 63925, + "name": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 10, + "write_count": 7, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15960, + "last_access": 48631, + "accesses": [ + { + "address": 63925, + "instruction_address": 15960, + "instruction": "MOV:G.B @H'F9B5, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16011, + "instruction": "CMP:G.B @H'F9B5, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16373, + "instruction": "CLR.B @H'F9B5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16479, + "instruction": "CMP:G.B @H'F9B5, R2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 47858, + "instruction": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 48493, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48497, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48584, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48588, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48627, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48631, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + } + ] + }, + { + "address": 63929, + "name": "ram_F9B9", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10246, + "last_access": 48752, + "accesses": [ + { + "address": 63929, + "instruction_address": 10246, + "instruction": "MOV:G.B @H'F9B9, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 10274, + "instruction": "MOV:G.B R1, @H'F9B9", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 1 + }, + { + "address": 63929, + "instruction_address": 16030, + "instruction": "MOV:G.B @H'F9B9, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 48752, + "instruction": "MOV:G.B @H'F9B9, R3", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + } + ] + }, + { + "address": 63936, + "name": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 4, + "write_count": 8, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16357, + "last_access": 48884, + "accesses": [ + { + "address": 63936, + "instruction_address": 16357, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47654, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47660, + "instruction": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47778, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47834, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47841, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47848, + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48669, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48702, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48878, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 48884, + "instruction": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + } + ] + }, + { + "address": 63937, + "name": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47853, + "last_access": 48894, + "accesses": [ + { + "address": 63937, + "instruction_address": 47853, + "instruction": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 47985, + "instruction": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 48035, + "instruction": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 1 + }, + { + "address": 63937, + "instruction_address": 48888, + "instruction": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 48894, + "instruction": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 1 + } + ] + }, + { + "address": 63938, + "name": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47734, + "last_access": 47811, + "accesses": [ + { + "address": 63938, + "instruction_address": 47734, + "instruction": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47787, + "instruction": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 0 + }, + { + "address": 63938, + "instruction_address": 47807, + "instruction": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47811, + "instruction": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + } + ] + }, + { + "address": 63939, + "name": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 10, + "read_count": 6, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16351, + "last_access": 48849, + "accesses": [ + { + "address": 63939, + "instruction_address": 16351, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 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"access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16454, + "last_access": 48941, + "accesses": [ + { + "address": 63940, + "instruction_address": 16454, + "instruction": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 0 + }, + { + "address": 63940, + "instruction_address": 16608, + "instruction": "MOV:G.B #H'14, @H'F9C4", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + }, + { + "address": 63940, + "instruction_address": 47665, + "instruction": "MOV:G.B #H'07, @H'F9C4", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + }, + { + "address": 63940, + "instruction_address": 48935, + "instruction": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 0 + }, + { + "address": 63940, + "instruction_address": 48941, + "instruction": "ADD:Q.B #-1, @H'F9C4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + } + ] + }, + { + "address": 63941, + "name": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16367, + "last_access": 48951, + "accesses": [ + { + "address": 63941, + "instruction_address": 16367, + "instruction": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48030, + "instruction": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 1 + }, + { + "address": 63941, + "instruction_address": 48868, + "instruction": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48945, + "instruction": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48951, + "instruction": "ADD:Q.B #-1, @H'F9C5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 1 + } + ] + }, + { + "address": 63942, + "name": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 47942, + "last_access": 48904, + "accesses": [ + { + "address": 63942, + "instruction_address": 47942, + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 1 + }, + { + "address": 63942, + "instruction_address": 48821, + "instruction": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "direction": "read", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 0 + }, + { + "address": 63942, + "instruction_address": 48837, + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 1 + }, + { + "address": 63942, + "instruction_address": 48898, + "instruction": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "direction": "read", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 0 + }, + { + "address": 63942, + "instruction_address": 48904, + "instruction": "ADD:Q.W #-1, @H'F9C6", + "mnemonic": "ADD:Q.W", + "direction": "read_write", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 1 + } + ] + }, + { + "address": 63944, + "name": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47948, + "last_access": 48833, + "accesses": [ + { + "address": 63944, + "instruction_address": 47948, + "instruction": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 1 + }, + { + "address": 63944, + "instruction_address": 48827, + "instruction": "TST.B @H'F9C8", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 0 + }, + { + "address": 63944, + "instruction_address": 48833, + "instruction": "ADD:Q.B #-1, @H'F9C8", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 1 + } + ] + }, + { + "address": 63995, + "name": "ram_F9FB", + "region": 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"instruction_address": 48501, + "instruction": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'FAA3", + "operand_index": 0 + }, + { + "address": 64163, + "instruction_address": 48592, + "instruction": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'FAA3", + "operand_index": 0 + }, + { + "address": 64163, + "instruction_address": 48635, + "instruction": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'FAA3", + "operand_index": 0 + }, + { + "address": 64163, + "instruction_address": 48707, + "instruction": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'FAA3", + "operand_index": 0 + }, + { + "address": 64163, + "instruction_address": 48805, + "instruction": "AND.B @H'FAA3, R0", + "mnemonic": "AND.B", + "direction": "read", + "width": "byte", + "operand": "@H'FAA3", + "operand_index": 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"start": 39307, + "end": 39579, + "count": 6, + "samples": [ + "AUTO SKIN X", + "START:PUSH AGAINX", + "GATE SIZE X", + "AUTO SKIN X", + "ON WINDOW OFF~X", + "H-POSI V-POSIX" + ] + }, + { + "start": 39719, + "end": 39918, + "count": 4, + "samples": [ + "AUTO SKIN X", + "ON WINDOW OFF~X", + "WIDTH HEIGHTX", + "AUTO SKIN" + ] + }, + { + "start": 40313, + "end": 40490, + "count": 4, + "samples": [ + "WHITE SHADING", + "AUTO SET", + "BLACK SHADING", + "AUTO SET" + ] + }, + { + "start": 40856, + "end": 41011, + "count": 4, + "samples": [ + "COPY", + "IN PROGRESS", + "COPY", + "COMPLETED" + ] + }, + { + "start": 41372, + "end": 41561, + "count": 5, + "samples": [ + "WHITE", + "AUTO", + "OK", + "OK:UNDER1700K", + "OK:OVER10000K" + ] + }, + { + "start": 41949, + "end": 41995, + "count": 2, + "samples": [ + "OPERATION", + "PRESET" + ] + }, + { + "start": 42178, + "end": 42278, + "count": 3, + "samples": [ + "BLACK", + "AUTO", + "OK" + ] + }, + { + "start": 42701, + "end": 42740, + "count": 2, + "samples": [ + "FLARE", + "RED GREEN BLUE" + ] + }, + { + "start": 43169, + "end": 43228, + "count": 2, + "samples": [ + "DETAIL X", + "FREQ H/V X" + ] + }, + { + "start": 43433, + "end": 43830, + "count": 8, + "samples": [ + "DETAIL X", + "ON OFF~X", + "DETAIL X", + "LEV V-DTLX", + "CRISP DEP LIMITX", + "DETAIL X", + "HIGH AFTERX", + "LIGHT GAMMAX" + ] + }, + { + "start": 43968, + "end": 44443, + "count": 11, + "samples": [ + "DETAIL X", + "APERTURE X", + "LEVEL X", + "ON OFF~X", + "DETAIL X", + "KNEE APERTURE X", + "LEVEL X", + "ON OFF~X" + ] + }, + { + "start": 44574, + "end": 44862, + "count": 7, + "samples": [ + "DETAIL X", + "ON RED OFF~X", + "COMB FILTER X", + "ON GRN OFF~X", + "GAMMA X", + "ON OFF~X", + "RED MAST BLUE X" + ] + }, + { + "start": 44997, + "end": 45107, + "count": 3, + "samples": [ + "GAMMA X", + "GAMMA INIT GAIN X", + "4.0 X" + ] + }, + { + "start": 45249, + "end": 46224, + "count": 16, + "samples": [ + "KNEE X", + "PRESET X", + "MANUAL KNEE X", + "VARIABLE X", + "KNEE X", + "POINT SLOPEX", + "PRESET X", + "AUTO X" + ] + }, + { + "start": 46391, + "end": 46474, + "count": 3, + "samples": [ + "RECALL X", + "SCENE F. RECALL~X", + "SEL X" + ] + }, + { + "start": 46632, + "end": 46715, + "count": 3, + "samples": [ + "RECALL X", + "SETUP F. RECALL~X", + "SEL X" + ] + }, + { + "start": 46875, + "end": 46958, + "count": 3, + "samples": [ + "STORE X", + "SCENE F. STORE~X", + "CUR SEL CHR X" + ] + }, + { + "start": 47139, + "end": 47221, + "count": 3, + "samples": [ + "STORE X", + "SETUP F. STORE~X", + "CUR SEL CHR X" + ] + }, + { + "start": 52953, + "end": 52966, + "count": 2, + "samples": [ + "1234", + "8965.,-(" + ] + } + ], + "searches": [ + { + "term": "CONNECT", + "literal_hits": [], + "candidate_hits": [], + "near_matches": [ + { + "address": 40997, + "text": " COMPLETED ", + "trimmed": "COMPLETED", + "score": 0.5 + }, + { + "address": 36473, + "text": "ON CONT1 OFF~X", + "trimmed": "ON CONT1 OFF~X", + "score": 0.444 + }, + { + "address": 36693, + "text": "ON CONT2 OFF~X", + "trimmed": "ON CONT2 OFF~X", + "score": 0.444 + }, + { + "address": 38057, + "text": " ON ", + "trimmed": "ON", + "score": 0.444 + }, + { + "address": 38707, + "text": " ON ", + "trimmed": "ON", + "score": 0.444 + }, + { + "address": 40342, + "text": " AUTO SET ", + "trimmed": "AUTO SET", + "score": 0.429 + }, + { + "address": 40476, + "text": " AUTO SET ", + "trimmed": "AUTO SET", + "score": 0.429 + }, + { + "address": 46908, + "text": " SCENE F. STORE~X", + "trimmed": "SCENE F. STORE~X", + "score": 0.421 + }, + { + "address": 29733, + "text": " OTHERS Xt%", + "trimmed": "OTHERS Xt%", + "score": 0.4 + }, + { + "address": 29796, + "text": " SAFETY ZONE Xtd", + "trimmed": "SAFETY ZONE Xtd", + "score": 0.4 + }, + { + "address": 46424, + "text": "SCENE F. RECALL~X", + "trimmed": "SCENE F. RECALL~X", + "score": 0.4 + }, + { + "address": 26243, + "text": "POINT1 POINT2Xf", + "trimmed": "POINT1 POINT2Xf", + "score": 0.381 + } + ], + "status": "not_found" + } + ], + "notes": [ + "LCD text scan is byte-oriented and conservative; strings may be inline script fields.", + "Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes." + ] + }, + "lcd_driver": { + "addresses": [ + { + "address": 61952, + "name": "lcd_status_control", + "role": "status/control register inferred from busy polling and command writes" + }, + { + "address": 61953, + "name": "lcd_data", + "role": "data register inferred from paired data reads/writes" + } + ], + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "polling_loops": [ + { + "read_address": 16202, + "test_address": 16207, + "branch_address": 16209, + "register": "R0", + "bit": 7, + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear" + } + ], + "routines": [ + { + "start": 16192, + "end": 16244, + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "roles": [ + "lcd_command_or_address_write", + "lcd_data_read", + "lcd_data_write", + "lcd_status_read" + ], + "role_hint": "lcd_wait_and_transfer" + } + ], + "instructions": { + "16202": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16219": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ], + "16226": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ], + "16237": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "16207": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16209": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + } + }, + "instructions": [ + { + "address": 4096, + "address_region": "program_or_external", + "bytes": "5FFE80", + "text": "MOV:I.W #H'FE80, R7", + "mnemonic": "MOV:I.W", + "operands": "#H'FE80, R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R7 = 0xFE80" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + } + } + } + }, + { + "address": 4099, + "address_region": "program_or_external", + "bytes": "0C070088", + "text": "LDC.W #H'0700, SR", + "mnemonic": "LDC.W", + "operands": "#H'0700, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + ], + "notes": [ + "SR = 0x0700" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4103, + "address_region": "program_or_external", + "bytes": "15FE8006FF", + "text": "MOV:G.B #H'FF, @P1DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @P1DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65152, + "name": "P1DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DDR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4108, + "address_region": "program_or_external", + "bytes": "15FE820600", + "text": "MOV:G.B #H'00, @P1DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4113, + "address_region": "program_or_external", + "bytes": "15FE8906F9", + "text": "MOV:G.B #H'F9, @P6DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'F9, @P6DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65161, + "name": "P6DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DDR = H'F9", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4118, + "address_region": "program_or_external", + "bytes": "15FE8B06F1", + "text": "MOV:G.B #H'F1, @P6DR", + "mnemonic": "MOV:G.B", + "operands": "#H'F1, @P6DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65163, + "name": "P6DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DR = H'F1", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4123, + "address_region": "program_or_external", + "bytes": "15FE8C0600", + "text": "MOV:G.B #H'00, @P7DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65164, + "name": "P7DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DDR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4128, + "address_region": "program_or_external", + "bytes": "15FE8E0600", + "text": "MOV:G.B #H'00, @P7DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4133, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'93", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4138, + "address_region": "program_or_external", + "bytes": "15FEFF0600", + "text": "MOV:G.B #H'00, @P9DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4143, + "address_region": "program_or_external", + "bytes": "15FEFC0687", + "text": "MOV:G.B #H'87, @SYSCR1", + "mnemonic": "MOV:G.B", + "operands": "#H'87, @SYSCR1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65276, + "name": "SYSCR1", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4148, + "address_region": "program_or_external", + "bytes": "15FEFD0684", + "text": "MOV:G.B #H'84, @SYSCR2", + "mnemonic": "MOV:G.B", + "operands": "#H'84, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM)", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4153, + "address_region": "program_or_external", + "bytes": "15FE900602", + "text": "MOV:G.B #H'02, @FRT1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4158, + "address_region": "program_or_external", + "bytes": "15FE910601", + "text": "MOV:G.B #H'01, @FRT1_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4163, + "address_region": "program_or_external", + "bytes": "1DFE920600", + "text": "MOV:G.W #H'00, @FRT1_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT1_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65170, + "name": "FRT1_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4163, + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "register": "FRT1_FRC", + "high_address": 65170, + "low_address": 65171, + "referenced_address": 65170, + "referenced_address_hex": "H'FE92", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4168, + "address_region": "program_or_external", + "bytes": "1DFE9407009C", + "text": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'009C, @FRT1_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65172, + "name": "FRT1_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_OCRA_H = H'9C", + "valid": true, + "peripheral_access": [ + { + "address": 4168, + "instruction": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "register": "FRT1_OCRA", + "high_address": 65172, + "low_address": 65173, + "referenced_address": 65172, + "referenced_address_hex": "H'FE94", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4174, + "address_region": "program_or_external", + "bytes": "15FEA00602", + "text": "MOV:G.B #H'02, @FRT2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4179, + "address_region": "program_or_external", + "bytes": "15FEA10601", + "text": "MOV:G.B #H'01, @FRT2_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT2_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65185, + "name": "FRT2_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4184, + "address_region": "program_or_external", + "bytes": "1DFEA20600", + "text": "MOV:G.W #H'00, @FRT2_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT2_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65186, + "name": "FRT2_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4184, + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "register": "FRT2_FRC", + "high_address": 65186, + "low_address": 65187, + "referenced_address": 65186, + "referenced_address_hex": "H'FEA2", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4189, + "address_region": "program_or_external", + "bytes": "1DFEA4077A12", + "text": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'7A12, @FRT2_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65188, + "name": "FRT2_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_OCRA_H = H'7A12", + "valid": true, + "peripheral_access": [ + { + "address": 4189, + "instruction": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "register": "FRT2_OCRA", + "high_address": 65188, + "low_address": 65189, + "referenced_address": 65188, + "referenced_address_hex": "H'FEA4", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4195, + "address_region": "program_or_external", + "bytes": "15FEB00600", + "text": "MOV:G.B #H'00, @FRT3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65200, + "name": "FRT3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4200, + "address_region": "program_or_external", + "bytes": "15FEB10600", + "text": "MOV:G.B #H'00, @FRT3_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65201, + "name": "FRT3_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4205, + "address_region": "program_or_external", + "bytes": "15FED00600", + "text": "MOV:G.B #H'00, @TMR_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @TMR_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65232, + "name": "TMR_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4210, + "address_region": "program_or_external", + "bytes": "15FED10610", + "text": "MOV:G.B #H'10, @TMR_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'10, @TMR_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65233, + "name": "TMR_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4215, + "address_region": "program_or_external", + "bytes": "15FEC00638", + "text": "MOV:G.B #H'38, @PWM1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65216, + "name": "PWM1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4220, + "address_region": "program_or_external", + "bytes": "15FEC106FF", + "text": "MOV:G.B #H'FF, @PWM1_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM1_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65217, + "name": "PWM1_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4225, + "address_region": "program_or_external", + "bytes": "15FEC40638", + "text": "MOV:G.B #H'38, @PWM2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65220, + "name": "PWM2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4230, + "address_region": "program_or_external", + "bytes": "15FEC506FF", + "text": "MOV:G.B #H'FF, @PWM2_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM2_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65221, + "name": "PWM2_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4235, + "address_region": "program_or_external", + "bytes": "15FEC8063B", + "text": "MOV:G.B #H'3B, @PWM3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3B, @PWM3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65224, + "name": "PWM3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4240, + "address_region": "program_or_external", + "bytes": "15FEC9067D", + "text": "MOV:G.B #H'7D, @PWM3_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'7D, @PWM3_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65225, + "name": "PWM3_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_DTR = H'7D", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4245, + "address_region": "program_or_external", + "bytes": "15FED80624", + "text": "MOV:G.B #H'24, @SCI1_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI1_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65240, + "name": "SCI1_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4250, + "address_region": "program_or_external", + "bytes": "15FEDA063C", + "text": "MOV:G.B #H'3C, @SCI1_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3C, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + } + ] + }, + "sci_protocol": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4255, + "address_region": "program_or_external", + "bytes": "15FED90607", + "text": "MOV:G.B #H'07, @SCI1_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI1_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65241, + "name": "SCI1_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4260, + "address_region": "program_or_external", + "bytes": "15FEF00624", + "text": "MOV:G.B #H'24, @SCI2_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI2_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65264, + "name": "SCI2_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4265, + "address_region": "program_or_external", + "bytes": "15FEF2060C", + "text": "MOV:G.B #H'0C, @SCI2_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'0C, @SCI2_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65266, + "name": "SCI2_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + } + ] + }, + "sci_protocol": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4270, + "address_region": "program_or_external", + "bytes": "15FEF10607", + "text": "MOV:G.B #H'07, @SCI2_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI2_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65265, + "name": "SCI2_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4275, + "address_region": "program_or_external", + "bytes": "15FEE80619", + "text": "MOV:G.B #H'19, @ADCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'19, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4280, + "address_region": "program_or_external", + "bytes": "15FEE9067F", + "text": "MOV:G.B #H'7F, @H'FEE9", + "mnemonic": "MOV:G.B", + "operands": "#H'7F, @H'FEE9", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65257, + "name": null, + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4285, + "address_region": "program_or_external", + "bytes": "15FF1006F0", + "text": "MOV:G.B #H'F0, @WCR", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @WCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65296, + "name": "WCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4290, + "address_region": "program_or_external", + "bytes": "15FF1106FF", + "text": "MOV:G.B #H'FF, @RAMCR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @RAMCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65297, + "name": "RAMCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "RAMCR = H'FF (RAME=1; on-chip RAM enabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4295, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4299, + "address_region": "program_or_external", + "bytes": "302EA8", + "text": "BRA loc_3F76", + "mnemonic": "BRA", + "operands": "loc_3F76", + "kind": "jump", + "targets": [ + 16246 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4302, + "address_region": "program_or_external", + "bytes": "5C0040", + "text": "MOV:I.W #H'0040, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0040, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, 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"reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 4311, + "address_region": "program_or_external", + "bytes": "5C0200", + "text": "MOV:I.W #H'0200, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0200, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": 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"changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 4320, + "address_region": "program_or_external", + "bytes": "5C0200", + "text": "MOV:I.W #H'0200, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0200, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0200" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + } + } + } + } + }, + { + "address": 4323, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 4326, + "address_region": "program_or_external", + "bytes": "1E2DE3", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } 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"address": 6615, + "address_region": "program_or_external", + "bytes": "ACA8", + "text": "MULXU.W R4, R0", + "mnemonic": "MULXU.W", + "operands": "R4, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 25, + "base_cycles": 25, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6615, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:MULXU.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 6617, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA 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"cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6627, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 6633, + "address_region": "program_or_external", + "bytes": "A982", + "text": "MOV:G.W R1, R2", + "mnemonic": "MOV:G.W", + "operands": "R1, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6627, + "changes": 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"assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6642, + "address_region": "program_or_external", + "bytes": "230F", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6644, + "address_region": "program_or_external", + "bytes": "590000", + "text": "MOV:I.W #H'0000, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + 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"targets": [ + 6780 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6763, + "changes": [], + "notes": [] + } + }, + { + "address": 6769, + "address_region": "program_or_external", + "bytes": "FBE80090", + "text": "MOV:G.W R0, @(-H'1800,R3)", + "mnemonic": "MOV:G.W", + "operands": "R0, @(-H'1800,R3)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6769, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": 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"address_region": "program_or_external", + "bytes": "01B9F9", + "text": "SCB/F R1, loc_1A90", + "mnemonic": "SCB/F", + "operands": "R1, loc_1A90", + "kind": "branch", + "targets": [ + 6800 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6804, + "changes": [], + "notes": [] + } + }, + { + "address": 6807, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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"address_region": "program_or_external", + "bytes": "240A", + "text": "BCC loc_2683", + "mnemonic": "BCC", + "operands": "loc_2683", + "kind": "branch", + "targets": [ + 9859 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 9845, + "changes": [], + "notes": [] + } + }, + { + "address": 9849, + "address_region": "program_or_external", + "bytes": "5049", + "text": "MOV:E.B #H'49, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'49, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + 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"notes": [] + } + }, + { + "address": 9855, + "address_region": "program_or_external", + "bytes": "2402", + "text": "BCC loc_2683", + "mnemonic": "BCC", + "operands": "loc_2683", + "kind": "branch", + "targets": [ + 9859 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 9853, + "changes": [], + "notes": [] + } + }, + { + "address": 9857, + "address_region": "program_or_external", + "bytes": "5016", + "text": "MOV:E.B #H'16, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'16, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": 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"decoded_code": true + }, + { + "index": 74, + "entry_address": 10554, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 75, + "entry_address": 10556, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 76, + "entry_address": 10558, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 77, + "entry_address": 10560, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 78, + "entry_address": 10562, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 79, + "entry_address": 10564, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 80, + "entry_address": 10566, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 81, + "entry_address": 10568, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 82, + "entry_address": 10570, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 83, + "entry_address": 10572, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 84, + "entry_address": 10574, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 85, + "entry_address": 10576, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 86, + "entry_address": 10578, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 87, + "entry_address": 10580, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 88, + "entry_address": 10582, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 89, + "entry_address": 10584, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 90, + "entry_address": 10586, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 91, + "entry_address": 10588, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 92, + "entry_address": 10590, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 93, + "entry_address": 10592, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 94, + "entry_address": 10594, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 95, + "entry_address": 10596, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 96, + "entry_address": 10598, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 97, + "entry_address": 10600, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 98, + "entry_address": 10602, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 99, + "entry_address": 10604, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 100, + "entry_address": 10606, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 101, + "entry_address": 10608, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 102, + "entry_address": 10610, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 103, + "entry_address": 10612, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 104, + "entry_address": 10614, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 105, + "entry_address": 10616, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 106, + "entry_address": 10618, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 107, + "entry_address": 10620, + "target": 12146, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 108, + "entry_address": 10622, + "target": 12207, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 109, + "entry_address": 10624, + "target": 12309, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 110, + "entry_address": 10626, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + "dataflow": { + "block": 10399, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + } + ], + "notes": [ + "indirect jump ends known register state" + ] + } + }, + { + "address": 11430, + "address_region": "program_or_external", + "bytes": "15F769D7", + "text": "BCLR.B #7, @H'F769", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11434, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [], + "notes": [] + } + }, + { + "address": 11435, + "address_region": "program_or_external", + "bytes": "1231", + "text": "STM.W {R0,R4,R5}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R4,R5}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 15, + "note": "6+3n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 11437, + "address_region": "program_or_external", + "bytes": "1E1C4A", + "text": "BSR loc_48FA", + "mnemonic": "BSR", + "operands": "loc_48FA", + "kind": "call", + "targets": [ + 18682 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 11440, + "address_region": "program_or_external", + "bytes": "0231", + "text": "LDM.W @SP+, {R0,R4,R5}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R4,R5}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 18, + "note": "6+4n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R4, R5" + ] + } + }, + { + "address": 11442, + "address_region": "program_or_external", + "bytes": "15F769C7", + "text": "BSET.B #7, @H'F769", + "mnemonic": "BSET.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11446, + "address_region": "program_or_external", + "bytes": "30FBE6", + "text": "BRA loc_289F", + "mnemonic": "BRA", + "operands": "loc_289F", + "kind": "jump", + "targets": [ + 10399 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 14640, + "address_region": "program_or_external", + "bytes": "580007", + "text": "MOV:I.W #H'0007, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14640, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x0007" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + } + } + } + }, + { + "address": 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"changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after memory load" + ] + } + }, + { + "address": 16136, + "address_region": "program_or_external", + "bytes": "D372", + "text": "CMP:G.B @R3, R2", + "mnemonic": "CMP:G.B", + "operands": "@R3, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16138, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_3F10", + "mnemonic": "BEQ", + "operands": "loc_3F10", + "kind": "branch", + "targets": [ + 16144 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16140, + "address_region": "program_or_external", + "bytes": "D392", + "text": "MOV:G.B R2, @R3", + "mnemonic": "MOV:G.B", + "operands": "R2, @R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + 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"bytes": "1DFB0094", + "text": "MOV:G.W R4, @H'FB00", + "mnemonic": "MOV:G.W", + "operands": "R4, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16178, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16182, + "address_region": "program_or_external", + "bytes": "0E08", + "text": "BSR loc_3F40", + "mnemonic": "BSR", + "operands": "loc_3F40", + "kind": "call", + "targets": [ + 16192 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16178, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16184, + "address_region": "program_or_external", + "bytes": "5C0200", + "text": "MOV:I.W #H'0200, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0200, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16184, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0200" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": "MOV:I.W #H'0200, R4" + } + } + } + } + }, + { + "address": 16187, + "address_region": "program_or_external", + "bytes": "A224", + "text": "ADD:G.B R2, R4", + "mnemonic": "ADD:G.B", + "operands": "R2, R4", + "kind": "normal", + "targets": [], + "cycles": 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"kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16191, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16184, + "changes": [], + "notes": [] + } + }, + { + "address": 16192, + "address_region": "program_or_external", + "bytes": "BF98", + "text": "STC.W SR, @-R7", + "mnemonic": "STC.W", + "operands": "SR, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 7, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + } + ], + "notes": [] + } + }, + { + "address": 16194, + "address_region": "program_or_external", + "bytes": "0C00FF58", + "text": "ANDC.W #H'00FF, SR", + "mnemonic": "ANDC.W", + "operands": "#H'00FF, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "SR unknown after ANDC" + ] + } + }, + { + "address": 16198, + "address_region": "program_or_external", + "bytes": "0C060048", + "text": "ORC.W #H'0600, SR", + "mnemonic": "ORC.W", + "operands": "#H'0600, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [], + "notes": [ + "SR unknown after ORC" + ] + } + }, + { + "address": 16202, + "address_region": "program_or_external", + "bytes": "15F2000080", + "text": "MOVFPE.B @H'F200, R0", + "mnemonic": "MOVFPE.B", + "operands": "@H'F200, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16207, + "address_region": "program_or_external", + "bytes": "A0F7", + "text": "BTST.B #7, R0", + "mnemonic": "BTST.B", + "operands": "#7, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16209, + "address_region": "program_or_external", + "bytes": "26F7", + "text": "BNE loc_3F4A", + "mnemonic": "BNE", + "operands": "loc_3F4A", + "kind": "branch", + "targets": [ + 16202 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16211, + "address_region": "program_or_external", + "bytes": "ACF8", + "text": "BTST.W #8, R4", + "mnemonic": "BTST.W", + "operands": "#8, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16213, + "address_region": "program_or_external", + "bytes": "2616", + "text": "BNE loc_3F6D", + "mnemonic": "BNE", + "operands": "loc_3F6D", + "kind": "branch", + "targets": [ + 16237 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [], + "notes": [] + } + }, + { + "address": 16215, + "address_region": "program_or_external", + "bytes": "ACF9", + "text": "BTST.W #9, R4", + "mnemonic": "BTST.W", + "operands": "#9, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16217, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_3F62", + "mnemonic": "BNE", + "operands": "loc_3F62", + "kind": "branch", + "targets": [ + 16226 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [], + "notes": [] + } + }, + { + "address": 16219, + "address_region": "program_or_external", + "bytes": "15F2000094", + "text": "MOVTPE.B R4, @H'F200", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F200", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ] + }, + { + "address": 16224, + "address_region": "program_or_external", + "bytes": "2010", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [], + "notes": [] + } + }, + { + "address": 16226, + "address_region": "program_or_external", + "bytes": "15F2010094", + "text": "MOVTPE.B R4, @H'F201", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F201", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ] + }, + { + "address": 16231, + "address_region": "program_or_external", + "bytes": "1DFB0008", + "text": "ADD:Q.W #1, @H'FB00", + "mnemonic": "ADD:Q.W", + "operands": "#1, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16235, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16237, + "address_region": "program_or_external", + "bytes": "15F2010084", + "text": "MOVFPE.B @H'F201, R4", + "mnemonic": "MOVFPE.B", + "operands": "@H'F201, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16237, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ] + }, + { + "address": 16242, + "address_region": "program_or_external", + "bytes": "CF88", + "text": "LDC.W @R7+, SR", + "mnemonic": "LDC.W", + "operands": "@R7+, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "SR unknown after memory load" + ] + } + }, + { + "address": 16244, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [], + "notes": [] + } + }, + { + "address": 16246, + "address_region": "program_or_external", + "bytes": "582710", + "text": "MOV:I.W #H'2710, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'2710, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x2710" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + } + } + } + }, + { + "address": 16249, + "address_region": "program_or_external", + "bytes": "59C350", + "text": "MOV:I.W #H'C350, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'C350, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + ], + "notes": [ + "R1 = 0xC350" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + }, + "R1": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + } + } + }, + { + "address": 16252, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": 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@P1DR", + "mnemonic": "BSET.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16263, + "address_region": "program_or_external", + "bytes": "01B9F9", + "text": "SCB/F R1, loc_3F83", + "mnemonic": "SCB/F", + "operands": "R1, loc_3F83", + "kind": "branch", + "targets": [ + 16259 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [], + "notes": [] + } + }, + { + "address": 16266, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16266, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 cleared" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + } + } + } + }, + { + "address": 16268, + "address_region": "program_or_external", + "bytes": "F8E00013", + "text": "CLR.W @(-H'2000,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'2000,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16272, + "address_region": "program_or_external", + "bytes": "F8E80013", + "text": "CLR.W @(-H'1800,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'1800,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16276, + "address_region": "program_or_external", + "bytes": "F8F68013", + "text": "CLR.W @(-H'0980,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16280, + "address_region": "program_or_external", + "bytes": "A809", + "text": "ADD:Q.W #2, R0", + "mnemonic": "ADD:Q.W", + "operands": "#2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R0 unknown after arithmetic" + ] + } + }, + { + "address": 16282, + "address_region": "program_or_external", + "bytes": "480800", + "text": "CMP:I #H'0800, R0", + "mnemonic": "CMP:I", + "operands": "#H'0800, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16285, + "address_region": "program_or_external", + "bytes": "26ED", + "text": "BNE loc_3F8C", + "mnemonic": "BNE", + "operands": "loc_3F8C", + "kind": "branch", + "targets": [ + 16268 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16287, + "address_region": "program_or_external", + "bytes": "1E036A", + "text": "BSR loc_430C", + "mnemonic": "BSR", + "operands": "loc_430C", + "kind": "call", + "targets": [ + 17164 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16290, + "address_region": "program_or_external", + "bytes": "1E037F", + "text": "BSR loc_4324", + "mnemonic": "BSR", + "operands": "loc_4324", + "kind": "call", + "targets": [ + 17188 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16293, + "address_region": "program_or_external", + "bytes": "1E00EE", + "text": "BSR loc_4096", + "mnemonic": "BSR", + "operands": "loc_4096", + "kind": "call", + "targets": [ + 16534 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16296, + "address_region": "program_or_external", + "bytes": "1E0110", + "text": "BSR loc_40BB", + "mnemonic": "BSR", + "operands": "loc_40BB", + "kind": "call", + "targets": [ + 16571 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16299, + "address_region": "program_or_external", + "bytes": "1E0269", + "text": "BSR loc_4217", + "mnemonic": "BSR", + "operands": "loc_4217", + "kind": "call", + "targets": [ + 16919 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16302, + "address_region": "program_or_external", + "bytes": "1E039B", + "text": "BSR loc_434C", + "mnemonic": "BSR", + "operands": "loc_434C", + "kind": "call", + "targets": [ + 17228 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"1EF962", + "text": "BSR loc_3930", + "mnemonic": "BSR", + "operands": "loc_3930", + "kind": "call", + "targets": [ + 14640 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16305, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16334, + "address_region": "program_or_external", + "bytes": "1ED60F", + "text": "BSR loc_15E0", + "mnemonic": "BSR", + "operands": "loc_15E0", + "kind": "call", + "targets": [ + 5600 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand 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"address": 16349, + "address_region": "program_or_external", + "bytes": "2706", + "text": "BEQ loc_3FE5", + "mnemonic": "BEQ", + "operands": "loc_3FE5", + "kind": "branch", + "targets": [ + 16357 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16345, + "changes": [], + "notes": [] + } + }, + { + "address": 16351, + "address_region": "program_or_external", + "bytes": "15F9C316", + "text": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 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"program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16357, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16361, + "address_region": "program_or_external", + "bytes": "2603", + "text": "BNE loc_3FEE", + "mnemonic": "BNE", + "operands": "loc_3FEE", + "kind": "branch", + "targets": [ + 16366 + ], + "cycles": { + "not_taken": 3, + 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"cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17221, + "address_region": "program_or_external", + "bytes": "1EFB84", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17224, + "address_region": "program_or_external", + "bytes": "1ECD83", + "text": "BSR loc_10CE", + "mnemonic": "BSR", + "operands": "loc_10CE", + "kind": "call", + "targets": [ + 4302 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17227, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [] + } + }, + { + "address": 17228, + "address_region": "program_or_external", + "bytes": "15FF000670", + "text": "MOV:G.B #H'70, @IPRA", + "mnemonic": "MOV:G.B", + "operands": "#H'70, @IPRA", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65280, + "name": "IPRA", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRA = H'70 (irq0 priority=7; irq1 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17233, + "address_region": "program_or_external", + "bytes": "15FF010644", + "text": "MOV:G.B #H'44, @IPRB", + "mnemonic": "MOV:G.B", + "operands": "#H'44, @IPRB", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65281, + "name": "IPRB", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17238, + "address_region": "program_or_external", + "bytes": "15FF020666", + "text": "MOV:G.B #H'66, @IPRC", + "mnemonic": "MOV:G.B", + "operands": "#H'66, @IPRC", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65282, + "name": "IPRC", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRC = H'66 (FRT1 priority=6; FRT2 priority=6)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17243, + "address_region": "program_or_external", + "bytes": "15FF030600", + "text": "MOV:G.B #H'00, @IPRD", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @IPRD", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65283, + "name": "IPRD", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17248, + "address_region": "program_or_external", + "bytes": "15FF040650", + "text": "MOV:G.B #H'50, @IPRE", + "mnemonic": "MOV:G.B", + "operands": "#H'50, @IPRE", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65284, + "name": "IPRE", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRE = H'50 (SCI1 priority=5; SCI2 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17253, + "address_region": "program_or_external", + "bytes": "15FF050640", + "text": "MOV:G.B #H'40, @IPRF", + "mnemonic": "MOV:G.B", + "operands": "#H'40, @IPRF", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65285, + "name": "IPRF", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRF = H'40 (A/D priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17258, + "address_region": "program_or_external", + "bytes": "15FEDAC6", + "text": "BSET.B #6, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#6, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set RIE (bit 6) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17262, + "address_region": "program_or_external", + "bytes": "15FE90C5", + "text": "BSET.B #5, @FRT1_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT1_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17266, + "address_region": "program_or_external", + "bytes": "15FEA0C5", + "text": "BSET.B #5, @FRT2_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT2_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17270, + "address_region": "program_or_external", + "bytes": "15FEE8C6", + "text": "BSET.B #6, @ADCSR", + "mnemonic": "BSET.B", + "operands": "#6, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set ADIE (bit 6) of ADCSR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17274, + "address_region": "program_or_external", + "bytes": "15FEFDC4", + "text": "BSET.B #4, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#4, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ3E (bit 4) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17278, + "address_region": "program_or_external", + "bytes": "15FEFDC5", + "text": "BSET.B #5, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#5, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ4E (bit 5) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17282, + "address_region": "program_or_external", + "bytes": "15FE8EF6", + "text": "BTST.B #6, @P7DR", + "mnemonic": "BTST.B", + "operands": "#6, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17286, + "address_region": "program_or_external", + "bytes": "2706", + "text": "BEQ loc_438E", + "mnemonic": "BEQ", + "operands": "loc_438E", + "kind": "branch", + "targets": [ + 17294 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17288, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 17288, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17294, + "address_region": "program_or_external", + "bytes": "0C030088", + "text": "LDC.W #H'0300, SR", + "mnemonic": "LDC.W", + "operands": "#H'0300, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + ], + "notes": [ + "SR = 0x0300" + ], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17298, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [], + "notes": [], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17299, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17299, + "changes": [], + "notes": [] + } + }, + { + "address": 17300, + "address_region": "program_or_external", + "bytes": "15F7310401", + "text": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "operands": "#H'01, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17305, + "address_region": "program_or_external", + "bytes": "320086", + "text": "BHI loc_4422", + "mnemonic": "BHI", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + 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"changes": [], + "notes": [] + } + }, + { + "address": 17529, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17531, + "address_region": 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"program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17724, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17726, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_4561", + "mnemonic": "BNE", + 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"base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17740, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17742, + "address_region": "program_or_external", + "bytes": "2643", + "text": "BNE loc_4593", + "mnemonic": "BNE", + "operands": "loc_4593", + "kind": "branch", + "targets": [ + 17811 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + 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"target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (8/52 decoded targets)" + }, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 18749, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18749, + "changes": [], + "notes": [] + } + }, + { + "address": 21760, + "address_region": "program_or_external", + "bytes": "15F795F7", + "text": "BTST.B #7, @H'F795", + "mnemonic": "BTST.B", + "operands": "#7, @H'F795", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63381, + "name": null, + "symbol": "ram_F795", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 21760, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 21764, + "address_region": "program_or_external", + "bytes": "3600A6", + "text": "BNE loc_55AD", + "mnemonic": "BNE", + "operands": "loc_55AD", + "kind": "branch", + "targets": [ + 21933 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21760, + "changes": [], + "notes": [] + } + }, + { + "address": 21767, + "address_region": "program_or_external", + "bytes": "15F76E82", + "text": "MOV:G.B @H'F76E, R2", + "mnemonic": "MOV:G.B", + "operands": "@H'F76E, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63342, + "name": null, + "symbol": "ram_F76E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after memory load" + ] + } + }, + { + "address": 21771, + "address_region": "program_or_external", + "bytes": "0C000F52", + "text": "AND.W #H'000F, R2", + "mnemonic": "AND.W", + "operands": "#H'000F, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:AND.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R2" + ] + } + }, + { + "address": 21775, + "address_region": "program_or_external", + "bytes": "AA83", + "text": "MOV:G.W R2, R3", + "mnemonic": "MOV:G.W", + "operands": "R2, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R3 unknown after MOV source" + ] + } + }, + { + "address": 21777, + "address_region": "program_or_external", + "bytes": "A31A", + "text": "SHLL.B R3", + "mnemonic": "SHLL.B", + "operands": "R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 21779, + "address_region": "program_or_external", + "bytes": "A31A", + "text": "SHLL.B R3", + "mnemonic": "SHLL.B", + "operands": "R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 21781, + "address_region": "program_or_external", + "bytes": "A31A", + "text": "SHLL.B R3", + "mnemonic": "SHLL.B", + "operands": "R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 21783, + "address_region": "program_or_external", + "bytes": "AC13", + "text": "CLR.W R4", + "mnemonic": "CLR.W", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R4" + } + } + ], + "notes": [ + "R4 cleared" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R4" + } + } + } + } + }, + { + "address": 21785, + "address_region": "program_or_external", + "bytes": "15F75E84", + "text": "MOV:G.B @H'F75E, R4", + "mnemonic": "MOV:G.B", + "operands": "@H'F75E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63326, + "name": null, + "symbol": "ram_F75E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R4" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 21789, + "address_region": "program_or_external", + "bytes": "F4CE7C85", + "text": "MOV:G.B @(-H'3184,R4), R5", + "mnemonic": "MOV:G.B", + "operands": "@(-H'3184,R4), R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 21793, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 21795, + "address_region": "program_or_external", + "bytes": "15F75F84", + "text": "MOV:G.B @H'F75F, R4", + "mnemonic": "MOV:G.B", + "operands": "@H'F75F, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63327, + "name": null, + "symbol": "ram_F75F", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 21799, + "address_region": "program_or_external", + "bytes": "F4CE7C85", + "text": "MOV:G.B @(-H'3184,R4), R5", + "mnemonic": "MOV:G.B", + "operands": "@(-H'3184,R4), R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 21803, + "address_region": "program_or_external", + "bytes": "FBF7B095", + "text": "MOV:G.W R5, @(-H'0850,R3)", + "mnemonic": "MOV:G.W", + "operands": "R5, @(-H'0850,R3)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [], + "notes": [] + } + }, + { + "address": 21807, + "address_region": "program_or_external", + "bytes": "AA84", + "text": "MOV:G.W R2, R4", + "mnemonic": "MOV:G.W", + "operands": "R2, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R4 unknown after MOV source" + ] + } + }, + { + "address": 21809, + "address_region": "program_or_external", + "bytes": "A410", + "text": "SWAP.B R4", + "mnemonic": "SWAP.B", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 21811, + "address_region": "program_or_external", + "bytes": "123C", + "text": "STM.W {R2,R3,R4,R5}, @-SP", + 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"known_after": { + "registers": { + "R5": { + "known": true, + "value": 3, + "hex": "0x0003", + "width": 16, + "source": "MOV:I.W #H'0003, R5" + } + } + } + } + }, + { + "address": 28645, + "address_region": "program_or_external", + "bytes": "1ECEE4", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28636, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 3, + "hex": "0x0003", + "width": 16, + "source": "MOV:I.W #H'0003, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 28648, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28636, + "changes": [], + "notes": [] + } + }, + { + "address": 28672, + "address_region": "program_or_external", + "bytes": "F7", + "text": ".db H'F7", + "mnemonic": ".db", + "operands": "H'F7", + "kind": "invalid", + "targets": [], + "cycles": null, + "references": [], + "comment": "", + "valid": false, + "dataflow": { + "block": 28672, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 28736, + "address_region": "program_or_external", + "bytes": "11C7", + "text": "PJMP @R7", + "mnemonic": "PJMP", + "operands": "@R7", + "kind": "jump", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 28736, + "instruction": "PJMP @R7", + "kind": "jump", + "target_register": "R7", + "confidence": "unknown", + "summary": "PJMP @R7 uses R7; target not resolved" + }, + "dataflow": { + "block": 28736, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + 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"block": 28743, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": 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"program_or_external", + "bytes": "2010", + "text": "BRA loc_70AF", + "mnemonic": "BRA", + "operands": "loc_70AF", + "kind": "jump", + "targets": [ + 28847 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28829, + "changes": [], + "notes": [] + } + }, + { + "address": 28847, + "address_region": "program_or_external", + "bytes": "58709F", + "text": "MOV:I.W #H'709F, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'709F, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28847, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 28831, + "hex": "0x709F", + "width": 16, + "source": "MOV:I.W #H'709F, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x709F" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 28831, + "hex": "0x709F", + "width": 16, + "source": "MOV:I.W #H'709F, R0" + } + } + } + }, + "lcd_text": { + "comment": "LCD text xref H'709F 'OTHERS Xp'" + } + }, + { + "address": 28850, + "address_region": "program_or_external", + "bytes": "1EE9DC", + "text": "BSR loc_5A91", + "mnemonic": "BSR", + "operands": "loc_5A91", + "kind": "call", + "targets": [ + 23185 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC 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"EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 28853, + "address_region": "program_or_external", + "bytes": "1EEA4A", + "text": "BSR loc_5B02", + "mnemonic": "BSR", + "operands": "loc_5B02", + "kind": "call", + "targets": [ + 23298 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28847, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 28856, + "address_region": "program_or_external", + "bytes": "5D0000", + "text": "MOV:I.W #H'0000, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28847, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x0000" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R5" + } + } + } + } + }, + { + "address": 28859, + "address_region": "program_or_external", + "bytes": "1ECE0E", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28847, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 28862, + "address_region": "program_or_external", + "bytes": "2010", + "text": "BRA loc_70D0", + "mnemonic": "BRA", + "operands": "loc_70D0", + "kind": "jump", + "targets": [ + 28880 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 28847, + "changes": [], + "notes": [] + } + }, + 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"source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 37704, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + "dataflow": { + "block": 37697, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 37706, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + 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"0x93E6", + "width": 16, + "source": "MOV:I.W #H'93E6, R3" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 = 0x93E6" + ], + "known_after": { + "registers": { + "R3": { + "known": true, + "value": 37862, + "hex": "0x93E6", + "width": 16, + "source": "MOV:I.W #H'93E6, R3" + } + } + } + } + }, + { + "address": 37847, + "address_region": "program_or_external", + "bytes": "5401", + "text": "MOV:E.B #H'01, R4", + "mnemonic": "MOV:E.B", + "operands": "#H'01, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37844, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x01", + "width": 8, + "source": "MOV:E.B #H'01, R4" + } + } + ], + "notes": [ + "R4 = 0x01" + ], + "known_after": { + "registers": { + "R3": { + "known": true, + "value": 37862, + "hex": "0x93E6", + "width": 16, + "source": "MOV:I.W #H'93E6, R3" + }, + "R4": { + "known": true, + "value": 1, + "hex": "0x01", + "width": 8, + "source": "MOV:E.B #H'01, R4" + } + } + } + } + }, + { + "address": 37849, + "address_region": "program_or_external", + "bytes": "1ECBF6", + "text": "BSR loc_5FD2", + "mnemonic": "BSR", + "operands": "loc_5FD2", + "kind": "call", + "targets": [ + 24530 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37844, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": true, + "value": 37862, + "hex": "0x93E6", + "width": 16, + "source": "MOV:I.W #H'93E6, R3" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 1, + "hex": "0x01", + "width": 8, + "source": "MOV:E.B #H'01, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 37852, + "address_region": "program_or_external", + "bytes": "FC93E684", + "text": "MOV:G.W @(-H'6C1A,R4), R4", + "mnemonic": "MOV:G.W", + "operands": "@(-H'6C1A,R4), R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37844, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + }, + "lcd_text": { + "comment": "LCD text xref H'6C16 'DIAG DATA Xl'" + } + }, + { + "address": 37856, + "address_region": "program_or_external", + "bytes": "11DC", + "text": "JSR @R4", + "mnemonic": "JSR", + "operands": "@R4", + "kind": "call", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 37856, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + "dataflow": { + "block": 37844, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 37858, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37844, + "changes": [], + "notes": [] + } + }, + { + "address": 47654, + "address_region": "program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47654, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47658, + "address_region": "program_or_external", + "bytes": "26FA", + "text": "BNE loc_BA26", + "mnemonic": "BNE", + "operands": "loc_BA26", + "kind": "branch", + "targets": [ + 47654 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47654, + "changes": [], + "notes": [] + } + }, + { + "address": 47660, + "address_region": "program_or_external", + "bytes": "15F9C00664", + "text": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'64, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47665, + "address_region": "program_or_external", + "bytes": "15F9C40607", + "text": "MOV:G.B #H'07, @H'F9C4", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @H'F9C4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63940, + "name": null, + "symbol": "ram_F9C4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47670, + "address_region": "program_or_external", + "bytes": "1DF85080", + "text": "MOV:G.W @H'F850, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F850, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47674, + "address_region": "program_or_external", + "bytes": "1DF85890", + "text": "MOV:G.W R0, @H'F858", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F858", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47674, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47678, + "address_region": "program_or_external", + "bytes": "1DF85280", + "text": "MOV:G.W @H'F852, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F852, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47682, + "address_region": "program_or_external", + "bytes": "1DF85A90", + "text": "MOV:G.W R0, @H'F85A", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F85A", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47682, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47686, + "address_region": "program_or_external", + "bytes": "15F85480", + "text": "MOV:G.B @H'F854, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F854, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47690, + "address_region": "program_or_external", + "bytes": "15F85C90", + "text": "MOV:G.B R0, @H'F85C", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85C", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47690, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47694, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47694, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_checksum_seed", + "evidence_summary": "candidate TX checksum starts from seed H'005A", + "evidence_addresses": [ + 47694 + ], + "evidence_addresses_hex": [ + "H'BA4E" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 47696, + "address_region": "program_or_external", + "bytes": "15F85860", + "text": "XOR.B @H'F858, R0", + "mnemonic": "XOR.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47700, + "address_region": "program_or_external", + "bytes": "15F85960", + "text": "XOR.B @H'F859, R0", + "mnemonic": "XOR.B", + "operands": "@H'F859, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63577, + "name": null, + "symbol": "ram_F859", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47704, + "address_region": "program_or_external", + "bytes": "15F85A60", + "text": "XOR.B @H'F85A, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47708, + "address_region": "program_or_external", + "bytes": "15F85B60", + "text": "XOR.B @H'F85B, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85B, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63579, + "name": null, + "symbol": "ram_F85B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47712, + "address_region": "program_or_external", + "bytes": "15F85C60", + "text": "XOR.B @H'F85C, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47716, + "address_region": "program_or_external", + "bytes": "15F85D90", + "text": "MOV:G.B R0, @H'F85D", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85D", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63581, + "name": null, + "symbol": "ram_F85D", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "checksum_byte", + "evidence_summary": "candidate checksum byte write targets H'F85D", + "evidence_addresses": [ + 47716 + ], + "evidence_addresses_hex": [ + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47720, + "address_region": "program_or_external", + "bytes": "15FEDCF7", + "text": "BTST.B #7, @SCI1_SSR", + "mnemonic": "BTST.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + } + ], + "board_profile": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47720, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47724, + "address_region": "program_or_external", + "bytes": "27FA", + "text": "BEQ loc_BA68", + "mnemonic": "BEQ", + "operands": "loc_BA68", + "kind": "branch", + "targets": [ + 47720 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + } + ], + "dataflow": { + "block": 47720, + "changes": [], + "notes": [] + } + }, + { + "address": 47726, + "address_region": "program_or_external", + "bytes": "15F85880", + "text": "MOV:G.B @H'F858, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47730, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47730, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47734, + "address_region": "program_or_external", + "bytes": "15F9C20601", + "text": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47734, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_initialized_to_one", + "evidence_summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "evidence_addresses": [ + 47734 + ], + "evidence_addresses_hex": [ + "H'BA76" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47739, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47743, + "address_region": "program_or_external", + "bytes": "15FEDAC7", + "text": "BSET.B #7, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + } + ] + }, + "sci_protocol": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47747, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47748, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47752, + "address_region": "program_or_external", + "bytes": "271F", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [], + "notes": [] + } + }, + { + "address": 47754, + "address_region": "program_or_external", + "bytes": "15FAA5F7", + "text": "BTST.B #7, @H'FAA5", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64165, + "name": null, + "symbol": "ram_FAA5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47758, + "address_region": "program_or_external", + "bytes": "2719", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [], + "notes": [] + } + }, + { + "address": 47760, + "address_region": "program_or_external", + "bytes": "15F9C316", + "text": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47764, + "address_region": "program_or_external", + "bytes": "2713", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [], + "notes": [] + } + }, + { + "address": 47766, + "address_region": "program_or_external", + "bytes": "15FAA2D3", + "text": "BCLR.B #3, @H'FAA2", + "mnemonic": "BCLR.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47770, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47774, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47778, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47783, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BAF1", + "mnemonic": "BRA", + "operands": "loc_BAF1", + "kind": "jump", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47785, + "address_region": "program_or_external", + "bytes": "BF90", + "text": "MOV:G.W R0, @-R7", + "mnemonic": "MOV:G.W", + "operands": "R0, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47787, + "address_region": "program_or_external", + "bytes": "15F9C280", + "text": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47787, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47791, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47793, + "address_region": "program_or_external", + "bytes": "F0F85880", + "text": "MOV:G.B @(-H'07A8,R0), R0", + "mnemonic": "MOV:G.B", + "operands": "@(-H'07A8,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47793, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47797, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47797, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47801, + "address_region": "program_or_external", + "bytes": "CF80", + "text": "MOV:G.W @R7+, R0", + "mnemonic": "MOV:G.W", + "operands": "@R7+, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47803, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47807, + "address_region": "program_or_external", + "bytes": "15F9C208", + "text": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47807, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_increment", + "evidence_summary": "candidate TX ISR increments TX index H'F9C2", + "evidence_addresses": [ + 47807 + ], + "evidence_addresses_hex": [ + "H'BABF" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47811, + "address_region": "program_or_external", + "bytes": "15F9C20406", + "text": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47811, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_compare_frame_length", + "evidence_summary": "candidate TX ISR compares TX index to frame length 6", + "evidence_addresses": [ + 47811 + ], + "evidence_addresses_hex": [ + "H'BAC3" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47816, + "address_region": "program_or_external", + "bytes": "2627", + "text": "BNE loc_BAF1", + "mnemonic": "BNE", + "operands": "loc_BAF1", + "kind": "branch", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47818, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47818, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47822, + "address_region": "program_or_external", + "bytes": "15F795F6", + "text": "BTST.B #6, @H'F795", + "mnemonic": "BTST.B", + "operands": "#6, @H'F795", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63381, + "name": null, + "symbol": "ram_F795", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47826, + "address_region": "program_or_external", + "bytes": "2614", + "text": "BNE loc_BAE8", + "mnemonic": "BNE", + "operands": "loc_BAE8", + "kind": "branch", + "targets": [ + 47848 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47828, + "address_region": "program_or_external", + "bytes": "15F791F7", + "text": "BTST.B #7, @H'F791", + "mnemonic": "BTST.B", + "operands": "#7, @H'F791", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63377, + "name": null, + "symbol": "ram_F791", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47832, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_BAE1", + "mnemonic": "BNE", + "operands": "loc_BAE1", + "kind": "branch", + "targets": [ + 47841 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [], + "notes": [] + } + }, + { + "address": 47834, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47839, + "address_region": "program_or_external", + "bytes": "200C", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [], + "notes": [] + } + }, + { + "address": 47841, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47846, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [], + "notes": [] + } + }, + { + "address": 47848, + "address_region": "program_or_external", + "bytes": "15F9C006F0", + "text": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47848, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47853, + "address_region": "program_or_external", + "bytes": "15F9C113", + "text": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47853, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47857, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47857, + "changes": [], + "notes": [] + } + }, + { + "address": 47858, + "address_region": "program_or_external", + "bytes": "15F9B581", + "text": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9B5, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 47862, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47864, + "address_region": "program_or_external", + "bytes": "15F9B071", + "text": "CMP:G.B @H'F9B0, R1", + "mnemonic": "CMP:G.B", + "operands": "@H'F9B0, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63920, + "name": null, + "symbol": "ram_F9B0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [], + "notes": [] + } + }, + { + "address": 47868, + "address_region": "program_or_external", + "bytes": "2602", + "text": "BNE loc_BB00", + "mnemonic": "BNE", + "operands": "loc_BB00", + "kind": "branch", + "targets": [ + 47872 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [], + "notes": [] + } + }, + { + "address": 47870, + "address_region": "program_or_external", + "bytes": "2056", + "text": "BRA loc_BB56", + "mnemonic": "BRA", + "operands": "loc_BB56", + "kind": "jump", + "targets": [ + 47958 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47870, + "changes": [], + "notes": [] + } + }, + { + "address": 47872, + "address_region": "program_or_external", + "bytes": "15FAA2C3", + "text": "BSET.B #3, @H'FAA2", + "mnemonic": "BSET.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47876, + "address_region": "program_or_external", + "bytes": "A980", + "text": "MOV:G.W R1, R0", + "mnemonic": "MOV:G.W", + "operands": "R1, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R0 unknown after MOV source" + ] + } + }, + { + "address": 47878, + "address_region": "program_or_external", + "bytes": "A81A", + "text": "SHLL.W R0", + "mnemonic": "SHLL.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47880, + "address_region": "program_or_external", + "bytes": "F8F87080", + "text": "MOV:G.W @(-H'0790,R0), R0", + "mnemonic": "MOV:G.W", + "operands": "@(-H'0790,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.W" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47884, + "address_region": "program_or_external", + "bytes": "A885", + "text": "MOV:G.W R0, R5", + "mnemonic": "MOV:G.W", + "operands": "R0, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R5 unknown after MOV source" + ] + } + }, + { + "address": 47886, + "address_region": "program_or_external", + "bytes": "1EA6F5", + "text": "BSR loc_6206", + "mnemonic": "BSR", + "operands": "loc_6206", + "kind": "call", + "targets": [ + 25094 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 47889, + "address_region": "program_or_external", + "bytes": "A881", + "text": "MOV:G.W R0, R1", + "mnemonic": "MOV:G.W", + "operands": "R0, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after MOV source" + ] + } + }, + { + "address": 47891, + "address_region": "program_or_external", + "bytes": "A110", + "text": "SWAP.B R1", + "mnemonic": "SWAP.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47893, + "address_region": "program_or_external", + "bytes": "A11B", + "text": "SHLR.B R1", + "mnemonic": "SHLR.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "unsupported:SHLR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47895, + "address_region": "program_or_external", + "bytes": "A182", + "text": "MOV:G.B R1, R2", + "mnemonic": "MOV:G.B", + "operands": "R1, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R2 unknown after MOV source" + ] + } + }, + { + "address": 47897, + "address_region": "program_or_external", + "bytes": "040751", + "text": "AND.B #H'07, R1", + "mnemonic": "AND.B", + "operands": "#H'07, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:SHLR.B" + }, + "after": { + "known": false, + "reason": "unsupported:AND.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47900, + "address_region": "program_or_external", + "bytes": "15F85091", + "text": "MOV:G.B R1, @H'F850", + "mnemonic": "MOV:G.B", + "operands": "R1, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47904, + "address_region": "program_or_external", + "bytes": "15F85295", + "text": "MOV:G.B R5, @H'F852", + "mnemonic": "MOV:G.B", + "operands": "R5, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47908, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 47910, + "address_region": "program_or_external", + "bytes": "047852", + "text": "AND.B #H'78, R2", + "mnemonic": "AND.B", + "operands": "#H'78, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:AND.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R2" + ] + } + }, + { + "address": 47913, + "address_region": "program_or_external", + "bytes": "A245", + "text": "OR.B R2, R5", + "mnemonic": "OR.B", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "unsupported:OR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 47915, + "address_region": "program_or_external", + "bytes": "15F85195", + "text": "MOV:G.B R5, @H'F851", + "mnemonic": "MOV:G.B", + "operands": "R5, @H'F851", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63569, + "name": null, + "symbol": "ram_F851", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47919, + "address_region": "program_or_external", + "bytes": "0C01FF50", + "text": "AND.W #H'01FF, R0", + "mnemonic": "AND.W", + "operands": "#H'01FF, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:AND.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47923, + "address_region": "program_or_external", + "bytes": "A81A", + "text": "SHLL.W R0", + "mnemonic": "SHLL.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:AND.W" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47925, + "address_region": "program_or_external", + "bytes": "F8E80084", + "text": "MOV:G.W @(-H'1800,R0), R4", + "mnemonic": "MOV:G.W", + "operands": "@(-H'1800,R0), R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 47929, + "address_region": "program_or_external", + "bytes": "15F85494", + "text": "MOV:G.B R4, @H'F854", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47933, + "address_region": "program_or_external", + "bytes": "A410", + "text": "SWAP.B R4", + "mnemonic": "SWAP.B", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 47935, + "address_region": "program_or_external", + "bytes": "15F85394", + "text": "MOV:G.B R4, @H'F853", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F853", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63571, + "name": null, + "symbol": "ram_F853", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47939, + "address_region": "program_or_external", + "bytes": "1EFEE0", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.W" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:OR.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 47942, + "address_region": "program_or_external", + "bytes": "1DF9C60701F4", + "text": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "operands": "#H'01F4, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47948, + "address_region": "program_or_external", + "bytes": "15F9C80614", + "text": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47953, + "address_region": "program_or_external", + "bytes": "15FAA30680", + "text": "MOV:G.B #H'80, @H'FAA3", + "mnemonic": "MOV:G.B", + "operands": "#H'80, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47958, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47958, + "changes": [], + "notes": [] + } + }, + { + "address": 47959, + "address_region": "program_or_external", + "bytes": "15FAA4C7", + "text": "BSET.B #7, @H'FAA4", + "mnemonic": "BSET.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47959, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "dataflow": { + "block": 47959, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47963, + "address_region": "program_or_external", + "bytes": "15FEDCD5", + "text": "BCLR.B #5, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#5, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear ORER (bit 5) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + } + ], + "serial_reconstruction": [ + { + "address": 47963, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47967, + "address_region": "program_or_external", + "bytes": "15FEDCD4", + "text": "BCLR.B #4, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#4, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear FER (bit 4) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + } + ], + "serial_reconstruction": [ + { + "address": 47967, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47971, + "address_region": "program_or_external", + "bytes": "15FEDCD3", + "text": "BCLR.B #3, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#3, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear PER (bit 3) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + } + ], + "serial_reconstruction": [ + { + "address": 47971, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47975, + "address_region": "program_or_external", + "bytes": "1203", + "text": "STM.W {R0,R1}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R1}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47977, + "address_region": "program_or_external", + "bytes": "15FEDCD6", + "text": "BCLR.B #6, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#6, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear RDRF (bit 6) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + } + ], + "serial_reconstruction": [ + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47981, + "address_region": "program_or_external", + "bytes": "15FEDD80", + "text": "MOV:G.B @SCI1_RDR, R0", + "mnemonic": "MOV:G.B", + "operands": "@SCI1_RDR, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65245, + "name": "SCI1_RDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdr_read", + "evidence_summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "evidence_addresses": [ + 47981 + ], + "evidence_addresses_hex": [ + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47985, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47989, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BB7D", + "mnemonic": "BNE", + "operands": "loc_BB7D", + "kind": "branch", + "targets": [ + 47997 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47991, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47995, + "address_region": "program_or_external", + "bytes": "200D", + "text": "BRA loc_BB8A", + "mnemonic": "BRA", + "operands": "loc_BB8A", + "kind": "jump", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [], + "notes": [] + } + }, + { + "address": 47997, + "address_region": "program_or_external", + "bytes": "15F9C30405", + "text": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'05, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48002, + "address_region": "program_or_external", + "bytes": "2306", + "text": "BLS loc_BB8A", + "mnemonic": "BLS", + "operands": "loc_BB8A", + "kind": "branch", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [], + "notes": [] + } + }, + { + "address": 48004, + "address_region": "program_or_external", + "bytes": "15FAA413", + "text": "CLR.B @H'FAA4", + "mnemonic": "CLR.B", + "operands": "@H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48008, + "address_region": "program_or_external", + "bytes": "2019", + "text": "BRA loc_BBA3", + "mnemonic": "BRA", + "operands": "loc_BBA3", + "kind": "jump", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [], + "notes": [] + } + }, + { + "address": 48010, + "address_region": "program_or_external", + "bytes": "15F9C381", + "text": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C3, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 48014, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 48016, + "address_region": "program_or_external", + "bytes": "F1F86890", + "text": "MOV:G.B R0, @(-H'0798,R1)", + "mnemonic": "MOV:G.B", + "operands": "R0, @(-H'0798,R1)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48016, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_indexed_store", + "evidence_summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "evidence_addresses": [ + 48016 + ], + "evidence_addresses_hex": [ + "H'BB90" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48020, + "address_region": "program_or_external", + "bytes": "A108", + "text": "ADD:Q.B #1, R1", + "mnemonic": "ADD:Q.B", + "operands": "#1, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48020, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 48022, + "address_region": "program_or_external", + "bytes": "15F9C391", + "text": "MOV:G.B R1, @H'F9C3", + "mnemonic": "MOV:G.B", + "operands": "R1, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48022, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48026, + "address_region": "program_or_external", + "bytes": "4106", + "text": "CMP:E #H'06, R1", + "mnemonic": "CMP:E", + "operands": "#H'06, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48026, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_isr_compare_frame_length", + "evidence_summary": "RX ISR compares incremented count to candidate frame length 6", + "evidence_addresses": [ + 48026 + ], + "evidence_addresses_hex": [ + "H'BB9A" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48028, + "address_region": "program_or_external", + "bytes": "2605", + "text": "BNE loc_BBA3", + "mnemonic": "BNE", + "operands": "loc_BBA3", + "kind": "branch", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48030, + "address_region": "program_or_external", + "bytes": "15F9C50614", + "text": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48030, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_complete_timer", + "evidence_summary": "RX ISR sets H'F9C5 after count reaches 6", + "evidence_addresses": [ + 48030 + ], + "evidence_addresses_hex": [ + "H'BB9E" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high" + } + ], + "dataflow": { + "block": 48030, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48035, + "address_region": "program_or_external", + "bytes": "15F9C10605", + "text": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "operands": "#H'05, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48040, + "address_region": "program_or_external", + "bytes": "0203", + "text": "LDM.W @SP+, {R0,R1}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R1}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R1" + ] + } + }, + { + "address": 48042, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [], + "notes": [] + } + }, + { + "address": 48043, + "address_region": "program_or_external", + "bytes": "15F9C30406", + "text": "CMP:G.B #H'06, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48043, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_processor_requires_six_bytes", + "evidence_summary": "RX processing path requires H'F9C3 to equal 6", + "evidence_addresses": [ + 48043 + ], + "evidence_addresses_hex": [ + "H'BBAB" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high" + } + ], + "dataflow": { + "block": 48043, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48048, + "address_region": "program_or_external", + "bytes": "3602BC", + "text": "BNE loc_BE6F", + "mnemonic": "BNE", + "operands": "loc_BE6F", + "kind": "branch", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48043, + "changes": [], + "notes": [] + } + }, + { + "address": 48051, + "address_region": "program_or_external", + "bytes": "1DF86880", + "text": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F868, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63592, + "name": null, + "symbol": "ram_F868", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48051, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48055, + "address_region": "program_or_external", + "bytes": "1DF86090", + "text": "MOV:G.W R0, @H'F860", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F860", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48055, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48059, + "address_region": "program_or_external", + "bytes": "1DF86A80", + "text": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63594, + "name": null, + "symbol": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48059, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48063, + "address_region": "program_or_external", + "bytes": "1DF86290", + "text": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F862", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48063, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48067, + "address_region": "program_or_external", + "bytes": "1DF86C80", + "text": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63596, + "name": null, + "symbol": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48067, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48071, + "address_region": "program_or_external", + "bytes": "1DF86490", + "text": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F864", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48071, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48075, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48079, + "address_region": "program_or_external", + "bytes": "15FAA4F7", + "text": "BTST.B #7, @H'FAA4", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48083, + "address_region": "program_or_external", + "bytes": "360253", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48086, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_checksum_seed", + "evidence_summary": "candidate RX checksum validation starts from seed H'005A", + "evidence_addresses": [ + 48086 + ], + "evidence_addresses_hex": [ + "H'BBD6" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high" + }, + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 48088, + "address_region": "program_or_external", + "bytes": "15F86060", + "text": "XOR.B @H'F860, R0", + "mnemonic": "XOR.B", + "operands": "@H'F860, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48088, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48092, + "address_region": "program_or_external", + "bytes": "15F86160", + "text": "XOR.B @H'F861, R0", + "mnemonic": "XOR.B", + "operands": "@H'F861, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48092, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48096, + "address_region": "program_or_external", + "bytes": "15F86260", + "text": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "operands": "@H'F862, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48096, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48100, + "address_region": "program_or_external", + "bytes": "15F86360", + "text": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "operands": "@H'F863, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63587, + "name": null, + "symbol": "ram_F863", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48100, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48104, + "address_region": "program_or_external", + "bytes": "15F86460", + "text": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "operands": "@H'F864, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48104, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48108, + "address_region": "program_or_external", + "bytes": "15F86570", + "text": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "operands": "@H'F865, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63589, + "name": null, + "symbol": "ram_F865", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48108, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48112, + "address_region": "program_or_external", + "bytes": "360236", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48115, + "address_region": "program_or_external", + "bytes": "15FAA613", + "text": "CLR.B @H'FAA6", + "mnemonic": "CLR.B", + "operands": "@H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48119, + "address_region": "program_or_external", + "bytes": "15F86185", + "text": "MOV:G.B @H'F861, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F861, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48123, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 48125, + "address_region": "program_or_external", + "bytes": "15F86285", + "text": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F862, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48129, + "address_region": "program_or_external", + "bytes": "1EA627", + "text": "BSR loc_622B", + "mnemonic": "BSR", + "operands": "loc_622B", + "kind": "call", + "targets": [ + 25131 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48132, + "address_region": "program_or_external", + "bytes": "AD84", + "text": "MOV:G.W R5, R4", + "mnemonic": "MOV:G.W", + "operands": "R5, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after MOV source" + ] + } + }, + { + "address": 48134, + "address_region": "program_or_external", + "bytes": "AC1A", + "text": "SHLL.W R4", + "mnemonic": "SHLL.W", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 48136, + "address_region": "program_or_external", + "bytes": "15F86080", + "text": "MOV:G.B @H'F860, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F860, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48140, + "address_region": "program_or_external", + "bytes": "040750", + "text": "AND.B #H'07, R0", + "mnemonic": "AND.B", + "operands": "#H'07, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:AND.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48143, + "address_region": "program_or_external", + "bytes": "15FAA216", + "text": "TST.B @H'FAA2", + "mnemonic": "TST.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [], + "notes": [] + } + }, + { + "address": 48147, + "address_region": "program_or_external", + "bytes": "2625", + "text": "BNE loc_BC3A", + "mnemonic": "BNE", + "operands": "loc_BC3A", + "kind": "branch", + "targets": [ + 48186 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [], + "notes": [] + } + }, + { + "address": 48149, + "address_region": "program_or_external", + "bytes": "15FAA2C7", + "text": "BSET.B #7, @H'FAA2", + "mnemonic": "BSET.B", + "operands": "#7, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48149, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48153, + "address_region": "program_or_external", + "bytes": "15F861F7", + "text": "BTST.B #7, @H'F861", + "mnemonic": "BTST.B", + "operands": "#7, @H'F861", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48149, + "changes": [], + "notes": [] + } + }, + { + "address": 48157, + "address_region": "program_or_external", + "bytes": "3600EB", + "text": "BNE loc_BD0B", + "mnemonic": "BNE", + "operands": "loc_BD0B", + "kind": "branch", + "targets": [ + 48395 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48149, + "changes": [], + "notes": [] + } + }, + { + "address": 48160, + "address_region": "program_or_external", + "bytes": "4000", + "text": "CMP:E #H'00, R0", + "mnemonic": "CMP:E", + "operands": "#H'00, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48160, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + 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instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48625, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_BDFB", + "mnemonic": "BEQ", + "operands": "loc_BDFB", + "kind": "branch", + "targets": [ + 48635 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48627, + "address_region": "program_or_external", + "bytes": "15F9B508", + "text": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48631, + "address_region": "program_or_external", + "bytes": "15F9B5D7", + "text": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [], + "notes": [] + } + }, + { + "address": 48635, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48639, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48643, + "address_region": "program_or_external", + "bytes": "206A", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48645, + "address_region": "program_or_external", + "bytes": "1DF85880", + "text": "MOV:G.W @H'F858, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48645, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48649, + "address_region": "program_or_external", + "bytes": "1DF85090", + "text": "MOV:G.W R0, @H'F850", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48653, + "address_region": "program_or_external", + "bytes": "1DF85A80", + "text": "MOV:G.W @H'F85A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48653, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48657, + "address_region": "program_or_external", + "bytes": "1DF85290", + "text": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48661, + "address_region": "program_or_external", + "bytes": "1DF85C80", + "text": "MOV:G.W @H'F85C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48661, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48665, + "address_region": "program_or_external", + "bytes": "1DF85490", + "text": "MOV:G.W R0, @H'F854", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48669, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48674, + "address_region": "program_or_external", + "bytes": "1EFC01", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48677, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48679, + "address_region": "program_or_external", + "bytes": "2046", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48679, + "changes": [], + "notes": [] + } + }, + { + "address": 48681, + "address_region": "program_or_external", + "bytes": "15FAA4D7", + "text": "BCLR.B #7, @H'FAA4", + "mnemonic": "BCLR.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": 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"BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48856, + "address_region": "program_or_external", + "bytes": "200E", + "text": "BRA loc_BEE8", + "mnemonic": "BRA", + "operands": "loc_BEE8", + "kind": "jump", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [], + "notes": [] + } + }, + { + "address": 48868, + "address_region": "program_or_external", + "bytes": "15F9C513", + "text": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "operands": "@H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48868, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48872, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48872, + "changes": [], + "notes": [] + } + }, + { + "address": 48874, + "address_region": "program_or_external", + "bytes": "15FE91D5", + "text": "BCLR.B #5, @FRT1_TCSR", + "mnemonic": "BCLR.B", + "operands": "#5, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear OCFA (bit 5) of FRT1_TCSR", + "valid": true, + "serial_reconstruction": [ + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48878, + "address_region": "program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48878, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48882, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BEF8", + "mnemonic": "BEQ", + "operands": "loc_BEF8", + "kind": "branch", + "targets": [ + 48888 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48884, + "address_region": "program_or_external", + "bytes": "15F9C00C", + "text": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48884, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48884, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48888, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48888, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48888, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48892, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF02", + "mnemonic": "BEQ", + "operands": "loc_BF02", + "kind": "branch", + "targets": [ + 48898 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48888, + "changes": [], + "notes": [] + } + }, + { + "address": 48894, + "address_region": "program_or_external", + "bytes": "15F9C10C", + "text": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48894, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48894, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48898, + "address_region": "program_or_external", + "bytes": "1DF9C616", + "text": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "operands": "@H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48898, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48898, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48902, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF0C", + "mnemonic": "BEQ", + "operands": "loc_BF0C", + "kind": "branch", + "targets": [ + 48908 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48898, + "changes": [], + "notes": [] + } + }, + { + "address": 48904, + "address_region": "program_or_external", + "bytes": "1DF9C60C", + "text": "ADD:Q.W #-1, @H'F9C6", + "mnemonic": "ADD:Q.W", + "operands": "#-1, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48904, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48904, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48908, + "address_region": "program_or_external", + "bytes": "15F6F6F7", + "text": "BTST.B #7, @H'F6F6", + "mnemonic": "BTST.B", + "operands": "#7, @H'F6F6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63222, + "name": null, + "symbol": "ram_F6F6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48908, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + 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"BEQ", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49075, + "changes": [], + "notes": [] + } + }, + { + "address": 49081, + "address_region": "program_or_external", + "bytes": "15F7980C", + "text": "ADD:Q.B #-1, @H'F798", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F798", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63384, + "name": null, + "symbol": "ram_F798", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49085, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_BFC3", + "mnemonic": "BNE", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [], + "notes": [] + } + }, + { + "address": 49087, + "address_region": "program_or_external", + "bytes": "15F731D7", + "text": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49087, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49091, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49091, + "changes": [], + "notes": [] + } + }, + { + "address": 49092, + "address_region": "program_or_external", + "bytes": "15FEECF7", + "text": "BTST.B #7, @WDT_TCSR_R", + "mnemonic": "BTST.B", + "operands": "#7, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49096, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49102, + "address_region": "program_or_external", + "bytes": "15F79408", + "text": "ADD:Q.B #1, @H'F794", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49106, + "address_region": "program_or_external", + "bytes": "15F794040A", + "text": "CMP:G.B #H'0A, @H'F794", + "mnemonic": "CMP:G.B", + "operands": "#H'0A, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49111, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BFDF", + "mnemonic": "BNE", + "operands": "loc_BFDF", + "kind": "branch", + "targets": [ + 49119 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49113, + "address_region": "program_or_external", + "bytes": "1DFEEC07A57F", + "text": "MOV:G.W #H'A57F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A57F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49113, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49119, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49119, + "changes": [], + "notes": [] + } + }, + { + "address": 49120, + "address_region": "program_or_external", + "bytes": "15F840060A", + "text": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "operands": "#H'0A, @H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49120, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49125, + "address_region": "program_or_external", + "bytes": "AD82", + "text": "MOV:G.W R5, R2", + "mnemonic": "MOV:G.W", + "operands": "R5, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after MOV source" + ] + } + }, + { + "address": 49127, + "address_region": "program_or_external", + "bytes": "0E27", + "text": "BSR loc_C010", + "mnemonic": "BSR", + "operands": "loc_C010", + "kind": "call", + "targets": [ + 49168 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49129, + "address_region": "program_or_external", + "bytes": "0E4E", + "text": "BSR loc_C039", + "mnemonic": "BSR", + "operands": "loc_C039", + "kind": "call", + "targets": [ + 49209 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49131, + "address_region": "program_or_external", + "bytes": "AA75", + "text": "CMP:G.W R2, R5", + "mnemonic": "CMP:G.W", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip 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"bytes": "15F84016", + "text": "TST.B @H'F840", + "mnemonic": "TST.B", + "operands": "@H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49135, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49139, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BFF9", + "mnemonic": "BEQ", + "operands": "loc_BFF9", + "kind": "branch", + "targets": [ + 49145 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49135, + "changes": [], + "notes": [] + } + }, + { + "address": 49141, + "address_region": "program_or_external", + "bytes": "AA85", + "text": "MOV:G.W R2, R5", + "mnemonic": "MOV:G.W", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49141, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + 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"source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49267, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 49271, + "address_region": "program_or_external", + "bytes": "A31A", + "text": "SHLL.B R3", + "mnemonic": "SHLL.B", + "operands": "R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49267, + "changes": [ + { + "kind": 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"address": 49291, + "address_region": "program_or_external", + "bytes": "590007", + "text": "MOV:I.W #H'0007, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49291, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R1" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 = 0x0007" + ], + "known_after": { + "registers": { + "R1": { + "known": true, + "value": 7, + "hex": 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"operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49327, + "changes": [], + "notes": [] + } + }, + { + "address": 49340, + "address_region": "program_or_external", + "bytes": "15FEFFF7", + "text": "BTST.B #7, @P9DR", + "mnemonic": "BTST.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + 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"address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49359, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49363, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": 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"address_region": "program_or_external", + "bytes": "15FEFE0613", + "text": "MOV:G.B #H'13, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'13, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'13", + "valid": true, + "dataflow": { + "block": 49371, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49376, + "address_region": "program_or_external", + "bytes": "590007", + "text": "MOV:I.W #H'0007, R1", + "mnemonic": "MOV:I.W", + "operands": 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"base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49383, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + 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"text": "BEQ loc_C0F5", + "mnemonic": "BEQ", + "operands": "loc_C0F5", + "kind": "branch", + "targets": [ + 49397 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [], + "notes": [] + } + }, + { + "address": 49393, + "address_region": "program_or_external", + "bytes": "A549", + "text": "BSET.B R1, R5", + "mnemonic": "BSET.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49393, + "changes": [ + { + "kind": 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"address": 49397, + "address_region": "program_or_external", + "bytes": "A559", + "text": "BCLR.B R1, R5", + "mnemonic": "BCLR.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49397, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 49399, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": 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"manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49407, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49411, + "address_region": "program_or_external", + "bytes": "01B9DD", + "text": "SCB/F R1, loc_C0E3", + "mnemonic": "SCB/F", + "operands": "R1, loc_C0E3", + "kind": "branch", + "targets": [ + 49379 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49414, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'93", + "valid": true, + "dataflow": { + "block": 49414, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49419, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49414, + "changes": [], + "notes": [] + } + }, + { + "address": 49420, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49424, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49428, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49432, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49436, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49440, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49441, + "address_region": "program_or_external", + "bytes": "15FEFFC7", + "text": "BSET.B #7, @P9DR", + "mnemonic": "BSET.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49445, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49449, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49453, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49457, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49461, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49465, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49469, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49473, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49474, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49478, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49482, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49486, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49490, + "address_region": "program_or_external", + "bytes": "15FEFFC7", + "text": "BSET.B #7, @P9DR", + "mnemonic": "BSET.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49494, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49498, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49502, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49506, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + } + ], + "decompiler_consistency": { + "kind": "decompiler_pseudocode_consistency", + "summary": "3 byte-immediate-to-word destination case(s) require explicit zero-extension in pseudocode.", + "checks": [ + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4163, + "address_hex": "H'1043", + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4184, + "address_hex": "H'1058", + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 16487, + "address_hex": "H'4067", + "instruction": "MOV:G.W #H'00, @(-H'0790,R2)", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + } + ] + }, + "serial_semantics": { + "kind": "serial_semantics", + "protocol_semantics": [ + { + "kind": "serial_semantics", + "scope": "evidence_supported_sci1_6_byte_frame", + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation.", + "frame_candidate": { + "channel": "SCI1", + "rx_frame_start": 63584, + "rx_frame_start_hex": "H'F860", + "rx_frame_end": 63589, + "rx_frame_end_hex": "H'F865", + "tx_staging_start": 63568, + "tx_staging_start_hex": "H'F850", + "tx_staging_end": 63572, + "tx_staging_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "frame_length": 6, + "tx_staging_length": 5, + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "serial_reconstruction_supported": true, + "rx_reconstruction_candidate_id": "sci1_rx_frame_f868_len6_candidate", + "tx_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + "byte_layout": [ + { + "offset": 0, + "rx_address": 63584, + "tx_staging_address": 63568, + "name_candidate": "op_flags", + "semantic": "low three bits select a command; upper bits are preserved or gated in some paths", + "confidence": "medium-high" + }, + { + "offset": 1, + "rx_address": 63585, + "tx_staging_address": 63569, + "name_candidate": "addr_page_flags", + "semantic": "candidate high/page byte for logical point/index; bit 7 is tested as a control flag", + "confidence": "medium" + }, + { + "offset": 2, + "rx_address": 63586, + "tx_staging_address": 63570, + "name_candidate": "addr_offset", + "semantic": "candidate low/offset byte for logical point/index", + "confidence": "medium" + }, + { + "offset": 3, + "rx_address": 63587, + "tx_staging_address": 63571, + "name_candidate": "value_hi", + "semantic": "candidate high byte of a word value", + "confidence": "medium" + }, + { + "offset": 4, + "rx_address": 63588, + "tx_staging_address": 63572, + "name_candidate": "value_lo", + "semantic": "candidate low byte of a word value", + "confidence": "medium" + }, + { + "offset": 5, + "rx_address": 63589, + "tx_staging_address": null, + "name_candidate": "checksum", + "semantic": "0x5A-seeded XOR of bytes 0..4", + "confidence": "high" + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2552 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2584 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2596 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2680 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2599 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2636 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2668 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2680 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "index_decoder": { + "kind": "logical_index_decoder_candidate", + "label": "loc_622B", + "address": 25131, + "address_hex": "H'622B", + "input_fields": [ + "addr_page_flags", + "addr_offset" + ], + "output_register": "R5", + "post_scale_register": "R4", + "post_scale": "R4 = R5 << 1", + "mapping_candidate": [ + { + "page": 0, + "offset_range": "0x00-0x7F", + "index_range": "0x000-0x07F" + }, + { + "page": 1, + "offset_range": "0x00-0xFF", + "index_range": "0x080-0x17F" + }, + { + "page": 2, + "offset_range": "0x00-0x7F", + "index_range": "0x180-0x1FF" + }, + { + "page": "other/overflow", + "index": "0x1FF" + } + ], + "evidence_addresses": [ + 48129 + ], + "evidence_addresses_hex": [ + "H'BC01" + ], + "confidence": "medium", + "caveat": "Mapping is inferred from loc_622B behavior and the nearby R4 = R5 << 1 table-index use." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, 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"access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "rx_fields": [ + { + "kind": "rx_field_semantic_candidate", + "offset": 0, + "name": "command_low3", + "address": 63584, + "address_hex": "H'F860", + "confidence": "candidate-high", + "caveat": "RX[0] is masked with 0x07 before command comparisons", + "evidence_addresses": [ + 48088, + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "mask": 7, + "mask_hex": "H'07" + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 1, + "name": "likely_id_or_index", + "address": 63585, + "address_hex": "H'F861", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 2, + "name": "likely_id_or_index", + "address": 63586, + "address_hex": "H'F862", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 3, + "name": "likely_value", + "address": 63587, + "address_hex": "H'F863", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 4, + "name": "likely_value", + "address": 63588, + "address_hex": "H'F864", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 5, + "name": "checksum", + "address": 63589, + "address_hex": "H'F865", + "confidence": "candidate-high", + "caveat": "RX[5] is validated by the serial reconstruction checksum evidence", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ] + } + ], + "response_builders": [ + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 47939, + "call_address_hex": "H'BB43", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48674, + "call_address_hex": "H'BE22", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "evidence": [ + { + "kind": "rx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 RX frame candidate", + "candidate_id": "sci1_rx_frame_f868_len6_candidate" + }, + { + "kind": "tx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 TX frame candidate", + "candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + { + "kind": "rx0_masked_command_dispatch", + "summary": "RX[0] is read, masked with 0x07, and compared against command values", + "addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + { + "kind": "responses_stage_f850_f854_before_send", + "summary": "F850-F854 writes are observed before calls to loc_BA26", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378, + 48649, + 48657, + 48665, + 48674, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "response_count": 5 + }, + { + "kind": "bb43_autonomous_tx_report_path", + "summary": "BB43 stages a candidate device-to-host report before loc_BA26; this is separate from RX command dispatch.", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + { + "kind": "rx_payload_bytes_read", + "summary": "RX[1..4] are read in the command-processing region", + "addresses": [ + 48092, + 48096, + 48100, + 48104, + 48119, + 48125, + 48153, + 48190, + 48237, + 48267, + 48273, + 48309, + 48317, + 48325, + 48348, + 48356, + 48402, + 48427, + 48433, + 48603, + 48609, + 48722, + 48730, + 48738 + ], + "addresses_hex": [ + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBF7", + "H'BBFD", + "H'BC19", + "H'BC3E", + "H'BC6D", + "H'BC8B", + "H'BC91", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCDC", + "H'BCE4", + "H'BD12", + "H'BD2B", + "H'BD31", + "H'BDDB", + "H'BDE1", + "H'BE52", + "H'BE5A", + "H'BE62" + ] + } + ] + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2552 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2584 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2596 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2680 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2599 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2636 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2668 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2680 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47841, + "instruction_address_hex": "H'BAE1", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47848, + "instruction_address_hex": "H'BAE8", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "immediate": 240, + "immediate_hex": "H'F0" + }, + { + "instruction_address": 48669, + "instruction_address_hex": "H'BE1D", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48702, + "instruction_address_hex": "H'BE3E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48878, + "instruction_address_hex": "H'BEEE", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation." + } +} \ No newline at end of file diff --git a/build/rom_others_menu_gate.asm b/build/rom_others_menu_gate.asm new file mode 100644 index 0000000..916b6a2 --- /dev/null +++ b/build/rom_others_menu_gate.asm @@ -0,0 +1,4295 @@ +; H8/536 ROM disassembly +; input: ROM\M27C512@DIP28_1.BIN +; bytes: 65536 +; vector mode: min +; analysis: recursive trace from vectors +; +; Notes from the manual: +; - H8/536 uses the H8/500 CPU instruction set. +; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC. +; - The register field is H'FE80-H'FFFF; names below come from appendix B. +; - @aa:8 short absolute operands use BR as the upper address byte. +; - SCI baud inference uses section 14.2.8 BRR formulas when SMR/BRR are known. +; - LCD inference treats E-clock H'F200/H'F201 accesses as status/control and data candidates. +; - Pass --clock-hz to convert SCI BRR settings into numeric baud rates. +; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states. + +; Memory Map +; H'0000-H'009F exception_vectors vectors +; H'00A0-H'00FF dtc_vectors dtc_vectors +; H'0100-H'F67F program_or_external program +; H'F680-H'FE7F on_chip_ram ram +; H'FE80-H'FFFF register_field registers + +; Vectors +; H'0000 reset -> vec_reset_1000 (H'1000) +; H'0004 invalid_instruction -> vec_reset_1000 (H'1000) +; H'0006 zero_divide -> vec_reset_1000 (H'1000) +; H'0008 trap_vs -> vec_reset_1000 (H'1000) +; H'0010 address_error -> vec_reset_1000 (H'1000) +; H'0012 trace -> vec_reset_1000 (H'1000) +; H'0016 nmi -> vec_nmi_4393 (H'4393) +; H'0020 trapa_0 -> vec_reset_1000 (H'1000) +; H'0022 trapa_1 -> vec_reset_1000 (H'1000) +; H'0024 trapa_2 -> vec_reset_1000 (H'1000) +; H'0026 trapa_3 -> vec_reset_1000 (H'1000) +; H'0028 trapa_4 -> vec_reset_1000 (H'1000) +; H'002A trapa_5 -> vec_reset_1000 (H'1000) +; H'002C trapa_6 -> vec_reset_1000 (H'1000) +; H'002E trapa_7 -> vec_reset_1000 (H'1000) +; H'0030 trapa_8 -> vec_reset_1000 (H'1000) +; H'0032 trapa_9 -> vec_reset_1000 (H'1000) +; H'0034 trapa_a -> vec_reset_1000 (H'1000) +; H'0036 trapa_b -> vec_reset_1000 (H'1000) +; H'0038 trapa_c -> vec_reset_1000 (H'1000) +; H'003A trapa_d -> vec_reset_1000 (H'1000) +; H'003C trapa_e -> vec_reset_1000 (H'1000) +; H'003E trapa_f -> vec_reset_1000 (H'1000) +; H'0040 irq0 -> vec_reset_1000 (H'1000) +; H'0042 interval_timer -> vec_interval_timer_BFC4 (H'BFC4) +; H'0048 irq1 -> vec_reset_1000 (H'1000) +; H'0050 irq2 -> vec_reset_1000 (H'1000) +; H'0052 irq3 -> vec_irq3_3C30 (H'3C30) +; H'0058 irq4 -> vec_irq4_3AC7 (H'3AC7) +; H'005A irq5 -> vec_reset_1000 (H'1000) +; H'0062 frt1_ocia -> vec_frt1_ocia_BEEA (H'BEEA) +; H'006A frt2_ocia -> vec_frt2_ocia_BF23 (H'BF23) +; H'0080 sci1_eri -> vec_sci1_eri_BB57 (H'BB57) +; H'0082 sci1_rxi -> vec_sci1_rxi_BB67 (H'BB67) +; H'0084 sci1_txi -> vec_sci1_txi_BA84 (H'BA84) +; H'0090 ad_adi -> vec_ad_adi_3D99 (H'3D99) + +; Unreached Data Candidates +; string H'2A52 len=11 '78785=5=5=,' +; string H'2BBA len=7 '8*8B8Z8' +; string H'41B2 len=32 '01020304050607080910111213141516' +; string H'57A4 len=7 'Z [ ' +; string H'582A len=6 'Z [ ' +; string H'5B55 len=10 '0123456789' +; string H'5B60 len=40 ' 0 1 2 3 4 5 6 7 8 910111213141516171819' +; string H'60F6 len=16 '0123456789ABCDEF' +; string H'630C len=9 'm*mDm^mxm' +; string H'633E len=6 'vpwhx6' +; string H'63D7 len=10 'OPERATION ' +; string H'63F5 len=10 ' PAINT ' +; string H'6410 len=18 ' ADV~Xd' +; string H'6443 len=10 'OPERATION ' +; string H'6461 len=10 'IRIS/M.BLK' +; string H'6490 len=10 'OPERATION ' +; string H'64AE len=10 ' LOCK ' +; string H'652F len=19 ' DYNA LATITUDE Xe/' +; string H'6551 len=18 'HIGH LOW~XeP' +; string H'6578 len=18 'STD OFF~Xew' +; string H'65C9 len=18 ' BLACK STR Xe' +; string H'6644 len=19 ' BLACK STR XfD' +; string H'6665 len=19 ' STRETCH LEVEL Xfe' +; string H'6683 len=18 'POINT1 POINT2Xf' +; string H'6706 len=18 ' BLACK STR Xg' +; string H'6727 len=19 " COMPRESS LEVEL Xg'" +; string H'6745 len=19 'POINT1 POINT2XgE' +; string H'67E0 len=18 ' TLCS Xg' +; string H'6802 len=17 'ON OFF~Xh' +; string H'681F len=18 ' AGC GAIN AE Xh' +; string H'686A len=136 ' CL F16 F11 F8 F5.6F4 F2.8F2 F1.8F1.4 OP DPR HYP HIGHMID LOW 36dB30dB24dB18dB12dB 9dB 6dB 3dB 0dB-3dB' +; string H'693B len=19 ' AUTO FUNC Xi;' +; string H'695C len=19 ' ATW Xi\\' +; string H'6984 len=17 'ON OFF~Xi' +; string H'6A4F len=19 ' AUTO FUNC XjO' +; string H'6A71 len=18 'STD SPOT.L~Xjp' +; string H'6A8E len=18 ' A.IRIS MODE Xj' +; string H'6AAD len=17 'AI BACK.L~Xj' +; string H'6B3D len=19 ' AUTO FUNC Xk=' +; string H'6B5E len=19 ' AUTO FOCUS Xk^' +; ptrtbl H'1A1E count=4 -> H'F6F8, H'FAFC, H'FDFE, H'FF00 +; ptrtbl H'1EB0 count=4 -> H'F730, H'F727, H'2815, H'F731 +; ptrtbl H'28A8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28B6 count=10 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'28DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28F2 count=29 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'292E count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'293C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2944 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'294C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2954 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'295C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2964 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'296C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2974 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2982 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'29AE count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29B8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29FA count=13 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A20 count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2A34 count=15 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A62 count=24 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A98 count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2AA2 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2AC8 count=115 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2BC4 count=113 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'33A0 count=3 -> H'FF26, H'11A9, H'F726 +; ptrtbl H'3478 count=3 -> H'F790, H'F727, H'441D +; ptrtbl H'35DC count=3 -> H'FE27, H'1215, H'F717 +; ptrtbl H'4698 count=3 -> H'F750, H'1627, H'10FB +; ptrtbl H'47AE count=3 -> H'F752, H'1627, H'10FB +; ptrtbl H'48AA count=4 -> H'FB03, H'F726, H'1215, H'F6D1 +; ptrtbl H'505A count=3 -> H'1627, H'5515, H'FB03 +; ptrtbl H'5A22 count=3 -> H'1AF8, H'F74C, H'1627 +; ptrtbl H'62EE count=4 -> H'FCE2, H'FC62, H'FA84, H'11DC +; ptrtbl H'74FC count=3 -> H'F772, H'1627, H'12A8 +; ptrtbl H'80F2 count=3 -> H'FC80, H'FC84, H'11DC +; ptrtbl H'9E10 count=3 -> H'FE1E, H'BC7D, H'5500 +; ptrtbl H'B5E0 count=3 -> H'F772, H'1627, H'11A0 + +; Symbols +; mem_1011 H'1011 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_10FB H'10FB program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1161 H'1161 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1170 H'1170 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1179 H'1179 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1188 H'1188 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1197 H'1197 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11A0 H'11A0 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_11A9 H'11A9 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11DC H'11DC program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1206 H'1206 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1215 H'1215 program_or_external memory r=0 w=0 width=unknown xrefs=3 +; mem_12A8 H'12A8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1314 H'1314 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1617 H'1617 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1627 H'1627 program_or_external memory r=0 w=0 width=unknown xrefs=7 +; mem_1630 H'1630 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1647 H'1647 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1664 H'1664 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1682 H'1682 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1700 H'1700 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1819 H'1819 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1A00 H'1A00 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1AF8 H'1AF8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2815 H'2815 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2CA6 H'2CA6 program_or_external memory r=0 w=0 width=unknown xrefs=429 +; mem_441D H'441D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449C H'449C program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449E H'449E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_44A0 H'44A0 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5500 H'5500 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5515 H'5515 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_602E H'602E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6030 H'6030 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6032 H'6032 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_BC7D H'BC7D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_E000 H'E000 program_or_external memory r=0 w=1 width=word +; mem_E004 H'E004 program_or_external memory r=1 w=0 width=word +; mem_E006 H'E006 program_or_external memory r=0 w=1 width=word +; mem_E046 H'E046 program_or_external memory r=0 w=1 width=word +; mem_E080 H'E080 program_or_external memory r=0 w=1 width=word +; mem_E102 H'E102 program_or_external memory r=2 w=0 width=word +; mem_E11E H'E11E program_or_external memory r=2 w=0 width=word +; mem_E124 H'E124 program_or_external memory r=2 w=0 width=word +; mem_E126 H'E126 program_or_external memory r=5 w=0 width=word +; mem_E14E H'E14E program_or_external memory r=1 w=0 width=word +; mem_E16E H'E16E program_or_external memory r=1 w=0 width=word +; mem_E172 H'E172 program_or_external memory r=1 w=0 width=word +; mem_E1EC H'E1EC program_or_external memory r=2 w=0 width=word +; mem_E220 H'E220 program_or_external memory r=1 w=0 width=word +; mem_E800 H'E800 program_or_external memory r=0 w=1 width=word +; mem_E806 H'E806 program_or_external memory r=0 w=1 width=word +; mem_E880 H'E880 program_or_external memory r=0 w=1 width=word +; mem_E902 H'E902 program_or_external memory r=0 w=1 width=word +; mem_E924 H'E924 program_or_external memory r=0 w=1 width=word +; mem_E9EC H'E9EC program_or_external memory r=0 w=1 width=word +; mem_F000 H'F000 program_or_external memory r=2 w=0 width=byte +; mem_F001 H'F001 program_or_external memory r=2 w=1 width=byte +; mem_F002 H'F002 program_or_external memory r=2 w=1 width=mixed +; mem_F003 H'F003 program_or_external memory r=1 w=1 width=byte +; mem_F004 H'F004 program_or_external memory r=2 w=1 width=mixed +; mem_F005 H'F005 program_or_external memory r=1 w=1 width=byte +; mem_F006 H'F006 program_or_external memory r=2 w=0 width=mixed +; mem_F007 H'F007 program_or_external memory r=1 w=0 width=byte +; mem_F008 H'F008 program_or_external memory r=2 w=0 width=mixed +; mem_F009 H'F009 program_or_external memory r=1 w=1 width=byte +; mem_F00A H'F00A program_or_external memory r=2 w=1 width=mixed +; mem_F00B H'F00B program_or_external memory r=0 w=1 width=byte +; mem_F00C H'F00C program_or_external memory r=2 w=1 width=mixed +; mem_F00D H'F00D program_or_external memory r=0 w=1 width=byte +; mem_F00E H'F00E program_or_external memory r=0 w=1 width=byte +; mem_F00F H'F00F program_or_external memory r=1 w=1 width=byte +; mem_F100 H'F100 program_or_external memory r=2 w=0 width=byte +; mem_F101 H'F101 program_or_external memory r=2 w=1 width=byte +; mem_F102 H'F102 program_or_external memory r=2 w=1 width=mixed +; mem_F103 H'F103 program_or_external memory r=1 w=1 width=byte +; mem_F104 H'F104 program_or_external memory r=2 w=1 width=mixed +; mem_F105 H'F105 program_or_external memory r=1 w=1 width=byte +; mem_F106 H'F106 program_or_external memory r=2 w=0 width=mixed +; mem_F107 H'F107 program_or_external memory r=1 w=0 width=byte +; ... 236 more symbols omitted from listing header + +; Board Profile +; Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver. +; H8 pin 66 P95/TXD (TXD) -> MAX202 pin 11 +; H8 pin 67 P96/RXD (RXD) -> MAX202 pin 12 +; SCI2 pin routing is disabled by SYSCR2.P9SCI2E=0 in the observed setup. + +; Serial Protocol Reconstruction +; TX candidate: 6 bytes H'F858-H'F85D, checksum H'F85D seeded by H'005A (confidence high 0.95) +; TX path: initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted +; RX candidate: 6 bytes capture H'F868-H'F86D, validate H'F860-H'F865 checksum H'F865 seeded by H'005A (confidence high 0.9) +; caveat: candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet +; Serial RAM role candidates +; H'F9C0: post_tx_report_delay - post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C1: secondary_tx_report_delay - secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C6: periodic_report_countdown - periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it + +; LCD/Text Scan +; search 'CONNECT': not literal, hits=0 +; near: H'A025 'COMPLETED', H'8E79 'ON CONT1 OFF~X', H'8F55 'ON CONT2 OFF~X', H'94A9 'ON' +; LCD text regions +; region H'63D7-H'6758 count=15 'OPERATION', 'PAINT', 'OPERATION', 'IRIS/M.BLK' +; region H'67E0-H'6831 count=2 'TLCS Xg', 'AGC GAIN AE Xh' +; region H'6A4F-H'6C47 count=8 'AUTO FUNC XjO', 'A.IRIS MODE Xj', 'AI BACK.L~Xj', 'AUTO FUNC Xk=' +; region H'6F84-H'6FC0 count=2 'OTHERS Xo', 'SHUTTER Xo' +; region H'7052-H'7477 count=15 'SET RCP', 'MASTER', 'OTHERS Xp', 'COPY TO SLAVES~Xp' +; region H'757A-H'7824 count=14 'BARS TYPE Xuz', 'SMPTE Xu', 'SPLIT Xu', 'FULLFIELD 75% Xu' +; region H'78B5-H'792F count=4 'OTHERS Xx', 'WHITE BLACK~Xx', 'COMM LINK ITEM-2Xx', 'FLARE Xy' +; region H'819C-H'87A9 count=28 'SHADING X', 'WHITE~X', 'SHADING AUTO SETX', 'BLACK~X' +; region H'883D-H'8959 count=7 'MATRIX X', 'STD FL~X', 'PRESET MATRIX X', 'H.SAT SPCL~X' +; region H'8A0C-H'8BAC count=7 'MATRIX X', 'ON SKIN OFF~X', 'SAT HUE X', 'MATRIX X' +; region H'8CB7-H'8CFD count=2 'FILTER X', '1 2 3 4 X' +; region H'8E57-H'8EA7 count=3 'LENS X', 'ON CONT1 OFF~X', 'FOCUS ZOOM X' +; ... 23 more LCD text regions +; LCD text candidates +; text H'41B0 len=35 medium '01020304050607080910111213141516X' +; text H'5B55 len=10 high '0123456789' xrefs=2 +; text H'60F6 len=16 high '0123456789ABCDEF' +; text H'63D7 len=10 high 'OPERATION' xrefs=1 +; text H'63F5 len=10 high 'PAINT' xrefs=1 +; text H'6443 len=10 high 'OPERATION' xrefs=1 +; text H'6461 len=10 high 'IRIS/M.BLK' xrefs=1 +; text H'6490 len=10 high 'OPERATION' xrefs=1 +; text H'64AE len=10 high 'LOCK' xrefs=1 +; text H'652F len=19 high 'DYNA LATITUDE Xe/' xrefs=1 +; text H'6551 len=18 medium 'HIGH LOW~XeP' xrefs=1 +; text H'65C9 len=18 medium 'BLACK STR Xe' xrefs=1 +; text H'6644 len=19 medium 'BLACK STR XfD' xrefs=1 +; text H'6665 len=19 medium 'STRETCH LEVEL Xfe' xrefs=1 +; text H'6683 len=18 high 'POINT1 POINT2Xf' xrefs=1 +; text H'6706 len=18 medium 'BLACK STR Xg' xrefs=1 +; text H'6727 len=19 medium "COMPRESS LEVEL Xg'" xrefs=1 +; text H'6745 len=19 high 'POINT1 POINT2XgE' xrefs=1 +; text H'67E0 len=18 medium 'TLCS Xg' xrefs=1 +; text H'681F len=18 medium 'AGC GAIN AE Xh' xrefs=1 +; text H'693B len=19 medium 'AUTO FUNC Xi;' xrefs=1 +; text H'6A4F len=19 medium 'AUTO FUNC XjO' xrefs=1 +; text H'6A8E len=18 medium 'A.IRIS MODE Xj' xrefs=1 +; text H'6AAD len=17 medium 'AI BACK.L~Xj' xrefs=1 +; text H'6B3D len=19 medium 'AUTO FUNC Xk=' xrefs=1 +; text H'6B5E len=19 medium 'AUTO FOCUS Xk^' xrefs=1 +; text H'6BEF len=18 medium 'DIAG Xk' xrefs=1 +; text H'6C16 len=18 medium 'DIAG DATA Xl' xrefs=1 +; text H'6C35 len=18 medium 'RESET REQ~Xl4' xrefs=1 +; text H'6F84 len=18 medium 'OTHERS Xo' xrefs=2 +; text H'6FAE len=18 medium 'SHUTTER Xo' xrefs=2 +; text H'7052 len=14 medium 'SET RCP' xrefs=1 +; text H'706F len=14 medium 'MASTER' xrefs=1 +; text H'709F len=18 medium 'OTHERS Xp' xrefs=2 +; text H'70C0 len=18 medium 'COPY TO SLAVES~Xp' xrefs=2 +; text H'7144 len=19 medium 'CAM ID SET~XqD' xrefs=2 +; text H'71C9 len=18 medium 'OTHERS Xq' xrefs=1 +; text H'71F9 len=18 medium 'CAM ID IND Xq' xrefs=1 +; text H'7213 len=18 medium 'TITLE IND Xr' xrefs=1 +; text H'72A5 len=18 medium 'OTHERS Xr' xrefs=1 +; text H'72C7 len=17 medium 'CAM BARS~Xr' xrefs=1 +; text H'72E4 len=18 medium 'CLOCK IND Xr' xrefs=1 +; text H'7369 len=19 medium 'OTHERS Xsi' xrefs=1 +; text H'7393 len=18 high 'CENTER MARKER Xs' xrefs=1 +; text H'7425 len=19 medium 'OTHERS Xt%' xrefs=1 +; text H'7464 len=19 medium 'SAFETY ZONE Xtd' xrefs=1 +; text H'757A len=19 medium 'BARS TYPE Xuz' xrefs=1 +; text H'75A4 len=18 medium 'SMPTE Xu' xrefs=1 +; ... 192 more LCD text candidates + +; LCD Driver Candidates +; H'F200 lcd_status_control status/control register inferred from busy polling and command writes +; H'F201 lcd_data data register inferred from paired data reads/writes +; LCD routines +; routine H'3F40-H'3F74 lcd_wait_and_transfer lcd_command_or_address_write, lcd_data_read, lcd_data_write, lcd_status_read +; LCD busy loops +; loop H'3F4A->H'3F51 LCD busy-flag poll: read H'F200, test bit 7, branch until clear + + +vec_reset_1000: +1000: 5F FE 80 MOV:I.W #H'FE80, R7 ; dataflow R7=H'FE80; cycles=3 +1003: 0C 07 00 88 LDC.W #H'0700, SR ; dataflow SR=H'0700; cycles=6 +1007: 15 FE 80 06 FF MOV:G.B #H'FF, @P1DDR ; P1DDR = H'FF; cycles=9 +100C: 15 FE 82 06 00 MOV:G.B #H'00, @P1DR ; P1DR = H'00; cycles=9 +1011: 15 FE 89 06 F9 MOV:G.B #H'F9, @P6DDR ; P6DDR = H'F9; cycles=9 +1016: 15 FE 8B 06 F1 MOV:G.B #H'F1, @P6DR ; P6DR = H'F1; cycles=9 +101B: 15 FE 8C 06 00 MOV:G.B #H'00, @P7DDR ; P7DDR = H'00; cycles=9 +1020: 15 FE 8E 06 00 MOV:G.B #H'00, @P7DR ; P7DR = H'00; cycles=9 +1025: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +102A: 15 FE FF 06 00 MOV:G.B #H'00, @P9DR ; P9DR = H'00; cycles=9 +102F: 15 FE FC 06 87 MOV:G.B #H'87, @SYSCR1 ; SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled); cycles=9 +1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; FRT1_FRC word write; TEMP byte-order hazard avoided; cycles=9 +1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_H ; FRT1_OCRA_H = H'9C; FRT1_OCRA word write; TEMP byte-order hazard avoided; cycles=11 +104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; FRT2_FRC word write; TEMP byte-order hazard avoided; cycles=11 +105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; FRT2_OCRA word write; TEMP byte-order hazard avoided; cycles=9 +1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 +1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 +106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1072: 15 FE D1 06 10 MOV:G.B #H'10, @TMR_TCSR ; TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0); cycles=9 +1077: 15 FE C0 06 38 MOV:G.B #H'38, @PWM1_TCR ; PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +107C: 15 FE C1 06 FF MOV:G.B #H'FF, @PWM1_DTR ; PWM1_DTR = H'FF; cycles=9 +1081: 15 FE C4 06 38 MOV:G.B #H'38, @PWM2_TCR ; PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1086: 15 FE C5 06 FF MOV:G.B #H'FF, @PWM2_DTR ; PWM2_DTR = H'FF; cycles=9 +108B: 15 FE C8 06 3B MOV:G.B #H'3B, @PWM3_TCR ; PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1); cycles=9 +1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D; cycles=9 +1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI1 receive and receive-error interrupts (RIE); enable SCI1 transmitter (TE); enable SCI1 receiver (RE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI2 receive and receive-error interrupts (RIE); disable SCI2 transmitter (TE); disable SCI2 receiver (RE); SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 +10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field; cycles=9 +10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 +10C2: 15 FF 11 06 FF MOV:G.B #H'FF, @RAMCR ; RAMCR = H'FF (RAME=1; on-chip RAM enabled); cycles=9 +10C7: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=8 +10CB: 30 2E A8 BRA loc_3F76 ; cycles=8 + +loc_10CE: +10CE: 5C 00 40 MOV:I.W #H'0040, R4 ; dataflow R4=H'0040; cycles=3 +10D1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10D4: 1E 2D F5 BSR loc_3ECC ; cycles=13 +10D7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10DA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10DD: 1E 2D EC BSR loc_3ECC ; cycles=14 +10E0: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10E3: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10E6: 1E 2D E3 BSR loc_3ECC ; cycles=13 +10E9: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10EC: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10EF: 1E 2D DA BSR loc_3ECC ; cycles=14 +10F2: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +10F5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10F8: 1E 2D D1 BSR loc_3ECC ; cycles=13 +10FB: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +10FE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1101: 1E 2D C8 BSR loc_3ECC ; cycles=14 +1104: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1107: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +110A: 1E 2D BF BSR loc_3ECC ; cycles=13 +110D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1110: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1113: 1E 2D B6 BSR loc_3ECC ; cycles=14 +1116: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1119: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +111C: 1E 2D AD BSR loc_3ECC ; cycles=13 +111F: 5C 00 48 MOV:I.W #H'0048, R4 ; dataflow R4=H'0048; cycles=3 +1122: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1125: 1E 2D A4 BSR loc_3ECC ; cycles=14 +1128: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +112B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +112E: 1E 2D 9B BSR loc_3ECC ; cycles=13 +1131: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1134: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1137: 1E 2D 92 BSR loc_3ECC ; cycles=14 +113A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +113D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1140: 1E 2D 89 BSR loc_3ECC ; cycles=13 +1143: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1146: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1149: 1E 2D 80 BSR loc_3ECC ; cycles=14 +114C: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +114F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1152: 1E 2D 77 BSR loc_3ECC ; cycles=13 +1155: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1158: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +115B: 1E 2D 6E BSR loc_3ECC ; cycles=14 +115E: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1161: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1164: 1E 2D 65 BSR loc_3ECC ; cycles=13 +1167: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +116A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +116D: 1E 2D 5C BSR loc_3ECC ; cycles=14 +1170: 5C 00 50 MOV:I.W #H'0050, R4 ; dataflow R4=H'0050; cycles=3 +1173: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1176: 1E 2D 53 BSR loc_3ECC ; cycles=13 +1179: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +117C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +117F: 1E 2D 4A BSR loc_3ECC ; cycles=14 +1182: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1185: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1188: 1E 2D 41 BSR loc_3ECC ; cycles=13 +118B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +118E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1191: 1E 2D 38 BSR loc_3ECC ; cycles=14 +1194: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +1197: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +119A: 1E 2D 2F BSR loc_3ECC ; cycles=13 +119D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11A3: 1E 2D 26 BSR loc_3ECC ; cycles=14 +11A6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11AC: 1E 2D 1D BSR loc_3ECC ; cycles=13 +11AF: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11B2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11B5: 1E 2D 14 BSR loc_3ECC ; cycles=14 +11B8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11BB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11BE: 1E 2D 0B BSR loc_3ECC ; cycles=13 +11C1: 5C 00 58 MOV:I.W #H'0058, R4 ; dataflow R4=H'0058; cycles=3 +11C4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11C7: 1E 2D 02 BSR loc_3ECC ; cycles=14 +11CA: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11CD: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D0: 1E 2C F9 BSR loc_3ECC ; cycles=13 +11D3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11D6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D9: 1E 2C F0 BSR loc_3ECC ; cycles=14 +11DC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11DF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11E2: 1E 2C E7 BSR loc_3ECC ; cycles=13 +11E5: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +11E8: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11EB: 1E 2C DE BSR loc_3ECC ; cycles=14 +11EE: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11F1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11F4: 1E 2C D5 BSR loc_3ECC ; cycles=13 +11F7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11FA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11FD: 1E 2C CC BSR loc_3ECC ; cycles=14 +1200: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1203: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1206: 1E 2C C3 BSR loc_3ECC ; cycles=13 +1209: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +120C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +120F: 1E 2C BA BSR loc_3ECC ; cycles=14 +1212: 5C 00 60 MOV:I.W #H'0060, R4 ; dataflow R4=H'0060; cycles=3 +1215: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1218: 1E 2C B1 BSR loc_3ECC ; cycles=13 +121B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +121E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1221: 1E 2C A8 BSR loc_3ECC ; cycles=14 +1224: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1227: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +122A: 1E 2C 9F BSR loc_3ECC ; cycles=13 +122D: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1230: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1233: 1E 2C 96 BSR loc_3ECC ; cycles=14 +1236: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1239: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +123C: 1E 2C 8D BSR loc_3ECC ; cycles=13 +123F: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1242: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1245: 1E 2C 84 BSR loc_3ECC ; cycles=14 +1248: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +124B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +124E: 1E 2C 7B BSR loc_3ECC ; cycles=13 +1251: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1254: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1257: 1E 2C 72 BSR loc_3ECC ; cycles=14 +125A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +125D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1260: 1E 2C 69 BSR loc_3ECC ; cycles=13 +1263: 5C 00 68 MOV:I.W #H'0068, R4 ; dataflow R4=H'0068; cycles=3 +1266: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1269: 1E 2C 60 BSR loc_3ECC ; cycles=14 +126C: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +126F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1272: 1E 2C 57 BSR loc_3ECC ; cycles=13 +1275: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1278: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +127B: 1E 2C 4E BSR loc_3ECC ; cycles=14 +127E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1281: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1284: 1E 2C 45 BSR loc_3ECC ; cycles=13 +1287: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +128A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +128D: 1E 2C 3C BSR loc_3ECC ; cycles=14 +1290: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1293: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1296: 1E 2C 33 BSR loc_3ECC ; cycles=13 +1299: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +129C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +129F: 1E 2C 2A BSR loc_3ECC ; cycles=14 +12A2: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12A5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12A8: 1E 2C 21 BSR loc_3ECC ; cycles=13 +12AB: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12AE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12B1: 1E 2C 18 BSR loc_3ECC ; cycles=14 +12B4: 5C 00 70 MOV:I.W #H'0070, R4 ; dataflow R4=H'0070; cycles=3 +12B7: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12BA: 1E 2C 0F BSR loc_3ECC ; cycles=13 +12BD: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12C3: 1E 2C 06 BSR loc_3ECC ; cycles=14 +12C6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12CC: 1E 2B FD BSR loc_3ECC ; cycles=13 +12CF: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12D2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12D5: 1E 2B F4 BSR loc_3ECC ; cycles=14 +12D8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12DB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12DE: 1E 2B EB BSR loc_3ECC ; cycles=13 +12E1: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12E4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12E7: 1E 2B E2 BSR loc_3ECC ; cycles=14 +12EA: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12ED: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F0: 1E 2B D9 BSR loc_3ECC ; cycles=13 +12F3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12F6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F9: 1E 2B D0 BSR loc_3ECC ; cycles=14 +12FC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12FF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1302: 1E 2B C7 BSR loc_3ECC ; cycles=13 +1305: 5C 00 78 MOV:I.W #H'0078, R4 ; dataflow R4=H'0078; cycles=3 +1308: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +130B: 1E 2B BE BSR loc_3ECC ; cycles=14 +130E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1311: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1314: 1E 2B B5 BSR loc_3ECC ; cycles=13 +1317: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +131A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +131D: 1E 2B AC BSR loc_3ECC ; cycles=14 +1320: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1323: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1326: 1E 2B A3 BSR loc_3ECC ; cycles=13 +1329: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +132C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +132F: 1E 2B 9A BSR loc_3ECC ; cycles=14 +1332: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1335: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1338: 1E 2B 91 BSR loc_3ECC ; cycles=13 +133B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +133E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1341: 1E 2B 88 BSR loc_3ECC ; cycles=14 +1344: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1347: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +134A: 1E 2B 7F BSR loc_3ECC ; cycles=13 +134D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1350: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1353: 1E 2B 76 BSR loc_3ECC ; cycles=14 +1356: 19 RTS ; cycles=12 + +loc_15E0: +15E0: 1E 10 6D BSR loc_2650 ; cycles=13 +15E3: 15 F6 89 D7 BCLR.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=8 +15E7: 27 10 BEQ loc_15F9 ; cycles=3/8 nt/t +15E9: 1D F6 8E 81 MOV:G.W @H'F68E, R1 ; refs ram_F68E in on_chip_ram; cycles=6 +15ED: 1D E9 02 91 MOV:G.W R1, @H'E902 ; refs mem_E902 in program_or_external; cycles=6 +15F1: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +15F3: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +15F6: 1E 28 5B BSR loc_3E54 ; cycles=13 + +loc_15F9: +15F9: 15 F6 F0 16 TST.B @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +15FD: 27 3E BEQ loc_163D ; cycles=3/8 nt/t +15FF: 15 F6 F0 D7 BCLR.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1603: 27 03 BEQ loc_1608 ; cycles=3/8 nt/t +1605: 18 43 94 JSR @loc_4394 ; cycles=14 + +loc_1608: +1608: 15 F6 F0 D6 BCLR.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +160C: 27 03 BEQ loc_1611 ; cycles=3/7 nt/t +160E: 18 44 57 JSR @loc_4457 ; cycles=13 + +loc_1611: +1611: 15 F6 F0 D5 BCLR.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1615: 27 03 BEQ loc_161A ; cycles=3/8 nt/t +1617: 18 45 1A JSR @loc_451A ; cycles=14 + +loc_161A: +161A: 15 F6 F0 D4 BCLR.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +161E: 15 F6 F0 D3 BCLR.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1622: 27 03 BEQ loc_1627 ; cycles=3/7 nt/t +1624: 18 17 05 JSR @loc_1705 ; cycles=13 + +loc_1627: +1627: 15 F6 F0 D2 BCLR.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +162B: 27 03 BEQ loc_1630 ; cycles=3/8 nt/t +162D: 18 17 4D JSR @loc_174D ; cycles=14 + +loc_1630: +1630: 15 F6 F0 D1 BCLR.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1634: 27 03 BEQ loc_1639 ; cycles=3/7 nt/t +1636: 18 17 95 JSR @loc_1795 ; cycles=13 + +loc_1639: +1639: 15 F6 F0 D0 BCLR.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 + +loc_163D: +163D: 15 F6 F1 16 TST.B @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=6 +1641: 27 43 BEQ loc_1686 ; cycles=3/8 nt/t +1643: 15 F6 F1 D7 BCLR.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1647: 27 03 BEQ loc_164C ; cycles=3/8 nt/t +1649: 18 17 C9 JSR @loc_17C9 ; cycles=14 + +loc_164C: +164C: 15 F6 F1 D6 BCLR.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1650: 27 03 BEQ loc_1655 ; cycles=3/7 nt/t +1652: 18 17 FB JSR @loc_17FB ; cycles=13 + +loc_1655: +1655: 15 F6 F1 D5 BCLR.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1659: 27 03 BEQ loc_165E ; cycles=3/8 nt/t +165B: 18 18 2D JSR @loc_182D ; cycles=14 + +loc_165E: +165E: 15 F6 F1 D4 BCLR.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1662: 27 03 BEQ loc_1667 ; cycles=3/7 nt/t +1664: 18 18 91 JSR @loc_1891 ; cycles=13 + +loc_1667: +1667: 15 F6 F1 D3 BCLR.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +166B: 27 03 BEQ loc_1670 ; cycles=3/8 nt/t +166D: 18 18 E7 JSR @loc_18E7 ; cycles=14 + +loc_1670: +1670: 15 F6 F1 D2 BCLR.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1674: 27 03 BEQ loc_1679 ; cycles=3/7 nt/t +1676: 18 19 4A JSR @loc_194A ; cycles=13 + +loc_1679: +1679: 15 F6 F1 D1 BCLR.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +167D: 27 03 BEQ loc_1682 ; cycles=3/8 nt/t +167F: 18 19 79 JSR @loc_1979 ; cycles=14 + +loc_1682: +1682: 15 F6 F1 D0 BCLR.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 + +loc_1686: +1686: 15 F6 F2 16 TST.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=7 +168A: 27 48 BEQ loc_16D4 ; cycles=3/7 nt/t +168C: 15 F6 F2 D7 BCLR.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +1690: 27 03 BEQ loc_1695 ; cycles=3/7 nt/t +1692: 18 1B 2D JSR @loc_1B2D ; cycles=13 + +loc_1695: +1695: 15 F6 F2 D6 BCLR.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +1699: 27 03 BEQ loc_169E ; cycles=3/8 nt/t +169B: 18 1B 44 JSR @loc_1B44 ; cycles=14 + +loc_169E: +169E: 15 F6 F2 D5 BCLR.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16A2: 27 03 BEQ loc_16A7 ; cycles=3/7 nt/t +16A4: 18 1B 5B JSR @loc_1B5B ; cycles=13 + +loc_16A7: +16A7: 15 F6 F2 D4 BCLR.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16AB: 27 03 BEQ loc_16B0 ; cycles=3/8 nt/t +16AD: 18 1B A0 JSR @loc_1BA0 ; cycles=14 + +loc_16B0: +16B0: 15 F6 F2 D3 BCLR.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16B4: 27 03 BEQ loc_16B9 ; cycles=3/7 nt/t +16B6: 18 1B B6 JSR @loc_1BB6 ; cycles=13 + +loc_16B9: +16B9: 15 F6 F2 D2 BCLR.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16BD: 27 03 BEQ loc_16C2 ; cycles=3/8 nt/t +16BF: 18 1B CC JSR @loc_1BCC ; cycles=14 + +loc_16C2: +16C2: 15 F6 F2 D1 BCLR.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16C6: 27 03 BEQ loc_16CB ; cycles=3/7 nt/t +16C8: 18 1B 72 JSR @loc_1B72 ; cycles=13 + +loc_16CB: +16CB: 15 F6 F2 D0 BCLR.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16CF: 27 03 BEQ loc_16D4 ; cycles=3/8 nt/t +16D1: 18 1B 89 JSR @loc_1B89 ; cycles=14 + +loc_16D4: +16D4: 15 F6 F3 16 TST.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=7 +16D8: 27 2A BEQ loc_1704 ; cycles=3/7 nt/t +16DA: 15 F6 F3 D7 BCLR.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16DE: 15 F6 F3 D6 BCLR.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E2: 15 F6 F3 D5 BCLR.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E6: 15 F6 F3 D4 BCLR.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16EA: 27 03 BEQ loc_16EF ; cycles=3/7 nt/t +16EC: 18 1B E2 JSR @loc_1BE2 ; cycles=13 + +loc_16EF: +16EF: 15 F6 F3 D3 BCLR.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=8 +16F3: 27 03 BEQ loc_16F8 ; cycles=3/8 nt/t +16F5: 18 1B F8 JSR @loc_1BF8 ; cycles=14 + +loc_16F8: +16F8: 15 F6 F3 D2 BCLR.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16FC: 15 F6 F3 D1 BCLR.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +1700: 15 F6 F3 D0 BCLR.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 + +loc_1704: +1704: 19 RTS ; cycles=12 + +loc_1705: +1705: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +170A: 22 38 BHI loc_1744 ; cycles=3/7 nt/t +170C: 1D E1 4E FF BTST.W #15, @H'E14E ; refs mem_E14E in program_or_external; cycles=7 +1710: 26 24 BNE loc_1736 ; cycles=3/7 nt/t +1712: 15 F7 30 F6 BTST.B #6, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1716: 26 1E BNE loc_1736 ; cycles=3/7 nt/t +1718: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +171C: 26 08 BNE loc_1726 ; cycles=3/7 nt/t +171E: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +1722: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_1726: +1726: 1D F7 32 07 1C 07 MOV:G.W #H'1C07, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +172C: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1731: 1E 31 C6 BSR loc_48FA ; cycles=14 +1734: 20 0E BRA loc_1744 ; cycles=7 + +loc_1736: +1736: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +173A: 1D F6 B6 34 SUB.W @H'F6B6, R4 ; refs ram_F6B6 in on_chip_ram; cycles=7 +173E: 5B 00 A9 MOV:I.W #H'00A9, R3 ; dataflow R3=H'00A9; cycles=3 +1741: 1E 02 5E BSR loc_19A2 ; cycles=14 + +loc_1744: +1744: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +1748: 1D F6 B6 94 MOV:G.W R4, @H'F6B6 ; refs ram_F6B6 in on_chip_ram; cycles=7 +174C: 19 RTS ; cycles=12 + +loc_174D: +174D: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1752: 22 38 BHI loc_178C ; cycles=3/7 nt/t +1754: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1758: 27 32 BEQ loc_178C ; cycles=3/7 nt/t +175A: 1D E1 6E FD BTST.W #13, @H'E16E ; refs mem_E16E in program_or_external; cycles=7 +175E: 26 1E BNE loc_177E ; cycles=3/7 nt/t +1760: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +1764: 26 08 BNE loc_176E ; cycles=3/7 nt/t +1766: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +176A: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_176E: +176E: 1D F7 32 07 1C 06 MOV:G.W #H'1C06, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +1774: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1779: 1E 31 7E BSR loc_48FA ; cycles=14 +177C: 20 0E BRA loc_178C ; cycles=7 + +loc_177E: +177E: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1782: 1D F6 B4 34 SUB.W @H'F6B4, R4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1786: 5B 00 C5 MOV:I.W #H'00C5, R3 ; dataflow R3=H'00C5; cycles=3 +1789: 1E 02 16 BSR loc_19A2 ; cycles=14 + +loc_178C: +178C: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1790: 1D F6 B4 94 MOV:G.W R4, @H'F6B4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1794: 19 RTS ; cycles=12 + +loc_1795: +1795: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +179A: 22 24 BHI loc_17C0 ; cycles=3/7 nt/t +179C: 1D E1 72 FD BTST.W #13, @H'E172 ; refs mem_E172 in program_or_external; cycles=7 +17A0: 26 05 BNE loc_17A7 ; cycles=3/7 nt/t +17A2: 1E 09 82 BSR loc_2127 ; cycles=13 +17A5: 20 19 BRA loc_17C0 ; cycles=8 + +loc_17A7: +17A7: 1D E2 20 FF BTST.W #15, @H'E220 ; refs mem_E220 in program_or_external; cycles=6 +17AB: 27 05 BEQ loc_17B2 ; cycles=3/8 nt/t +17AD: 1E 09 77 BSR loc_2127 ; cycles=14 +17B0: 20 0E BRA loc_17C0 ; cycles=7 + +loc_17B2: +17B2: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17B6: 1D F6 B2 34 SUB.W @H'F6B2, R4 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17BA: 5B 00 BC MOV:I.W #H'00BC, R3 ; dataflow R3=H'00BC; cycles=3 +17BD: 1E 01 E2 BSR loc_19A2 ; cycles=14 + +loc_17C0: +17C0: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17C4: 1D F6 B2 94 MOV:G.W R4, @H'F6B2 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17C8: 19 RTS ; cycles=12 + +loc_17C9: +17C9: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +17CE: 22 22 BHI loc_17F2 ; cycles=3/7 nt/t +17D0: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +17D4: 27 1C BEQ loc_17F2 ; cycles=3/7 nt/t +17D6: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17DA: 1D F6 CE 34 SUB.W @H'F6CE, R4 ; refs ram_F6CE in on_chip_ram; cycles=7 +17DE: 5B 00 A3 MOV:I.W #H'00A3, R3 ; dataflow R3=H'00A3; cycles=3 +17E1: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +17E5: 27 08 BEQ loc_17EF ; cycles=3/8 nt/t +17E7: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +17EB: 27 02 BEQ loc_17EF ; cycles=3/8 nt/t +17ED: AB CE BSET.W #14, R3 ; cycles=3 + +loc_17EF: +17EF: 1E 01 B0 BSR loc_19A2 ; cycles=14 + +loc_17F2: +17F2: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17F6: 1D F6 CE 94 MOV:G.W R4, @H'F6CE ; refs ram_F6CE in on_chip_ram; cycles=7 +17FA: 19 RTS ; cycles=12 + +loc_17FB: +17FB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1800: 22 22 BHI loc_1824 ; cycles=3/7 nt/t +1802: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +1806: 27 1C BEQ loc_1824 ; cycles=3/7 nt/t +1808: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +180C: 1D F6 CC 34 SUB.W @H'F6CC, R4 ; refs ram_F6CC in on_chip_ram; cycles=7 +1810: 5B 00 A4 MOV:I.W #H'00A4, R3 ; dataflow R3=H'00A4; cycles=3 +1813: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1817: 27 08 BEQ loc_1821 ; cycles=3/8 nt/t +1819: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +181D: 27 02 BEQ loc_1821 ; cycles=3/8 nt/t +181F: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1821: +1821: 1E 01 7E BSR loc_19A2 ; cycles=14 + +loc_1824: +1824: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +1828: 1D F6 CC 94 MOV:G.W R4, @H'F6CC ; refs ram_F6CC in on_chip_ram; cycles=7 +182C: 19 RTS ; cycles=12 + +loc_182D: +182D: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1831: 26 32 BNE loc_1865 ; cycles=3/8 nt/t +1833: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1838: 22 22 BHI loc_185C ; cycles=3/7 nt/t +183A: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +183E: 27 1C BEQ loc_185C ; cycles=3/7 nt/t +1840: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1844: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1848: 5B 00 A5 MOV:I.W #H'00A5, R3 ; dataflow R3=H'00A5; cycles=3 +184B: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +184F: 27 08 BEQ loc_1859 ; cycles=3/8 nt/t +1851: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1855: 27 02 BEQ loc_1859 ; cycles=3/8 nt/t +1857: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1859: +1859: 1E 01 46 BSR loc_19A2 ; cycles=14 + +loc_185C: +185C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1860: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1864: 19 RTS ; cycles=12 + +loc_1865: +1865: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +186A: 22 1C BHI loc_1888 ; cycles=3/7 nt/t +186C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1870: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1874: 5B 00 D8 MOV:I.W #H'00D8, R3 ; dataflow R3=H'00D8; cycles=3 +1877: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +187B: 27 08 BEQ loc_1885 ; cycles=3/8 nt/t +187D: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1881: 27 02 BEQ loc_1885 ; cycles=3/8 nt/t +1883: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1885: +1885: 1E 01 1A BSR loc_19A2 ; cycles=14 + +loc_1888: +1888: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +188C: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1890: 19 RTS ; cycles=12 + +loc_1891: +1891: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1895: 26 24 BNE loc_18BB ; cycles=3/8 nt/t +1897: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +189C: 22 14 BHI loc_18B2 ; cycles=3/7 nt/t +189E: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18A2: 27 0E BEQ loc_18B2 ; cycles=3/7 nt/t +18A4: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18A8: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18AC: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +18AF: 1E 00 F0 BSR loc_19A2 ; cycles=14 + +loc_18B2: +18B2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18B6: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18BA: 19 RTS ; cycles=12 + +loc_18BB: +18BB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18C0: 22 1C BHI loc_18DE ; cycles=3/7 nt/t +18C2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18C6: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18CA: 5B 00 D9 MOV:I.W #H'00D9, R3 ; dataflow R3=H'00D9; cycles=3 +18CD: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +18D1: 27 08 BEQ loc_18DB ; cycles=3/8 nt/t +18D3: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +18D7: 27 02 BEQ loc_18DB ; cycles=3/8 nt/t +18D9: AB CE BSET.W #14, R3 ; cycles=3 + +loc_18DB: +18DB: 1E 00 C4 BSR loc_19A2 ; cycles=14 + +loc_18DE: +18DE: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18E2: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18E6: 19 RTS ; cycles=12 + +loc_18E7: +18E7: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +18EB: 26 32 BNE loc_191F ; cycles=3/8 nt/t +18ED: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18F2: 22 22 BHI loc_1916 ; cycles=3/7 nt/t +18F4: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18F8: 27 1C BEQ loc_1916 ; cycles=3/7 nt/t +18FA: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +18FE: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +1902: 5B 00 A6 MOV:I.W #H'00A6, R3 ; dataflow R3=H'00A6; cycles=3 +1905: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1909: 27 08 BEQ loc_1913 ; cycles=3/8 nt/t +190B: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +190F: 27 02 BEQ loc_1913 ; cycles=3/8 nt/t +1911: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1913: +1913: 1E 00 8C BSR loc_19A2 ; cycles=14 + +loc_1916: +1916: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +191A: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=7 +191E: 19 RTS ; cycles=12 + +loc_191F: +191F: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1924: 22 1B BHI loc_1941 ; cycles=3/7 nt/t +1926: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +192A: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +192E: 5B 00 DA MOV:I.W #H'00DA, R3 ; dataflow R3=H'00DA; cycles=3 +1931: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1935: 27 08 BEQ loc_193F ; cycles=3/8 nt/t +1937: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +193B: 27 02 BEQ loc_193F ; cycles=3/8 nt/t +193D: AB CE BSET.W #14, R3 ; cycles=3 + +loc_193F: +193F: 0E 61 BSR loc_19A2 ; cycles=14 + +loc_1941: +1941: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=6 +1945: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=6 +1949: 19 RTS ; cycles=13 + +loc_194A: +194A: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +194F: 22 1F BHI loc_1970 ; cycles=3/8 nt/t +1951: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=6 +1955: 1D F6 C4 34 SUB.W @H'F6C4, R4 ; refs ram_F6C4 in on_chip_ram; cycles=6 +1959: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +195D: 26 00 BNE loc_195F ; cycles=3/8 nt/t + +loc_195F: +195F: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +1962: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +1966: 27 02 BEQ loc_196A ; cycles=3/7 nt/t +1968: AB CE BSET.W #14, R3 ; cycles=3 + +loc_196A: +196A: 0E 36 BSR loc_19A2 ; cycles=13 +196C: 15 F7 6D C7 BSET.B #7, @H'F76D ; refs ram_F76D in on_chip_ram; cycles=9 + +loc_1970: +1970: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=7 +1974: 1D F6 C4 94 MOV:G.W R4, @H'F6C4 ; refs ram_F6C4 in on_chip_ram; cycles=7 +1978: 19 RTS ; cycles=12 + +loc_1979: +1979: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +197E: 22 19 BHI loc_1999 ; cycles=3/7 nt/t +1980: 1D F6 A2 80 MOV:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +1984: 1D F6 C2 30 SUB.W @H'F6C2, R0 ; refs ram_F6C2 in on_chip_ram; cycles=7 +1988: 1D F6 8C A8 MULXU.W @H'F68C, R0 ; refs ram_F68C in on_chip_ram; cycles=26 +198C: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +198F: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1993: 27 02 BEQ loc_1997 ; cycles=3/8 nt/t +1995: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1997: +1997: 0E 42 BSR loc_19DB ; cycles=14 + +loc_1999: +1999: 1D F6 A2 84 MOV:G.W @H'F6A2, R4 ; refs ram_F6A2 in on_chip_ram; cycles=6 +199D: 1D F6 C2 94 MOV:G.W R4, @H'F6C2 ; refs ram_F6C2 in on_chip_ram; cycles=6 +19A1: 19 RTS ; cycles=13 + +loc_19A2: +19A2: AB 85 MOV:G.W R3, R5 ; cycles=3 +19A4: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19A8: AB 1A SHLL.W R3 ; cycles=3 +19AA: FB E4 00 80 MOV:G.W @(-H'1C00,R3), R0 ; cycles=7 +19AE: 48 FC 00 CMP:I #H'FC00, R0 ; cycles=3 +19B1: 22 03 BHI loc_19B6 ; cycles=3/8 nt/t +19B3: 58 FE 00 MOV:I.W #H'FE00, R0 ; dataflow R0=H'FE00; cycles=3 + +loc_19B6: +19B6: A8 15 NOT.W R0 ; cycles=3 +19B8: A8 08 ADD:Q.W #1, R0 ; cycles=4 +19BA: 4C 00 0F CMP:I #H'000F, R4 ; cycles=3 +19BD: 23 14 BLS loc_19D3 ; cycles=3/8 nt/t +19BF: 4C FF F0 CMP:I #H'FFF0, R4 ; cycles=3 +19C2: 24 0F BCC loc_19D3 ; cycles=3/7 nt/t +19C4: 4C 80 00 CMP:I #H'8000, R4 ; cycles=3 +19C7: 24 05 BCC loc_19CE ; cycles=3/8 nt/t +19C9: 5C 00 1A MOV:I.W #H'001A, R4 ; dataflow R4=H'001A; cycles=3 +19CC: 20 09 BRA loc_19D7 ; cycles=7 + +loc_19CE: +19CE: 5C FF 1C MOV:I.W #H'FF1C, R4 ; dataflow R4=H'FF1C; cycles=3 +19D1: 20 04 BRA loc_19D7 ; cycles=8 + +loc_19D3: +19D3: F4 1A 25 84 MOV:G.B @(H'1A25,R4), R4 ; cycles=6 + +loc_19D7: +19D7: AC A8 MULXU.W R4, R0 ; cycles=25 +19D9: 20 08 BRA loc_19E3 ; cycles=8 + +loc_19DB: +19DB: AB 85 MOV:G.W R3, R5 ; cycles=3 +19DD: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19E1: AB 1A SHLL.W R3 ; cycles=3 + +loc_19E3: +19E3: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +19E7: A8 21 ADD:G.W R0, R1 ; cycles=3 +19E9: A9 82 MOV:G.W R1, R2 ; cycles=3 +19EB: 25 0C BCS loc_19F9 ; cycles=3/8 nt/t +19ED: A8 32 SUB.W R0, R2 ; cycles=3 +19EF: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +19F2: 23 0F BLS loc_1A03 ; cycles=3/7 nt/t +19F4: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +19F7: 20 0A BRA loc_1A03 ; cycles=8 + +loc_19F9: +19F9: AA 30 SUB.W R2, R0 ; cycles=3 +19FB: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +19FE: 23 03 BLS loc_1A03 ; cycles=3/7 nt/t +1A00: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_1A03: +1A03: FB E0 00 71 CMP:G.W @(-H'2000,R3), R1 ; cycles=6 +1A07: 27 0B BEQ loc_1A14 ; cycles=3/8 nt/t +1A09: FB E8 00 91 MOV:G.W R1, @(-H'1800,R3) ; cycles=6 +1A0D: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A0F: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A11: 1E 24 40 BSR loc_3E54 ; cycles=14 + +loc_1A14: +1A14: 19 RTS ; cycles=12 + +loc_1A35: +1A35: AB 85 MOV:G.W R3, R5 ; cycles=3 +1A37: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +1A3B: AB 1A SHLL.W R3 ; cycles=3 +1A3D: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +1A41: 27 3A BEQ loc_1A7D ; cycles=3/8 nt/t +1A43: 0E 48 BSR loc_1A8D ; cycles=14 + +loc_1A45: +1A45: AC 16 TST.W R4 ; cycles=3 +1A47: 26 10 BNE loc_1A59 ; cycles=3/8 nt/t +1A49: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A4B: +1A4B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A4F: A8 1B SHLR.W R0 ; cycles=3 +1A51: 27 16 BEQ loc_1A69 ; cycles=3/8 nt/t +1A53: A8 51 AND.W R0, R1 ; cycles=3 +1A55: 27 F4 BEQ loc_1A4B ; cycles=3/8 nt/t +1A57: 20 12 BRA loc_1A6B ; cycles=8 + +loc_1A59: +1A59: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A5B: +1A5B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A5F: A8 1A SHLL.W R0 ; cycles=3 +1A61: 27 06 BEQ loc_1A69 ; cycles=3/8 nt/t +1A63: A8 51 AND.W R0, R1 ; cycles=3 +1A65: 27 F4 BEQ loc_1A5B ; cycles=3/8 nt/t +1A67: 20 02 BRA loc_1A6B ; cycles=8 + +loc_1A69: +1A69: AA 80 MOV:G.W R2, R0 ; cycles=3 + +loc_1A6B: +1A6B: FB E0 00 70 CMP:G.W @(-H'2000,R3), R0 ; cycles=6 +1A6F: 27 0B BEQ loc_1A7C ; cycles=3/8 nt/t +1A71: FB E8 00 90 MOV:G.W R0, @(-H'1800,R3) ; cycles=6 +1A75: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A77: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A79: 1E 23 D8 BSR loc_3E54 ; cycles=14 + +loc_1A7C: +1A7C: 19 RTS ; cycles=12 + +loc_1A7D: +1A7D: A8 CF BSET.W #15, R0 ; cycles=3 + +loc_1A7F: +1A7F: A8 81 MOV:G.W R0, R1 ; cycles=3 +1A81: FB E4 00 51 AND.W @(-H'1C00,R3), R1 ; cycles=6 +1A85: 26 04 BNE loc_1A8B ; cycles=3/8 nt/t +1A87: A8 1B SHLR.W R0 ; cycles=3 +1A89: 20 F4 BRA loc_1A7F ; cycles=8 + +loc_1A8B: +1A8B: 20 B8 BRA loc_1A45 ; cycles=8 + +loc_1A8D: +1A8D: 59 00 0F MOV:I.W #H'000F, R1 ; dataflow R1=H'000F; cycles=3 + +loc_1A90: +1A90: A8 79 BTST.W R1, R0 ; cycles=3 +1A92: 26 03 BNE loc_1A97 ; cycles=3/7 nt/t +1A94: 01 B9 F9 SCB/F R1, loc_1A90 ; cycles=3/4/8 false/-1/t + +loc_1A97: +1A97: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +1A99: A8 49 BSET.W R1, R0 ; cycles=3 +1A9B: 19 RTS ; cycles=13 + +loc_1A9C: +1A9C: AB 16 TST.W R3 ; cycles=3 +1A9E: 27 32 BEQ loc_1AD2 ; cycles=3/7 nt/t +1AA0: AB 1A SHLL.W R3 ; cycles=3 +1AA2: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +1AA6: A0 15 NOT.B R0 ; cycles=2 +1AA8: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AAB: AC 16 TST.W R4 ; cycles=3 +1AAD: 26 0D BNE loc_1ABC ; cycles=3/8 nt/t + +loc_1AAF: +1AAF: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1AB1: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AB4: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=7 +1AB8: 27 F5 BEQ loc_1AAF ; cycles=3/7 nt/t +1ABA: 20 0B BRA loc_1AC7 ; cycles=7 + +loc_1ABC: +1ABC: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1ABE: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AC1: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=6 +1AC5: 27 F5 BEQ loc_1ABC ; cycles=3/8 nt/t + +loc_1AC7: +1AC7: A0 15 NOT.B R0 ; cycles=2 +1AC9: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1ACC: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +1AD0: 20 0E BRA loc_1AE0 ; cycles=7 + +loc_1AD2: +1AD2: AC 16 TST.W R4 ; cycles=3 +1AD4: 26 06 BNE loc_1ADC ; cycles=3/7 nt/t +1AD6: 15 F7 33 08 ADD:Q.B #1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +1ADA: 20 04 BRA loc_1AE0 ; cycles=7 + +loc_1ADC: +1ADC: 15 F7 33 0C ADD:Q.B #-1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 + +loc_1AE0: +1AE0: 1E 2E 17 BSR loc_48FA ; cycles=13 +1AE3: 19 RTS ; cycles=13 + +loc_1AE4: +1AE4: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=7 +1AE8: A0 12 EXTU.B R0 ; cycles=3 +1AEA: F0 F7 5D 81 MOV:G.B @(-H'08A3,R0), R1 ; cycles=7 +1AEE: AC 16 TST.W R4 ; cycles=3 +1AF0: 26 0A BNE loc_1AFC ; cycles=3/7 nt/t +1AF2: A1 08 ADD:Q.B #1, R1 ; cycles=4 +1AF4: 41 2E CMP:E #H'2E, R1 ; cycles=2 +1AF6: 23 0B BLS loc_1B03 ; cycles=3/7 nt/t +1AF8: 51 00 MOV:E.B #H'00, R1 ; dataflow R1=H'00; cycles=2 +1AFA: 20 07 BRA loc_1B03 ; cycles=7 + +loc_1AFC: +1AFC: 04 01 31 SUB.B #H'01, R1 ; cycles=3 +1AFF: 24 02 BCC loc_1B03 ; cycles=3/8 nt/t +1B01: 51 2E MOV:E.B #H'2E, R1 ; dataflow R1=H'2E; cycles=2 + +loc_1B03: +1B03: F0 F7 5D 91 MOV:G.B R1, @(-H'08A3,R0) ; cycles=6 +1B07: 1E 2D F0 BSR loc_48FA ; cycles=14 +1B0A: 19 RTS ; cycles=12 + +loc_1B0B: +1B0B: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=6 +1B0F: AC 16 TST.W R4 ; cycles=3 +1B11: 26 0A BNE loc_1B1D ; cycles=3/8 nt/t +1B13: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1B15: 40 08 CMP:E #H'08, R0 ; cycles=2 +1B17: 23 0C BLS loc_1B25 ; cycles=3/8 nt/t +1B19: 50 08 MOV:E.B #H'08, R0 ; dataflow R0=H'08; cycles=2 +1B1B: 20 08 BRA loc_1B25 ; cycles=8 + +loc_1B1D: +1B1D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1B1F: 40 01 CMP:E #H'01, R0 ; cycles=2 +1B21: 24 02 BCC loc_1B25 ; cycles=3/8 nt/t +1B23: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_1B25: +1B25: 15 F7 5B 90 MOV:G.B R0, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=6 +1B29: 1E 2D CE BSR loc_48FA ; cycles=14 +1B2C: 19 RTS ; cycles=12 + +loc_1B2D: +1B2D: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B31: 15 F6 E7 64 XOR.B @H'F6E7, R4 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B35: 5D 00 7E MOV:I.W #H'007E, R5 ; dataflow R5=H'007E; cycles=3 +1B38: 1E 00 D3 BSR loc_1C0E ; cycles=13 +1B3B: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B3F: 15 F6 E7 94 MOV:G.B R4, @H'F6E7 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B43: 19 RTS ; cycles=13 + +loc_1B44: +1B44: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B48: 15 F6 E6 64 XOR.B @H'F6E6, R4 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B4C: 5D 00 6E MOV:I.W #H'006E, R5 ; dataflow R5=H'006E; cycles=3 +1B4F: 1E 00 BC BSR loc_1C0E ; cycles=14 +1B52: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B56: 15 F6 E6 94 MOV:G.B R4, @H'F6E6 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B5A: 19 RTS ; cycles=12 + +loc_1B5B: +1B5B: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B5F: 15 F6 E5 64 XOR.B @H'F6E5, R4 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B63: 5D 00 5E MOV:I.W #H'005E, R5 ; dataflow R5=H'005E; cycles=3 +1B66: 1E 00 A5 BSR loc_1C0E ; cycles=13 +1B69: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B6D: 15 F6 E5 94 MOV:G.B R4, @H'F6E5 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B71: 19 RTS ; cycles=13 + +loc_1B72: +1B72: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B76: 15 F6 E1 64 XOR.B @H'F6E1, R4 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B7A: 5D 00 1E MOV:I.W #H'001E, R5 ; dataflow R5=H'001E; cycles=3 +1B7D: 1E 00 8E BSR loc_1C0E ; cycles=14 +1B80: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B84: 15 F6 E1 94 MOV:G.B R4, @H'F6E1 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B88: 19 RTS ; cycles=12 + +loc_1B89: +1B89: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B8D: 15 F6 E0 64 XOR.B @H'F6E0, R4 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B91: 5D 00 0E MOV:I.W #H'000E, R5 ; dataflow R5=H'000E; cycles=3 +1B94: 1E 00 77 BSR loc_1C0E ; cycles=13 +1B97: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B9B: 15 F6 E0 94 MOV:G.B R4, @H'F6E0 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B9F: 19 RTS ; cycles=13 + +loc_1BA0: +1BA0: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=7 +1BA4: 15 F6 E4 64 XOR.B @H'F6E4, R4 ; refs ram_F6E4 in on_chip_ram; cycles=7 +1BA8: 5D 00 4E MOV:I.W #H'004E, R5 ; dataflow R5=H'004E; cycles=3 +1BAB: 0E 61 BSR loc_1C0E ; cycles=14 +1BAD: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=6 +1BB1: 15 F6 E4 94 MOV:G.B R4, @H'F6E4 ; refs ram_F6E4 in on_chip_ram; cycles=6 +1BB5: 19 RTS ; cycles=13 + +loc_1BB6: +1BB6: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=7 +1BBA: 15 F6 E3 64 XOR.B @H'F6E3, R4 ; refs ram_F6E3 in on_chip_ram; cycles=7 +1BBE: 5D 00 3E MOV:I.W #H'003E, R5 ; dataflow R5=H'003E; cycles=3 +1BC1: 0E 4B BSR loc_1C0E ; cycles=14 +1BC3: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=6 +1BC7: 15 F6 E3 94 MOV:G.B R4, @H'F6E3 ; refs ram_F6E3 in on_chip_ram; cycles=6 +1BCB: 19 RTS ; cycles=13 + +loc_1BCC: +1BCC: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=7 +1BD0: 15 F6 E2 64 XOR.B @H'F6E2, R4 ; refs ram_F6E2 in on_chip_ram; cycles=7 +1BD4: 5D 00 2E MOV:I.W #H'002E, R5 ; dataflow R5=H'002E; cycles=3 +1BD7: 0E 35 BSR loc_1C0E ; cycles=14 +1BD9: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=6 +1BDD: 15 F6 E2 94 MOV:G.B R4, @H'F6E2 ; refs ram_F6E2 in on_chip_ram; cycles=6 +1BE1: 19 RTS ; cycles=13 + +loc_1BE2: +1BE2: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=7 +1BE6: 15 F6 EC 64 XOR.B @H'F6EC, R4 ; refs ram_F6EC in on_chip_ram; cycles=7 +1BEA: 5D 00 CE MOV:I.W #H'00CE, R5 ; dataflow R5=H'00CE; cycles=3 +1BED: 0E 1F BSR loc_1C0E ; cycles=14 +1BEF: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=6 +1BF3: 15 F6 EC 94 MOV:G.B R4, @H'F6EC ; refs ram_F6EC in on_chip_ram; cycles=6 +1BF7: 19 RTS ; cycles=13 + +loc_1BF8: +1BF8: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=7 +1BFC: 15 F6 EB 64 XOR.B @H'F6EB, R4 ; refs ram_F6EB in on_chip_ram; cycles=7 +1C00: 5D 00 BE MOV:I.W #H'00BE, R5 ; dataflow R5=H'00BE; cycles=3 +1C03: 0E 09 BSR loc_1C0E ; cycles=14 +1C05: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=6 +1C09: 15 F6 EB 94 MOV:G.B R4, @H'F6EB ; refs ram_F6EB in on_chip_ram; cycles=6 +1C0D: 19 RTS ; cycles=13 + +loc_1C0E: +1C0E: A4 1A SHLL.B R4 ; cycles=2 +1C10: 24 0A BCC loc_1C1C ; cycles=3/7 nt/t +1C12: FD 27 06 80 MOV:G.W @(H'2706,R5), R0 ; cycles=7 +1C16: 12 30 STM.W {R4,R5}, @-SP ; cycles=12 +1C18: 11 D8 JSR @R0 ; JSR @R0 uses R0; target not resolved; cycles=13 +1C1A: 02 30 LDM.W @SP+, {R4,R5} ; cycles=14 + +loc_1C1C: +1C1C: A4 16 TST.B R4 ; cycles=2 +1C1E: 27 04 BEQ loc_1C24 ; cycles=3/7 nt/t +1C20: AD 0D ADD:Q.W #-2, R5 ; cycles=4 +1C22: 20 EA BRA loc_1C0E ; cycles=7 + +loc_1C24: +1C24: 19 RTS ; cycles=12 + +loc_2127: +2127: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=8 +212B: 26 08 BNE loc_2135 ; cycles=3/8 nt/t +212D: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=6 +2131: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=6 + +loc_2135: +2135: 1D F7 32 07 1C 03 MOV:G.W #H'1C03, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +213B: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +2140: 1E 27 B7 BSR loc_48FA ; cycles=13 +2143: 19 RTS ; cycles=13 + +loc_2650: +2650: 15 F6 F6 D5 BCLR.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +2654: 37 00 68 BEQ loc_26BF ; cycles=3/7 nt/t +2657: 1D E1 24 80 MOV:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +265B: A8 1A SHLL.W R0 ; cycles=3 +265D: A0 10 SWAP.B R0 ; cycles=3 +265F: 15 F6 F6 F6 BTST.B #6, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=6 +2663: 26 08 BNE loc_266D ; cycles=3/8 nt/t +2665: A0 08 ADD:Q.B #1, R0 ; cycles=4 +2667: 24 1A BCC loc_2683 ; cycles=3/8 nt/t +2669: 50 FF MOV:E.B #H'FF, R0 ; dataflow R0=H'FF; cycles=2 +266B: 20 16 BRA loc_2683 ; cycles=8 + +loc_266D: +266D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +266F: 1D E0 04 FD BTST.W #13, @H'E004 ; refs mem_E004 in program_or_external; cycles=6 +2673: 26 08 BNE loc_267D ; cycles=3/8 nt/t +2675: 40 49 CMP:E #H'49, R0 ; cycles=2 +2677: 24 0A BCC loc_2683 ; cycles=3/8 nt/t +2679: 50 49 MOV:E.B #H'49, R0 ; dataflow R0=H'49; cycles=2 +267B: 20 06 BRA loc_2683 ; cycles=8 + +loc_267D: +267D: 40 16 CMP:E #H'16, R0 ; cycles=2 +267F: 24 02 BCC loc_2683 ; cycles=3/8 nt/t +2681: 50 16 MOV:E.B #H'16, R0 ; dataflow R0=H'16; cycles=2 + +loc_2683: +2683: A0 12 EXTU.B R0 ; cycles=3 +2685: A0 10 SWAP.B R0 ; cycles=3 +2687: A8 1B SHLR.W R0 ; cycles=3 +2689: A8 CF BSET.W #15, R0 ; cycles=3 +268B: 1D E1 24 70 CMP:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +268F: 27 2E BEQ loc_26BF ; cycles=3/8 nt/t +2691: 1D E9 24 90 MOV:G.W R0, @H'E924 ; refs mem_E924 in program_or_external; cycles=6 +2695: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +2697: 5B 00 92 MOV:I.W #H'0092, R3 ; dataflow R3=H'0092; cycles=3 +269A: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +269E: 27 08 BEQ loc_26A8 ; cycles=3/7 nt/t +26A0: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs mem_F404 in program_or_external; cycles=7 +26A4: 27 02 BEQ loc_26A8 ; cycles=3/7 nt/t +26A6: AB CE BSET.W #14, R3 ; cycles=3 + +loc_26A8: +26A8: 1E 17 A9 BSR loc_3E54 ; cycles=13 +26AB: 15 F6 F6 C0 BSET.B #0, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=8 +26AF: 26 08 BNE loc_26B9 ; cycles=3/8 nt/t +26B1: 1D F6 F4 07 07 D0 MOV:G.W #H'07D0, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 +26B7: 20 06 BRA loc_26BF ; cycles=8 + +loc_26B9: +26B9: 1D F6 F4 07 00 C8 MOV:G.W #H'00C8, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_26BF: +26BF: 19 RTS ; cycles=13 + +loc_2806: +2806: 15 F9 B9 81 MOV:G.B @H'F9B9, R1 ; refs ram_F9B9 in on_chip_ram; cycles=7 +280A: A1 12 EXTU.B R1 ; cycles=3 +280C: 15 F9 B4 71 CMP:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +2810: 26 03 BNE loc_2815 ; cycles=3/7 nt/t +2812: 30 04 91 BRA loc_2CA6 ; cycles=7 + +loc_2815: +2815: A9 80 MOV:G.W R1, R0 ; cycles=3 +2817: A8 1A SHLL.W R0 ; cycles=3 +2819: F8 F9 70 80 MOV:G.W @(-H'0690,R0), R0 ; cycles=6 +281D: A1 08 ADD:Q.B #1, R1 ; cycles=4 +281F: 04 1F 51 AND.B #H'1F, R1 ; cycles=3 +2822: 15 F9 B9 91 MOV:G.B R1, @H'F9B9 ; refs ram_F9B9 in on_chip_ram; cycles=7 +2826: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +282A: A8 85 MOV:G.W R0, R5 ; cycles=3 +282C: 1E 39 D7 BSR loc_6206 ; cycles=13 +282F: A8 84 MOV:G.W R0, R4 ; cycles=3 +2831: AC 1A SHLL.W R4 ; cycles=3 +2833: A8 16 TST.W R0 ; cycles=3 +2835: 27 68 BEQ loc_289F ; cycles=3/8 nt/t +2837: 1D F7 36 81 MOV:G.W @H'F736, R1 ; refs ram_F736 in on_chip_ram; cycles=6 +283B: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +283F: A9 70 CMP:G.W R1, R0 ; cycles=3 +2841: 37 04 67 BEQ loc_2CAB ; cycles=3/8 nt/t +2844: 1D F7 38 81 MOV:G.W @H'F738, R1 ; refs ram_F738 in on_chip_ram; cycles=7 +2848: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +284C: A9 70 CMP:G.W R1, R0 ; cycles=3 +284E: 37 04 5A BEQ loc_2CAB ; cycles=3/7 nt/t +2851: 1D F7 3A 81 MOV:G.W @H'F73A, R1 ; refs ram_F73A in on_chip_ram; cycles=6 +2855: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2859: A9 70 CMP:G.W R1, R0 ; cycles=3 +285B: 37 04 4D BEQ loc_2CAB ; cycles=3/8 nt/t +285E: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs ram_F73C in on_chip_ram; cycles=7 +2862: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2866: A9 70 CMP:G.W R1, R0 ; cycles=3 +2868: 37 04 40 BEQ loc_2CAB ; cycles=3/7 nt/t +286B: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +286F: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2873: A9 70 CMP:G.W R1, R0 ; cycles=3 +2875: 37 04 33 BEQ loc_2CAB ; cycles=3/8 nt/t +2878: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs ram_F740 in on_chip_ram; cycles=7 +287C: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2880: A9 70 CMP:G.W R1, R0 ; cycles=3 +2882: 37 04 26 BEQ loc_2CAB ; cycles=3/7 nt/t +2885: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +2889: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +288D: A9 70 CMP:G.W R1, R0 ; cycles=3 +288F: 37 04 19 BEQ loc_2CAB ; cycles=3/8 nt/t +2892: 1D F7 54 81 MOV:G.W @H'F754, R1 ; refs ram_F754 in on_chip_ram; cycles=7 +2896: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +289A: A9 70 CMP:G.W R1, R0 ; cycles=3 +289C: 37 04 0C BEQ loc_2CAB ; cycles=3/7 nt/t + +loc_289F: +289F: FC 28 A6 81 MOV:G.W @(H'28A6,R4), R1 ; cycles=6 +28A3: 11 D1 JMP @R1 ; JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets); cycles=7 + +loc_2CA6: +2CA6: 15 F7 69 D7 BCLR.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CAA: 19 RTS ; cycles=12 + +loc_2CAB: +2CAB: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +2CAD: 1E 1C 4A BSR loc_48FA ; cycles=14 +2CB0: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 +2CB2: 15 F7 69 C7 BSET.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CB6: 30 FB E6 BRA loc_289F ; cycles=7 + +loc_3930: +3930: 58 00 07 MOV:I.W #H'0007, R0 ; dataflow R0=H'0007; cycles=3 + +loc_3933: +3933: 15 FE 8E 78 BTST.B R0, @P7DR ; refs P7DR in register_field; cycles=6 +3937: 27 0A BEQ loc_3943 ; cycles=3/8 nt/t +3939: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 +393D: F0 F6 80 C0 BSET.B #0, @(-H'0980,R0) ; cycles=8 +3941: 20 04 BRA loc_3947 ; cycles=8 + +loc_3943: +3943: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 + +loc_3947: +3947: F0 F6 80 04 FF CMP:G.B #H'FF, @(-H'0980,R0) ; cycles=6 +394C: 26 06 BNE loc_3954 ; cycles=3/7 nt/t +394E: 15 F6 88 48 BSET.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=9 +3952: 20 0B BRA loc_395F ; cycles=7 + +loc_3954: +3954: F0 F6 80 04 00 CMP:G.B #H'00, @(-H'0980,R0) ; cycles=7 +3959: 26 04 BNE loc_395F ; cycles=3/8 nt/t +395B: 15 F6 88 58 BCLR.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=8 + +loc_395F: +395F: 01 B8 D1 SCB/F R0, loc_3933 ; cycles=3/4/9 false/-1/t +3962: 15 F7 22 08 ADD:Q.B #1, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=9 +3966: 15 F7 22 04 3C CMP:G.B #H'3C, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +396B: 27 0F BEQ loc_397C ; cycles=3/8 nt/t +396D: 15 F7 22 04 78 CMP:G.B #H'78, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=6 +3972: 27 0B BEQ loc_397F ; cycles=3/7 nt/t +3974: 15 F7 22 04 B4 CMP:G.B #H'B4, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +3979: 27 08 BEQ loc_3983 ; cycles=3/8 nt/t +397B: 19 RTS ; cycles=13 + +loc_397C: +397C: 0E 17 BSR loc_3995 ; cycles=13 +397E: 19 RTS ; cycles=12 + +loc_397F: +397F: 1E 00 AC BSR loc_3A2E ; cycles=14 +3982: 19 RTS ; cycles=12 + +loc_3983: +3983: 0E 05 BSR loc_398A ; cycles=14 +3985: 15 F7 22 13 CLR.B @H'F722 ; refs ram_F722 in on_chip_ram; cycles=8 +3989: 19 RTS ; cycles=13 + +loc_398A: +398A: 15 FE E8 F7 BTST.B #7, @ADCSR ; refs ADCSR in register_field; cycles=7 +398E: 26 04 BNE loc_3994 ; cycles=3/7 nt/t +3990: 15 FE E8 C5 BSET.B #5, @ADCSR ; set ADST (bit 5) of ADCSR; cycles=9 + +loc_3994: +3994: 19 RTS ; cycles=12 + +loc_3995: +3995: 15 F7 20 16 TST.B @H'F720 ; refs ram_F720 in on_chip_ram; cycles=6 +3999: 36 00 91 BNE loc_3A2D ; cycles=3/8 nt/t +399C: 15 F1 01 06 A0 MOV:G.B #H'A0, @H'F101 ; refs mem_F101 in program_or_external; cycles=9 +39A1: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +39A5: 37 00 85 BEQ loc_3A2D ; cycles=3/8 nt/t +39A8: 15 F7 1B 80 MOV:G.B @H'F71B, R0 ; refs ram_F71B in on_chip_ram; cycles=7 +39AC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39B0: 15 F7 13 50 AND.B @H'F713, R0 ; refs ram_F713 in on_chip_ram; cycles=7 +39B4: 15 F1 02 90 MOV:G.B R0, @H'F102 ; refs mem_F102 in program_or_external; cycles=7 +39B8: 15 F7 1A 80 MOV:G.B @H'F71A, R0 ; refs ram_F71A in on_chip_ram; cycles=7 +39BC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39C0: 15 F7 12 50 AND.B @H'F712, R0 ; refs ram_F712 in on_chip_ram; cycles=7 +39C4: 15 F1 03 90 MOV:G.B R0, @H'F103 ; refs mem_F103 in program_or_external; cycles=7 +39C8: 15 F7 19 80 MOV:G.B @H'F719, R0 ; refs ram_F719 in on_chip_ram; cycles=7 +39CC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39D0: 15 F7 11 50 AND.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=7 +39D4: 15 F1 04 90 MOV:G.B R0, @H'F104 ; refs mem_F104 in program_or_external; cycles=7 +39D8: 15 F7 18 80 MOV:G.B @H'F718, R0 ; refs ram_F718 in on_chip_ram; cycles=7 +39DC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39E0: 15 F7 10 50 AND.B @H'F710, R0 ; refs ram_F710 in on_chip_ram; cycles=7 +39E4: 15 F1 05 90 MOV:G.B R0, @H'F105 ; refs mem_F105 in program_or_external; cycles=7 +39E8: 15 F7 02 80 MOV:G.B @H'F702, R0 ; refs ram_F702 in on_chip_ram; cycles=7 +39EC: 15 F1 09 90 MOV:G.B R0, @H'F109 ; refs mem_F109 in program_or_external; cycles=7 +39F0: 15 F7 03 80 MOV:G.B @H'F703, R0 ; refs ram_F703 in on_chip_ram; cycles=7 +39F4: 15 F1 0A 90 MOV:G.B R0, @H'F10A ; refs mem_F10A in program_or_external; cycles=7 +39F8: 15 F7 04 80 MOV:G.B @H'F704, R0 ; refs ram_F704 in on_chip_ram; cycles=7 +39FC: 15 F1 0B 90 MOV:G.B R0, @H'F10B ; refs mem_F10B in program_or_external; cycles=7 +3A00: 15 F7 05 80 MOV:G.B @H'F705, R0 ; refs ram_F705 in on_chip_ram; cycles=7 +3A04: 15 F1 0C 90 MOV:G.B R0, @H'F10C ; refs mem_F10C in program_or_external; cycles=7 +3A08: 15 F7 00 80 MOV:G.B @H'F700, R0 ; refs ram_F700 in on_chip_ram; cycles=7 +3A0C: 15 F1 0D 90 MOV:G.B R0, @H'F10D ; refs mem_F10D in program_or_external; cycles=7 +3A10: 15 F7 01 80 MOV:G.B @H'F701, R0 ; refs ram_F701 in on_chip_ram; cycles=7 +3A14: 15 F1 0E 90 MOV:G.B R0, @H'F10E ; refs mem_F10E in program_or_external; cycles=7 +3A18: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=7 +3A1C: A0 15 NOT.B R0 ; cycles=2 +3A1E: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3A21: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3A24: 15 F1 0F 90 MOV:G.B R0, @H'F10F ; refs mem_F10F in program_or_external; cycles=7 +3A28: 15 F7 20 06 03 MOV:G.B #H'03, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=9 + +loc_3A2D: +3A2D: 19 RTS ; cycles=13 + +loc_3A2E: +3A2E: 15 F7 21 16 TST.B @H'F721 ; refs ram_F721 in on_chip_ram; cycles=7 +3A32: 36 00 91 BNE loc_3AC6 ; cycles=3/7 nt/t +3A35: 15 F0 01 06 A0 MOV:G.B #H'A0, @H'F001 ; refs mem_F001 in program_or_external; cycles=9 +3A3A: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3A3E: 37 00 85 BEQ loc_3AC6 ; cycles=3/7 nt/t +3A41: 15 F7 1F 80 MOV:G.B @H'F71F, R0 ; refs ram_F71F in on_chip_ram; cycles=6 +3A45: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A49: 15 F7 17 50 AND.B @H'F717, R0 ; refs ram_F717 in on_chip_ram; cycles=6 +3A4D: 15 F0 02 90 MOV:G.B R0, @H'F002 ; refs mem_F002 in program_or_external; cycles=6 +3A51: 15 F7 1E 80 MOV:G.B @H'F71E, R0 ; refs ram_F71E in on_chip_ram; cycles=6 +3A55: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A59: 15 F7 16 50 AND.B @H'F716, R0 ; refs ram_F716 in on_chip_ram; cycles=6 +3A5D: 15 F0 03 90 MOV:G.B R0, @H'F003 ; refs mem_F003 in program_or_external; cycles=6 +3A61: 15 F7 1D 80 MOV:G.B @H'F71D, R0 ; refs ram_F71D in on_chip_ram; cycles=6 +3A65: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A69: 15 F7 15 50 AND.B @H'F715, R0 ; refs ram_F715 in on_chip_ram; cycles=6 +3A6D: 15 F0 04 90 MOV:G.B R0, @H'F004 ; refs mem_F004 in program_or_external; cycles=6 +3A71: 15 F7 1C 80 MOV:G.B @H'F71C, R0 ; refs ram_F71C in on_chip_ram; cycles=6 +3A75: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A79: 15 F7 14 50 AND.B @H'F714, R0 ; refs ram_F714 in on_chip_ram; cycles=6 +3A7D: 15 F0 05 90 MOV:G.B R0, @H'F005 ; refs mem_F005 in program_or_external; cycles=6 +3A81: 15 F7 08 80 MOV:G.B @H'F708, R0 ; refs ram_F708 in on_chip_ram; cycles=6 +3A85: 15 F0 09 90 MOV:G.B R0, @H'F009 ; refs mem_F009 in program_or_external; cycles=6 +3A89: 15 F7 09 80 MOV:G.B @H'F709, R0 ; refs ram_F709 in on_chip_ram; cycles=6 +3A8D: 15 F0 0A 90 MOV:G.B R0, @H'F00A ; refs mem_F00A in program_or_external; cycles=6 +3A91: 15 F7 0A 80 MOV:G.B @H'F70A, R0 ; refs ram_F70A in on_chip_ram; cycles=6 +3A95: 15 F0 0B 90 MOV:G.B R0, @H'F00B ; refs mem_F00B in program_or_external; cycles=6 +3A99: 15 F7 0B 80 MOV:G.B @H'F70B, R0 ; refs ram_F70B in on_chip_ram; cycles=6 +3A9D: 15 F0 0C 90 MOV:G.B R0, @H'F00C ; refs mem_F00C in program_or_external; cycles=6 +3AA1: 15 F7 06 80 MOV:G.B @H'F706, R0 ; refs ram_F706 in on_chip_ram; cycles=6 +3AA5: 15 F0 0D 90 MOV:G.B R0, @H'F00D ; refs mem_F00D in program_or_external; cycles=6 +3AA9: 15 F7 07 80 MOV:G.B @H'F707, R0 ; refs ram_F707 in on_chip_ram; cycles=6 +3AAD: 15 F0 0E 90 MOV:G.B R0, @H'F00E ; refs mem_F00E in program_or_external; cycles=6 +3AB1: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=6 +3AB5: A0 15 NOT.B R0 ; cycles=2 +3AB7: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3ABA: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3ABD: 15 F0 0F 90 MOV:G.B R0, @H'F00F ; refs mem_F00F in program_or_external; cycles=6 +3AC1: 15 F7 21 06 03 MOV:G.B #H'03, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3AC6: +3AC6: 19 RTS ; cycles=12 + +vec_irq4_3AC7: +3AC7: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +3AC9: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +3ACD: 36 01 5D BNE loc_3C2D ; cycles=3/8 nt/t +3AD0: 15 F1 0F 80 MOV:G.B @H'F10F, R0 ; refs mem_F10F in program_or_external; cycles=7 +3AD4: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3AD6: 27 08 BEQ loc_3AE0 ; cycles=3/7 nt/t +3AD8: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3ADA: 37 00 85 BEQ loc_3B62 ; cycles=3/7 nt/t +3ADD: 30 01 4D BRA loc_3C2D ; cycles=8 + +loc_3AE0: +3AE0: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3AE4: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3AE7: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3AEB: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3AEF: 1D F6 9A 70 CMP:G.W @H'F69A, R0 ; refs ram_F69A in on_chip_ram; cycles=6 +3AF3: 27 08 BEQ loc_3AFD ; cycles=3/8 nt/t +3AF5: 15 F6 F0 C5 BSET.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3AF9: 1D F6 9A 90 MOV:G.W R0, @H'F69A ; refs ram_F69A in on_chip_ram; cycles=6 + +loc_3AFD: +3AFD: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B01: 1D F6 98 70 CMP:G.W @H'F698, R0 ; refs ram_F698 in on_chip_ram; cycles=6 +3B05: 27 08 BEQ loc_3B0F ; cycles=3/8 nt/t +3B07: 15 F6 F0 C4 BSET.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B0B: 1D F6 98 90 MOV:G.W R0, @H'F698 ; refs ram_F698 in on_chip_ram; cycles=6 + +loc_3B0F: +3B0F: 1D F1 08 80 MOV:G.W @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3B13: 1D F6 96 70 CMP:G.W @H'F696, R0 ; refs ram_F696 in on_chip_ram; cycles=6 +3B17: 27 08 BEQ loc_3B21 ; cycles=3/8 nt/t +3B19: 15 F6 F0 C3 BSET.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B1D: 1D F6 96 90 MOV:G.W R0, @H'F696 ; refs ram_F696 in on_chip_ram; cycles=6 + +loc_3B21: +3B21: 1D F1 06 80 MOV:G.W @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3B25: 1D F6 94 70 CMP:G.W @H'F694, R0 ; refs ram_F694 in on_chip_ram; cycles=6 +3B29: 27 08 BEQ loc_3B33 ; cycles=3/8 nt/t +3B2B: 15 F6 F0 C2 BSET.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B2F: 1D F6 94 90 MOV:G.W R0, @H'F694 ; refs ram_F694 in on_chip_ram; cycles=6 + +loc_3B33: +3B33: 1D F1 04 80 MOV:G.W @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3B37: 1D F6 92 70 CMP:G.W @H'F692, R0 ; refs ram_F692 in on_chip_ram; cycles=6 +3B3B: 27 08 BEQ loc_3B45 ; cycles=3/8 nt/t +3B3D: 15 F6 F0 C1 BSET.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B41: 1D F6 92 90 MOV:G.W R0, @H'F692 ; refs ram_F692 in on_chip_ram; cycles=6 + +loc_3B45: +3B45: 1D F1 02 80 MOV:G.W @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3B49: 1D F6 90 70 CMP:G.W @H'F690, R0 ; refs ram_F690 in on_chip_ram; cycles=6 +3B4D: 27 08 BEQ loc_3B57 ; cycles=3/8 nt/t +3B4F: 15 F6 F0 C0 BSET.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B53: 1D F6 90 90 MOV:G.W R0, @H'F690 ; refs ram_F690 in on_chip_ram; cycles=6 + +loc_3B57: +3B57: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3B5B: 15 F7 20 D0 BCLR.B #0, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 +3B5F: 30 00 CB BRA loc_3C2D ; cycles=8 + +loc_3B62: +3B62: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3B66: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3B69: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3B6D: 15 F6 F2 13 CLR.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3B71: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3B75: 1D F6 9E 70 CMP:G.W @H'F69E, R0 ; refs ram_F69E in on_chip_ram; cycles=6 +3B79: 27 08 BEQ loc_3B83 ; cycles=3/8 nt/t +3B7B: 15 F6 F0 C7 BSET.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B7F: 1D F6 9E 90 MOV:G.W R0, @H'F69E ; refs ram_F69E in on_chip_ram; cycles=6 + +loc_3B83: +3B83: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B87: 1D F6 9C 70 CMP:G.W @H'F69C, R0 ; refs ram_F69C in on_chip_ram; cycles=6 +3B8B: 27 08 BEQ loc_3B95 ; cycles=3/8 nt/t +3B8D: 15 F6 F0 C6 BSET.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B91: 1D F6 9C 90 MOV:G.W R0, @H'F69C ; refs ram_F69C in on_chip_ram; cycles=6 + +loc_3B95: +3B95: 15 F1 09 80 MOV:G.B @H'F109, R0 ; refs mem_F109 in program_or_external; cycles=6 +3B99: 15 F6 D0 70 CMP:G.B @H'F6D0, R0 ; refs ram_F6D0 in on_chip_ram; cycles=6 +3B9D: 27 08 BEQ loc_3BA7 ; cycles=3/8 nt/t +3B9F: 15 F6 F2 C0 BSET.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BA3: 15 F6 D0 90 MOV:G.B R0, @H'F6D0 ; refs ram_F6D0 in on_chip_ram; cycles=6 + +loc_3BA7: +3BA7: 15 F1 08 80 MOV:G.B @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3BAB: 15 F6 D1 70 CMP:G.B @H'F6D1, R0 ; refs ram_F6D1 in on_chip_ram; cycles=6 +3BAF: 27 08 BEQ loc_3BB9 ; cycles=3/8 nt/t +3BB1: 15 F6 F2 C1 BSET.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BB5: 15 F6 D1 90 MOV:G.B R0, @H'F6D1 ; refs ram_F6D1 in on_chip_ram; cycles=6 + +loc_3BB9: +3BB9: 15 F1 07 80 MOV:G.B @H'F107, R0 ; refs mem_F107 in program_or_external; cycles=6 +3BBD: 15 F6 D2 70 CMP:G.B @H'F6D2, R0 ; refs ram_F6D2 in on_chip_ram; cycles=6 +3BC1: 27 08 BEQ loc_3BCB ; cycles=3/8 nt/t +3BC3: 15 F6 F2 C2 BSET.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BC7: 15 F6 D2 90 MOV:G.B R0, @H'F6D2 ; refs ram_F6D2 in on_chip_ram; cycles=6 + +loc_3BCB: +3BCB: 15 F1 06 80 MOV:G.B @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3BCF: 15 F6 D3 70 CMP:G.B @H'F6D3, R0 ; refs ram_F6D3 in on_chip_ram; cycles=6 +3BD3: 27 08 BEQ loc_3BDD ; cycles=3/8 nt/t +3BD5: 15 F6 F2 C3 BSET.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BD9: 15 F6 D3 90 MOV:G.B R0, @H'F6D3 ; refs ram_F6D3 in on_chip_ram; cycles=6 + +loc_3BDD: +3BDD: 15 F1 05 80 MOV:G.B @H'F105, R0 ; refs mem_F105 in program_or_external; cycles=6 +3BE1: 15 F6 D4 70 CMP:G.B @H'F6D4, R0 ; refs ram_F6D4 in on_chip_ram; cycles=6 +3BE5: 27 08 BEQ loc_3BEF ; cycles=3/8 nt/t +3BE7: 15 F6 F2 C4 BSET.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BEB: 15 F6 D4 90 MOV:G.B R0, @H'F6D4 ; refs ram_F6D4 in on_chip_ram; cycles=6 + +loc_3BEF: +3BEF: 15 F1 04 80 MOV:G.B @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3BF3: 15 F6 D5 70 CMP:G.B @H'F6D5, R0 ; refs ram_F6D5 in on_chip_ram; cycles=6 +3BF7: 27 08 BEQ loc_3C01 ; cycles=3/8 nt/t +3BF9: 15 F6 F2 C5 BSET.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BFD: 15 F6 D5 90 MOV:G.B R0, @H'F6D5 ; refs ram_F6D5 in on_chip_ram; cycles=6 + +loc_3C01: +3C01: 15 F1 03 80 MOV:G.B @H'F103, R0 ; refs mem_F103 in program_or_external; cycles=6 +3C05: 15 F6 D6 70 CMP:G.B @H'F6D6, R0 ; refs ram_F6D6 in on_chip_ram; cycles=6 +3C09: 27 08 BEQ loc_3C13 ; cycles=3/8 nt/t +3C0B: 15 F6 F2 C6 BSET.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C0F: 15 F6 D6 90 MOV:G.B R0, @H'F6D6 ; refs ram_F6D6 in on_chip_ram; cycles=6 + +loc_3C13: +3C13: 15 F1 02 80 MOV:G.B @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3C17: 15 F6 D7 70 CMP:G.B @H'F6D7, R0 ; refs ram_F6D7 in on_chip_ram; cycles=6 +3C1B: 27 08 BEQ loc_3C25 ; cycles=3/8 nt/t +3C1D: 15 F6 F2 C7 BSET.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C21: 15 F6 D7 90 MOV:G.B R0, @H'F6D7 ; refs ram_F6D7 in on_chip_ram; cycles=6 + +loc_3C25: +3C25: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3C29: 15 F7 20 D1 BCLR.B #1, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 + +loc_3C2D: +3C2D: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +3C2F: 0A RTE ; cycles=14 + +vec_irq3_3C30: +3C30: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +3C32: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3C36: 36 01 5D BNE loc_3D96 ; cycles=3/7 nt/t +3C39: 15 F0 0F 80 MOV:G.B @H'F00F, R0 ; refs mem_F00F in program_or_external; cycles=6 +3C3D: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3C3F: 27 08 BEQ loc_3C49 ; cycles=3/8 nt/t +3C41: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3C43: 37 00 85 BEQ loc_3CCB ; cycles=3/8 nt/t +3C46: 30 01 4D BRA loc_3D96 ; cycles=7 + +loc_3C49: +3C49: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3C4D: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3C50: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3C54: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3C58: 1D F6 AA 70 CMP:G.W @H'F6AA, R0 ; refs ram_F6AA in on_chip_ram; cycles=7 +3C5C: 27 08 BEQ loc_3C66 ; cycles=3/7 nt/t +3C5E: 15 F6 F1 C5 BSET.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C62: 1D F6 AA 90 MOV:G.W R0, @H'F6AA ; refs ram_F6AA in on_chip_ram; cycles=7 + +loc_3C66: +3C66: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3C6A: 1D F6 A8 70 CMP:G.W @H'F6A8, R0 ; refs ram_F6A8 in on_chip_ram; cycles=7 +3C6E: 27 08 BEQ loc_3C78 ; cycles=3/7 nt/t +3C70: 15 F6 F1 C4 BSET.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C74: 1D F6 A8 90 MOV:G.W R0, @H'F6A8 ; refs ram_F6A8 in on_chip_ram; cycles=7 + +loc_3C78: +3C78: 1D F0 08 80 MOV:G.W @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3C7C: 1D F6 A6 70 CMP:G.W @H'F6A6, R0 ; refs ram_F6A6 in on_chip_ram; cycles=7 +3C80: 27 08 BEQ loc_3C8A ; cycles=3/7 nt/t +3C82: 15 F6 F1 C3 BSET.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C86: 1D F6 A6 90 MOV:G.W R0, @H'F6A6 ; refs ram_F6A6 in on_chip_ram; cycles=7 + +loc_3C8A: +3C8A: 1D F0 06 80 MOV:G.W @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3C8E: 1D F6 A4 70 CMP:G.W @H'F6A4, R0 ; refs ram_F6A4 in on_chip_ram; cycles=7 +3C92: 27 08 BEQ loc_3C9C ; cycles=3/7 nt/t +3C94: 15 F6 F1 C2 BSET.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C98: 1D F6 A4 90 MOV:G.W R0, @H'F6A4 ; refs ram_F6A4 in on_chip_ram; cycles=7 + +loc_3C9C: +3C9C: 1D F0 04 80 MOV:G.W @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3CA0: 1D F6 A2 70 CMP:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +3CA4: 27 08 BEQ loc_3CAE ; cycles=3/7 nt/t +3CA6: 15 F6 F1 C1 BSET.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CAA: 1D F6 A2 90 MOV:G.W R0, @H'F6A2 ; refs ram_F6A2 in on_chip_ram; cycles=7 + +loc_3CAE: +3CAE: 1D F0 02 80 MOV:G.W @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3CB2: 1D F6 A0 70 CMP:G.W @H'F6A0, R0 ; refs ram_F6A0 in on_chip_ram; cycles=7 +3CB6: 27 08 BEQ loc_3CC0 ; cycles=3/7 nt/t +3CB8: 15 F6 F1 C0 BSET.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CBC: 1D F6 A0 90 MOV:G.W R0, @H'F6A0 ; refs ram_F6A0 in on_chip_ram; cycles=7 + +loc_3CC0: +3CC0: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3CC4: 15 F7 21 D0 BCLR.B #0, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 +3CC8: 30 00 CB BRA loc_3D96 ; cycles=7 + +loc_3CCB: +3CCB: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3CCF: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3CD2: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3CD6: 15 F6 F3 13 CLR.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3CDA: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3CDE: 1D F6 AE 70 CMP:G.W @H'F6AE, R0 ; refs ram_F6AE in on_chip_ram; cycles=7 +3CE2: 27 08 BEQ loc_3CEC ; cycles=3/7 nt/t +3CE4: 15 F6 F1 C7 BSET.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CE8: 1D F6 AE 90 MOV:G.W R0, @H'F6AE ; refs ram_F6AE in on_chip_ram; cycles=7 + +loc_3CEC: +3CEC: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3CF0: 1D F6 AC 70 CMP:G.W @H'F6AC, R0 ; refs ram_F6AC in on_chip_ram; cycles=7 +3CF4: 27 08 BEQ loc_3CFE ; cycles=3/7 nt/t +3CF6: 15 F6 F1 C6 BSET.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CFA: 1D F6 AC 90 MOV:G.W R0, @H'F6AC ; refs ram_F6AC in on_chip_ram; cycles=7 + +loc_3CFE: +3CFE: 15 F0 09 80 MOV:G.B @H'F009, R0 ; refs mem_F009 in program_or_external; cycles=7 +3D02: 15 F6 D8 70 CMP:G.B @H'F6D8, R0 ; refs ram_F6D8 in on_chip_ram; cycles=7 +3D06: 27 08 BEQ loc_3D10 ; cycles=3/7 nt/t +3D08: 15 F6 F3 C0 BSET.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D0C: 15 F6 D8 90 MOV:G.B R0, @H'F6D8 ; refs ram_F6D8 in on_chip_ram; cycles=7 + +loc_3D10: +3D10: 15 F0 08 80 MOV:G.B @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3D14: 15 F6 D9 70 CMP:G.B @H'F6D9, R0 ; refs ram_F6D9 in on_chip_ram; cycles=7 +3D18: 27 08 BEQ loc_3D22 ; cycles=3/7 nt/t +3D1A: 15 F6 F3 C1 BSET.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D1E: 15 F6 D9 90 MOV:G.B R0, @H'F6D9 ; refs ram_F6D9 in on_chip_ram; cycles=7 + +loc_3D22: +3D22: 15 F0 07 80 MOV:G.B @H'F007, R0 ; refs mem_F007 in program_or_external; cycles=7 +3D26: 15 F6 DA 70 CMP:G.B @H'F6DA, R0 ; refs ram_F6DA in on_chip_ram; cycles=7 +3D2A: 27 08 BEQ loc_3D34 ; cycles=3/7 nt/t +3D2C: 15 F6 F3 C2 BSET.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D30: 15 F6 DA 90 MOV:G.B R0, @H'F6DA ; refs ram_F6DA in on_chip_ram; cycles=7 + +loc_3D34: +3D34: 15 F0 06 80 MOV:G.B @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3D38: 15 F6 DB 70 CMP:G.B @H'F6DB, R0 ; refs ram_F6DB in on_chip_ram; cycles=7 +3D3C: 27 08 BEQ loc_3D46 ; cycles=3/7 nt/t +3D3E: 15 F6 F3 C3 BSET.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D42: 15 F6 DB 90 MOV:G.B R0, @H'F6DB ; refs ram_F6DB in on_chip_ram; cycles=7 + +loc_3D46: +3D46: 15 F0 05 80 MOV:G.B @H'F005, R0 ; refs mem_F005 in program_or_external; cycles=7 +3D4A: 15 F6 DC 70 CMP:G.B @H'F6DC, R0 ; refs ram_F6DC in on_chip_ram; cycles=7 +3D4E: 27 08 BEQ loc_3D58 ; cycles=3/7 nt/t +3D50: 15 F6 F3 C4 BSET.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D54: 15 F6 DC 90 MOV:G.B R0, @H'F6DC ; refs ram_F6DC in on_chip_ram; cycles=7 + +loc_3D58: +3D58: 15 F0 04 80 MOV:G.B @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3D5C: 15 F6 DD 70 CMP:G.B @H'F6DD, R0 ; refs ram_F6DD in on_chip_ram; cycles=7 +3D60: 27 08 BEQ loc_3D6A ; cycles=3/7 nt/t +3D62: 15 F6 F3 C5 BSET.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D66: 15 F6 DD 90 MOV:G.B R0, @H'F6DD ; refs ram_F6DD in on_chip_ram; cycles=7 + +loc_3D6A: +3D6A: 15 F0 03 80 MOV:G.B @H'F003, R0 ; refs mem_F003 in program_or_external; cycles=7 +3D6E: 15 F6 DE 70 CMP:G.B @H'F6DE, R0 ; refs ram_F6DE in on_chip_ram; cycles=7 +3D72: 27 08 BEQ loc_3D7C ; cycles=3/7 nt/t +3D74: 15 F6 F3 C6 BSET.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D78: 15 F6 DE 90 MOV:G.B R0, @H'F6DE ; refs ram_F6DE in on_chip_ram; cycles=7 + +loc_3D7C: +3D7C: 15 F0 02 80 MOV:G.B @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3D80: 15 F6 DF 70 CMP:G.B @H'F6DF, R0 ; refs ram_F6DF in on_chip_ram; cycles=7 +3D84: 27 08 BEQ loc_3D8E ; cycles=3/7 nt/t +3D86: 15 F6 F3 C7 BSET.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D8A: 15 F6 DF 90 MOV:G.B R0, @H'F6DF ; refs ram_F6DF in on_chip_ram; cycles=7 + +loc_3D8E: +3D8E: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3D92: 15 F7 21 D1 BCLR.B #1, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3D96: +3D96: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +3D98: 0A RTE ; cycles=13 + +vec_ad_adi_3D99: +3D99: 15 FE E8 D5 BCLR.B #5, @ADCSR ; clear ADST (bit 5) of ADCSR; cycles=8 +3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DA3: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; ADDRA word read; TEMP byte-order hazard avoided; refs ADDRA_H in register_field; cycles=7 +3DAA: A1 10 SWAP.B R1 ; cycles=3 +3DAC: A1 12 EXTU.B R1 ; cycles=3 +3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 ; cycles=7 +3DB2: A9 20 ADD:G.W R1, R0 ; cycles=3 +3DB4: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3DB7: 15 F6 8A 70 CMP:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DBB: 27 4B BEQ loc_3E08 ; cycles=3/8 nt/t +3DBD: 15 F6 8A 82 MOV:G.B @H'F68A, R2 ; refs ram_F68A in on_chip_ram; cycles=6 +3DC1: 15 F6 8A 90 MOV:G.B R0, @H'F68A ; refs ram_F68A in on_chip_ram; cycles=6 +3DC5: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +3DCA: 22 3C BHI loc_3E08 ; cycles=3/7 nt/t +3DCC: A0 12 EXTU.B R0 ; cycles=3 +3DCE: A2 12 EXTU.B R2 ; cycles=3 +3DD0: 0C 01 01 A8 MULXU.W #H'0101, R0 ; cycles=25 +3DD4: 0C 01 01 AA MULXU.W #H'0101, R2 ; cycles=25 +3DD8: AB 31 SUB.W R3, R1 ; cycles=3 +3DDA: 1D E1 02 80 MOV:G.W @H'E102, R0 ; refs mem_E102 in program_or_external; cycles=7 +3DDE: A8 21 ADD:G.W R0, R1 ; cycles=3 +3DE0: A9 82 MOV:G.W R1, R2 ; cycles=3 +3DE2: 25 0C BCS loc_3DF0 ; cycles=3/7 nt/t +3DE4: A8 32 SUB.W R0, R2 ; cycles=3 +3DE6: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +3DE9: 23 0F BLS loc_3DFA ; cycles=3/8 nt/t +3DEB: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +3DEE: 20 0A BRA loc_3DFA ; cycles=7 + +loc_3DF0: +3DF0: AA 30 SUB.W R2, R0 ; cycles=3 +3DF2: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +3DF5: 23 03 BLS loc_3DFA ; cycles=3/8 nt/t +3DF7: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_3DFA: +3DFA: 1D E1 02 71 CMP:G.W @H'E102, R1 ; refs mem_E102 in program_or_external; cycles=7 +3DFE: 27 08 BEQ loc_3E08 ; cycles=3/7 nt/t +3E00: 1D F6 8E 91 MOV:G.W R1, @H'F68E ; refs ram_F68E in on_chip_ram; cycles=7 +3E04: 15 F6 89 C7 BSET.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=9 + +loc_3E08: +3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E0C: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; ADDRB word read; TEMP byte-order hazard avoided; refs ADDRB_H in register_field; cycles=6 +3E13: A1 10 SWAP.B R1 ; cycles=3 +3E15: A1 12 EXTU.B R1 ; cycles=3 +3E17: A9 20 ADD:G.W R1, R0 ; cycles=3 +3E19: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3E1C: 1D F6 8C 16 TST.W @H'F68C ; refs ram_F68C in on_chip_ram; cycles=7 +3E20: 27 06 BEQ loc_3E28 ; cycles=3/7 nt/t +3E22: 15 F6 8B 70 CMP:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E26: 27 25 BEQ loc_3E4D ; cycles=3/7 nt/t + +loc_3E28: +3E28: 15 F6 8B 90 MOV:G.B R0, @H'F68B ; refs ram_F68B in on_chip_ram; cycles=7 +3E2C: A0 12 EXTU.B R0 ; cycles=3 +3E2E: A8 83 MOV:G.W R0, R3 ; cycles=3 +3E30: A3 AB MULXU.B R3, R3 ; cycles=18 +3E32: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +3E34: 0C 00 C8 BA DIVXU.W #H'00C8, R2 ; cycles=29 +3E38: 04 04 A8 MULXU.B #H'04, R0 ; cycles=19 +3E3B: 0C 00 AB 20 ADD:G.W #H'00AB, R0 ; cycles=4 +3E3F: AB 20 ADD:G.W R3, R0 ; cycles=3 +3E41: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +3E45: 26 02 BNE loc_3E49 ; cycles=3/8 nt/t +3E47: A8 1B SHLR.W R0 ; cycles=3 + +loc_3E49: +3E49: 1D F6 8C 90 MOV:G.W R0, @H'F68C ; refs ram_F68C in on_chip_ram; cycles=6 + +loc_3E4D: +3E4D: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 +3E4F: 15 FE E8 D7 BCLR.B #7, @ADCSR ; clear ADF (bit 7) of ADCSR; cycles=8 +3E53: 0A RTE ; cycles=14 + +loc_3E54: +3E54: A2 F7 BTST.B #7, R2 ; cycles=2 +3E56: 27 42 BEQ loc_3E9A ; cycles=3/7 nt/t +3E58: 15 F9 B5 80 MOV:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=7 +3E5C: A0 12 EXTU.B R0 ; cycles=3 +3E5E: A8 1A SHLL.W R0 ; cycles=3 +3E60: 15 F9 B0 81 MOV:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E64: A1 12 EXTU.B R1 ; cycles=3 +3E66: A9 1A SHLL.W R1 ; cycles=3 + +loc_3E68: +3E68: A0 71 CMP:G.B R0, R1 ; cycles=2 +3E6A: 27 0A BEQ loc_3E76 ; cycles=3/7 nt/t +3E6C: F8 F8 70 73 CMP:G.W @(-H'0790,R0), R3 ; cycles=7 +3E70: 27 28 BEQ loc_3E9A ; cycles=3/7 nt/t +3E72: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3E74: 20 F2 BRA loc_3E68 ; cycles=7 + +loc_3E76: +3E76: F9 F8 70 93 MOV:G.W R3, @(-H'0790,R1) ; cycles=7 +3E7A: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +3E7E: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_3E82: +3E82: 15 F9 B0 80 MOV:G.B @H'F9B0, R0 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E86: A0 08 ADD:Q.B #1, R0 ; cycles=4 +3E88: 04 7F 50 AND.B #H'7F, R0 ; cycles=3 +3E8B: 15 F9 B5 70 CMP:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=6 +3E8F: 26 09 BNE loc_3E9A ; cycles=3/8 nt/t +3E91: 12 0C STM.W {R2,R3}, @-SP ; cycles=12 +3E93: 1E 01 3D BSR loc_3FD3 ; cycles=14 +3E96: 02 0C LDM.W @SP+, {R2,R3} ; cycles=14 +3E98: 20 E8 BRA loc_3E82 ; cycles=7 + +loc_3E9A: +3E9A: A2 F6 BTST.B #6, R2 ; cycles=2 +3E9C: 27 2D BEQ loc_3ECB ; cycles=3/7 nt/t +3E9E: 15 F9 B9 80 MOV:G.B @H'F9B9, R0 ; refs ram_F9B9 in on_chip_ram; cycles=7 +3EA2: A0 12 EXTU.B R0 ; cycles=3 +3EA4: A8 1A SHLL.W R0 ; cycles=3 +3EA6: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +3EAA: A1 12 EXTU.B R1 ; cycles=3 +3EAC: A9 1A SHLL.W R1 ; cycles=3 + +loc_3EAE: +3EAE: A0 71 CMP:G.B R0, R1 ; cycles=2 +3EB0: 27 0D BEQ loc_3EBF ; cycles=3/7 nt/t +3EB2: F8 F9 70 73 CMP:G.W @(-H'0690,R0), R3 ; cycles=7 +3EB6: 27 13 BEQ loc_3ECB ; cycles=3/7 nt/t +3EB8: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3EBA: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3EBD: 20 EF BRA loc_3EAE ; cycles=8 + +loc_3EBF: +3EBF: F9 F9 70 93 MOV:G.W R3, @(-H'0690,R1) ; cycles=6 +3EC3: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +3EC7: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_3ECB: +3ECB: 19 RTS ; cycles=13 + +loc_3ECC: +3ECC: 12 1F STM.W {R0,R1,R2,R3,R4}, @-SP ; cycles=21 +3ECE: A5 12 EXTU.B R5 ; cycles=3 +3ED0: 45 03 CMP:E #H'03, R5 ; cycles=2 +3ED2: 23 05 BLS loc_3ED9 ; cycles=3/7 nt/t +3ED4: 1E 00 69 BSR loc_3F40 ; cycles=13 +3ED7: 20 4C BRA loc_3F25 ; cycles=8 + +loc_3ED9: +3ED9: A5 83 MOV:G.B R5, R3 ; cycles=2 +3EDB: 45 00 CMP:E #H'00, R5 ; cycles=2 +3EDD: 27 0A BEQ loc_3EE9 ; cycles=3/8 nt/t +3EDF: 45 01 CMP:E #H'01, R5 ; cycles=2 +3EE1: 27 0B BEQ loc_3EEE ; cycles=3/8 nt/t +3EE3: 45 02 CMP:E #H'02, R5 ; cycles=2 +3EE5: 27 0C BEQ loc_3EF3 ; cycles=3/8 nt/t +3EE7: 20 0F BRA loc_3EF8 ; cycles=8 + +loc_3EE9: +3EE9: 5D 00 80 MOV:I.W #H'0080, R5 ; dataflow R5=H'0080; cycles=3 +3EEC: 20 0D BRA loc_3EFB ; cycles=7 + +loc_3EEE: +3EEE: 5D 00 C0 MOV:I.W #H'00C0, R5 ; dataflow R5=H'00C0; cycles=3 +3EF1: 20 08 BRA loc_3EFB ; cycles=8 + +loc_3EF3: +3EF3: 5D 00 90 MOV:I.W #H'0090, R5 ; dataflow R5=H'0090; cycles=3 +3EF6: 20 03 BRA loc_3EFB ; cycles=7 + +loc_3EF8: +3EF8: 5D 00 D0 MOV:I.W #H'00D0, R5 ; dataflow R5=H'00D0; cycles=3 + +loc_3EFB: +3EFB: 04 10 AB MULXU.B #H'10, R3 ; cycles=19 +3EFE: 0C FA B0 23 ADD:G.W #H'FAB0, R3 ; cycles=4 +3F02: A9 13 CLR.W R1 ; dataflow R1=H'0000; cycles=3 + +loc_3F04: +3F04: F1 FA F0 82 MOV:G.B @(-H'0510,R1), R2 ; cycles=7 +3F08: D3 72 CMP:G.B @R3, R2 ; cycles=6 +3F0A: 27 04 BEQ loc_3F10 ; cycles=3/7 nt/t +3F0C: D3 92 MOV:G.B R2, @R3 ; cycles=6 +3F0E: 0E 18 BSR loc_3F28 ; cycles=13 + +loc_3F10: +3F10: A1 08 ADD:Q.B #1, R1 ; cycles=4 +3F12: A3 08 ADD:Q.B #1, R3 ; cycles=4 +3F14: 41 10 CMP:E #H'10, R1 ; cycles=2 +3F16: 27 02 BEQ loc_3F1A ; cycles=3/7 nt/t +3F18: 20 EA BRA loc_3F04 ; cycles=7 + +loc_3F1A: +3F1A: 1D FB 00 07 00 E0 MOV:G.W #H'00E0, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=11 +3F20: 5C 00 E0 MOV:I.W #H'00E0, R4 ; dataflow R4=H'00E0; cycles=3 +3F23: 0E 1B BSR loc_3F40 ; cycles=14 + +loc_3F25: +3F25: 02 1F LDM.W @SP+, {R0,R1,R2,R3,R4} ; cycles=26 +3F27: 19 RTS ; cycles=13 + +loc_3F28: +3F28: AD 84 MOV:G.W R5, R4 ; cycles=3 +3F2A: A1 24 ADD:G.B R1, R4 ; cycles=2 +3F2C: 1D FB 00 74 CMP:G.W @H'FB00, R4 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F30: 27 06 BEQ loc_3F38 ; cycles=3/7 nt/t +3F32: 1D FB 00 94 MOV:G.W R4, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F36: 0E 08 BSR loc_3F40 ; cycles=13 + +loc_3F38: +3F38: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +3F3B: A2 24 ADD:G.B R2, R4 ; cycles=2 +3F3D: 0E 01 BSR loc_3F40 ; cycles=14 +3F3F: 19 RTS ; cycles=13 + +loc_3F40: +3F40: BF 98 STC.W SR, @-R7 ; cycles=8 +3F42: 0C 00 FF 58 ANDC.W #H'00FF, SR ; cycles=4 +3F46: 0C 06 00 48 ORC.W #H'0600, SR ; cycles=4 + +loc_3F4A: +3F4A: 15 F2 00 00 80 MOVFPE.B @H'F200, R0 ; LCD status read from E-clock H'F200; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; refs mem_F200 in program_or_external; cycles=13 +3F4F: A0 F7 BTST.B #7, R0 ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=2 +3F51: 26 F7 BNE loc_3F4A ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=3/8 nt/t +3F53: AC F8 BTST.W #8, R4 ; cycles=3 +3F55: 26 16 BNE loc_3F6D ; cycles=3/8 nt/t +3F57: AC F9 BTST.W #9, R4 ; cycles=3 +3F59: 26 07 BNE loc_3F62 ; cycles=3/8 nt/t +3F5B: 15 F2 00 00 94 MOVTPE.B R4, @H'F200 ; LCD command/address write to E-clock H'F200; refs mem_F200 in program_or_external; cycles=13 +3F60: 20 10 BRA loc_3F72 ; cycles=7 + +loc_3F62: +3F62: 15 F2 01 00 94 MOVTPE.B R4, @H'F201 ; LCD data write to E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 +3F67: 1D FB 00 08 ADD:Q.W #1, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=8 +3F6B: 20 05 BRA loc_3F72 ; cycles=8 + +loc_3F6D: +3F6D: 15 F2 01 00 84 MOVFPE.B @H'F201, R4 ; LCD data read from E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 + +loc_3F72: +3F72: CF 88 LDC.W @R7+, SR ; cycles=7 +3F74: 19 RTS ; cycles=12 + +loc_3F76: +3F76: 58 27 10 MOV:I.W #H'2710, R0 ; dataflow R0=H'2710; cycles=3 +3F79: 59 C3 50 MOV:I.W #H'C350, R1 ; dataflow R1=H'C350; cycles=3 + +loc_3F7C: +3F7C: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=9 +3F80: 01 B8 F9 SCB/F R0, loc_3F7C ; cycles=3/4/8 false/-1/t + +loc_3F83: +3F83: 15 FE 82 C7 BSET.B #7, @P1DR ; set bit 7 of P1DR; cycles=8 +3F87: 01 B9 F9 SCB/F R1, loc_3F83 ; cycles=3/4/9 false/-1/t +3F8A: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_3F8C: +3F8C: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=9 +3F90: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=9 +3F94: F8 F6 80 13 CLR.W @(-H'0980,R0) ; cycles=9 +3F98: A8 09 ADD:Q.W #2, R0 ; cycles=4 +3F9A: 48 08 00 CMP:I #H'0800, R0 ; cycles=3 +3F9D: 26 ED BNE loc_3F8C ; cycles=3/8 nt/t +3F9F: 1E 03 6A BSR loc_430C ; cycles=14 +3FA2: 1E 03 7F BSR loc_4324 ; cycles=13 +3FA5: 1E 00 EE BSR loc_4096 ; cycles=14 +3FA8: 1E 01 10 BSR loc_40BB ; cycles=13 +3FAB: 1E 02 69 BSR loc_4217 ; cycles=14 +3FAE: 1E 03 9B BSR loc_434C ; cycles=13 + +loc_3FB1: +3FB1: 1D FE EC 07 5A 00 MOV:G.W #H'5A00, @WDT_TCSR_R ; WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00); cycles=9 +3FB7: 15 F7 94 13 CLR.B @H'F794 ; refs ram_F794 in on_chip_ram; cycles=8 +3FBB: 0E 16 BSR loc_3FD3 ; cycles=14 +3FBD: 1E 7B EB BSR loc_BBAB ; cycles=14 +3FC0: 0E 2D BSR loc_3FEF ; cycles=13 +3FC2: 1E 00 81 BSR loc_4046 ; cycles=13 +3FC5: 1E 7E D6 BSR loc_BE9E ; cycles=14 +3FC8: 1E E8 3B BSR loc_2806 ; cycles=13 +3FCB: 1E F9 62 BSR loc_3930 ; cycles=14 +3FCE: 1E D6 0F BSR loc_15E0 ; cycles=13 +3FD1: 20 DE BRA loc_3FB1 ; cycles=8 + +loc_3FD3: +3FD3: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +3FD7: 26 15 BNE loc_3FEE ; cycles=3/8 nt/t +3FD9: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +3FDD: 27 06 BEQ loc_3FE5 ; cycles=3/8 nt/t +3FDF: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +3FE3: 26 09 BNE loc_3FEE ; cycles=3/8 nt/t + +loc_3FE5: +3FE5: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=6 +3FE9: 26 03 BNE loc_3FEE ; cycles=3/8 nt/t +3FEB: 1E 7B 04 BSR loc_BAF2 ; cycles=14 + +loc_3FEE: +3FEE: 19 RTS ; cycles=12 + +loc_3FEF: +3FEF: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +3FF3: 26 12 BNE loc_4007 ; cycles=3/8 nt/t +3FF5: 15 F9 B5 13 CLR.B @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +3FF9: 15 F9 B0 13 CLR.B @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=8 +3FFD: 15 FA A5 D7 BCLR.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 +4001: 27 08 BEQ loc_400B ; cycles=3/8 nt/t +4003: 0E 07 BSR loc_400C ; cycles=14 +4005: 20 04 BRA loc_400B ; cycles=8 + +loc_4007: +4007: 15 FA A5 C7 BSET.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 + +loc_400B: +400B: 19 RTS ; cycles=13 + +loc_400C: +400C: 15 F7 30 13 CLR.B @H'F730 ; refs ram_F730 in on_chip_ram; cycles=9 +4010: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=9 +4014: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=9 +4018: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=9 +401C: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=9 +4020: 1D F7 32 13 CLR.W @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +4024: 1D F7 5C 13 CLR.W @H'F75C ; refs ram_F75C in on_chip_ram; cycles=9 +4028: 15 FB 03 13 CLR.B @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +402C: 1D E0 46 13 CLR.W @H'E046 ; refs mem_E046 in program_or_external; cycles=9 +4030: 1D F7 6A 13 CLR.W @H'F76A ; refs ram_F76A in on_chip_ram; cycles=9 +4034: 15 F7 91 13 CLR.B @H'F791 ; refs ram_F791 in on_chip_ram; cycles=9 +4038: 15 F7 95 13 CLR.B @H'F795 ; refs ram_F795 in on_chip_ram; cycles=9 +403C: 15 F7 6E 13 CLR.B @H'F76E ; refs ram_F76E in on_chip_ram; cycles=9 +4040: 0E 33 BSR loc_4075 ; cycles=13 +4042: 1E 01 D2 BSR loc_4217 ; cycles=13 +4045: 19 RTS ; cycles=13 + +loc_4046: +4046: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=7 +404A: 26 0C BNE loc_4058 ; cycles=3/7 nt/t +404C: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +4050: 27 07 BEQ loc_4059 ; cycles=3/7 nt/t +4052: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +4056: 27 01 BEQ loc_4059 ; cycles=3/7 nt/t + +loc_4058: +4058: 19 RTS ; cycles=12 + +loc_4059: +4059: 15 F9 B0 82 MOV:G.B @H'F9B0, R2 ; refs ram_F9B0 in on_chip_ram; cycles=6 +405D: A2 12 EXTU.B R2 ; cycles=3 +405F: 15 F9 B5 72 CMP:G.B @H'F9B5, R2 ; refs ram_F9B5 in on_chip_ram; cycles=6 +4063: 26 0F BNE loc_4074 ; cycles=3/8 nt/t +4065: A2 1A SHLL.B R2 ; cycles=2 +4067: FA F8 70 06 00 MOV:G.W #H'00, @(-H'0790,R2) ; cycles=11 +406C: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +4070: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_4074: +4074: 19 RTS ; cycles=12 + +loc_4075: +4075: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_4077: +4077: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=8 +407B: F8 E4 00 13 CLR.W @(-H'1C00,R0) ; cycles=8 +407F: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=8 +4083: 48 02 00 CMP:I #H'0200, R0 ; cycles=3 +4086: 24 04 BCC loc_408C ; cycles=3/7 nt/t +4088: F8 EC 00 13 CLR.W @(-H'1400,R0) ; cycles=9 + +loc_408C: +408C: A8 09 ADD:Q.W #2, R0 ; cycles=4 +408E: 48 04 00 CMP:I #H'0400, R0 ; cycles=3 +4091: 26 E4 BNE loc_4077 ; cycles=3/8 nt/t +4093: 0E 01 BSR loc_4096 ; cycles=14 +4095: 19 RTS ; cycles=13 + +loc_4096: +4096: 1D E0 00 07 00 80 MOV:G.W #H'0080, @H'E000 ; refs mem_E000 in program_or_external; cycles=11 +409C: 1D E0 06 07 80 00 MOV:G.W #H'8000, @H'E006 ; refs mem_E006 in program_or_external; cycles=11 +40A2: 1D E0 80 07 FF FF MOV:G.W #H'FFFF, @H'E080 ; refs mem_E080 in program_or_external; cycles=11 +40A8: 1D E8 00 07 00 80 MOV:G.W #H'0080, @H'E800 ; refs mem_E800 in program_or_external; cycles=11 +40AE: 1D E8 06 07 80 00 MOV:G.W #H'8000, @H'E806 ; refs mem_E806 in program_or_external; cycles=11 +40B4: 1D E8 80 07 FF FF MOV:G.W #H'FFFF, @H'E880 ; refs mem_E880 in program_or_external; cycles=11 +40BA: 19 RTS ; cycles=12 + +loc_40BB: +40BB: 58 00 40 MOV:I.W #H'0040, R0 ; dataflow R0=H'0040; cycles=3 + +loc_40BE: +40BE: F8 F8 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0792,R0) ; cycles=9 +40C4: F8 F8 AE 07 FF FF MOV:G.W #H'FFFF, @(-H'0752,R0) ; cycles=9 +40CA: F8 F8 EE 07 FF FF MOV:G.W #H'FFFF, @(-H'0712,R0) ; cycles=9 +40D0: F8 F9 2E 07 FF FF MOV:G.W #H'FFFF, @(-H'06D2,R0) ; cycles=9 +40D6: F8 F9 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0692,R0) ; cycles=9 +40DC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +40DE: 26 DE BNE loc_40BE ; cycles=3/7 nt/t +40E0: 15 F9 C4 06 14 MOV:G.B #H'14, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +40E5: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +40EA: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +40EF: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +40F4: 15 FE 8E F7 BTST.B #7, @P7DR ; refs P7DR in register_field; cycles=7 +40F8: 27 09 BEQ loc_4103 ; cycles=3/7 nt/t +40FA: 1D F4 02 05 6B 6F CMP:G.W #H'6B6F, @H'F402 ; refs mem_F402 in program_or_external; cycles=7 +4100: 37 00 AD BEQ loc_41B0 ; cycles=3/7 nt/t + +loc_4103: +4103: 58 01 00 MOV:I.W #H'0100, R0 ; dataflow R0=H'0100; cycles=3 + +loc_4106: +4106: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +4108: F8 C9 64 85 MOV:G.W @(-H'369C,R0), R5 ; cycles=7 +410C: F8 F4 00 95 MOV:G.W R5, @(-H'0C00,R0) ; cycles=7 +4110: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +4112: A8 84 MOV:G.W R0, R4 ; cycles=3 +4114: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4117: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +411B: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +411E: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4122: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4125: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4129: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +412C: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4130: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4133: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4137: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +413A: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +413E: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4141: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4145: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4148: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +414C: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +414F: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4153: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4156: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +415A: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +415D: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4161: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4164: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4168: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +416B: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +416F: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4172: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4176: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4179: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +417D: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4180: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +4182: 26 82 BNE loc_4106 ; cycles=3/7 nt/t +4184: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_4187: +4187: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +4189: A8 84 MOV:G.W R0, R4 ; cycles=3 +418B: A4 10 SWAP.B R4 ; cycles=3 +418D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4190: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4193: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4195: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4198: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +419B: AC 09 ADD:Q.W #2, R4 ; cycles=4 +419D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A0: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41A3: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41A5: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A8: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41AB: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +41AD: 01 B8 D7 SCB/F R0, loc_4187 ; cycles=3/4/9 false/-1/t + +loc_41B0: +41B0: 20 20 BRA loc_41D2 ; cycles=7 + +loc_41D2: +41D2: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_41D5: +41D5: A8 81 MOV:G.W R0, R1 ; cycles=3 +41D7: A1 1A SHLL.B R1 ; cycles=2 +41D9: A1 1A SHLL.B R1 ; cycles=2 +41DB: A1 1A SHLL.B R1 ; cycles=2 +41DD: A8 84 MOV:G.W R0, R4 ; cycles=3 +41DF: A4 10 SWAP.B R4 ; cycles=3 +41E1: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41E3: 18 BF FE JSR @loc_BFFE ; cycles=14 +41E6: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41E8: F9 F7 B0 95 MOV:G.W R5, @(-H'0850,R1) ; cycles=7 +41EC: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41EE: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41F0: 18 BF FE JSR @loc_BFFE ; cycles=13 +41F3: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41F5: F9 F7 B2 95 MOV:G.W R5, @(-H'084E,R1) ; cycles=6 +41F9: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41FB: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41FD: 18 BF FE JSR @loc_BFFE ; cycles=14 +4200: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +4202: F9 F7 B4 95 MOV:G.W R5, @(-H'084C,R1) ; cycles=7 +4206: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4208: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +420A: 18 BF FE JSR @loc_BFFE ; cycles=13 +420D: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +420F: F9 F7 B6 95 MOV:G.W R5, @(-H'084A,R1) ; cycles=6 +4213: 01 B8 BF SCB/F R0, loc_41D5 ; cycles=3/4/9 false/-1/t +4216: 19 RTS ; cycles=12 + +loc_4217: +4217: 15 F7 98 13 CLR.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +421B: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +421F: 15 FE 82 D2 BCLR.B #2, @P1DR ; clear bit 2 of P1DR; cycles=8 +4223: 1D F7 00 07 24 24 MOV:G.W #H'2424, @H'F700 ; refs ram_F700 in on_chip_ram; cycles=9 +4229: 1D F7 02 07 24 24 MOV:G.W #H'2424, @H'F702 ; refs ram_F702 in on_chip_ram; cycles=9 +422F: 1D F7 04 07 24 24 MOV:G.W #H'2424, @H'F704 ; refs ram_F704 in on_chip_ram; cycles=9 +4235: 1D F7 06 07 24 24 MOV:G.W #H'2424, @H'F706 ; refs ram_F706 in on_chip_ram; cycles=9 +423B: 15 F7 08 06 7F MOV:G.B #H'7F, @H'F708 ; refs ram_F708 in on_chip_ram; cycles=9 +4240: 15 F7 09 06 24 MOV:G.B #H'24, @H'F709 ; refs ram_F709 in on_chip_ram; cycles=9 +4245: 1D F7 0A 07 24 24 MOV:G.W #H'2424, @H'F70A ; refs ram_F70A in on_chip_ram; cycles=9 +424B: 15 F7 10 13 CLR.B @H'F710 ; refs ram_F710 in on_chip_ram; cycles=8 +424F: 15 F7 11 13 CLR.B @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +4253: 15 F7 12 13 CLR.B @H'F712 ; refs ram_F712 in on_chip_ram; cycles=8 +4257: 15 F7 13 13 CLR.B @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +425B: 15 F7 14 13 CLR.B @H'F714 ; refs ram_F714 in on_chip_ram; cycles=8 +425F: 15 F7 15 13 CLR.B @H'F715 ; refs ram_F715 in on_chip_ram; cycles=8 +4263: 15 F7 16 13 CLR.B @H'F716 ; refs ram_F716 in on_chip_ram; cycles=8 +4267: 15 F7 17 13 CLR.B @H'F717 ; refs ram_F717 in on_chip_ram; cycles=8 +426B: 15 F7 18 06 FF MOV:G.B #H'FF, @H'F718 ; refs ram_F718 in on_chip_ram; cycles=9 +4270: 15 F7 19 06 FF MOV:G.B #H'FF, @H'F719 ; refs ram_F719 in on_chip_ram; cycles=9 +4275: 15 F7 1A 06 FF MOV:G.B #H'FF, @H'F71A ; refs ram_F71A in on_chip_ram; cycles=9 +427A: 15 F7 1B 06 FF MOV:G.B #H'FF, @H'F71B ; refs ram_F71B in on_chip_ram; cycles=9 +427F: 15 F7 1C 06 FF MOV:G.B #H'FF, @H'F71C ; refs ram_F71C in on_chip_ram; cycles=9 +4284: 15 F7 1D 06 FF MOV:G.B #H'FF, @H'F71D ; refs ram_F71D in on_chip_ram; cycles=9 +4289: 15 F7 1E 06 FF MOV:G.B #H'FF, @H'F71E ; refs ram_F71E in on_chip_ram; cycles=9 +428E: 15 F7 1F 06 FF MOV:G.B #H'FF, @H'F71F ; refs ram_F71F in on_chip_ram; cycles=9 +4293: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +4299: 1D FA F2 07 4F 4E MOV:G.W #H'4F4E, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +429F: 1D FA F4 07 4E 45 MOV:G.W #H'4E45, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42A5: 1D FA F6 07 43 54 MOV:G.W #H'4354, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42AB: 1D FA F8 07 3A 4E MOV:G.W #H'3A4E, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42B1: 1D FA FA 07 4F 54 MOV:G.W #H'4F54, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42B7: 1D FA FC 07 20 41 MOV:G.W #H'2041, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42BD: 1D FA FE 07 43 54 MOV:G.W #H'4354, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42C3: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +42C6: 1E FC 03 BSR loc_3ECC ; cycles=13 +42C9: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +42CF: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +42D5: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42DB: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42E1: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42E7: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42ED: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42F3: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42F9: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +42FC: 1E FB CD BSR loc_3ECC ; cycles=13 +42FF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +4302: 1E FB C7 BSR loc_3ECC ; cycles=13 +4305: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +4308: 1E FB C1 BSR loc_3ECC ; cycles=13 +430B: 19 RTS ; cycles=13 + +loc_430C: +430C: 15 FE 8B D0 BCLR.B #0, @P6DR ; clear bit 0 of P6DR; cycles=9 +4310: 15 F5 55 06 AA MOV:G.B #H'AA, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +4315: 15 F4 AA 06 55 MOV:G.B #H'55, @H'F4AA ; refs mem_F4AA in program_or_external; cycles=9 +431A: 15 F5 55 06 CC MOV:G.B #H'CC, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +431F: 15 FE 8B C0 BSET.B #0, @P6DR ; set bit 0 of P6DR; cycles=8 +4323: 19 RTS ; cycles=13 + +loc_4324: +4324: 5C 00 38 MOV:I.W #H'0038, R4 ; dataflow R4=H'0038; cycles=3 +4327: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +432A: 1E FB 9F BSR loc_3ECC ; cycles=13 +432D: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 +4330: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4333: 1E FB 96 BSR loc_3ECC ; cycles=14 +4336: 5C 00 0E MOV:I.W #H'000E, R4 ; dataflow R4=H'000E; cycles=3 +4339: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +433C: 1E FB 8D BSR loc_3ECC ; cycles=13 +433F: 5C 00 06 MOV:I.W #H'0006, R4 ; dataflow R4=H'0006; cycles=3 +4342: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4345: 1E FB 84 BSR loc_3ECC ; cycles=14 +4348: 1E CD 83 BSR loc_10CE ; cycles=13 +434B: 19 RTS ; cycles=13 + +loc_434C: +434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9 +4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9 +4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9 +435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9 +4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9 +4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40 (A/D priority=4); cycles=9 +436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR; enable SCI1 receive and receive-error interrupts (RIE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR; cycles=9 +4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR; cycles=9 +4376: 15 FE E8 C6 BSET.B #6, @ADCSR ; set ADIE (bit 6) of ADCSR; cycles=9 +437A: 15 FE FD C4 BSET.B #4, @SYSCR2 ; set IRQ3E (bit 4) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +437E: 15 FE FD C5 BSET.B #5, @SYSCR2 ; set IRQ4E (bit 5) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +4382: 15 FE 8E F6 BTST.B #6, @P7DR ; refs P7DR in register_field; cycles=7 +4386: 27 06 BEQ loc_438E ; cycles=3/7 nt/t +4388: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 + +loc_438E: +438E: 0C 03 00 88 LDC.W #H'0300, SR ; dataflow SR=H'0300; cycles=6 +4392: 19 RTS ; cycles=12 + +vec_nmi_4393: +4393: 0A RTE ; cycles=14 + +loc_4394: +4394: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +4399: 32 00 86 BHI loc_4422 ; cycles=3/8 nt/t +439C: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +43A0: 36 00 7F BNE loc_4422 ; cycles=3/7 nt/t +43A3: 1D F7 36 83 MOV:G.W @H'F736, R3 ; refs ram_F736 in on_chip_ram; cycles=6 +43A7: 37 00 78 BEQ loc_4422 ; cycles=3/8 nt/t +43AA: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +43AE: 1D F6 BE 34 SUB.W @H'F6BE, R4 ; refs ram_F6BE in on_chip_ram; cycles=7 +43B2: AB DF BCLR.W #15, R3 ; cycles=3 +43B4: 26 19 BNE loc_43CF ; cycles=3/7 nt/t +43B6: AB DE BCLR.W #14, R3 ; cycles=3 +43B8: 26 21 BNE loc_43DB ; cycles=3/7 nt/t +43BA: AB DD BCLR.W #13, R3 ; cycles=3 +43BC: 26 29 BNE loc_43E7 ; cycles=3/7 nt/t +43BE: AB DC BCLR.W #12, R3 ; cycles=3 +43C0: 26 31 BNE loc_43F3 ; cycles=3/7 nt/t +43C2: AB DB BCLR.W #11, R3 ; cycles=3 +43C4: 26 39 BNE loc_43FF ; cycles=3/7 nt/t +43C6: AB DA BCLR.W #10, R3 ; cycles=3 +43C8: 26 43 BNE loc_440D ; cycles=3/7 nt/t +43CA: 1E D5 D5 BSR loc_19A2 ; cycles=13 +43CD: 20 53 BRA loc_4422 ; cycles=8 + +loc_43CF: +43CF: 0E 5E BSR loc_442F ; cycles=14 +43D1: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43D4: 27 03 BEQ loc_43D9 ; cycles=3/7 nt/t +43D6: 1E D6 5C BSR loc_1A35 ; cycles=13 + +loc_43D9: +43D9: 20 47 BRA loc_4422 ; cycles=8 + +loc_43DB: +43DB: 0E 52 BSR loc_442F ; cycles=14 +43DD: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43E0: 27 03 BEQ loc_43E5 ; cycles=3/7 nt/t +43E2: 1E D6 B7 BSR loc_1A9C ; cycles=13 + +loc_43E5: +43E5: 20 3B BRA loc_4422 ; cycles=8 + +loc_43E7: +43E7: 0E 46 BSR loc_442F ; cycles=14 +43E9: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43EC: 27 03 BEQ loc_43F1 ; cycles=3/7 nt/t +43EE: 1E D6 F3 BSR loc_1AE4 ; cycles=13 + +loc_43F1: +43F1: 20 2F BRA loc_4422 ; cycles=8 + +loc_43F3: +43F3: 0E 3A BSR loc_442F ; cycles=14 +43F5: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43F8: 27 03 BEQ loc_43FD ; cycles=3/7 nt/t +43FA: 1E D7 0E BSR loc_1B0B ; cycles=13 + +loc_43FD: +43FD: 20 23 BRA loc_4422 ; cycles=8 + +loc_43FF: +43FF: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4404: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +4408: 1E 04 EF BSR loc_48FA ; cycles=13 +440B: 20 15 BRA loc_4422 ; cycles=8 + +loc_440D: +440D: 0E 20 BSR loc_442F ; cycles=14 +440F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4412: 27 0C BEQ loc_4420 ; cycles=3/7 nt/t +4414: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4419: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +441D: 1E 04 DA BSR loc_48FA ; cycles=14 + +loc_4420: +4420: 20 00 BRA loc_4422 ; cycles=7 + +loc_4422: +4422: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +4426: 1D F6 BE 94 MOV:G.W R4, @H'F6BE ; refs ram_F6BE in on_chip_ram; cycles=7 +442A: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +442E: 19 RTS ; cycles=12 + +loc_442F: +442F: 15 F6 F7 24 ADD:G.B @H'F6F7, R4 ; refs ram_F6F7 in on_chip_ram; cycles=6 +4433: 44 88 CMP:E #H'88, R4 ; cycles=2 +4435: 24 0D BCC loc_4444 ; cycles=3/8 nt/t +4437: 44 78 CMP:E #H'78, R4 ; cycles=2 +4439: 23 13 BLS loc_444E ; cycles=3/8 nt/t +443B: 15 F6 F7 94 MOV:G.B R4, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=6 +443F: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4442: 20 12 BRA loc_4456 ; cycles=7 + +loc_4444: +4444: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4449: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +444C: 20 08 BRA loc_4456 ; cycles=7 + +loc_444E: +444E: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4453: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4456: +4456: 19 RTS ; cycles=12 + +loc_4457: +4457: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +445C: 32 00 86 BHI loc_44E5 ; cycles=3/7 nt/t +445F: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=6 +4463: 36 00 7F BNE loc_44E5 ; cycles=3/8 nt/t +4466: 1D F7 38 83 MOV:G.W @H'F738, R3 ; refs ram_F738 in on_chip_ram; cycles=7 +446A: 37 00 78 BEQ loc_44E5 ; cycles=3/7 nt/t +446D: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +4471: 1D F6 BC 34 SUB.W @H'F6BC, R4 ; refs ram_F6BC in on_chip_ram; cycles=6 +4475: AB DF BCLR.W #15, R3 ; cycles=3 +4477: 26 19 BNE loc_4492 ; cycles=3/8 nt/t +4479: AB DE BCLR.W #14, R3 ; cycles=3 +447B: 26 21 BNE loc_449E ; cycles=3/8 nt/t +447D: AB DD BCLR.W #13, R3 ; cycles=3 +447F: 26 29 BNE loc_44AA ; cycles=3/8 nt/t +4481: AB DC BCLR.W #12, R3 ; cycles=3 +4483: 26 31 BNE loc_44B6 ; cycles=3/8 nt/t +4485: AB DB BCLR.W #11, R3 ; cycles=3 +4487: 26 39 BNE loc_44C2 ; cycles=3/8 nt/t +4489: AB DA BCLR.W #10, R3 ; cycles=3 +448B: 26 43 BNE loc_44D0 ; cycles=3/8 nt/t +448D: 1E D5 12 BSR loc_19A2 ; cycles=14 +4490: 20 53 BRA loc_44E5 ; cycles=7 + +loc_4492: +4492: 0E 5E BSR loc_44F2 ; cycles=13 +4494: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4497: 27 03 BEQ loc_449C ; cycles=3/8 nt/t +4499: 1E D5 99 BSR loc_1A35 ; cycles=14 + +loc_449C: +449C: 20 47 BRA loc_44E5 ; cycles=7 + +loc_449E: +449E: 0E 52 BSR loc_44F2 ; cycles=13 +44A0: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44A3: 27 03 BEQ loc_44A8 ; cycles=3/8 nt/t +44A5: 1E D5 F4 BSR loc_1A9C ; cycles=14 + +loc_44A8: +44A8: 20 3B BRA loc_44E5 ; cycles=7 + +loc_44AA: +44AA: 0E 46 BSR loc_44F2 ; cycles=13 +44AC: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44AF: 27 03 BEQ loc_44B4 ; cycles=3/8 nt/t +44B1: 1E D6 30 BSR loc_1AE4 ; cycles=14 + +loc_44B4: +44B4: 20 2F BRA loc_44E5 ; cycles=7 + +loc_44B6: +44B6: 0E 3A BSR loc_44F2 ; cycles=13 +44B8: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44BB: 27 03 BEQ loc_44C0 ; cycles=3/8 nt/t +44BD: 1E D6 4B BSR loc_1B0B ; cycles=14 + +loc_44C0: +44C0: 20 23 BRA loc_44E5 ; cycles=7 + +loc_44C2: +44C2: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44C7: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +44CB: 1E 04 2C BSR loc_48FA ; cycles=14 +44CE: 20 15 BRA loc_44E5 ; cycles=7 + +loc_44D0: +44D0: 0E 20 BSR loc_44F2 ; cycles=13 +44D2: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44D5: 27 0C BEQ loc_44E3 ; cycles=3/8 nt/t +44D7: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44DC: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +44E0: 1E 04 17 BSR loc_48FA ; cycles=13 + +loc_44E3: +44E3: 20 00 BRA loc_44E5 ; cycles=8 + +loc_44E5: +44E5: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +44E9: 1D F6 BC 94 MOV:G.W R4, @H'F6BC ; refs ram_F6BC in on_chip_ram; cycles=6 +44ED: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=8 +44F1: 19 RTS ; cycles=13 + +loc_44F2: +44F2: 15 F6 F8 24 ADD:G.B @H'F6F8, R4 ; refs ram_F6F8 in on_chip_ram; cycles=7 +44F6: 44 88 CMP:E #H'88, R4 ; cycles=2 +44F8: 24 0D BCC loc_4507 ; cycles=3/7 nt/t +44FA: 44 78 CMP:E #H'78, R4 ; cycles=2 +44FC: 23 13 BLS loc_4511 ; cycles=3/7 nt/t +44FE: 15 F6 F8 94 MOV:G.B R4, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=7 +4502: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4505: 20 12 BRA loc_4519 ; cycles=8 + +loc_4507: +4507: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +450C: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +450F: 20 08 BRA loc_4519 ; cycles=8 + +loc_4511: +4511: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +4516: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4519: +4519: 19 RTS ; cycles=13 + +loc_451A: +451A: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +451F: 32 00 86 BHI loc_45A8 ; cycles=3/8 nt/t +4522: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +4526: 36 00 7F BNE loc_45A8 ; cycles=3/7 nt/t +4529: 1D F7 3A 83 MOV:G.W @H'F73A, R3 ; refs ram_F73A in on_chip_ram; cycles=6 +452D: 37 00 78 BEQ loc_45A8 ; cycles=3/8 nt/t +4530: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +4534: 1D F6 BA 34 SUB.W @H'F6BA, R4 ; refs ram_F6BA in on_chip_ram; cycles=7 +4538: AB DF BCLR.W #15, R3 ; cycles=3 +453A: 26 19 BNE loc_4555 ; cycles=3/7 nt/t +453C: AB DE BCLR.W #14, R3 ; cycles=3 +453E: 26 21 BNE loc_4561 ; cycles=3/7 nt/t +4540: AB DD BCLR.W #13, R3 ; cycles=3 +4542: 26 29 BNE loc_456D ; cycles=3/7 nt/t +4544: AB DC BCLR.W #12, R3 ; cycles=3 +4546: 26 31 BNE loc_4579 ; cycles=3/7 nt/t +4548: AB DB BCLR.W #11, R3 ; cycles=3 +454A: 26 39 BNE loc_4585 ; cycles=3/7 nt/t +454C: AB DA BCLR.W #10, R3 ; cycles=3 +454E: 26 43 BNE loc_4593 ; cycles=3/7 nt/t +4550: 1E D4 4F BSR loc_19A2 ; cycles=13 +4553: 20 53 BRA loc_45A8 ; cycles=8 + +loc_4555: +4555: 0E 5E BSR loc_45B5 ; cycles=14 +4557: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +455A: 27 03 BEQ loc_455F ; cycles=3/7 nt/t +455C: 1E D4 D6 BSR loc_1A35 ; cycles=13 + +loc_455F: +455F: 20 47 BRA loc_45A8 ; cycles=8 + +loc_4561: +4561: 0E 52 BSR loc_45B5 ; cycles=14 +4563: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4566: 27 03 BEQ loc_456B ; cycles=3/7 nt/t +4568: 1E D5 31 BSR loc_1A9C ; cycles=13 + +loc_456B: +456B: 20 3B BRA loc_45A8 ; cycles=8 + +loc_456D: +456D: 0E 46 BSR loc_45B5 ; cycles=14 +456F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4572: 27 03 BEQ loc_4577 ; cycles=3/7 nt/t +4574: 1E D5 6D BSR loc_1AE4 ; cycles=13 + +loc_4577: +4577: 20 2F BRA loc_45A8 ; cycles=8 + +loc_4579: +4579: 0E 3A BSR loc_45B5 ; cycles=14 +457B: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +457E: 27 03 BEQ loc_4583 ; cycles=3/7 nt/t +4580: 1E D5 88 BSR loc_1B0B ; cycles=13 + +loc_4583: +4583: 20 23 BRA loc_45A8 ; cycles=8 + +loc_4585: +4585: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +458A: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +458E: 1E 03 69 BSR loc_48FA ; cycles=13 +4591: 20 15 BRA loc_45A8 ; cycles=8 + +loc_4593: +4593: 0E 20 BSR loc_45B5 ; cycles=14 +4595: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4598: 27 0C BEQ loc_45A6 ; cycles=3/7 nt/t +459A: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +459F: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +45A3: 1E 03 54 BSR loc_48FA ; cycles=14 + +loc_45A6: +45A6: 20 00 BRA loc_45A8 ; cycles=7 + +loc_45A8: +45A8: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +45AC: 1D F6 BA 94 MOV:G.W R4, @H'F6BA ; refs ram_F6BA in on_chip_ram; cycles=7 +45B0: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +45B4: 19 RTS ; cycles=12 + +loc_45B5: +45B5: 15 F6 F9 24 ADD:G.B @H'F6F9, R4 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45B9: 44 88 CMP:E #H'88, R4 ; cycles=2 +45BB: 24 0D BCC loc_45CA ; cycles=3/8 nt/t +45BD: 44 78 CMP:E #H'78, R4 ; cycles=2 +45BF: 23 13 BLS loc_45D4 ; cycles=3/8 nt/t +45C1: 15 F6 F9 94 MOV:G.B R4, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45C5: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +45C8: 20 12 BRA loc_45DC ; cycles=7 + +loc_45CA: +45CA: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45CF: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +45D2: 20 08 BRA loc_45DC ; cycles=7 + +loc_45D4: +45D4: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45D9: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_45DC: +45DC: 19 RTS ; cycles=12 + +loc_48EF: +48EF: 1D F7 34 80 MOV:G.W @H'F734, R0 ; refs ram_F734 in on_chip_ram; cycles=6 +48F3: 1D F7 32 90 MOV:G.W R0, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +48F7: 0E 01 BSR loc_48FA ; cycles=14 +48F9: 19 RTS ; cycles=13 + +loc_48FA: +48FA: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +48FE: 26 29 BNE loc_4929 ; cycles=3/7 nt/t +4900: 15 F7 32 04 1A CMP:G.B #H'1A, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=7 +4905: 27 22 BEQ loc_4929 ; cycles=3/8 nt/t +4907: 1D F7 32 05 19 00 CMP:G.W #H'1900, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +490D: 27 1A BEQ loc_4929 ; cycles=3/8 nt/t +490F: 1D E1 EC FD BTST.W #13, @H'E1EC ; refs mem_E1EC in program_or_external; cycles=6 +4913: 27 14 BEQ loc_4929 ; cycles=3/8 nt/t +4915: 1D E1 EC 80 MOV:G.W @H'E1EC, R0 ; refs mem_E1EC in program_or_external; cycles=6 +4919: 0C 9F FF 50 AND.W #H'9FFF, R0 ; cycles=4 +491D: 1D E9 EC 90 MOV:G.W R0, @H'E9EC ; refs mem_E9EC in program_or_external; cycles=6 +4921: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +4923: 5B 00 F6 MOV:I.W #H'00F6, R3 ; dataflow R3=H'00F6; cycles=3 +4926: 1E F5 2B BSR loc_3E54 ; cycles=13 + +loc_4929: +4929: 15 F7 6E F6 BTST.B #6, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +492D: 26 0E BNE loc_493D ; cycles=3/8 nt/t +492F: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +4933: A0 12 EXTU.B R0 ; cycles=3 +4935: A0 1A SHLL.B R0 ; cycles=2 +4937: F8 49 3E 80 MOV:G.W @(H'493E,R0), R0 ; cycles=6 +493B: 11 D8 JSR @R0 ; JSR @R0 uses R0 loaded from pointer table H'493E via R0 (1/52 decoded targets); cycles=14 + +loc_493D: +493D: 19 RTS ; cycles=13 + +loc_5500: +5500: 15 F7 95 F7 BTST.B #7, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +5504: 36 00 A6 BNE loc_55AD ; cycles=3/7 nt/t +5507: 15 F7 6E 82 MOV:G.B @H'F76E, R2 ; refs ram_F76E in on_chip_ram; cycles=6 +550B: 0C 00 0F 52 AND.W #H'000F, R2 ; cycles=4 +550F: AA 83 MOV:G.W R2, R3 ; cycles=3 +5511: A3 1A SHLL.B R3 ; cycles=2 +5513: A3 1A SHLL.B R3 ; cycles=2 +5515: A3 1A SHLL.B R3 ; cycles=2 +5517: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5519: 15 F7 5E 84 MOV:G.B @H'F75E, R4 ; refs ram_F75E in on_chip_ram; cycles=6 +551D: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5521: A5 10 SWAP.B R5 ; cycles=3 +5523: 15 F7 5F 84 MOV:G.B @H'F75F, R4 ; refs ram_F75F in on_chip_ram; cycles=6 +5527: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +552B: FB F7 B0 95 MOV:G.W R5, @(-H'0850,R3) ; cycles=6 +552F: AA 84 MOV:G.W R2, R4 ; cycles=3 +5531: A4 10 SWAP.B R4 ; cycles=3 +5533: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5535: 1E 6A A8 BSR loc_BFE0 ; cycles=14 +5538: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +553A: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +553C: 15 F7 60 84 MOV:G.B @H'F760, R4 ; refs ram_F760 in on_chip_ram; cycles=7 +5540: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5544: A5 10 SWAP.B R5 ; cycles=3 +5546: 15 F7 61 84 MOV:G.B @H'F761, R4 ; refs ram_F761 in on_chip_ram; cycles=7 +554A: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +554E: FB F7 B2 95 MOV:G.W R5, @(-H'084E,R3) ; cycles=7 +5552: AA 84 MOV:G.W R2, R4 ; cycles=3 +5554: A4 10 SWAP.B R4 ; cycles=3 +5556: AC 09 ADD:Q.W #2, R4 ; cycles=4 +5558: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +555A: 1E 6A 83 BSR loc_BFE0 ; cycles=13 +555D: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +555F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5561: 15 F7 62 84 MOV:G.B @H'F762, R4 ; refs ram_F762 in on_chip_ram; cycles=6 +5565: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5569: A5 10 SWAP.B R5 ; cycles=3 +556B: 15 F7 63 84 MOV:G.B @H'F763, R4 ; refs ram_F763 in on_chip_ram; cycles=6 +556F: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5573: FB F7 B4 95 MOV:G.W R5, @(-H'084C,R3) ; cycles=6 +5577: AA 84 MOV:G.W R2, R4 ; cycles=3 +5579: A4 10 SWAP.B R4 ; cycles=3 +557B: 0C 00 04 24 ADD:G.W #H'0004, R4 ; cycles=4 +557F: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5581: 1E 6A 5C BSR loc_BFE0 ; cycles=14 +5584: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +5586: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5588: 15 F7 64 84 MOV:G.B @H'F764, R4 ; refs ram_F764 in on_chip_ram; cycles=7 +558C: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5590: A5 10 SWAP.B R5 ; cycles=3 +5592: 15 F7 65 84 MOV:G.B @H'F765, R4 ; refs ram_F765 in on_chip_ram; cycles=7 +5596: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +559A: FB F7 B6 95 MOV:G.W R5, @(-H'084A,R3) ; cycles=7 +559E: AA 84 MOV:G.W R2, R4 ; cycles=3 +55A0: A4 10 SWAP.B R4 ; cycles=3 +55A2: 0C 00 06 24 ADD:G.W #H'0006, R4 ; cycles=4 +55A6: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +55A8: 1E 6A 35 BSR loc_BFE0 ; cycles=13 +55AB: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 + +loc_55AD: +55AD: AD 13 CLR.W R5 ; dataflow R5=H'0000; cycles=3 + +loc_55AF: +55AF: FD C5 64 84 MOV:G.W @(-H'3A9C,R5), R4 ; cycles=6 +55B3: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=6 +55B7: 27 06 BEQ loc_55BF ; cycles=3/8 nt/t +55B9: AC FE BTST.W #14, R4 ; cycles=3 +55BB: 27 13 BEQ loc_55D0 ; cycles=3/8 nt/t +55BD: 20 04 BRA loc_55C3 ; cycles=8 + +loc_55BF: +55BF: AC FD BTST.W #13, R4 ; cycles=3 +55C1: 27 0D BEQ loc_55D0 ; cycles=3/8 nt/t + +loc_55C3: +55C3: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55C5: AD 83 MOV:G.W R5, R3 ; cycles=3 +55C7: AB 1B SHLR.W R3 ; cycles=3 +55C9: 0C 02 00 43 OR.W #H'0200, R3 ; cycles=4 +55CD: 1E E8 84 BSR loc_3E54 ; cycles=14 + +loc_55D0: +55D0: AD 09 ADD:Q.W #2, R5 ; cycles=4 +55D2: 4D 04 00 CMP:I #H'0400, R5 ; cycles=3 +55D5: 25 D8 BCS loc_55AF ; cycles=3/8 nt/t +55D7: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55D9: 5B 00 6C MOV:I.W #H'006C, R3 ; dataflow R3=H'006C; cycles=3 +55DC: 1E E8 75 BSR loc_3E54 ; cycles=13 +55DF: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=8 +55E3: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=8 +55E7: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=8 +55EB: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=8 +55EF: 19 RTS ; cycles=13 + +loc_58F7: +58F7: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +58FD: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5903: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +5905: 15 F7 5E 82 MOV:G.B @H'F75E, R2 ; refs ram_F75E in on_chip_ram; cycles=6 +5909: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +590D: A1 10 SWAP.B R1 ; cycles=3 +590F: 15 F7 5F 82 MOV:G.B @H'F75F, R2 ; refs ram_F75F in on_chip_ram; cycles=6 +5913: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5917: 1D FA F4 91 MOV:G.W R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=6 +591B: 15 F7 60 82 MOV:G.B @H'F760, R2 ; refs ram_F760 in on_chip_ram; cycles=6 +591F: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5923: A1 10 SWAP.B R1 ; cycles=3 +5925: 15 F7 61 82 MOV:G.B @H'F761, R2 ; refs ram_F761 in on_chip_ram; cycles=6 +5929: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +592D: 1D FA F6 91 MOV:G.W R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=6 +5931: 15 F7 62 82 MOV:G.B @H'F762, R2 ; refs ram_F762 in on_chip_ram; cycles=6 +5935: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5939: A1 10 SWAP.B R1 ; cycles=3 +593B: 15 F7 63 82 MOV:G.B @H'F763, R2 ; refs ram_F763 in on_chip_ram; cycles=6 +593F: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5943: 1D FA F8 91 MOV:G.W R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=6 +5947: 15 F7 64 82 MOV:G.B @H'F764, R2 ; refs ram_F764 in on_chip_ram; cycles=6 +594B: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +594F: A1 10 SWAP.B R1 ; cycles=3 +5951: 15 F7 65 82 MOV:G.B @H'F765, R2 ; refs ram_F765 in on_chip_ram; cycles=6 +5955: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5959: 1D FA FA 91 MOV:G.W R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=6 +595D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5963: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5969: 19 RTS ; cycles=13 + +loc_596A: +596A: 40 00 CMP:E #H'00, R0 ; cycles=2 +596C: 27 0A BEQ loc_5978 ; cycles=3/7 nt/t +596E: 40 01 CMP:E #H'01, R0 ; cycles=2 +5970: 27 0B BEQ loc_597D ; cycles=3/7 nt/t +5972: 40 02 CMP:E #H'02, R0 ; cycles=2 +5974: 27 0C BEQ loc_5982 ; cycles=3/7 nt/t +5976: 20 0F BRA loc_5987 ; cycles=7 + +loc_5978: +5978: 5C 00 83 MOV:I.W #H'0083, R4 ; dataflow R4=H'0083; cycles=3 +597B: 20 0D BRA loc_598A ; cycles=8 + +loc_597D: +597D: 5C 00 C3 MOV:I.W #H'00C3, R4 ; dataflow R4=H'00C3; cycles=3 +5980: 20 08 BRA loc_598A ; cycles=7 + +loc_5982: +5982: 5C 00 93 MOV:I.W #H'0093, R4 ; dataflow R4=H'0093; cycles=3 +5985: 20 03 BRA loc_598A ; cycles=8 + +loc_5987: +5987: 5C 00 D3 MOV:I.W #H'00D3, R4 ; dataflow R4=H'00D3; cycles=3 + +loc_598A: +598A: 15 F7 5B 24 ADD:G.B @H'F75B, R4 ; refs ram_F75B in on_chip_ram; cycles=7 +598E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +5991: 1E E5 38 BSR loc_3ECC ; cycles=14 +5994: 19 RTS ; cycles=12 + +loc_5A7A: +5A7A: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=7 +5A7E: 26 10 BNE loc_5A90 ; cycles=3/7 nt/t +5A80: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A84: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A88: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A8C: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 + +loc_5A90: +5A90: 19 RTS ; cycles=12 + +loc_5A91: +5A91: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5A94: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5A98: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5A9B: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5A9F: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5AA2: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5AA6: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5AA9: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5AAD: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5AB0: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5AB4: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5AB7: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5ABB: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5ABE: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5AC2: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5AC5: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5AC9: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5ACC: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5AD0: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5AD3: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5AD7: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5ADA: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5ADE: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5AE1: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5AE5: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5AE8: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5AEC: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5AEF: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5AF3: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5AF6: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5AFA: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5AFD: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5B01: 19 RTS ; cycles=13 + +loc_5B02: +5B02: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=7 +5B06: A0 12 EXTU.B R0 ; cycles=3 +5B08: 40 01 CMP:E #H'01, R0 ; cycles=2 +5B0A: 23 48 BLS loc_5B54 ; cycles=3/7 nt/t +5B0C: 40 09 CMP:E #H'09, R0 ; cycles=2 +5B0E: 22 1D BHI loc_5B2D ; cycles=3/7 nt/t +5B10: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=7 +5B14: 15 FA FF 90 MOV:G.B R0, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=7 +5B18: 15 FA FE 06 2F MOV:G.B #H'2F, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5B1D: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=6 +5B21: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B23: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=6 +5B27: 15 FA FD 90 MOV:G.B R0, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5B2B: 20 27 BRA loc_5B54 ; cycles=8 + +loc_5B2D: +5B2D: A0 1A SHLL.B R0 ; cycles=2 +5B2F: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=6 +5B33: 1D FA FE 90 MOV:G.W R0, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=6 +5B37: 15 FA FD 06 2F MOV:G.B #H'2F, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=9 +5B3C: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +5B40: A0 12 EXTU.B R0 ; cycles=3 +5B42: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B44: A0 1A SHLL.B R0 ; cycles=2 +5B46: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=7 +5B4A: 15 FA FC 90 MOV:G.B R0, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5B4E: A0 10 SWAP.B R0 ; cycles=3 +5B50: 15 FA FB 90 MOV:G.B R0, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=7 + +loc_5B54: +5B54: 19 RTS ; cycles=12 + +loc_5C91: +5C91: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +5C95: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5C99: 27 62 BEQ loc_5CFD ; cycles=3/8 nt/t +5C9B: A9 1A SHLL.W R1 ; cycles=3 +5C9D: 1D F7 4E 16 TST.W @H'F74E ; refs ram_F74E in on_chip_ram; cycles=6 +5CA1: 27 10 BEQ loc_5CB3 ; cycles=3/8 nt/t +5CA3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CA7: 1D F7 4E 52 AND.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAB: 1D F7 4E 72 CMP:G.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAF: 27 12 BEQ loc_5CC3 ; cycles=3/8 nt/t +5CB1: 20 4A BRA loc_5CFD ; cycles=8 + +loc_5CB3: +5CB3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CB7: 1D F7 46 52 AND.W @H'F746, R2 ; refs ram_F746 in on_chip_ram; cycles=6 +5CBB: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CBF: 27 3C BEQ loc_5CFD ; cycles=3/8 nt/t +5CC1: 20 00 BRA loc_5CC3 ; cycles=8 + +loc_5CC3: +5CC3: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5CC6: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5CCA: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5CCD: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5CD1: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5CD4: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5CD8: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5CDB: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5CDF: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5CE2: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5CE6: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5CE9: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5CED: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5CF0: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5CF4: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5CF7: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5CFB: 20 18 BRA loc_5D15 ; cycles=8 + +loc_5CFD: +5CFD: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +5D03: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5D09: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +5D0F: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 + +loc_5D15: +5D15: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +5D19: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5D1D: 27 62 BEQ loc_5D81 ; cycles=3/8 nt/t +5D1F: A9 1A SHLL.W R1 ; cycles=3 +5D21: 1D F7 52 16 TST.W @H'F752 ; refs ram_F752 in on_chip_ram; cycles=6 +5D25: 27 10 BEQ loc_5D37 ; cycles=3/8 nt/t +5D27: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D2B: 1D F7 52 52 AND.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D2F: 1D F7 52 72 CMP:G.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D33: 27 12 BEQ loc_5D47 ; cycles=3/8 nt/t +5D35: 20 4A BRA loc_5D81 ; cycles=8 + +loc_5D37: +5D37: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D3B: 1D F7 4A 52 AND.W @H'F74A, R2 ; refs ram_F74A in on_chip_ram; cycles=6 +5D3F: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D43: 27 3C BEQ loc_5D81 ; cycles=3/8 nt/t +5D45: 20 00 BRA loc_5D47 ; cycles=8 + +loc_5D47: +5D47: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5D4A: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5D4E: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5D51: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5D55: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5D58: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5D5C: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5D5F: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5D63: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5D66: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5D6A: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5D6D: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5D71: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5D74: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5D78: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5D7B: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5D7F: 20 18 BRA loc_5D99 ; cycles=8 + +loc_5D81: +5D81: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +5D87: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +5D8D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5D93: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 + +loc_5D99: +5D99: 19 RTS ; cycles=13 + +loc_5FD2: +5FD2: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=7 +5FD6: 15 F7 2F 70 CMP:G.B @H'F72F, R0 ; refs ram_F72F in on_chip_ram; cycles=7 +5FDA: 27 41 BEQ loc_601D ; cycles=3/7 nt/t +5FDC: 1D F7 2C 13 CLR.W @H'F72C ; refs ram_F72C in on_chip_ram; cycles=9 +5FE0: 15 F7 2E 13 CLR.B @H'F72E ; refs ram_F72E in on_chip_ram; cycles=9 +5FE4: 15 F7 2F 90 MOV:G.B R0, @H'F72F ; refs ram_F72F in on_chip_ram; cycles=7 +5FE8: A4 12 EXTU.B R4 ; cycles=3 + +loc_5FEA: +5FEA: AC 80 MOV:G.W R4, R0 ; cycles=3 +5FEC: A0 1A SHLL.B R0 ; cycles=2 +5FEE: AB 20 ADD:G.W R3, R0 ; cycles=3 +5FF0: D8 80 MOV:G.W @R0, R0 ; cycles=6 +5FF2: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +5FF4: D8 81 MOV:G.W @R0, R1 ; cycles=6 +5FF6: 15 F7 31 71 CMP:G.B @H'F731, R1 ; refs ram_F731 in on_chip_ram; cycles=7 +5FFA: 25 1E BCS loc_601A ; cycles=3/7 nt/t +5FFC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +5FFE: D8 16 TST.W @R0 ; cycles=6 +6000: 27 10 BEQ loc_6012 ; cycles=3/7 nt/t + +loc_6002: +6002: D8 81 MOV:G.W @R0, R1 ; cycles=6 +6004: 27 14 BEQ loc_601A ; cycles=3/7 nt/t +6006: A9 1A SHLL.W R1 ; cycles=3 +6008: F9 E4 00 16 TST.W @(-H'1C00,R1) ; cycles=7 +600C: 26 04 BNE loc_6012 ; cycles=3/7 nt/t +600E: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +6010: 20 F0 BRA loc_6002 ; cycles=7 + +loc_6012: +6012: 1D F7 2C 4C BSET.W R4, @H'F72C ; refs ram_F72C in on_chip_ram; cycles=9 +6016: 15 F7 2E 08 ADD:Q.B #1, @H'F72E ; refs ram_F72E in on_chip_ram; cycles=9 + +loc_601A: +601A: 01 BC CD SCB/F R4, loc_5FEA ; cycles=3/4/8 false/-1/t + +loc_601D: +601D: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=6 +6021: 27 1D BEQ loc_6040 ; cycles=3/8 nt/t +6023: 15 F7 33 04 FF CMP:G.B #H'FF, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=6 +6028: 27 08 BEQ loc_6032 ; cycles=3/7 nt/t +602A: 15 F7 33 70 CMP:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +602E: 23 0A BLS loc_603A ; cycles=3/7 nt/t +6030: 20 20 BRA loc_6052 ; cycles=7 + +loc_6032: +6032: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +6034: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +6038: 20 18 BRA loc_6052 ; cycles=7 + +loc_603A: +603A: 15 F7 33 13 CLR.B @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +603E: 20 12 BRA loc_6052 ; cycles=7 + +loc_6040: +6040: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +6044: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +6049: 15 F7 2F 13 CLR.B @H'F72F ; refs ram_F72F in on_chip_ram; cycles=8 +604D: 5C FF FE MOV:I.W #H'FFFE, R4 ; dataflow R4=H'FFFE; cycles=3 +6050: 20 18 BRA loc_606A ; cycles=7 + +loc_6052: +6052: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +6056: A0 12 EXTU.B R0 ; cycles=3 +6058: 1D F7 2C 81 MOV:G.W @H'F72C, R1 ; refs ram_F72C in on_chip_ram; cycles=7 +605C: 5C 00 FF MOV:I.W #H'00FF, R4 ; dataflow R4=H'00FF; cycles=3 + +loc_605F: +605F: A4 08 ADD:Q.B #1, R4 ; cycles=4 +6061: A9 1B SHLR.W R1 ; cycles=3 +6063: 24 FA BCC loc_605F ; cycles=3/8 nt/t +6065: 01 B8 F7 SCB/F R0, loc_605F ; cycles=3/4/9 false/-1/t +6068: A4 1A SHLL.B R4 ; cycles=2 + +loc_606A: +606A: 19 RTS ; cycles=12 + +loc_606B: +606B: 1D F7 32 80 MOV:G.W @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +606F: 1D F7 5C 70 CMP:G.W @H'F75C, R0 ; refs ram_F75C in on_chip_ram; cycles=6 +6073: 27 65 BEQ loc_60DA ; cycles=3/8 nt/t +6075: 1D F7 5C 90 MOV:G.W R0, @H'F75C ; refs ram_F75C in on_chip_ram; cycles=6 +6079: A9 1A SHLL.W R1 ; cycles=3 +607B: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +607D: F1 E0 00 80 MOV:G.B @(-H'2000,R1), R0 ; cycles=6 +6081: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +6085: A2 10 SWAP.B R2 ; cycles=3 +6087: F1 E0 01 80 MOV:G.B @(-H'1FFF,R1), R0 ; cycles=6 +608B: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +608F: 1D F7 5E 92 MOV:G.W R2, @H'F75E ; refs ram_F75E in on_chip_ram; cycles=6 +6093: F1 E0 02 80 MOV:G.B @(-H'1FFE,R1), R0 ; cycles=6 +6097: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +609B: A2 10 SWAP.B R2 ; cycles=3 +609D: F1 E0 03 80 MOV:G.B @(-H'1FFD,R1), R0 ; cycles=6 +60A1: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60A5: 1D F7 60 92 MOV:G.W R2, @H'F760 ; refs ram_F760 in on_chip_ram; cycles=6 +60A9: F1 E0 04 80 MOV:G.B @(-H'1FFC,R1), R0 ; cycles=6 +60AD: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60B1: A2 10 SWAP.B R2 ; cycles=3 +60B3: F1 E0 05 80 MOV:G.B @(-H'1FFB,R1), R0 ; cycles=6 +60B7: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60BB: 1D F7 62 92 MOV:G.W R2, @H'F762 ; refs ram_F762 in on_chip_ram; cycles=6 +60BF: F1 E0 06 80 MOV:G.B @(-H'1FFA,R1), R0 ; cycles=6 +60C3: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60C7: A2 10 SWAP.B R2 ; cycles=3 +60C9: F1 E0 07 80 MOV:G.B @(-H'1FF9,R1), R0 ; cycles=6 +60CD: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60D1: 1D F7 64 92 MOV:G.W R2, @H'F764 ; refs ram_F764 in on_chip_ram; cycles=6 +60D5: 15 F7 5B 06 01 MOV:G.B #H'01, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=9 + +loc_60DA: +60DA: 19 RTS ; cycles=12 + +loc_6173: +6173: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +6179: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +617F: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +6185: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +618B: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +6191: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +6197: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +619D: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +61A3: 19 RTS ; cycles=13 + +loc_61D5: +61D5: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +61DB: 1D FA F2 07 55 52 MOV:G.W #H'5552, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +61E1: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +61E7: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +61ED: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +61F3: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +61F9: 1D FA FC 07 43 48 MOV:G.W #H'4348, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +61FF: 1D FA FE 07 52 20 MOV:G.W #H'5220, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +6205: 19 RTS ; cycles=13 + +loc_6206: +6206: 0C 01 FF 55 AND.W #H'01FF, R5 ; cycles=4 +620A: 4D 00 7F CMP:I #H'007F, R5 ; cycles=3 +620D: 23 07 BLS loc_6216 ; cycles=3/8 nt/t +620F: 4D 01 7F CMP:I #H'017F, R5 ; cycles=3 +6212: 23 04 BLS loc_6218 ; cycles=3/7 nt/t +6214: 20 0C BRA loc_6222 ; cycles=7 + +loc_6216: +6216: 20 12 BRA loc_622A ; cycles=7 + +loc_6218: +6218: 0C 00 80 35 SUB.W #H'0080, R5 ; cycles=4 +621C: 0C 01 00 25 ADD:G.W #H'0100, R5 ; cycles=4 +6220: 20 08 BRA loc_622A ; cycles=7 + +loc_6222: +6222: 0C 01 80 35 SUB.W #H'0180, R5 ; cycles=4 +6226: 0C 02 00 25 ADD:G.W #H'0200, R5 ; cycles=4 + +loc_622A: +622A: 19 RTS ; cycles=12 + +loc_622B: +622B: AD 84 MOV:G.W R5, R4 ; cycles=3 +622D: A5 12 EXTU.B R5 ; cycles=3 +622F: A4 10 SWAP.B R4 ; cycles=3 +6231: 04 07 54 AND.B #H'07, R4 ; cycles=3 +6234: 44 00 CMP:E #H'00, R4 ; cycles=2 +6236: 27 0C BEQ loc_6244 ; cycles=3/7 nt/t +6238: 44 01 CMP:E #H'01, R4 ; cycles=2 +623A: 27 11 BEQ loc_624D ; cycles=3/7 nt/t +623C: 44 02 CMP:E #H'02, R4 ; cycles=2 +623E: 27 16 BEQ loc_6256 ; cycles=3/7 nt/t +6240: 44 03 CMP:E #H'03, R4 ; cycles=2 +6242: 27 1B BEQ loc_625F ; cycles=3/7 nt/t + +loc_6244: +6244: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6246: 22 17 BHI loc_625F ; cycles=3/7 nt/t +6248: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +624B: 20 17 BRA loc_6264 ; cycles=8 + +loc_624D: +624D: 45 FF CMP:E #H'FF, R5 ; cycles=2 +624F: 22 0E BHI loc_625F ; cycles=3/8 nt/t +6251: 5C 00 80 MOV:I.W #H'0080, R4 ; dataflow R4=H'0080; cycles=3 +6254: 20 0E BRA loc_6264 ; cycles=7 + +loc_6256: +6256: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6258: 22 05 BHI loc_625F ; cycles=3/7 nt/t +625A: 5C 01 80 MOV:I.W #H'0180, R4 ; dataflow R4=H'0180; cycles=3 +625D: 20 05 BRA loc_6264 ; cycles=8 + +loc_625F: +625F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +6261: 5D 01 FF MOV:I.W #H'01FF, R5 ; dataflow R5=H'01FF; cycles=3 + +loc_6264: +6264: AC 25 ADD:G.W R4, R5 ; cycles=3 +6266: 19 RTS ; cycles=12 +6F64: 1E CE ED BSR loc_3E54 ; cycles=13 +6F67: 15 F7 11 80 MOV:G.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=6 +6F6B: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +6F6E: 1D E1 1E FB BTST.W #11, @H'E11E ; refs mem_E11E in program_or_external; cycles=7 +6F72: 27 02 BEQ loc_6F76 ; cycles=3/7 nt/t +6F74: A0 C6 BSET.B #6, R0 ; cycles=2 + +loc_6F76: +6F76: 1D E1 1E FC BTST.W #12, @H'E11E ; refs mem_E11E in program_or_external; cycles=7 +6F7A: 27 02 BEQ loc_6F7E ; cycles=3/7 nt/t +6F7C: A0 C4 BSET.B #4, R0 ; cycles=2 + +loc_6F7E: +6F7E: 15 F7 11 90 MOV:G.B R0, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=7 +6F82: 20 10 BRA loc_6F94 ; cycles=7 + +loc_6F94: +6F94: 58 6F 84 MOV:I.W #H'6F84, R0 ; LCD text xref H'6F84 'OTHERS Xo'; dataflow R0=H'6F84; cycles=3 +6F97: 1E EA F7 BSR loc_5A91 ; cycles=14 +6F9A: 1E EB 65 BSR loc_5B02 ; cycles=13 +6F9D: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +6FA0: 1E CF 29 BSR loc_3ECC ; cycles=13 +6FA3: 1E F1 CD BSR loc_6173 ; cycles=14 +6FA6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +6FA9: 1E CF 20 BSR loc_3ECC ; cycles=14 +6FAC: 20 10 BRA loc_6FBE ; cycles=7 + +loc_6FBE: +6FBE: 58 6F AE MOV:I.W #H'6FAE, R0 ; LCD text xref H'6FAE 'SHUTTER Xo'; dataflow R0=H'6FAE; cycles=3 +6FC1: 1E EA CD BSR loc_5A91 ; cycles=14 +6FC4: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +6FC7: 1E CF 02 BSR loc_3ECC ; cycles=14 +6FCA: 20 10 BRA loc_6FDC ; cycles=7 + +loc_6FDC: +6FDC: 58 6F CC MOV:I.W #H'6FCC, R0 ; dataflow R0=H'6FCC; cycles=3 +6FDF: 1E EC AF BSR loc_5C91 ; cycles=14 +6FE2: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +6FE5: 1E CE E4 BSR loc_3ECC ; cycles=14 +6FE8: 19 RTS ; cycles=12 +7042: 15 F7 26 06 64 MOV:G.B #H'64, @H'F726 ; refs ram_F726 in on_chip_ram; cycles=9 +7047: 1E E4 B6 BSR loc_5500 ; cycles=14 +704A: 20 51 BRA loc_709D ; cycles=7 + +loc_709D: +709D: 20 10 BRA loc_70AF ; cycles=8 + +loc_70AF: +70AF: 58 70 9F MOV:I.W #H'709F, R0 ; LCD text xref H'709F 'OTHERS Xp'; dataflow R0=H'709F; cycles=3 +70B2: 1E E9 DC BSR loc_5A91 ; cycles=13 +70B5: 1E EA 4A BSR loc_5B02 ; cycles=14 +70B8: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +70BB: 1E CE 0E BSR loc_3ECC ; cycles=14 +70BE: 20 10 BRA loc_70D0 ; cycles=7 + +loc_70D0: +70D0: 58 70 C0 MOV:I.W #H'70C0, R0 ; LCD text xref H'70C0 'COPY TO SLAVES~Xp'; dataflow R0=H'70C0; cycles=3 +70D3: 1E E9 BB BSR loc_5A91 ; cycles=14 +70D6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +70D9: 1E CD F0 BSR loc_3ECC ; cycles=14 +70DC: 1E F0 94 BSR loc_6173 ; cycles=13 +70DF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +70E2: 1E CD E7 BSR loc_3ECC ; cycles=13 +70E5: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +70E8: 1E CD E1 BSR loc_3ECC ; cycles=13 +70EB: 1E E9 8C BSR loc_5A7A ; cycles=14 +70EE: 19 RTS ; cycles=12 +70F6: 1D F7 36 07 10 43 MOV:G.W #H'1043, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +70FC: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=11 +7101: 1D F7 3A 07 20 43 MOV:G.W #H'2043, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=9 +7107: 1D F7 3C 06 00 MOV:G.W #H'00, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +710C: 1D F7 40 07 20 43 MOV:G.W #H'2043, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +7112: 1D F7 3E 06 00 MOV:G.W #H'00, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=11 +7117: 1D F7 42 06 00 MOV:G.W #H'00, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=9 +711C: 1D F7 54 06 46 MOV:G.W #H'46, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +7121: 20 10 BRA loc_7133 ; cycles=8 + +loc_7133: +7133: 58 71 23 MOV:I.W #H'7123, R0 ; dataflow R0=H'7123; cycles=3 +7136: 1E E9 58 BSR loc_5A91 ; cycles=13 +7139: 1E E9 C6 BSR loc_5B02 ; cycles=14 +713C: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +713F: 1E CD 8A BSR loc_3ECC ; cycles=14 +7142: 20 10 BRA loc_7154 ; cycles=7 + +loc_7154: +7154: 58 71 44 MOV:I.W #H'7144, R0 ; LCD text xref H'7144 'CAM ID SET~XqD'; dataflow R0=H'7144; cycles=3 +7157: 1E E9 37 BSR loc_5A91 ; cycles=14 +715A: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +715D: 1E CD 6C BSR loc_3ECC ; cycles=14 +7160: 59 00 43 MOV:I.W #H'0043, R1 ; dataflow R1=H'0043; cycles=3 +7163: 1E EF 05 BSR loc_606B ; cycles=14 +7166: 1E E7 8E BSR loc_58F7 ; cycles=13 +7169: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +716C: 1E CD 5D BSR loc_3ECC ; cycles=13 +716F: 1E F0 63 BSR loc_61D5 ; cycles=14 +7172: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +7175: 1E CD 54 BSR loc_3ECC ; cycles=14 +7178: 58 00 02 MOV:I.W #H'0002, R0 ; dataflow R0=H'0002; cycles=3 +717B: 1E E7 EC BSR loc_596A ; cycles=14 +717E: 1E E8 F9 BSR loc_5A7A ; cycles=13 +7181: 19 RTS ; cycles=13 +930A: 5B 93 1C MOV:I.W #H'931C, R3 ; dataflow R3=H'931C; cycles=3 +930D: 54 04 MOV:E.B #H'04, R4 ; dataflow R4=H'04; cycles=2 +930F: 1E CC C0 BSR loc_5FD2 ; cycles=14 +9312: FC 93 1C 84 MOV:G.W @(-H'6CE4,R4), R4 ; cycles=7 +9316: 11 DC JSR @R4 ; JSR @R4 uses R4; target not resolved; cycles=13 +9318: 19 RTS ; cycles=12 + +loc_BA26: +BA26: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=7 +BA2A: 26 FA BNE loc_BA26 ; cycles=3/7 nt/t +BA2C: 15 F9 C0 06 64 MOV:G.B #H'64, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BA31: 15 F9 C4 06 07 MOV:G.B #H'07, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +BA36: 1D F8 50 80 MOV:G.W @H'F850, R0 ; refs ram_F850 in on_chip_ram; cycles=7 +BA3A: 1D F8 58 90 MOV:G.W R0, @H'F858 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA3E: 1D F8 52 80 MOV:G.W @H'F852, R0 ; refs ram_F852 in on_chip_ram; cycles=7 +BA42: 1D F8 5A 90 MOV:G.W R0, @H'F85A ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA46: 15 F8 54 80 MOV:G.B @H'F854, R0 ; refs ram_F854 in on_chip_ram; cycles=7 +BA4A: 15 F8 5C 90 MOV:G.B R0, @H'F85C ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA4E: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high; dataflow R0=H'5A; cycles=2 +BA50: 15 F8 58 60 XOR.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA54: 15 F8 59 60 XOR.B @H'F859, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F859 in on_chip_ram; cycles=7 +BA58: 15 F8 5A 60 XOR.B @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA5C: 15 F8 5B 60 XOR.B @H'F85B, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85B in on_chip_ram; cycles=7 +BA60: 15 F8 5C 60 XOR.B @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA64: 15 F8 5D 90 MOV:G.B R0, @H'F85D ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85D in on_chip_ram; cycles=7 + +loc_BA68: +BA68: 15 FE DC F7 BTST.B #7, @SCI1_SSR ; wait for SCI1 transmit data register empty (TDRE=1); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR in register_field; cycles=7 +BA6C: 27 FA BEQ loc_BA68 ; repeat SCI1 transmit-empty wait while TDRE=0; cycles=3/7 nt/t +BA6E: 15 F8 58 80 MOV:G.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA72: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=7 +BA76: 15 F9 C2 06 01 MOV:G.B #H'01, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high; refs ram_F9C2 in on_chip_ram; cycles=9 +BA7B: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BA7F: 15 FE DA C7 BSET.B #7, @SCI1_SCR ; set TIE (bit 7) of SCI1_SCR; enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=8 +BA83: 19 RTS ; cycles=13 + +vec_sci1_txi_BA84: +BA84: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BA88: 27 1F BEQ loc_BAA9 ; cycles=3/7 nt/t +BA8A: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BA8E: 27 19 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA90: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BA94: 27 13 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA96: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BA9A: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BA9E: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BAA2: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAA7: 20 48 BRA loc_BAF1 ; cycles=8 + +loc_BAA9: +BAA9: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +BAAB: 15 F9 C2 80 MOV:G.B @H'F9C2, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAAF: A0 12 EXTU.B R0 ; cycles=3 +BAB1: F0 F8 58 80 MOV:G.B @(-H'07A8,R0), R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; cycles=6 +BAB5: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=6 +BAB9: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +BABB: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BABF: 15 F9 C2 08 ADD:Q.B #1, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high; refs ram_F9C2 in on_chip_ram; cycles=8 +BAC3: 15 F9 C2 04 06 CMP:G.B #H'06, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAC8: 26 27 BNE loc_BAF1 ; cycles=3/7 nt/t +BACA: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BACE: 15 F7 95 F6 BTST.B #6, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +BAD2: 26 14 BNE loc_BAE8 ; cycles=3/7 nt/t +BAD4: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +BAD8: 26 07 BNE loc_BAE1 ; cycles=3/7 nt/t +BADA: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BADF: 20 0C BRA loc_BAED ; cycles=8 + +loc_BAE1: +BAE1: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAE6: 20 05 BRA loc_BAED ; cycles=7 + +loc_BAE8: +BAE8: 15 F9 C0 06 F0 MOV:G.B #H'F0, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BAED: +BAED: 15 F9 C1 13 CLR.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=8 + +loc_BAF1: +BAF1: 0A RTE ; cycles=14 + +loc_BAF2: +BAF2: 15 F9 B5 81 MOV:G.B @H'F9B5, R1 ; refs ram_F9B5 in on_chip_ram; cycles=7 +BAF6: A1 12 EXTU.B R1 ; cycles=3 +BAF8: 15 F9 B0 71 CMP:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +BAFC: 26 02 BNE loc_BB00 ; cycles=3/7 nt/t +BAFE: 20 56 BRA loc_BB56 ; cycles=7 + +loc_BB00: +BB00: 15 FA A2 C3 BSET.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BB04: A9 80 MOV:G.W R1, R0 ; cycles=3 +BB06: A8 1A SHLL.W R0 ; cycles=3 +BB08: F8 F8 70 80 MOV:G.W @(-H'0790,R0), R0 ; cycles=7 +BB0C: A8 85 MOV:G.W R0, R5 ; cycles=3 +BB0E: 1E A6 F5 BSR loc_6206 ; cycles=13 +BB11: A8 81 MOV:G.W R0, R1 ; cycles=3 +BB13: A1 10 SWAP.B R1 ; cycles=3 +BB15: A1 1B SHLR.B R1 ; cycles=2 +BB17: A1 82 MOV:G.B R1, R2 ; cycles=2 +BB19: 04 07 51 AND.B #H'07, R1 ; cycles=3 +BB1C: 15 F8 50 91 MOV:G.B R1, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=7 +BB20: 15 F8 52 95 MOV:G.B R5, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BB24: A5 10 SWAP.B R5 ; cycles=3 +BB26: 04 78 52 AND.B #H'78, R2 ; cycles=3 +BB29: A2 45 OR.B R2, R5 ; cycles=2 +BB2B: 15 F8 51 95 MOV:G.B R5, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BB2F: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +BB33: A8 1A SHLL.W R0 ; cycles=3 +BB35: F8 E8 00 84 MOV:G.W @(-H'1800,R0), R4 ; cycles=6 +BB39: 15 F8 54 94 MOV:G.B R4, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BB3D: A4 10 SWAP.B R4 ; cycles=3 +BB3F: 15 F8 53 94 MOV:G.B R4, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=6 +BB43: 1E FE E0 BSR loc_BA26 ; cycles=14 +BB46: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=11 +BB4C: 15 F9 C8 06 14 MOV:G.B #H'14, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=9 +BB51: 15 FA A3 06 80 MOV:G.B #H'80, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 + +loc_BB56: +BB56: 19 RTS ; cycles=12 + +vec_sci1_eri_BB57: +BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; refs ram_FAA4 in on_chip_ram; cycles=8 +BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 + +vec_sci1_rxi_BB67: +BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR in register_field; cycles=6 +BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=6 +BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t +BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BB7B: 20 0D BRA loc_BB8A ; cycles=8 + +loc_BB7D: +BB7D: 15 F9 C3 04 05 CMP:G.B #H'05, @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +BB82: 23 06 BLS loc_BB8A ; cycles=3/7 nt/t +BB84: 15 FA A4 13 CLR.B @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=9 +BB88: 20 19 BRA loc_BBA3 ; cycles=7 + +loc_BB8A: +BB8A: 15 F9 C3 81 MOV:G.B @H'F9C3, R1 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BB8E: A1 12 EXTU.B R1 ; cycles=3 +BB90: F1 F8 68 90 MOV:G.B R0, @(-H'0798,R1) ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high; cycles=7 +BB94: A1 08 ADD:Q.B #1, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; cycles=4 +BB96: 15 F9 C3 91 MOV:G.B R1, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; refs ram_F9C3 in on_chip_ram; cycles=7 +BB9A: 41 06 CMP:E #H'06, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high; cycles=2 +BB9C: 26 05 BNE loc_BBA3 ; cycles=3/7 nt/t +BB9E: 15 F9 C5 06 14 MOV:G.B #H'14, @H'F9C5 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BBA3: +BBA3: 15 F9 C1 06 05 MOV:G.B #H'05, @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=9 +BBA8: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +BBAA: 0A RTE ; cycles=13 + +loc_BBAB: +BBAB: 15 F9 C3 04 06 CMP:G.B #H'06, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high; refs ram_F9C3 in on_chip_ram; cycles=6 +BBB0: 36 02 BC BNE loc_BE6F ; cycles=3/7 nt/t +BBB3: 1D F8 68 80 MOV:G.W @H'F868, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F868 in on_chip_ram; cycles=6 +BBB7: 1D F8 60 90 MOV:G.W R0, @H'F860 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=6 +BBBB: 1D F8 6A 80 MOV:G.W @H'F86A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86A in on_chip_ram; cycles=6 +BBBF: 1D F8 62 90 MOV:G.W R0, @H'F862 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=6 +BBC3: 1D F8 6C 80 MOV:G.W @H'F86C, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86C in on_chip_ram; cycles=6 +BBC7: 1D F8 64 90 MOV:G.W R0, @H'F864 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=6 +BBCB: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BBCF: 15 FA A4 F7 BTST.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=6 +BBD3: 36 02 53 BNE loc_BE29 ; cycles=3/8 nt/t +BBD6: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; dataflow R0=H'5A; cycles=2 +BBD8: 15 F8 60 60 XOR.B @H'F860, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=7 +BBDC: 15 F8 61 60 XOR.B @H'F861, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F861 in on_chip_ram; cycles=7 +BBE0: 15 F8 62 60 XOR.B @H'F862, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=7 +BBE4: 15 F8 63 60 XOR.B @H'F863, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F863 in on_chip_ram; cycles=7 +BBE8: 15 F8 64 60 XOR.B @H'F864, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=7 +BBEC: 15 F8 65 70 CMP:G.B @H'F865, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F865 in on_chip_ram; cycles=7 +BBF0: 36 02 36 BNE loc_BE29 ; cycles=3/7 nt/t +BBF3: 15 FA A6 13 CLR.B @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BBF7: 15 F8 61 85 MOV:G.B @H'F861, R5 ; refs ram_F861 in on_chip_ram; cycles=6 +BBFB: A5 10 SWAP.B R5 ; cycles=3 +BBFD: 15 F8 62 85 MOV:G.B @H'F862, R5 ; refs ram_F862 in on_chip_ram; cycles=6 +BC01: 1E A6 27 BSR loc_622B ; cycles=14 +BC04: AD 84 MOV:G.W R5, R4 ; cycles=3 +BC06: AC 1A SHLL.W R4 ; cycles=3 +BC08: 15 F8 60 80 MOV:G.B @H'F860, R0 ; refs ram_F860 in on_chip_ram; cycles=7 +BC0C: 04 07 50 AND.B #H'07, R0 ; cycles=3 +BC0F: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BC13: 26 25 BNE loc_BC3A ; cycles=3/8 nt/t + +loc_BC15: +BC15: 15 FA A2 C7 BSET.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC19: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=6 +BC1D: 36 00 EB BNE loc_BD0B ; cycles=3/8 nt/t +BC20: 40 00 CMP:E #H'00, R0 ; cycles=2 +BC22: 27 45 BEQ loc_BC69 ; cycles=3/7 nt/t +BC24: 40 01 CMP:E #H'01, R0 ; cycles=2 +BC26: 37 00 AE BEQ loc_BCD7 ; cycles=3/7 nt/t +BC29: 40 02 CMP:E #H'02, R0 ; cycles=2 +BC2B: 37 00 D6 BEQ loc_BD04 ; cycles=3/8 nt/t +BC2E: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC30: 37 01 D2 BEQ loc_BE05 ; cycles=3/7 nt/t +BC33: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC37: 30 02 35 BRA loc_BE6F ; cycles=8 + +loc_BC3A: +BC3A: A0 F2 BTST.B #2, R0 ; cycles=2 +BC3C: 27 1E BEQ loc_BC5C ; cycles=3/7 nt/t +BC3E: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=7 +BC42: 36 01 E2 BNE loc_BE27 ; cycles=3/7 nt/t +BC45: 40 04 CMP:E #H'04, R0 ; cycles=2 +BC47: 37 00 C4 BEQ loc_BD0E ; cycles=3/8 nt/t +BC4A: 40 05 CMP:E #H'05, R0 ; cycles=2 +BC4C: 37 01 31 BEQ loc_BD80 ; cycles=3/7 nt/t +BC4F: 40 06 CMP:E #H'06, R0 ; cycles=2 +BC51: 37 01 87 BEQ loc_BDDB ; cycles=3/8 nt/t +BC54: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC56: 37 01 AC BEQ loc_BE05 ; cycles=3/7 nt/t +BC59: 30 02 13 BRA loc_BE6F ; cycles=8 + +loc_BC5C: +BC5C: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BC60: 37 02 0C BEQ loc_BE6F ; cycles=3/7 nt/t +BC63: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BC67: 20 AC BRA loc_BC15 ; cycles=8 + +loc_BC69: +BC69: AD 16 TST.W R5 ; cycles=3 +BC6B: 26 1E BNE loc_BC8B ; cycles=3/8 nt/t +BC6D: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC71: A0 10 SWAP.B R0 ; cycles=3 +BC73: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BC75: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC79: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC7D: 15 F8 64 06 80 MOV:G.B #H'80, @H'F864 ; refs ram_F864 in on_chip_ram; cycles=9 +BC82: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BC86: 1E 01 E7 BSR loc_BE70 ; cycles=13 +BC89: 20 25 BRA loc_BCB0 ; cycles=8 + +loc_BC8B: +BC8B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC8F: A0 10 SWAP.B R0 ; cycles=3 +BC91: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BC95: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC99: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC9D: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BCA1: FC C5 64 81 MOV:G.W @(-H'3A9C,R4), R1 ; cycles=6 +BCA5: A1 12 EXTU.B R1 ; cycles=3 +BCA7: 27 04 BEQ loc_BCAD ; cycles=3/8 nt/t +BCA9: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 + +loc_BCAD: +BCAD: 1E 01 C0 BSR loc_BE70 ; cycles=14 + +loc_BCB0: +BCB0: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCB5: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=6 +BCB9: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BCBD: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=6 +BCC1: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BCC5: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BCC9: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BCCD: 1E FD 56 BSR loc_BA26 ; cycles=14 +BCD0: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BCD4: 30 01 98 BRA loc_BE6F ; cycles=7 + +loc_BCD7: +BCD7: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCDC: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BCE0: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCE4: 15 F8 62 80 MOV:G.B @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BCE8: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCEC: FC E0 00 80 MOV:G.W @(-H'2000,R4), R0 ; cycles=7 +BCF0: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BCF4: A0 10 SWAP.B R0 ; cycles=3 +BCF6: 15 F8 53 90 MOV:G.B R0, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=7 +BCFA: 1E FD 29 BSR loc_BA26 ; cycles=13 +BCFD: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD01: 30 01 6B BRA loc_BE6F ; cycles=8 + +loc_BD04: +BD04: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BD08: 30 01 64 BRA loc_BE6F ; cycles=7 + +loc_BD0B: +BD0B: 30 01 61 BRA loc_BE6F ; cycles=8 + +loc_BD0E: +BD0E: AD 16 TST.W R5 ; cycles=3 +BD10: 26 19 BNE loc_BD2B ; cycles=3/7 nt/t +BD12: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=7 +BD16: A0 10 SWAP.B R0 ; cycles=3 +BD18: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BD1A: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=7 +BD1E: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=7 +BD22: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BD26: 1E 01 47 BSR loc_BE70 ; cycles=13 +BD29: 20 3C BRA loc_BD67 ; cycles=8 + +loc_BD2B: +BD2B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BD2F: A0 10 SWAP.B R0 ; cycles=3 +BD31: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BD35: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BD39: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BD3D: F4 C5 65 81 MOV:G.B @(-H'3A9B,R4), R1 ; cycles=6 +BD41: A1 12 EXTU.B R1 ; cycles=3 +BD43: 27 1F BEQ loc_BD64 ; cycles=3/8 nt/t +BD45: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 +BD49: 15 F7 6E F7 BTST.B #7, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +BD4D: 27 15 BEQ loc_BD64 ; cycles=3/8 nt/t +BD4F: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +BD51: 15 F7 6E 84 MOV:G.B @H'F76E, R4 ; refs ram_F76E in on_chip_ram; cycles=6 +BD55: A4 10 SWAP.B R4 ; cycles=3 +BD57: A1 84 MOV:G.B R1, R4 ; cycles=2 +BD59: 0C 0F FE 54 AND.W #H'0FFE, R4 ; cycles=4 +BD5D: A8 85 MOV:G.W R0, R5 ; cycles=3 +BD5F: 1E 02 7E BSR loc_BFE0 ; cycles=14 +BD62: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 + +loc_BD64: +BD64: 1E 01 09 BSR loc_BE70 ; cycles=13 + +loc_BD67: +BD67: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BD6B: 27 08 BEQ loc_BD75 ; cycles=3/8 nt/t +BD6D: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BD71: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BD75: +BD75: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BD79: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD7D: 30 00 EF BRA loc_BE6F ; cycles=8 + +loc_BD80: +BD80: 4D 00 6C CMP:I #H'006C, R5 ; cycles=3 +BD83: 27 3A BEQ loc_BDBF ; cycles=3/8 nt/t +BD85: 4D 00 6D CMP:I #H'006D, R5 ; cycles=3 +BD88: 27 35 BEQ loc_BDBF ; cycles=3/7 nt/t +BD8A: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD8D: 27 30 BEQ loc_BDBF ; cycles=3/8 nt/t +BD8F: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD92: 27 2B BEQ loc_BDBF ; cycles=3/7 nt/t +BD94: 15 F7 31 F7 BTST.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +BD98: 27 28 BEQ loc_BDC2 ; cycles=3/7 nt/t +BD9A: 4D 00 6B CMP:I #H'006B, R5 ; cycles=3 +BD9D: 27 16 BEQ loc_BDB5 ; cycles=3/8 nt/t +BD9F: 4D 00 96 CMP:I #H'0096, R5 ; cycles=3 +BDA2: 27 11 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDA4: 4D 00 97 CMP:I #H'0097, R5 ; cycles=3 +BDA7: 27 0C BEQ loc_BDB5 ; cycles=3/8 nt/t +BDA9: 4D 00 C6 CMP:I #H'00C6, R5 ; cycles=3 +BDAC: 27 07 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDAE: 4D 00 F8 CMP:I #H'00F8, R5 ; cycles=3 +BDB1: 27 02 BEQ loc_BDB5 ; cycles=3/8 nt/t +BDB3: 20 0D BRA loc_BDC2 ; cycles=8 + +loc_BDB5: +BDB5: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +BDB9: 15 F7 90 D7 BCLR.B #7, @H'F790 ; refs ram_F790 in on_chip_ram; cycles=8 +BDBD: 20 03 BRA loc_BDC2 ; cycles=8 + +loc_BDBF: +BDBF: 1E 00 AE BSR loc_BE70 ; cycles=14 + +loc_BDC2: +BDC2: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BDC6: 27 08 BEQ loc_BDD0 ; cycles=3/7 nt/t +BDC8: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 +BDCC: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 + +loc_BDD0: +BDD0: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BDD4: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BDD8: 30 00 94 BRA loc_BE6F ; cycles=7 + +loc_BDDB: +BDDB: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BDDF: A0 10 SWAP.B R0 ; cycles=3 +BDE1: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BDE5: FC E4 00 90 MOV:G.W R0, @(-H'1C00,R4) ; cycles=6 +BDE9: F5 EC 00 C6 BSET.B #6, @(-H'1400,R5) ; cycles=8 +BDED: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BDF1: 27 08 BEQ loc_BDFB ; cycles=3/8 nt/t +BDF3: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BDF7: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BDFB: +BDFB: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BDFF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE03: 20 6A BRA loc_BE6F ; cycles=8 + +loc_BE05: +BE05: 1D F8 58 80 MOV:G.W @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=6 +BE09: 1D F8 50 90 MOV:G.W R0, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=6 +BE0D: 1D F8 5A 80 MOV:G.W @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=6 +BE11: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BE15: 1D F8 5C 80 MOV:G.W @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=6 +BE19: 1D F8 54 90 MOV:G.W R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BE1D: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE22: 1E FC 01 BSR loc_BA26 ; cycles=13 +BE25: 20 48 BRA loc_BE6F ; cycles=8 + +loc_BE27: +BE27: 20 46 BRA loc_BE6F ; cycles=8 + +loc_BE29: +BE29: 15 FA A4 D7 BCLR.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=8 +BE2D: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +BE31: 27 3A BEQ loc_BE6D ; cycles=3/8 nt/t +BE33: 15 FA A6 08 ADD:Q.B #1, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BE37: 15 FA A6 04 02 CMP:G.B #H'02, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=6 +BE3C: 25 0F BCS loc_BE4D ; cycles=3/7 nt/t +BE3E: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE43: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BE47: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE4B: 20 20 BRA loc_BE6D ; cycles=8 + +loc_BE4D: +BE4D: 15 F8 50 06 07 MOV:G.B #H'07, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BE52: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BE56: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BE5A: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BE5E: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BE62: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=7 +BE66: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BE6A: 1E FB B9 BSR loc_BA26 ; cycles=13 + +loc_BE6D: +BE6D: 20 00 BRA loc_BE6F ; cycles=8 + +loc_BE6F: +BE6F: 19 RTS ; cycles=13 + +loc_BE70: +BE70: 15 F9 B9 83 MOV:G.B @H'F9B9, R3 ; refs ram_F9B9 in on_chip_ram; cycles=7 +BE74: A3 12 EXTU.B R3 ; cycles=3 +BE76: AB 1A SHLL.W R3 ; cycles=3 +BE78: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +BE7C: A1 12 EXTU.B R1 ; cycles=3 +BE7E: A9 1A SHLL.W R1 ; cycles=3 + +loc_BE80: +BE80: A3 71 CMP:G.B R3, R1 ; cycles=2 +BE82: 27 0D BEQ loc_BE91 ; cycles=3/7 nt/t +BE84: FB F9 70 75 CMP:G.W @(-H'0690,R3), R5 ; cycles=7 +BE88: 27 13 BEQ loc_BE9D ; cycles=3/7 nt/t +BE8A: A3 09 ADD:Q.B #2, R3 ; cycles=4 +BE8C: 04 3F 53 AND.B #H'3F, R3 ; cycles=3 +BE8F: 20 EF BRA loc_BE80 ; cycles=8 + +loc_BE91: +BE91: F9 F9 70 95 MOV:G.W R5, @(-H'0690,R1) ; cycles=6 +BE95: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +BE99: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_BE9D: +BE9D: 19 RTS ; cycles=13 + +loc_BE9E: +BE9E: 15 FA A5 80 MOV:G.B @H'FAA5, R0 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BEA2: 04 80 50 AND.B #H'80, R0 ; cycles=3 +BEA5: 15 FA A3 50 AND.B @H'FAA3, R0 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEA9: 15 FA A3 90 MOV:G.B R0, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEAD: 26 06 BNE loc_BEB5 ; cycles=3/8 nt/t +BEAF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BEB3: 20 33 BRA loc_BEE8 ; cycles=8 + +loc_BEB5: +BEB5: 1D F9 C6 16 TST.W @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=6 +BEB9: 26 2D BNE loc_BEE8 ; cycles=3/8 nt/t +BEBB: 15 F9 C8 16 TST.B @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=6 +BEBF: 27 23 BEQ loc_BEE4 ; cycles=3/8 nt/t +BEC1: 15 F9 C8 0C ADD:Q.B #-1, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=8 +BEC5: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=9 +BECB: 15 FA A3 F7 BTST.B #7, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BECF: 27 17 BEQ loc_BEE8 ; cycles=3/8 nt/t +BED1: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BED5: 1E FB 4E BSR loc_BA26 ; cycles=14 +BED8: 20 0E BRA loc_BEE8 ; cycles=7 + +loc_BEE4: +BEE4: 15 F9 C5 13 CLR.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BEE8: +BEE8: 19 RTS ; cycles=12 + +vec_frt1_ocia_BEEA: +BEEA: 15 FE 91 D5 BCLR.B #5, @FRT1_TCSR ; clear OCFA (bit 5) of FRT1_TCSR; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; cycles=9 +BEEE: 15 F9 C0 16 TST.B @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=7 +BEF2: 27 04 BEQ loc_BEF8 ; cycles=3/7 nt/t +BEF4: 15 F9 C0 0C ADD:Q.B #-1, @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BEF8: +BEF8: 15 F9 C1 16 TST.B @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=7 +BEFC: 27 04 BEQ loc_BF02 ; cycles=3/7 nt/t +BEFE: 15 F9 C1 0C ADD:Q.B #-1, @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=9 + +loc_BF02: +BF02: 1D F9 C6 16 TST.W @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=7 +BF06: 27 04 BEQ loc_BF0C ; cycles=3/7 nt/t +BF08: 1D F9 C6 0C ADD:Q.W #-1, @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=9 + +loc_BF0C: +BF0C: 15 F6 F6 F7 BTST.B #7, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=7 +BF10: 27 10 BEQ loc_BF22 ; cycles=3/7 nt/t +BF12: 1D F6 F4 16 TST.W @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=7 +BF16: 26 06 BNE loc_BF1E ; cycles=3/7 nt/t +BF18: 15 F6 F6 C5 BSET.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +BF1C: 20 04 BRA loc_BF22 ; cycles=7 + +loc_BF1E: +BF1E: 1D F6 F4 0C ADD:Q.W #-1, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_BF22: +BF22: 0A RTE ; cycles=13 + +vec_frt2_ocia_BF23: +BF23: 15 FE A1 D5 BCLR.B #5, @FRT2_TCSR ; clear OCFA (bit 5) of FRT2_TCSR; cycles=8 +BF27: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=6 +BF2B: 27 04 BEQ loc_BF31 ; cycles=3/8 nt/t +BF2D: 15 F9 C4 0C ADD:Q.B #-1, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=8 + +loc_BF31: +BF31: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +BF35: 27 04 BEQ loc_BF3B ; cycles=3/8 nt/t +BF37: 15 F9 C5 0C ADD:Q.B #-1, @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=8 + +loc_BF3B: +BF3B: 15 F7 24 16 TST.B @H'F724 ; refs ram_F724 in on_chip_ram; cycles=6 +BF3F: 27 06 BEQ loc_BF47 ; cycles=3/8 nt/t +BF41: 15 F7 24 0C ADD:Q.B #-1, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=8 +BF45: 20 09 BRA loc_BF50 ; cycles=8 + +loc_BF47: +BF47: 15 F7 24 06 03 MOV:G.B #H'03, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=9 +BF4C: 15 F7 23 15 NOT.B @H'F723 ; refs ram_F723 in on_chip_ram; cycles=9 + +loc_BF50: +BF50: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +BF54: 27 17 BEQ loc_BF6D ; cycles=3/7 nt/t +BF56: 15 FB 02 16 TST.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=7 +BF5A: 27 06 BEQ loc_BF62 ; cycles=3/7 nt/t +BF5C: 15 FB 02 0C ADD:Q.B #-1, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +BF60: 20 0B BRA loc_BF6D ; cycles=7 + +loc_BF62: +BF62: 15 FB 03 D7 BCLR.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +BF66: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +BF68: 1E 89 84 BSR loc_48EF ; cycles=13 +BF6B: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 + +loc_BF6D: +BF6D: 15 F7 6C 16 TST.B @H'F76C ; refs ram_F76C in on_chip_ram; cycles=6 +BF71: 27 04 BEQ loc_BF77 ; cycles=3/8 nt/t +BF73: 15 F7 6C 0C ADD:Q.B #-1, @H'F76C ; refs ram_F76C in on_chip_ram; cycles=8 + +loc_BF77: +BF77: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BF7B: 27 04 BEQ loc_BF81 ; cycles=3/8 nt/t +BF7D: 15 F8 40 0C ADD:Q.B #-1, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=8 + +loc_BF81: +BF81: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=6 +BF85: 27 1C BEQ loc_BFA3 ; cycles=3/8 nt/t +BF87: 15 F7 26 0C ADD:Q.B #-1, @H'F726 ; refs ram_F726 in on_chip_ram; cycles=8 +BF8B: 26 16 BNE loc_BFA3 ; cycles=3/8 nt/t +BF8D: 15 F7 13 D6 BCLR.B #6, @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +BF91: 26 10 BNE loc_BFA3 ; cycles=3/8 nt/t +BF93: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF97: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9B: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9F: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 + +loc_BFA3: +BFA3: 15 F7 97 16 TST.B @H'F797 ; refs ram_F797 in on_chip_ram; cycles=6 +BFA7: 27 0A BEQ loc_BFB3 ; cycles=3/8 nt/t +BFA9: 15 F7 97 0C ADD:Q.B #-1, @H'F797 ; refs ram_F797 in on_chip_ram; cycles=8 +BFAD: 26 04 BNE loc_BFB3 ; cycles=3/8 nt/t +BFAF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFB3: +BFB3: 15 F7 98 16 TST.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=6 +BFB7: 27 0A BEQ loc_BFC3 ; cycles=3/8 nt/t +BFB9: 15 F7 98 0C ADD:Q.B #-1, @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +BFBD: 26 04 BNE loc_BFC3 ; cycles=3/8 nt/t +BFBF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFC3: +BFC3: 0A RTE ; cycles=14 + +vec_interval_timer_BFC4: +BFC4: 15 FE EC F7 BTST.B #7, @WDT_TCSR_R ; refs WDT_TCSR_R in register_field; cycles=7 +BFC8: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 +BFCE: 15 F7 94 08 ADD:Q.B #1, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=9 +BFD2: 15 F7 94 04 0A CMP:G.B #H'0A, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=7 +BFD7: 26 06 BNE loc_BFDF ; cycles=3/8 nt/t +BFD9: 1D FE EC 07 A5 7F MOV:G.W #H'A57F, @WDT_TCSR_R ; WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096); cycles=9 + +loc_BFDF: +BFDF: 0A RTE ; cycles=14 + +loc_BFE0: +BFE0: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 + +loc_BFE5: +BFE5: AD 82 MOV:G.W R5, R2 ; cycles=3 +BFE7: 0E 27 BSR loc_C010 ; cycles=14 +BFE9: 0E 4E BSR loc_C039 ; cycles=14 +BFEB: AA 75 CMP:G.W R2, R5 ; cycles=3 +BFED: 27 0E BEQ loc_BFFD ; cycles=3/8 nt/t +BFEF: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BFF3: 27 04 BEQ loc_BFF9 ; cycles=3/8 nt/t +BFF5: AA 85 MOV:G.W R2, R5 ; cycles=3 +BFF7: 20 EC BRA loc_BFE5 ; cycles=8 + +loc_BFF9: +BFF9: 15 F8 41 C7 BSET.B #7, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_BFFD: +BFFD: 19 RTS ; cycles=13 + +loc_BFFE: +BFFE: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 +C003: 0E 34 BSR loc_C039 ; cycles=14 +C005: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C009: 26 04 BNE loc_C00F ; cycles=3/8 nt/t +C00B: 15 F8 41 C6 BSET.B #6, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_C00F: +C00F: 19 RTS ; cycles=13 + +loc_C010: +C010: 0E 58 BSR loc_C06A ; cycles=13 + +loc_C012: +C012: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=7 +C016: 27 20 BEQ loc_C038 ; cycles=3/7 nt/t +C018: 1E 01 06 BSR loc_C121 ; cycles=13 +C01B: A3 80 MOV:G.B R3, R0 ; cycles=2 +C01D: 0E 6C BSR loc_C08B ; cycles=14 +C01F: 27 F1 BEQ loc_C012 ; cycles=3/8 nt/t +C021: A4 80 MOV:G.B R4, R0 ; cycles=2 +C023: 0E 66 BSR loc_C08B ; cycles=14 +C025: 27 EB BEQ loc_C012 ; cycles=3/8 nt/t +C027: AD 80 MOV:G.W R5, R0 ; cycles=3 +C029: A0 10 SWAP.B R0 ; cycles=3 +C02B: 0E 5E BSR loc_C08B ; cycles=14 +C02D: 27 E3 BEQ loc_C012 ; cycles=3/8 nt/t +C02F: A5 80 MOV:G.B R5, R0 ; cycles=2 +C031: 0E 58 BSR loc_C08B ; cycles=14 +C033: 27 DD BEQ loc_C012 ; cycles=3/8 nt/t +C035: 1E 01 0A BSR loc_C142 ; cycles=14 + +loc_C038: +C038: 19 RTS ; cycles=12 + +loc_C039: +C039: 0E 2F BSR loc_C06A ; cycles=14 + +loc_C03B: +C03B: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C03F: 27 28 BEQ loc_C069 ; cycles=3/8 nt/t +C041: 1E 00 DD BSR loc_C121 ; cycles=14 +C044: A3 80 MOV:G.B R3, R0 ; cycles=2 +C046: 0E 43 BSR loc_C08B ; cycles=13 +C048: 27 F1 BEQ loc_C03B ; cycles=3/7 nt/t +C04A: A4 80 MOV:G.B R4, R0 ; cycles=2 +C04C: 0E 3D BSR loc_C08B ; cycles=13 +C04E: 27 EB BEQ loc_C03B ; cycles=3/7 nt/t +C050: 1E 00 CE BSR loc_C121 ; cycles=13 +C053: A3 80 MOV:G.B R3, R0 ; cycles=2 +C055: A0 C0 BSET.B #0, R0 ; cycles=2 +C057: 0E 32 BSR loc_C08B ; cycles=14 +C059: 27 E0 BEQ loc_C03B ; cycles=3/8 nt/t +C05B: 1E 00 7D BSR loc_C0DB ; cycles=14 +C05E: A5 10 SWAP.B R5 ; cycles=3 +C060: 1E 00 A9 BSR loc_C10C ; cycles=13 +C063: 1E 00 75 BSR loc_C0DB ; cycles=14 +C066: 1E 00 D9 BSR loc_C142 ; cycles=13 + +loc_C069: +C069: 19 RTS ; cycles=13 + +loc_C06A: +C06A: 0C 0F FF 54 AND.W #H'0FFF, R4 ; cycles=4 +C06E: 4C 08 00 CMP:I #H'0800, R4 ; cycles=3 +C071: 24 0B BCC loc_C07E ; cycles=3/8 nt/t +C073: AC 83 MOV:G.W R4, R3 ; cycles=3 +C075: A3 10 SWAP.B R3 ; cycles=3 +C077: A3 1A SHLL.B R3 ; cycles=2 +C079: 04 A0 43 OR.B #H'A0, R3 ; cycles=3 +C07C: 20 0C BRA loc_C08A ; cycles=7 + +loc_C07E: +C07E: AC 83 MOV:G.W R4, R3 ; cycles=3 +C080: A3 10 SWAP.B R3 ; cycles=3 +C082: A3 1A SHLL.B R3 ; cycles=2 +C084: 04 0E 53 AND.B #H'0E, R3 ; cycles=3 +C087: 04 E0 43 OR.B #H'E0, R3 ; cycles=3 + +loc_C08A: +C08A: 19 RTS ; cycles=12 + +loc_C08B: +C08B: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C08E: +C08E: A0 1A SHLL.B R0 ; cycles=2 +C090: 24 06 BCC loc_C098 ; cycles=3/7 nt/t +C092: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C096: 20 04 BRA loc_C09C ; cycles=7 + +loc_C098: +C098: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 + +loc_C09C: +C09C: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A0: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A8: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0AC: 01 B9 DF SCB/F R1, loc_C08E ; cycles=3/4/8 false/-1/t +C0AF: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0B4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0B8: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0BC: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=7 +C0C0: 27 0D BEQ loc_C0CF ; cycles=3/7 nt/t +C0C2: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0C6: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0CB: 50 00 MOV:E.B #H'00, R0 ; dataflow R0=H'00; cycles=2 +C0CD: 20 0B BRA loc_C0DA ; cycles=8 + +loc_C0CF: +C0CF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0D3: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0D8: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_C0DA: +C0DA: 19 RTS ; cycles=12 + +loc_C0DB: +C0DB: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0E0: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C0E3: +C0E3: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0E7: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0EB: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=6 +C0EF: 27 04 BEQ loc_C0F5 ; cycles=3/8 nt/t +C0F1: A5 49 BSET.B R1, R5 ; cycles=2 +C0F3: 20 02 BRA loc_C0F7 ; cycles=8 + +loc_C0F5: +C0F5: A5 59 BCLR.B R1, R5 ; cycles=2 + +loc_C0F7: +C0F7: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FB: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C103: 01 B9 DD SCB/F R1, loc_C0E3 ; cycles=3/4/9 false/-1/t +C106: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C10B: 19 RTS ; cycles=13 + +loc_C10C: +C10C: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C110: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C114: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C118: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C11C: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C120: 19 RTS ; cycles=12 + +loc_C121: +C121: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=8 +C125: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C129: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C12D: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C131: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=8 +C135: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C139: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C13D: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C141: 19 RTS ; cycles=13 + +loc_C142: +C142: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C146: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14E: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C152: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C156: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15E: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C162: 19 RTS ; cycles=12 diff --git a/build/rom_others_menu_gate.json b/build/rom_others_menu_gate.json new file mode 100644 index 0000000..69e04b1 --- /dev/null +++ b/build/rom_others_menu_gate.json @@ -0,0 +1,221410 @@ +{ + "vectors": [ + { + "address": 0, + "name": "reset", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 4, + "name": "invalid_instruction", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 6, + "name": "zero_divide", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 8, + "name": "trap_vs", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 16, + "name": "address_error", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 18, + "name": "trace", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 22, + "name": "nmi", + "target": 17299, + "target_label": "vec_nmi_4393" + }, + { + "address": 32, + "name": "trapa_0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 34, + "name": "trapa_1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 36, + "name": "trapa_2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 38, + "name": "trapa_3", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 40, + "name": "trapa_4", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 42, + "name": "trapa_5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 44, + "name": "trapa_6", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 46, + "name": "trapa_7", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 48, + "name": "trapa_8", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 50, + "name": "trapa_9", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 52, + "name": "trapa_a", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 54, + "name": "trapa_b", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 56, + "name": "trapa_c", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 58, + "name": "trapa_d", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 60, + "name": "trapa_e", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 62, + "name": "trapa_f", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 64, + "name": "irq0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 66, + "name": "interval_timer", + "target": 49092, + "target_label": "vec_interval_timer_BFC4" + }, + { + "address": 72, + "name": "irq1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 80, + "name": "irq2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 82, + "name": "irq3", + "target": 15408, + "target_label": "vec_irq3_3C30" + }, + { + "address": 88, + "name": "irq4", + "target": 15047, + "target_label": "vec_irq4_3AC7" + }, + { + "address": 90, + "name": "irq5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 98, + "name": "frt1_ocia", + "target": 48874, + "target_label": "vec_frt1_ocia_BEEA" + }, + { + "address": 106, + "name": "frt2_ocia", + "target": 48931, + "target_label": "vec_frt2_ocia_BF23" + }, + { + "address": 128, + "name": "sci1_eri", + "target": 47959, + "target_label": "vec_sci1_eri_BB57" + }, + { + "address": 130, + "name": "sci1_rxi", + "target": 47975, + "target_label": "vec_sci1_rxi_BB67" + }, + { + "address": 132, + "name": "sci1_txi", + "target": 47748, + "target_label": "vec_sci1_txi_BA84" + }, + { + "address": 144, + "name": "ad_adi", + "target": 15769, + "target_label": "vec_ad_adi_3D99" + } + ], + "dtc_vectors": [], + "memory_regions": [ + { + "name": "exception_vectors", + "start": 0, + "end": 159, + "kind": "vectors", + "manual": "section 2 address space" + }, + { + "name": "dtc_vectors", + "start": 160, + "end": 255, + "kind": "dtc_vectors", + "manual": "section 2 address space" + }, + { + "name": "program_or_external", + "start": 256, + "end": 63103, + "kind": "program", + "manual": "section 2/17 mode-dependent ROM or external space" + }, + { + "name": "on_chip_ram", + "start": 63104, + "end": 65151, + "kind": "ram", + "manual": "section 16 RAM" + }, + { + "name": "register_field", + "start": 65152, + "end": 65535, + "kind": "registers", + "manual": "appendix B register map" + } + ], + "data_candidates": { + "strings": [ + { + "address": 10834, + "length": 11, + "text": "78785=5=5=,", + "terminated": false + }, + { + "address": 11194, + "length": 7, + "text": "8*8B8Z8", + "terminated": false + }, + { + "address": 16818, + "length": 32, + "text": "01020304050607080910111213141516", + "terminated": false + }, + { + "address": 22436, + "length": 7, + "text": "Z [ ", + "terminated": false + }, + { + "address": 22570, + "length": 6, + "text": "Z [ ", + "terminated": false + }, + { + "address": 23381, + "length": 10, + "text": "0123456789", + "terminated": true + }, + { + "address": 23392, + "length": 40, + "text": " 0 1 2 3 4 5 6 7 8 910111213141516171819", + "terminated": false + }, + { + "address": 24822, + "length": 16, + "text": "0123456789ABCDEF", + "terminated": false + }, + { + "address": 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"Manual/0900766b802125d0.md:16410 SCI clock source selection tables" + ], + "channels": { + "SCI1": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ], + "configurations": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "SCI2": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "configurations": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + } + } + }, + "sci_protocol": { + "manual_references": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "channels": { + "SCI1": { + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "SCI2": { + "events": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ] + } + }, + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "serial_reconstruction": { + "kind": "serial_reconstruction", + "candidates": [ + { + "id": "sci1_tx_frame_f858_len6_candidate", + "kind": "candidate_sci1_tx_frame", + "channel": "SCI1", + "frame_length": 6, + "buffer_start": 63576, + "buffer_start_hex": "H'F858", + "buffer_end": 63581, + "buffer_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "tx_index_address": 63938, + "tx_index_address_hex": "H'F9C2", + "tdr_address": 65243, + "tdr_address_hex": "H'FEDB", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "roles": [ + { + "name": "tx_frame", + "address": 63576, + "address_hex": "H'F858", + "end_address": 63581, + "end_address_hex": "H'F85D", + "summary": "evidence-supported candidate SCI1 TX frame buffer" + }, + { + "name": "tx_checksum", + "address": 63581, + "address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "summary": "evidence-supported candidate SCI1 TX XOR checksum byte" + }, + { + "name": "tx_index", + "address": 63938, + "address_hex": "H'F9C2", + "summary": "evidence-supported candidate SCI1 TX frame index" + } + ], + "tx_path": { + "kind": "interrupt_driven_txi", + "initial_tdr_write_address": 47730, + "initial_tdr_write_address_hex": "H'BA72", + "txi_indexed_tdr_write_address": 47797, + "txi_indexed_tdr_write_address_hex": "H'BAB5", + "summary": "initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted", + "tdre_caveat": "TDRE reassertion is hardware/emulator timing context; static evidence is the indexed TXI send path." + }, + "confidence": "high", + "confidence_score": 0.95, + "confidence_reason": "all required independent evidence groups were observed", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "missing_evidence": [], + "evidence_addresses": { + "tx_buffer_region": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "tx_checksum_seed": [ + 47694 + ], + "checksum_byte": [ + 47716 + ], + "xor_checksum_chain": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "initial_send_from_buffer_start": [ + 47726, + 47730 + ], + "tx_index_initialized_to_one": [ + 47734 + ], + "tx_isr_indexed_send": [ + 47787, + 47793, + 47797 + ], + "tx_index_increment": [ + 47807 + ], + "tx_index_compare_frame_length": [ + 47811 + ] + }, + "evidence_addresses_hex": { + "tx_buffer_region": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "tx_checksum_seed": [ + "H'BA4E" + ], + "checksum_byte": [ + "H'BA64" + ], + "xor_checksum_chain": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "initial_send_from_buffer_start": [ + "H'BA6E", + "H'BA72" + ], + "tx_index_initialized_to_one": [ + "H'BA76" + ], + "tx_isr_indexed_send": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "tx_index_increment": [ + "H'BABF" + ], + "tx_index_compare_frame_length": [ + "H'BAC3" + ] + }, + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + } + ], + "short_comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis using buffer H'F858-H'F85D with checksum byte H'F85D seeded by H'005A" + }, + { + "id": "sci1_rx_frame_f868_len6_candidate", + "kind": "candidate_sci1_rx_frame", + "channel": "SCI1", + "frame_length": 6, + "capture_buffer_start": 63592, + "capture_buffer_start_hex": "H'F868", + "capture_buffer_end": 63597, + "capture_buffer_end_hex": "H'F86D", + "validation_buffer_start": 63584, + "validation_buffer_start_hex": "H'F860", + "validation_buffer_end": 63589, + "validation_buffer_end_hex": "H'F865", + "checksum_address": 63589, + "checksum_address_hex": "H'F865", + "rx_index_address": 63939, + "rx_index_address_hex": "H'F9C3", + "rdr_address": 65245, + "rdr_address_hex": "H'FEDD", + "interbyte_timeout_address": 63937, + "interbyte_timeout_address_hex": "H'F9C1", + "complete_timer_address": 63941, + "complete_timer_address_hex": "H'F9C5", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "confidence": "high", + "confidence_score": 0.9, + "confidence_reason": "RX count, copy, and checksum-validation evidence were observed; no explicit header/sync byte was identified", + "caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "optional_evidence_count": 2, + "missing_evidence": [], + "evidence_addresses": { + "rx_rdr_read": [ + 47981 + ], + "rx_indexed_store": [ + 48016 + ], + "rx_index_increment_store": [ + 48020, + 48022 + ], + "rx_isr_compare_frame_length": [ + 48026 + ], + "rx_complete_timer": [ + 48030 + ], + "rx_processor_requires_six_bytes": [ + 48043 + ], + "rx_copy_capture_to_frame_buffer": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "rx_checksum_seed": [ + 48086 + ], + "rx_xor_checksum_validation": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "rx_rdrf_clear_before_rdr_read": [ + 47977, + 47981 + ], + "rx_eri_falls_through_to_rxi": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ] + }, + "evidence_addresses_hex": { + "rx_rdr_read": [ + "H'BB6D" + ], + "rx_indexed_store": [ + "H'BB90" + ], + "rx_index_increment_store": [ + "H'BB94", + "H'BB96" + ], + "rx_isr_compare_frame_length": [ + "H'BB9A" + ], + "rx_complete_timer": [ + "H'BB9E" + ], + "rx_processor_requires_six_bytes": [ + "H'BBAB" + ], + "rx_copy_capture_to_frame_buffer": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "rx_checksum_seed": [ + "H'BBD6" + ], + "rx_xor_checksum_validation": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "rx_rdrf_clear_before_rdr_read": [ + "H'BB69", + "H'BB6D" + ], + "rx_eri_falls_through_to_rxi": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ] + }, + "evidence": [ + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + } + ], + "rx_error_handling": { + "kind": "sci1_rx_error_handling_candidate", + "error_latch_address": 64164, + "error_latch_address_hex": "H'FAA4", + "error_latch_bit": 7, + "fallthrough_to_rx_byte_path": true, + "rdrf_clear_before_rdr_read": true, + "summary": "SCI1 ERI appears to mark a physical receive error and continue into the RXI byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order.", + "manual_caveat": "Manual text distinguishes ORER from FER/PER data transfer into RDR and describes the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order.", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "candidate-medium" + }, + "short_comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A" + } + ], + "ram_roles": [ + { + "kind": "candidate_ram_role", + "name": "post_tx_report_delay", + "address": 63936, + "address_hex": "H'F9C0", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "post_tx_report_delay_tick_decrement": [ + 48878, + 48884 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "post_tx_report_delay_tick_decrement": [ + "H'BEEE", + "H'BEF4" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "secondary_tx_report_delay", + "address": 63937, + "address_hex": "H'F9C1", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "secondary_tx_report_delay_tick_decrement": [ + 48888, + 48894 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "secondary_tx_report_delay_tick_decrement": [ + "H'BEF8", + "H'BEFE" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "periodic_report_countdown", + "address": 63942, + "address_hex": "H'F9C6", + "width_bits": 16, + "confidence": "candidate/evidence-supported", + "summary": "periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "periodic_report_countdown_tick_decrement": [ + 48898, + 48904 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "periodic_report_countdown_tick_decrement": [ + "H'BF02", + "H'BF08" + ] + } + } + ], + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + }, + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "required_evidence": { + "tx": [ + "tx_buffer_region", + "tx_checksum_seed", + "checksum_byte", + "xor_checksum_chain", + "initial_send_from_buffer_start", + "tx_index_initialized_to_one", + "tx_isr_indexed_send", + "tx_index_increment", + "tx_index_compare_frame_length" + ], + "rx": [ + "rx_rdr_read", + "rx_indexed_store", + "rx_index_increment_store", + "rx_isr_compare_frame_length", + "rx_complete_timer", + "rx_processor_requires_six_bytes", + "rx_copy_capture_to_frame_buffer", + "rx_checksum_seed", + "rx_xor_checksum_validation" + ] + } + }, + "board_profile": { + "board": "sony_rcp_tx7", + "name": "Sony RCP-TX7", + "summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.", + "manual_references": [ + "Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD", + "Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD", + "Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals", + "Manual/0900766b802125d0.md:11201 P96 is RXD1 input", + "Manual/0900766b802125d0.md:11202 P95 is TXD1 output", + "Manual/0900766b802125d0.md:15725 SCI1 RXD input pin", + "Manual/0900766b802125d0.md:15726 SCI1 TXD output pin", + "Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15794 RDR receive data register", + "Manual/0900766b802125d0.md:15823 TDR transmit data register", + "Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions", + "Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output", + "Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input", + "Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags", + "Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions", + "Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94" + ], + "traces": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "channels": { + "SCI1": { + "traced_to_max202": true, + "path": "RS232/MAX202", + "pins": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + }, + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ] + }, + "SCI2": { + "traced_to_max202": false, + "path": null, + "note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.", + "p9sci2e": false, + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ] + } + }, + "instructions": { + "4148": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "4245": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4250": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "4255": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4260": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4265": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4270": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "17258": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "17274": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "17278": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "47720": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47730": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47739": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47743": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47774": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47797": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47803": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47818": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47963": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47967": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47971": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47977": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47981": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + }, + "state": { + "SYSCR2": { + "value": 180, + "value_hex": "H'B4" + }, + "P9SCI2E": false + } + }, + "peripheral_access": { + "manual_references": [ + "Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access", + "Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte", + "Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP", + "Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP", + "Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte" + ], + "warnings": [] + }, + "indirect_flow": { + "sites": [ + { + "address": 7192, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "unknown", + "summary": "JSR @R0 uses R0; target not resolved" + }, + { + "address": 10403, + "instruction": "JMP @R1", + "kind": "jump", + "target_register": "R1", + "confidence": "table_load", + "table": { + "base": 10406, + "index_register": "R4", + "target_register": "R1", + "load_address": 10399, + "load_instruction": "MOV:G.W @(H'28A6,R4), R1", + "entry_size": 2, + "entry_count": 128, + "decoded_target_count": 103, + "entries": [ + { + "index": 0, + "entry_address": 10406, + "target": 11449, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 10408, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 2, + "entry_address": 10410, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 3, + "entry_address": 10412, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 4, + "entry_address": 10414, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 5, + "entry_address": 10416, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 6, + "entry_address": 10418, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 7, + "entry_address": 10420, + "target": 11715, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 10422, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 9, + "entry_address": 10424, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 10, + "entry_address": 10426, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 11, + "entry_address": 10428, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 12, + "entry_address": 10430, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 13, + "entry_address": 10432, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 14, + "entry_address": 10434, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 15, + "entry_address": 10436, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 16, + "entry_address": 10438, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 17, + "entry_address": 10440, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 18, + "entry_address": 10442, + "target": 11779, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 10444, + "target": 11782, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 10446, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 21, + "entry_address": 10448, + "target": 11833, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 10450, + "target": 11866, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 10452, + "target": 11909, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 10454, + "target": 11887, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 10456, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 10458, + "target": 11972, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 10460, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 28, + "entry_address": 10462, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 29, + "entry_address": 10464, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 30, + "entry_address": 10466, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 31, + "entry_address": 10468, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 32, + "entry_address": 10470, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 33, + "entry_address": 10472, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 34, + "entry_address": 10474, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 35, + "entry_address": 10476, + "target": 12006, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 10478, + "target": 12044, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 10480, + "target": 12060, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 10482, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 39, + "entry_address": 10484, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 40, + "entry_address": 10486, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 41, + "entry_address": 10488, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 42, + "entry_address": 10490, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 43, + "entry_address": 10492, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 44, + "entry_address": 10494, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 45, + "entry_address": 10496, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 46, + "entry_address": 10498, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 47, + "entry_address": 10500, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 48, + "entry_address": 10502, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 49, + "entry_address": 10504, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 50, + "entry_address": 10506, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 51, + "entry_address": 10508, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 52, + "entry_address": 10510, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 53, + "entry_address": 10512, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 54, + "entry_address": 10514, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 55, + "entry_address": 10516, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 56, + "entry_address": 10518, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 57, + "entry_address": 10520, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 58, + "entry_address": 10522, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 59, + "entry_address": 10524, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 60, + "entry_address": 10526, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 61, + "entry_address": 10528, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 62, + "entry_address": 10530, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 63, + "entry_address": 10532, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 64, + "entry_address": 10534, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 65, + "entry_address": 10536, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 66, + "entry_address": 10538, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 67, + "entry_address": 10540, + "target": 12106, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 68, + "entry_address": 10542, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 69, + "entry_address": 10544, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 70, + "entry_address": 10546, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 71, + "entry_address": 10548, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 72, + "entry_address": 10550, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 73, + "entry_address": 10552, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 74, + "entry_address": 10554, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 75, + "entry_address": 10556, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 76, + "entry_address": 10558, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 77, + "entry_address": 10560, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 78, + "entry_address": 10562, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 79, + "entry_address": 10564, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 80, + "entry_address": 10566, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 81, + "entry_address": 10568, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 82, + "entry_address": 10570, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 83, + "entry_address": 10572, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 84, + "entry_address": 10574, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 85, + "entry_address": 10576, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 86, + "entry_address": 10578, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 87, + "entry_address": 10580, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 88, + "entry_address": 10582, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 89, + "entry_address": 10584, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 90, + "entry_address": 10586, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 91, + "entry_address": 10588, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 92, + "entry_address": 10590, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 93, + "entry_address": 10592, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 94, + "entry_address": 10594, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 95, + "entry_address": 10596, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 96, + "entry_address": 10598, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 97, + "entry_address": 10600, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 98, + "entry_address": 10602, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 99, + "entry_address": 10604, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 100, + "entry_address": 10606, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 101, + "entry_address": 10608, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 102, + "entry_address": 10610, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 103, + "entry_address": 10612, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 104, + "entry_address": 10614, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 105, + "entry_address": 10616, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 106, + "entry_address": 10618, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 107, + "entry_address": 10620, + "target": 12146, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 108, + "entry_address": 10622, + "target": 12207, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 109, + "entry_address": 10624, + "target": 12309, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 110, + "entry_address": 10626, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 1, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 3, + "entry_address": 18756, + "target": 25292, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 4, + "entry_address": 18758, + "target": 25268, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 5, + "entry_address": 18760, + "target": 25248, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 6, + "entry_address": 18762, + "target": 25224, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 7, + "entry_address": 18764, + "target": 25205, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 18766, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 9, + "entry_address": 18768, + "target": 33086, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 10, + "entry_address": 18770, + "target": 33062, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 11, + "entry_address": 18772, + "target": 33042, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 12, + "entry_address": 18774, + "target": 33022, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (1/52 decoded targets)" + }, + { + "address": 37654, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + } + ] + }, + "dataflow": { + "blocks": [ + { + "start": 4096, + "instructions": [ + 4096, + 4099, + 4103, + 4108, + 4113, + 4118, + 4123, + 4128, + 4133, + 4138, + 4143, + 4148, + 4153, + 4158, + 4163, + 4168, + 4174, + 4179, + 4184, + 4189, + 4195, + 4200, + 4205, + 4210, + 4215, + 4220, + 4225, + 4230, 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"address": 61708, + "instruction_address": 15083, + "instruction": "MOV:G.W @H'F10C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F10C", + "operand_index": 0 + }, + { + "address": 61708, + "instruction_address": 15217, + "instruction": "MOV:G.W @H'F10C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F10C", + "operand_index": 0 + } + ] + }, + { + "address": 61709, + "name": "mem_F10D", + "region": "program_or_external", + "kind": "memory", + "access_count": 1, + "read_count": 0, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14860, + "last_access": 14860, + "accesses": [ + { + "address": 61709, + "instruction_address": 14860, + "instruction": "MOV:G.B R0, @H'F10D", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F10D", + "operand_index": 1 + } + ] + }, + { + "address": 61710, + "name": "mem_F10E", + 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"address": 63112, + "instruction_address": 14683, + "instruction": "BCLR.B R0, @H'F688", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F688", + "operand_index": 1 + } + ] + }, + { + "address": 63113, + "name": "ram_F689", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5603, + "last_access": 15876, + "accesses": [ + { + "address": 63113, + "instruction_address": 5603, + "instruction": "BCLR.B #7, @H'F689", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F689", + "operand_index": 1 + }, + { + "address": 63113, + "instruction_address": 15876, + "instruction": "BSET.B #7, @H'F689", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F689", + "operand_index": 1 + } + ] + }, + { + "address": 63114, + "name": "ram_F68A", + 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"address": 63195, + "instruction_address": 15672, + "instruction": "CMP:G.B @H'F6DB, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DB", + "operand_index": 0 + }, + { + "address": 63195, + "instruction_address": 15682, + "instruction": "MOV:G.B R0, @H'F6DB", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6DB", + "operand_index": 1 + } + ] + }, + { + "address": 63196, + "name": "ram_F6DC", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7138, + "last_access": 15700, + "accesses": [ + { + "address": 63196, + "instruction_address": 7138, + "instruction": "MOV:G.B @H'F6DC, R4", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6DC", + "operand_index": 0 + }, + { + "address": 63196, + "instruction_address": 7151, + "instruction": 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@H'F6F0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 0 + }, + { + "address": 63216, + "instruction_address": 15209, + "instruction": "MOV:G.B R0, @H'F6F0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15227, + "instruction": "BSET.B #7, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15245, + "instruction": "BSET.B #6, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + } + ] + }, + { + "address": 63217, + "name": "ram_F6F1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 21, + "read_count": 19, + "write_count": 18, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + 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"instruction": "BCLR.B #4, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5735, + "instruction": "BCLR.B #3, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5744, + "instruction": "BCLR.B #2, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5753, + "instruction": "BCLR.B #1, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5762, + "instruction": "BCLR.B #0, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + 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"BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15508, + "instruction": "BSET.B #2, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15526, + "instruction": "BSET.B #1, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15544, + "instruction": "BSET.B #0, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15563, + "instruction": "MOV:G.B @H'F6F1, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 0 + }, + { + "address": 63217, + "instruction_address": 15570, + "instruction": "MOV:G.B R0, @H'F6F1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15588, + "instruction": "BSET.B #7, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15606, + "instruction": "BSET.B #6, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + } + ] + }, + { + "address": 63218, + "name": "ram_F6F2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 18, + "read_count": 17, + "write_count": 17, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5766, + "last_access": 15389, + "accesses": [ + { + "address": 63218, + "instruction_address": 5766, + "instruction": "TST.B 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"address": 63218, + "instruction_address": 5808, + "instruction": "BCLR.B #3, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5817, + "instruction": "BCLR.B #2, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5826, + "instruction": "BCLR.B #1, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 5835, + "instruction": "BCLR.B #0, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15213, + "instruction": "CLR.B @H'F6F2", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 0 + }, + { + "address": 63218, + "instruction_address": 15263, + "instruction": "BSET.B #0, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15281, + "instruction": "BSET.B #1, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15299, + "instruction": "BSET.B #2, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15317, + "instruction": "BSET.B #3, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15335, + "instruction": "BSET.B #4, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15353, + "instruction": "BSET.B #5, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15371, + "instruction": "BSET.B #6, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15389, + "instruction": "BSET.B #7, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + } + ] + }, + { + "address": 63219, + "name": "ram_F6F3", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 18, + "read_count": 17, + "write_count": 17, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5844, + "last_access": 15750, + "accesses": [ + { + "address": 63219, + "instruction_address": 5844, + "instruction": "TST.B @H'F6F3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 0 + }, + { + "address": 63219, + "instruction_address": 5850, + "instruction": "BCLR.B #7, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5854, + "instruction": "BCLR.B #6, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5858, + "instruction": "BCLR.B #5, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5862, + "instruction": "BCLR.B #4, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5871, + "instruction": "BCLR.B #3, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5880, + "instruction": "BCLR.B #2, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5884, + "instruction": "BCLR.B #1, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F3", + "operand_index": 1 + }, + { + "address": 63219, + "instruction_address": 5888, + "instruction": "BCLR.B #0, @H'F6F3", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": 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] + }, + { + "address": 63220, + "name": "ram_F6F4", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 2, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 9905, + "last_access": 48926, + "accesses": [ + { + "address": 63220, + "instruction_address": 9905, + "instruction": "MOV:G.W #H'07D0, @H'F6F4", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F6F4", + "operand_index": 1 + }, + { + "address": 63220, + "instruction_address": 9913, + "instruction": "MOV:G.W #H'00C8, @H'F6F4", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F6F4", + "operand_index": 1 + }, + { + "address": 63220, + "instruction_address": 48914, + "instruction": "TST.W @H'F6F4", + "mnemonic": "TST.W", + "direction": "read", + "width": "word", + "operand": "@H'F6F4", + "operand_index": 0 + }, + { + "address": 63220, + "instruction_address": 48926, + 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"address": 63255, + "name": "ram_F717", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 4, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 6189, + "last_access": 16999, + "accesses": [ + { + "address": 63255, + "instruction_address": 6189, + "instruction": "BTST.B #2, @H'F717", + "mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F717", + "operand_index": 1 + }, + { + "address": 63255, + "instruction_address": 6289, + "instruction": "BTST.B #2, @H'F717", + "mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F717", + "operand_index": 1 + }, + { + "address": 63255, + "instruction_address": 6375, + "instruction": "BTST.B #2, @H'F717", + "mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F717", + "operand_index": 1 + }, + { + "address": 63255, + "instruction_address": 14921, + "instruction": "AND.B @H'F717, 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"width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 23298, + "last_access": 24605, + "accesses": [ + { + "address": 63278, + "instruction_address": 23298, + "instruction": "MOV:G.B @H'F72E, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + }, + { + "address": 63278, + "instruction_address": 24544, + "instruction": "CLR.B @H'F72E", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + }, + { + "address": 63278, + "instruction_address": 24598, + "instruction": "ADD:Q.B #1, @H'F72E", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 1 + }, + { + "address": 63278, + "instruction_address": 24605, + "instruction": "MOV:G.B @H'F72E, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + } + ] + }, + { + "address": 63279, + "name": "ram_F72F", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 24534, + "last_access": 24649, + "accesses": [ + { + "address": 63279, + "instruction_address": 24534, + "instruction": "CMP:G.B @H'F72F, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72F", + "operand_index": 0 + }, + { + "address": 63279, + "instruction_address": 24548, + "instruction": "MOV:G.B R0, @H'F72F", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F72F", + "operand_index": 1 + }, + { + "address": 63279, + "instruction_address": 24649, + "instruction": "CLR.B @H'F72F", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F72F", + "operand_index": 0 + } + ] + }, + { + "address": 63280, + "name": "ram_F730", + "region": "on_chip_ram", + "kind": "ram", + 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"instruction_address": 49071, + "instruction": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 49087, + "instruction": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + } + ], + "xref_count": 1, + "xrefs": [ + { + "source": "pointer_table", + "address": 7856, + "target": 63281 + } + ] + }, + { + "address": 63282, + "name": "ram_F732", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 13, + "read_count": 8, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 5918, + "last_access": 24683, + "accesses": [ + { + "address": 63282, + "instruction_address": 5918, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 5926, + "instruction": "MOV:G.W #H'1C07, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 5990, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 5998, + "instruction": "MOV:G.W #H'1C06, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 8493, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 8501, + "instruction": "MOV:G.W #H'1C03, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 16416, + "instruction": "CLR.W @H'F732", + "mnemonic": "CLR.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 18675, + "instruction": "MOV:G.W R0, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 18688, + "instruction": "CMP:G.B #H'1A, @H'F732", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 18695, + "instruction": "CMP:G.W #H'1900, @H'F732", + "mnemonic": "CMP:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 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@H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 6860, + "instruction": "MOV:G.B R0, @H'F733", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 6870, + "instruction": "ADD:Q.B #1, @H'F733", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 6876, + "instruction": "ADD:Q.B #-1, @H'F733", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 23325, + "instruction": "MOV:G.B @H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 23356, + "instruction": "MOV:G.B @H'F733, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 24611, + "instruction": "CMP:G.B #H'FF, @H'F733", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 24618, + "instruction": "CMP:G.B @H'F733, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F733", + "operand_index": 0 + }, + { + "address": 63283, + "instruction_address": 24628, + "instruction": "MOV:G.B R0, @H'F733", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F733", + "operand_index": 1 + }, + { + "address": 63283, + "instruction_address": 24634, + "instruction": "CLR.B @H'F733", + "mnemonic": "CLR.B", + "direction": "write", + "width": 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"address": 63284, + "instruction_address": 8497, + "instruction": "MOV:G.W R1, @H'F734", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F734", + "operand_index": 1 + }, + { + "address": 63284, + "instruction_address": 18671, + "instruction": "MOV:G.W @H'F734, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F734", + "operand_index": 0 + } + ] + }, + { + "address": 63286, + "name": "ram_F736", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 10295, + "last_access": 28918, + "accesses": [ + { + "address": 63286, + "instruction_address": 10295, + "instruction": "MOV:G.W @H'F736, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F736", + "operand_index": 0 + }, + { + "address": 63286, + "instruction_address": 17315, + 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"address": 63552, + "instruction_address": 49120, + "instruction": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F840", + "operand_index": 1 + }, + { + "address": 63552, + "instruction_address": 49135, + "instruction": "TST.B @H'F840", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F840", + "operand_index": 0 + }, + { + "address": 63552, + "instruction_address": 49150, + "instruction": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F840", + "operand_index": 1 + }, + { + "address": 63552, + "instruction_address": 49157, + "instruction": "TST.B @H'F840", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F840", + "operand_index": 0 + }, + { + "address": 63552, + "instruction_address": 49170, + "instruction": "TST.B @H'F840", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F840", + "operand_index": 0 + }, + { + "address": 63552, + "instruction_address": 49211, + "instruction": "TST.B @H'F840", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F840", + "operand_index": 0 + } + ] + }, + { + "address": 63553, + "name": "ram_F841", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 49145, + "last_access": 49163, + "accesses": [ + { + "address": 63553, + "instruction_address": 49145, + "instruction": "BSET.B #7, @H'F841", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F841", + "operand_index": 1 + }, + { + "address": 63553, + "instruction_address": 49163, + "instruction": "BSET.B #6, @H'F841", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F841", + "operand_index": 1 + } + ] + }, + { + "address": 63568, + "name": "ram_F850", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 1, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47670, + "last_access": 48717, + "accesses": [ + { + "address": 63568, + "instruction_address": 47670, + "instruction": "MOV:G.W @H'F850, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F850", + "operand_index": 0 + }, + { + "address": 63568, + "instruction_address": 47900, + "instruction": "MOV:G.B R1, @H'F850", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F850", + "operand_index": 1 + }, + { + "address": 63568, + "instruction_address": 48304, + "instruction": "MOV:G.B #H'04, @H'F850", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F850", + "operand_index": 1 + }, + { + "address": 63568, + "instruction_address": 48343, + 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"name": "ram_F852", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 1, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47678, + "last_access": 48734, + "accesses": [ + { + "address": 63570, + "instruction_address": 47678, + "instruction": "MOV:G.W @H'F852, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F852", + "operand_index": 0 + }, + { + "address": 63570, + "instruction_address": 47904, + "instruction": "MOV:G.B R5, @H'F852", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F852", + "operand_index": 1 + }, + { + "address": 63570, + "instruction_address": 48321, + "instruction": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F852", + "operand_index": 1 + }, + { + "address": 63570, + "instruction_address": 48657, + "instruction": "MOV:G.W R0, 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"width": "byte", + "operand": "@H'F853", + "operand_index": 1 + } + ] + }, + { + "address": 63572, + "name": "ram_F854", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 1, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47686, + "last_access": 48742, + "accesses": [ + { + "address": 63572, + "instruction_address": 47686, + "instruction": "MOV:G.B @H'F854, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F854", + "operand_index": 0 + }, + { + "address": 63572, + "instruction_address": 47929, + "instruction": "MOV:G.B R4, @H'F854", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F854", + "operand_index": 1 + }, + { + "address": 63572, + "instruction_address": 48329, + "instruction": "MOV:G.B R0, @H'F854", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F854", + 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0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47700, + "last_access": 47700, + "accesses": [ + { + "address": 63577, + "instruction_address": 47700, + "instruction": "XOR.B @H'F859, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F859", + "operand_index": 0 + } + ] + }, + { + "address": 63578, + "name": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47682, + "last_access": 48653, + "accesses": [ + { + "address": 63578, + "instruction_address": 47682, + "instruction": "MOV:G.W R0, @H'F85A", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F85A", + "operand_index": 1 + }, + { + "address": 63578, + "instruction_address": 47704, + "instruction": "XOR.B @H'F85A, R0", + "mnemonic": "XOR.B", + "direction": "read", + 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63586, + "name": "ram_F862", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 5, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48063, + "last_access": 48730, + "accesses": [ + { + "address": 63586, + "instruction_address": 48063, + "instruction": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F862", + "operand_index": 1 + }, + { + "address": 63586, + "instruction_address": 48096, + "instruction": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48125, + "instruction": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48317, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48356, + "instruction": "MOV:G.B @H'F862, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48730, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + } + ] + }, + { + "address": 63587, + "name": "ram_F863", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 6, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48100, + "last_access": 48603, + "accesses": [ + { + "address": 63587, + "instruction_address": 48100, + "instruction": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48237, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48267, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48402, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48427, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48603, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + } + ] + }, + { + "address": 63588, + "name": "ram_F864", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 8, + "read_count": 6, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48071, + "last_access": 48738, + "accesses": [ + { + "address": 63588, + "instruction_address": 48071, + "instruction": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48104, + "instruction": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48253, + "instruction": "MOV:G.B #H'80, @H'F864", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48273, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48325, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48433, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48609, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48738, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + } + ] + }, + { + "address": 63589, + "name": "ram_F865", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48108, + "last_access": 48108, + "accesses": [ + { + "address": 63589, + "instruction_address": 48108, + "instruction": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F865", + "operand_index": 0 + } + ] + }, + { + "address": 63592, + "name": "ram_F868", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48051, + "last_access": 48051, + "accesses": [ + { + "address": 63592, + "instruction_address": 48051, + "instruction": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F868", + "operand_index": 0 + } + ] + }, + { + "address": 63594, + "name": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48059, + "last_access": 48059, + "accesses": [ + { + "address": 63594, + "instruction_address": 48059, + "instruction": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86A", + "operand_index": 0 + } + ] + }, + { + "address": 63596, + "name": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48067, + "last_access": 48067, + "accesses": [ + { + "address": 63596, + "instruction_address": 48067, + "instruction": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86C", + "operand_index": 0 + } + ] + }, + { + "address": 63920, + "name": "ram_F9B0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 9, + "read_count": 8, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15968, + "last_access": 47864, + "accesses": [ + { + "address": 63920, + "instruction_address": 15968, + "instruction": "MOV:G.B @H'F9B0, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 15994, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 15998, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16002, + "instruction": "MOV:G.B @H'F9B0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16377, + "instruction": "CLR.B @H'F9B0", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16473, + "instruction": "MOV:G.B @H'F9B0, R2", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16492, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16496, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 47864, + "instruction": "CMP:G.B @H'F9B0, R1", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + } + ] + }, + { + "address": 63924, + "name": "ram_F9B4", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 7, + "read_count": 7, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10252, + "last_access": 48793, + "accesses": [ + { + "address": 63924, + "instruction_address": 10252, + "instruction": "CMP:G.B @H'F9B4, R1", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 16038, + "instruction": "MOV:G.B @H'F9B4, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 16067, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 16071, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48760, + "instruction": "MOV:G.B @H'F9B4, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 48789, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48793, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + } + ] + }, + { + "address": 63925, + "name": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 10, + "write_count": 7, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15960, + "last_access": 48631, + "accesses": [ + { + "address": 63925, + "instruction_address": 15960, + "instruction": "MOV:G.B @H'F9B5, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16011, + "instruction": "CMP:G.B @H'F9B5, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16373, + "instruction": "CLR.B @H'F9B5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16479, + "instruction": "CMP:G.B @H'F9B5, R2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 47858, + "instruction": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 48493, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48497, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48584, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48588, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48627, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48631, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + } + ] + }, + { + "address": 63929, + "name": "ram_F9B9", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10246, + "last_access": 48752, + "accesses": [ + { + "address": 63929, + "instruction_address": 10246, + "instruction": "MOV:G.B @H'F9B9, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 10274, + "instruction": "MOV:G.B R1, @H'F9B9", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 1 + }, + { + "address": 63929, + "instruction_address": 16030, + "instruction": "MOV:G.B @H'F9B9, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 48752, + "instruction": "MOV:G.B @H'F9B9, R3", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + } + ] + }, + { + "address": 63936, + "name": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 4, + "write_count": 8, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16357, + "last_access": 48884, + "accesses": [ + { + "address": 63936, + "instruction_address": 16357, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47654, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47660, + "instruction": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47778, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47834, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47841, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47848, + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48669, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48702, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48878, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 48884, + "instruction": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + } + ] + }, + { + "address": 63937, + "name": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47853, + "last_access": 48894, + "accesses": [ + { + "address": 63937, + "instruction_address": 47853, + "instruction": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 47985, + "instruction": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 48035, + "instruction": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 1 + }, + { + "address": 63937, + "instruction_address": 48888, + "instruction": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 48894, + "instruction": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 1 + } + ] + }, + { + "address": 63938, + "name": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47734, + "last_access": 47811, + "accesses": [ + { + "address": 63938, + "instruction_address": 47734, + "instruction": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47787, + "instruction": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 0 + }, + { + "address": 63938, + "instruction_address": 47807, + "instruction": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "direction": 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0 + }, + { + "address": 63939, + "instruction_address": 47760, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47991, + "instruction": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47997, + "instruction": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 1 + }, + { + "address": 63939, + "instruction_address": 48010, + "instruction": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 48022, + "instruction": "MOV:G.B R1, @H'F9C3", + "mnemonic": "MOV:G.B", + "direction": "write", + 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"address": 63940, + "instruction_address": 16454, + "instruction": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 0 + }, + { + "address": 63940, + "instruction_address": 16608, + "instruction": "MOV:G.B #H'14, @H'F9C4", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + }, + { + "address": 63940, + "instruction_address": 47665, + "instruction": "MOV:G.B #H'07, @H'F9C4", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + }, + { + "address": 63940, + "instruction_address": 48935, + "instruction": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 0 + }, + { + "address": 63940, + "instruction_address": 48941, + "instruction": "ADD:Q.B #-1, @H'F9C4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + } + ] + }, + { + "address": 63941, + "name": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16367, + "last_access": 48951, + "accesses": [ + { + "address": 63941, + "instruction_address": 16367, + "instruction": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48030, + "instruction": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 1 + }, + { + "address": 63941, + "instruction_address": 48868, + "instruction": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48945, + "instruction": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48951, + "instruction": "ADD:Q.B #-1, @H'F9C5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 1 + } + ] + }, + { + "address": 63942, + "name": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 47942, + "last_access": 48904, + "accesses": [ + { + "address": 63942, + "instruction_address": 47942, + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 1 + }, + { + "address": 63942, + "instruction_address": 48821, + "instruction": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "direction": "read", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 0 + }, + { + "address": 63942, + "instruction_address": 48837, + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 1 + }, + { + "address": 63942, + "instruction_address": 48898, + "instruction": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "direction": "read", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 0 + }, + { + "address": 63942, + "instruction_address": 48904, + "instruction": "ADD:Q.W #-1, @H'F9C6", + "mnemonic": "ADD:Q.W", + "direction": "read_write", + "width": "word", + "operand": "@H'F9C6", + "operand_index": 1 + } + ] + }, + { + "address": 63944, + "name": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47948, + "last_access": 48833, + "accesses": [ + { + "address": 63944, + "instruction_address": 47948, + "instruction": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 1 + }, + { + "address": 63944, + "instruction_address": 48827, + "instruction": "TST.B @H'F9C8", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 0 + }, + { + "address": 63944, + "instruction_address": 48833, + "instruction": "ADD:Q.B #-1, @H'F9C8", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 1 + } + ] + }, + { + "address": 63995, + "name": "ram_F9FB", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 0, + "read_count": 0, + "write_count": 0, + "unknown_count": 0, + "width_hints": [], + "width": null, + "first_access": null, + "last_access": null, + "accesses": [], + "xref_count": 1, + "xrefs": [ + { + "source": "pointer_table", + "address": 53384, + "target": 63995 + } + ] + }, + { + "address": 64132, + "name": "ram_FA84", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 0, + "read_count": 0, + "write_count": 0, + "unknown_count": 0, + "width_hints": [], + "width": null, + "first_access": null, + "last_access": null, + "accesses": [], + "xref_count": 1, + "xrefs": [ + { + "source": "pointer_table", + "address": 25326, + "target": 64132 + } + ] + }, + { + "address": 64162, + "name": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 19, + "read_count": 13, + "write_count": 13, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16339, + "last_access": 48815, + "accesses": [ + { + "address": 64162, + "instruction_address": 16339, + "instruction": "TST.B @H'FAA2", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'FAA2", + "operand_index": 0 + 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"text": "4.0 X", + "trimmed": "4.0 X", + "kind": "printable_run", + "score": 0.981, + "confidence": "medium", + "xrefs": [ + { + "address": 45106, + "kind": "raw_mov_iw", + "target": 45090, + "delta": -1, + "register": "R0", + "instruction": "MOV:I.W #H'B022, R0", + "following_bsr": { + "address": 45109, + "target": 23697, + "instruction": "BSR H'5C91" + } + } + ], + "xref_count": 1 + }, + { + "address": 45249, + "length": 17, + "text": " KNEE X", + "trimmed": "KNEE X", + "kind": "printable_run", + "score": 1.041, + "confidence": "medium", + "xrefs": [ + { + "address": 45265, + "kind": "raw_mov_iw", + "target": 45249, + "delta": 0, + "register": "R0", + "instruction": "MOV:I.W #H'B0C1, R0", + "following_bsr": { + "address": 45268, + "target": 23185, + "instruction": "BSR H'5A91" + } + } + ], + "xref_count": 1 + }, + { + "address": 45283, + "length": 16, + "text": "PRESET X", + "trimmed": "PRESET X", + "kind": "printable_run", + "score": 1.038, + "confidence": "medium", + "xrefs": [ + { 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RECALL~X", + "score": 0.4 + }, + { + "address": 26243, + "text": "POINT1 POINT2Xf", + "trimmed": "POINT1 POINT2Xf", + "score": 0.381 + } + ], + "status": "not_found" + } + ], + "notes": [ + "LCD text scan is byte-oriented and conservative; strings may be inline script fields.", + "Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes." + ] + }, + "lcd_driver": { + "addresses": [ + { + "address": 61952, + "name": "lcd_status_control", + "role": "status/control register inferred from busy polling and command writes" + }, + { + "address": 61953, + "name": "lcd_data", + "role": "data register inferred from paired data reads/writes" + } + ], + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "polling_loops": [ + { + "read_address": 16202, + "test_address": 16207, + "branch_address": 16209, + "register": "R0", + "bit": 7, + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear" + } + ], + "routines": [ + { + "start": 16192, + "end": 16244, + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "roles": [ + "lcd_command_or_address_write", + "lcd_data_read", + "lcd_data_write", + "lcd_status_read" + ], + "role_hint": "lcd_wait_and_transfer" + } + ], + "instructions": { + "16202": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16219": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ], + "16226": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ], + "16237": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "16207": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16209": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + } + }, + "instructions": [ + { + "address": 4096, + "address_region": "program_or_external", + "bytes": "5FFE80", + "text": "MOV:I.W #H'FE80, R7", + "mnemonic": "MOV:I.W", + "operands": "#H'FE80, R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R7 = 0xFE80" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + } + } + } + }, + { + "address": 4099, + "address_region": "program_or_external", + "bytes": "0C070088", + "text": "LDC.W #H'0700, SR", + "mnemonic": "LDC.W", + "operands": "#H'0700, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + ], + "notes": [ + "SR = 0x0700" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4103, + "address_region": "program_or_external", + "bytes": "15FE8006FF", + "text": "MOV:G.B #H'FF, @P1DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @P1DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65152, + "name": "P1DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DDR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4108, + "address_region": "program_or_external", + "bytes": "15FE820600", + "text": "MOV:G.B #H'00, @P1DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4113, + "address_region": "program_or_external", + "bytes": "15FE8906F9", + "text": "MOV:G.B #H'F9, @P6DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'F9, @P6DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65161, + "name": "P6DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DDR = H'F9", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4118, + "address_region": "program_or_external", + "bytes": "15FE8B06F1", + "text": "MOV:G.B #H'F1, @P6DR", + "mnemonic": "MOV:G.B", + "operands": "#H'F1, @P6DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65163, + "name": "P6DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DR = H'F1", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4123, + "address_region": "program_or_external", + "bytes": "15FE8C0600", + "text": "MOV:G.B #H'00, @P7DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65164, + "name": "P7DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DDR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4128, + "address_region": "program_or_external", + "bytes": "15FE8E0600", + "text": "MOV:G.B #H'00, @P7DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4133, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'93", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4138, + "address_region": "program_or_external", + "bytes": "15FEFF0600", + "text": "MOV:G.B #H'00, @P9DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4143, + "address_region": "program_or_external", + "bytes": "15FEFC0687", + "text": "MOV:G.B #H'87, @SYSCR1", + "mnemonic": "MOV:G.B", + "operands": "#H'87, @SYSCR1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65276, + "name": "SYSCR1", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4148, + "address_region": "program_or_external", + "bytes": "15FEFD0684", + "text": "MOV:G.B #H'84, @SYSCR2", + "mnemonic": "MOV:G.B", + "operands": "#H'84, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM)", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4153, + "address_region": "program_or_external", + "bytes": "15FE900602", + "text": "MOV:G.B #H'02, @FRT1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4158, + "address_region": "program_or_external", + "bytes": "15FE910601", + "text": "MOV:G.B #H'01, @FRT1_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4163, + "address_region": "program_or_external", + "bytes": "1DFE920600", + "text": "MOV:G.W #H'00, @FRT1_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT1_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65170, + "name": "FRT1_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4163, + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "register": "FRT1_FRC", + "high_address": 65170, + "low_address": 65171, + "referenced_address": 65170, + "referenced_address_hex": "H'FE92", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4168, + "address_region": "program_or_external", + "bytes": "1DFE9407009C", + "text": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'009C, @FRT1_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65172, + "name": "FRT1_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_OCRA_H = H'9C", + "valid": true, + "peripheral_access": [ + { + "address": 4168, + "instruction": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "register": "FRT1_OCRA", + "high_address": 65172, + "low_address": 65173, + "referenced_address": 65172, + "referenced_address_hex": "H'FE94", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4174, + "address_region": "program_or_external", + "bytes": "15FEA00602", + "text": "MOV:G.B #H'02, @FRT2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4179, + "address_region": "program_or_external", + "bytes": "15FEA10601", + "text": "MOV:G.B #H'01, @FRT2_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT2_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65185, + "name": "FRT2_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4184, + "address_region": "program_or_external", + "bytes": "1DFEA20600", + "text": "MOV:G.W #H'00, @FRT2_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT2_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65186, + "name": "FRT2_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4184, + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "register": "FRT2_FRC", + "high_address": 65186, + "low_address": 65187, + "referenced_address": 65186, + "referenced_address_hex": "H'FEA2", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4189, + "address_region": "program_or_external", + "bytes": "1DFEA4077A12", + "text": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'7A12, @FRT2_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65188, + "name": "FRT2_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_OCRA_H = H'7A12", + "valid": true, + "peripheral_access": [ + { + "address": 4189, + "instruction": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "register": "FRT2_OCRA", + "high_address": 65188, + "low_address": 65189, + "referenced_address": 65188, + "referenced_address_hex": "H'FEA4", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4195, + "address_region": "program_or_external", + "bytes": "15FEB00600", + "text": "MOV:G.B #H'00, @FRT3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65200, + "name": "FRT3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4200, + "address_region": "program_or_external", + "bytes": "15FEB10600", + "text": "MOV:G.B #H'00, @FRT3_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65201, + "name": "FRT3_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4205, + "address_region": "program_or_external", + "bytes": "15FED00600", + "text": "MOV:G.B #H'00, @TMR_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @TMR_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65232, + "name": "TMR_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4210, + "address_region": "program_or_external", + "bytes": "15FED10610", + "text": "MOV:G.B #H'10, @TMR_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'10, @TMR_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65233, + "name": "TMR_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4215, + "address_region": "program_or_external", + "bytes": "15FEC00638", + "text": "MOV:G.B #H'38, @PWM1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65216, + "name": "PWM1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4220, + "address_region": "program_or_external", + "bytes": "15FEC106FF", + "text": "MOV:G.B #H'FF, @PWM1_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM1_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65217, + "name": "PWM1_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4225, + "address_region": "program_or_external", + "bytes": "15FEC40638", + "text": "MOV:G.B #H'38, @PWM2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65220, + "name": "PWM2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4230, + "address_region": "program_or_external", + "bytes": "15FEC506FF", + "text": "MOV:G.B #H'FF, @PWM2_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM2_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65221, + "name": "PWM2_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4235, + "address_region": "program_or_external", + "bytes": "15FEC8063B", + "text": "MOV:G.B #H'3B, @PWM3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3B, @PWM3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65224, + "name": "PWM3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4240, + "address_region": "program_or_external", + "bytes": "15FEC9067D", + "text": "MOV:G.B #H'7D, @PWM3_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'7D, @PWM3_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65225, + "name": "PWM3_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_DTR = H'7D", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4245, + "address_region": "program_or_external", + "bytes": "15FED80624", + "text": "MOV:G.B #H'24, @SCI1_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI1_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65240, + "name": "SCI1_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4250, + "address_region": "program_or_external", + "bytes": "15FEDA063C", + "text": "MOV:G.B #H'3C, @SCI1_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3C, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + } + ] + }, + "sci_protocol": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4255, + "address_region": "program_or_external", + "bytes": "15FED90607", + "text": "MOV:G.B #H'07, @SCI1_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI1_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65241, + "name": "SCI1_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4260, + "address_region": "program_or_external", + "bytes": "15FEF00624", + "text": "MOV:G.B #H'24, @SCI2_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI2_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65264, + "name": "SCI2_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4265, + "address_region": "program_or_external", + "bytes": "15FEF2060C", + "text": "MOV:G.B #H'0C, @SCI2_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'0C, @SCI2_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65266, + "name": "SCI2_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + } + ] + }, + "sci_protocol": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4270, + "address_region": "program_or_external", + "bytes": "15FEF10607", + "text": "MOV:G.B #H'07, @SCI2_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI2_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65265, + "name": "SCI2_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4275, + "address_region": "program_or_external", + "bytes": "15FEE80619", + "text": "MOV:G.B #H'19, @ADCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'19, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4280, + "address_region": "program_or_external", + "bytes": "15FEE9067F", + "text": "MOV:G.B #H'7F, @H'FEE9", + "mnemonic": "MOV:G.B", + "operands": "#H'7F, @H'FEE9", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65257, + "name": null, + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4285, + "address_region": "program_or_external", + "bytes": "15FF1006F0", + "text": "MOV:G.B #H'F0, @WCR", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @WCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65296, + "name": "WCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4290, + "address_region": "program_or_external", + "bytes": "15FF1106FF", + "text": "MOV:G.B #H'FF, @RAMCR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @RAMCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65297, + "name": "RAMCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "RAMCR = H'FF (RAME=1; on-chip RAM enabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4295, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4299, + "address_region": "program_or_external", + "bytes": "302EA8", + "text": "BRA loc_3F76", + "mnemonic": "BRA", + "operands": "loc_3F76", + "kind": "jump", + "targets": [ + 16246 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4302, + "address_region": "program_or_external", + "bytes": "5C0040", + "text": "MOV:I.W #H'0040, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0040, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0040" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + } + } + } + }, + { + "address": 4305, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 4308, + "address_region": "program_or_external", + "bytes": "1E2DF5", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 4311, + "address_region": "program_or_external", + "bytes": "5C0200", + "text": "MOV:I.W #H'0200, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0200, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": 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"cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6627, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 6633, + "address_region": "program_or_external", + "bytes": "A982", + "text": "MOV:G.W R1, R2", + "mnemonic": "MOV:G.W", + "operands": "R1, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6627, + "changes": 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"assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6642, + "address_region": "program_or_external", + "bytes": "230F", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6644, + "address_region": "program_or_external", + "bytes": "590000", + "text": "MOV:I.W #H'0000, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6644, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R1" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 = 0x0000" + ], + "known_after": { + "registers": { + "R1": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R1" + } + } + } + } + }, + { + "address": 6647, + "address_region": "program_or_external", + "bytes": "200A", + "text": "BRA loc_1A03", + "mnemonic": "BRA", + "operands": "loc_1A03", + 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"address_region": "program_or_external", + "bytes": "2303", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6649, + "changes": [], + "notes": [] + } + }, + { + "address": 6656, + "address_region": "program_or_external", + "bytes": "59FFFF", + "text": "MOV:I.W #H'FFFF, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'FFFF, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6656, + "changes": [ + { + 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"name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": 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"address_region": "program_or_external", + "bytes": "01B9F9", + "text": "SCB/F R1, loc_1A90", + "mnemonic": "SCB/F", + "operands": "R1, loc_1A90", + "kind": "branch", + "targets": [ + 6800 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6804, + "changes": [], + "notes": [] + } + }, + { + "address": 6807, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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"text": "BSR loc_1C0E", + "mnemonic": "BSR", + "operands": "loc_1C0E", + "kind": "call", + "targets": [ + 7182 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 7072, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + 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"bytes": "15F6E494", + "text": "MOV:G.B R4, @H'F6E4", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F6E4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63204, + "name": null, + "symbol": "ram_F6E4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 7072, + "changes": [], + "notes": [] + } + }, + { + "address": 7093, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, 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"base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63377, + "name": null, + "symbol": "ram_F791", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 9873, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R2": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "R3": { + "known": true, + "value": 146, + "hex": "0x0092", + "width": 16, + "source": "MOV:I.W #H'0092, R3" + } + } + } + } + }, + { + "address": 9886, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_26A8", + "mnemonic": "BEQ", + "operands": "loc_26A8", + "kind": "branch", + "targets": [ + 9896 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix 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"symbol": "mem_F404", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 9888, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 9892, + "address_region": "program_or_external", + "bytes": "2702", + "text": "BEQ loc_26A8", + "mnemonic": "BEQ", + "operands": "loc_26A8", + "kind": "branch", + "targets": [ + 9896 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 9888, + "changes": [], + "notes": [] + } + }, + { + "address": 9894, + "address_region": "program_or_external", + "bytes": "ABCE", + "text": "BSET.W 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"program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + "dataflow": { + "block": 10399, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + } + ], + "notes": [ + "indirect jump ends known register state" + ] + } + }, + { + "address": 11430, + "address_region": "program_or_external", + "bytes": "15F769D7", + "text": "BCLR.B #7, @H'F769", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11434, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [], + "notes": [] + } + }, + { + "address": 11435, + "address_region": "program_or_external", + "bytes": "1231", + "text": "STM.W {R0,R4,R5}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R4,R5}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 15, + "note": "6+3n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 11437, + "address_region": "program_or_external", + "bytes": "1E1C4A", + "text": "BSR loc_48FA", + "mnemonic": "BSR", + "operands": "loc_48FA", + "kind": "call", + "targets": [ + 18682 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 11440, + "address_region": "program_or_external", + "bytes": "0231", + "text": "LDM.W @SP+, {R0,R4,R5}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R4,R5}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 18, + "note": "6+4n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R4, R5" + ] + } + }, + { + "address": 11442, + "address_region": "program_or_external", + "bytes": "15F769C7", + "text": "BSET.B #7, @H'F769", + "mnemonic": "BSET.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11446, + "address_region": "program_or_external", + "bytes": "30FBE6", + "text": "BRA loc_289F", + "mnemonic": "BRA", + "operands": "loc_289F", + "kind": "jump", + "targets": [ + 10399 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 14640, + "address_region": "program_or_external", + "bytes": "580007", + "text": "MOV:I.W #H'0007, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14640, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x0007" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + } + } + } + }, + { + "address": 14643, + "address_region": "program_or_external", + "bytes": "15FE8E78", + "text": "BTST.B R0, @P7DR", + "mnemonic": "BTST.B", + "operands": "R0, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 14643, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14647, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_3943", + "mnemonic": "BEQ", + "operands": "loc_3943", + "kind": "branch", + "targets": [ + 14659 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14643, + "changes": [], + "notes": [] + } + }, + { + "address": 14649, + "address_region": "program_or_external", + "bytes": "F0F6801A", + "text": "SHLL.B @(-H'0980,R0)", + "mnemonic": "SHLL.B", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14653, + "address_region": "program_or_external", + "bytes": "F0F680C0", + "text": "BSET.B #0, @(-H'0980,R0)", + "mnemonic": "BSET.B", + "operands": "#0, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [], + "notes": [] + } + }, + { + "address": 14657, + "address_region": "program_or_external", + "bytes": "2004", + "text": "BRA loc_3947", + "mnemonic": "BRA", + "operands": "loc_3947", + "kind": "jump", + "targets": [ + 14663 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [], + "notes": [] + } + }, + { + "address": 14659, + "address_region": "program_or_external", + "bytes": "F0F6801A", + "text": "SHLL.B @(-H'0980,R0)", + "mnemonic": "SHLL.B", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14659, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14663, + "address_region": "program_or_external", + "bytes": "F0F68004FF", + "text": "CMP:G.B #H'FF, @(-H'0980,R0)", + "mnemonic": "CMP:G.B", + "operands": "#H'FF, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14663, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14668, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_3954", + "mnemonic": "BNE", + "operands": "loc_3954", + "kind": "branch", + "targets": [ + 14676 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14663, + "changes": [], + "notes": [] + } + }, + { + "address": 14670, + "address_region": "program_or_external", + "bytes": "15F68848", + "text": "BSET.B R0, @H'F688", + "mnemonic": "BSET.B", + "operands": "R0, @H'F688", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63112, + "name": null, + "symbol": "ram_F688", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 14670, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } 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"base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63115, + "name": null, + "symbol": "ram_F68B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 15906, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 15910, + "address_region": "program_or_external", + "bytes": "2725", + "text": "BEQ loc_3E4D", + "mnemonic": "BEQ", + "operands": "loc_3E4D", + "kind": "branch", + "targets": [ + 15949 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"address_region": "program_or_external", + "bytes": "15FE8EF4", + "text": "BTST.B #4, @P7DR", + "mnemonic": "BTST.B", + "operands": "#4, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 15912, + "changes": [], + "notes": [] + } + }, + { + "address": 15941, + "address_region": "program_or_external", + "bytes": "2602", + "text": "BNE loc_3E49", + "mnemonic": "BNE", + "operands": "loc_3E49", + "kind": "branch", + "targets": [ + 15945 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip 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"address_region": "program_or_external", + "bytes": "270B", + "text": "BEQ loc_3EEE", + "mnemonic": "BEQ", + "operands": "loc_3EEE", + "kind": "branch", + "targets": [ + 16110 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16095, + "changes": [], + "notes": [] + } + }, + { + "address": 16099, + "address_region": "program_or_external", + "bytes": "4502", + "text": "CMP:E #H'02, R5", + "mnemonic": "CMP:E", + "operands": "#H'02, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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"notes": [], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 128, + "hex": "0x0080", + "width": 16, + "source": "MOV:I.W #H'0080, R5" + } + } + } + } + }, + { + "address": 16110, + "address_region": "program_or_external", + "bytes": "5D00C0", + "text": "MOV:I.W #H'00C0, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'00C0, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16110, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x00C0" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + } + } + } + }, + { + "address": 16113, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA loc_3EFB", + "mnemonic": "BRA", + "operands": "loc_3EFB", + "kind": "jump", + "targets": [ + 16123 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16110, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + } + 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"normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16120, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 208, + "hex": "0x00D0", + "width": 16, + "source": "MOV:I.W #H'00D0, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x00D0" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 208, + "hex": "0x00D0", + "width": 16, + "source": "MOV:I.W #H'00D0, R5" + } + } + } + } + }, + { + "address": 16123, + "address_region": "program_or_external", + "bytes": "0410AB", + "text": "MULXU.B #H'10, R3", + "mnemonic": "MULXU.B", + "operands": "#H'10, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16123, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:MULXU.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 16126, + "address_region": "program_or_external", + "bytes": "0CFAB023", + "text": "ADD:G.W #H'FAB0, R3", + "mnemonic": "ADD:G.W", + "operands": "#H'FAB0, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16123, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unsupported:MULXU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R3 unknown after arithmetic" + ] + } + }, + { + "address": 16130, + "address_region": "program_or_external", + "bytes": "A913", + "text": "CLR.W R1", + "mnemonic": "CLR.W", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": 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"changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after memory load" + ] + } + }, + { + "address": 16136, + "address_region": "program_or_external", + "bytes": "D372", + "text": "CMP:G.B @R3, R2", + "mnemonic": "CMP:G.B", + "operands": "@R3, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16138, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_3F10", + "mnemonic": "BEQ", + "operands": "loc_3F10", + "kind": "branch", + "targets": [ + 16144 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16140, + "address_region": "program_or_external", + "bytes": "D392", + "text": "MOV:G.B R2, @R3", + "mnemonic": "MOV:G.B", + "operands": "R2, @R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16140, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16142, + "address_region": "program_or_external", + "bytes": "0E18", + "text": "BSR loc_3F28", + "mnemonic": "BSR", + "operands": "loc_3F28", + "kind": "call", + "targets": [ + 16168 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16140, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": 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"cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [], + "notes": [] + } + }, + { + "address": 16150, + "address_region": "program_or_external", + "bytes": "2702", + "text": "BEQ loc_3F1A", + "mnemonic": "BEQ", + "operands": "loc_3F1A", + "kind": "branch", + "targets": [ + 16154 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [], + "notes": [] + } + }, + { + "address": 16152, + "address_region": "program_or_external", + "bytes": "20EA", + "text": "BRA loc_3F04", + "mnemonic": "BRA", + "operands": "loc_3F04", + "kind": "jump", + "targets": [ + 16132 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16152, + "changes": [], + "notes": [] + } + }, + { + "address": 16154, + "address_region": "program_or_external", + "bytes": "1DFB000700E0", + "text": "MOV:G.W #H'00E0, @H'FB00", + "mnemonic": "MOV:G.W", + "operands": "#H'00E0, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": 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"bytes": "1DFB0094", + "text": "MOV:G.W R4, @H'FB00", + "mnemonic": "MOV:G.W", + "operands": "R4, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16178, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16182, + "address_region": "program_or_external", + "bytes": "0E08", + "text": "BSR loc_3F40", + "mnemonic": "BSR", + "operands": "loc_3F40", + "kind": "call", + "targets": [ + 16192 + ], + "cycles": { + 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"kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16191, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16184, + "changes": [], + "notes": [] + } + }, + { + "address": 16192, + "address_region": "program_or_external", + "bytes": "BF98", + "text": "STC.W SR, @-R7", + "mnemonic": "STC.W", + "operands": "SR, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 7, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + } + ], + "notes": [] + } + }, + { + "address": 16194, + "address_region": "program_or_external", + "bytes": "0C00FF58", + "text": "ANDC.W #H'00FF, SR", + "mnemonic": "ANDC.W", + "operands": "#H'00FF, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "SR unknown after ANDC" + ] + } + }, + { + "address": 16198, + "address_region": "program_or_external", + "bytes": "0C060048", + "text": "ORC.W #H'0600, SR", + "mnemonic": "ORC.W", + "operands": "#H'0600, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16192, + "changes": [], + "notes": [ + "SR unknown after ORC" + ] + } + }, + { + "address": 16202, + "address_region": "program_or_external", + "bytes": "15F2000080", + "text": "MOVFPE.B @H'F200, R0", + "mnemonic": "MOVFPE.B", + "operands": "@H'F200, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16207, + "address_region": "program_or_external", + "bytes": "A0F7", + "text": "BTST.B #7, R0", + "mnemonic": "BTST.B", + "operands": "#7, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16209, + "address_region": "program_or_external", + "bytes": "26F7", + "text": "BNE loc_3F4A", + "mnemonic": "BNE", + "operands": "loc_3F4A", + "kind": "branch", + "targets": [ + 16202 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16211, + "address_region": "program_or_external", + "bytes": "ACF8", + "text": "BTST.W #8, R4", + "mnemonic": "BTST.W", + "operands": "#8, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16213, + "address_region": "program_or_external", + "bytes": "2616", + "text": "BNE loc_3F6D", + "mnemonic": "BNE", + "operands": "loc_3F6D", + "kind": "branch", + "targets": [ + 16237 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [], + "notes": [] + } + }, + { + "address": 16215, + "address_region": "program_or_external", + "bytes": "ACF9", + "text": "BTST.W #9, R4", + "mnemonic": "BTST.W", + "operands": "#9, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16217, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_3F62", + "mnemonic": "BNE", + "operands": "loc_3F62", + "kind": "branch", + "targets": [ + 16226 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [], + "notes": [] + } + }, + { + "address": 16219, + "address_region": "program_or_external", + "bytes": "15F2000094", + "text": "MOVTPE.B R4, @H'F200", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F200", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ] + }, + { + "address": 16224, + "address_region": "program_or_external", + "bytes": "2010", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [], + "notes": [] + } + }, + { + "address": 16226, + "address_region": "program_or_external", + "bytes": "15F2010094", + "text": "MOVTPE.B R4, @H'F201", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F201", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ] + }, + { + "address": 16231, + "address_region": "program_or_external", + "bytes": "1DFB0008", + "text": "ADD:Q.W #1, @H'FB00", + "mnemonic": "ADD:Q.W", + "operands": "#1, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16235, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16237, + "address_region": "program_or_external", + "bytes": "15F2010084", + "text": "MOVFPE.B @H'F201, R4", + "mnemonic": "MOVFPE.B", + "operands": "@H'F201, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16237, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ] + }, + { + "address": 16242, + "address_region": "program_or_external", + "bytes": "CF88", + "text": "LDC.W @R7+, SR", + "mnemonic": "LDC.W", + "operands": "@R7+, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "SR unknown after memory load" + ] + } + }, + { + "address": 16244, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [], + "notes": [] + } + }, + { + "address": 16246, + "address_region": "program_or_external", + "bytes": "582710", + "text": "MOV:I.W #H'2710, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'2710, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x2710" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + } + } + } + }, + { + "address": 16249, + "address_region": "program_or_external", + "bytes": "59C350", + "text": "MOV:I.W #H'C350, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'C350, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + ], + "notes": [ + "R1 = 0xC350" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + }, + "R1": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + } + } + }, + { + "address": 16252, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 16252, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16256, + "address_region": "program_or_external", + "bytes": "01B8F9", + "text": "SCB/F R0, loc_3F7C", + "mnemonic": "SCB/F", + "operands": "R0, loc_3F7C", + "kind": "branch", + "targets": [ + 16252 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 8, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16252, + "changes": [], + "notes": [] + } + }, + { + "address": 16259, + "address_region": "program_or_external", + "bytes": "15FE82C7", + "text": "BSET.B #7, @P1DR", + "mnemonic": "BSET.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16263, + "address_region": "program_or_external", + "bytes": "01B9F9", + "text": "SCB/F R1, loc_3F83", + "mnemonic": "SCB/F", + "operands": "R1, loc_3F83", + "kind": "branch", + "targets": [ + 16259 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [], + "notes": [] + } + }, + { + "address": 16266, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16266, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 cleared" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + } + } + } + }, + { + "address": 16268, + "address_region": "program_or_external", + "bytes": "F8E00013", + "text": "CLR.W @(-H'2000,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'2000,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16272, + "address_region": "program_or_external", + "bytes": "F8E80013", + "text": "CLR.W @(-H'1800,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'1800,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16276, + "address_region": "program_or_external", + "bytes": "F8F68013", + "text": "CLR.W @(-H'0980,R0)", + "mnemonic": "CLR.W", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16280, + "address_region": "program_or_external", + "bytes": "A809", + "text": "ADD:Q.W #2, R0", + "mnemonic": "ADD:Q.W", + "operands": "#2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R0 unknown after arithmetic" + ] + } + }, + { + "address": 16282, + "address_region": "program_or_external", + "bytes": "480800", + "text": "CMP:I #H'0800, R0", + "mnemonic": "CMP:I", + "operands": "#H'0800, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + }, + { + "address": 16285, + "address_region": "program_or_external", + "bytes": "26ED", + "text": "BNE loc_3F8C", + "mnemonic": "BNE", + "operands": "loc_3F8C", + "kind": "branch", + "targets": [ + 16268 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16268, + "changes": [], + "notes": [] + } + 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"address_region": "program_or_external", + "bytes": "1E037F", + "text": "BSR loc_4324", + "mnemonic": "BSR", + "operands": "loc_4324", + "kind": "call", + "targets": [ + 17188 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16293, + "address_region": "program_or_external", + "bytes": "1E00EE", + "text": "BSR loc_4096", + "mnemonic": "BSR", + "operands": "loc_4096", + "kind": "call", + "targets": [ + 16534 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16296, + "address_region": "program_or_external", + "bytes": "1E0110", + "text": "BSR loc_40BB", + "mnemonic": "BSR", + "operands": "loc_40BB", + "kind": "call", + "targets": [ + 16571 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16299, + "address_region": "program_or_external", + "bytes": "1E0269", + "text": "BSR loc_4217", + "mnemonic": "BSR", + "operands": "loc_4217", + "kind": "call", + "targets": [ + 16919 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16287, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16302, + "address_region": "program_or_external", + "bytes": "1E039B", + "text": "BSR loc_434C", + "mnemonic": "BSR", + "operands": "loc_434C", + "kind": "call", + "targets": [ + 17228 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16311, + "address_region": "program_or_external", + "bytes": "15F79413", + "text": "CLR.B @H'F794", + "mnemonic": "CLR.B", + "operands": "@H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16305, + "changes": [], + "notes": [] + } + }, + { + "address": 16315, + "address_region": "program_or_external", + "bytes": "0E16", + "text": "BSR loc_3FD3", + "mnemonic": "BSR", + "operands": "loc_3FD3", + "kind": "call", + "targets": [ + 16339 + ], + "cycles": { + "cycles": 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"kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 16317, + "address_region": "program_or_external", + "bytes": "1E7BEB", + "text": "BSR loc_BBAB", + "mnemonic": "BSR", + "operands": "loc_BBAB", + "kind": "call", + "targets": [ + 48043 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 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"control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17197, + "address_region": "program_or_external", + "bytes": "5C0001", + "text": "MOV:I.W #H'0001, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0001, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0001" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + } + } + }, + { + "address": 17200, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17203, + "address_region": "program_or_external", + "bytes": "1EFB96", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17206, + "address_region": "program_or_external", + "bytes": "5C000E", + "text": "MOV:I.W #H'000E, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'000E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x000E" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + } + } + } + } + }, + { + "address": 17209, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17212, + "address_region": "program_or_external", + "bytes": "1EFB8D", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17215, + "address_region": "program_or_external", + "bytes": "5C0006", + "text": "MOV:I.W #H'0006, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0006, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0006" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + } + } + } + } + }, + { + "address": 17218, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17221, + "address_region": "program_or_external", + "bytes": "1EFB84", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17224, + "address_region": "program_or_external", + "bytes": "1ECD83", + "text": "BSR loc_10CE", + "mnemonic": "BSR", + "operands": "loc_10CE", + "kind": "call", + "targets": [ + 4302 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17227, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [] + } + }, + { + "address": 17228, + "address_region": "program_or_external", + "bytes": "15FF000670", + "text": "MOV:G.B #H'70, @IPRA", + "mnemonic": "MOV:G.B", + "operands": "#H'70, @IPRA", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65280, + "name": "IPRA", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRA = H'70 (irq0 priority=7; irq1 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17233, + "address_region": "program_or_external", + "bytes": "15FF010644", + "text": "MOV:G.B #H'44, @IPRB", + "mnemonic": "MOV:G.B", + "operands": "#H'44, @IPRB", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65281, + "name": "IPRB", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17238, + "address_region": "program_or_external", + "bytes": "15FF020666", + "text": "MOV:G.B #H'66, @IPRC", + "mnemonic": "MOV:G.B", + "operands": "#H'66, @IPRC", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65282, + "name": "IPRC", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRC = H'66 (FRT1 priority=6; FRT2 priority=6)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17243, + "address_region": "program_or_external", + "bytes": "15FF030600", + "text": "MOV:G.B #H'00, @IPRD", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @IPRD", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65283, + "name": "IPRD", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17248, + "address_region": "program_or_external", + "bytes": "15FF040650", + "text": "MOV:G.B #H'50, @IPRE", + "mnemonic": "MOV:G.B", + "operands": "#H'50, @IPRE", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65284, + "name": "IPRE", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRE = H'50 (SCI1 priority=5; SCI2 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17253, + "address_region": "program_or_external", + "bytes": "15FF050640", + "text": "MOV:G.B #H'40, @IPRF", + "mnemonic": "MOV:G.B", + "operands": "#H'40, @IPRF", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65285, + "name": "IPRF", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRF = H'40 (A/D priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17258, + "address_region": "program_or_external", + "bytes": "15FEDAC6", + "text": "BSET.B #6, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#6, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set RIE (bit 6) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17262, + "address_region": "program_or_external", + "bytes": "15FE90C5", + "text": "BSET.B #5, @FRT1_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT1_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17266, + "address_region": "program_or_external", + "bytes": "15FEA0C5", + "text": "BSET.B #5, @FRT2_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT2_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17270, + "address_region": "program_or_external", + "bytes": "15FEE8C6", + "text": "BSET.B #6, @ADCSR", + "mnemonic": "BSET.B", + "operands": "#6, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set ADIE (bit 6) of ADCSR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17274, + "address_region": "program_or_external", + "bytes": "15FEFDC4", + "text": "BSET.B #4, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#4, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ3E (bit 4) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17278, + "address_region": "program_or_external", + "bytes": "15FEFDC5", + "text": "BSET.B #5, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#5, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ4E (bit 5) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17282, + "address_region": "program_or_external", + "bytes": "15FE8EF6", + "text": "BTST.B #6, @P7DR", + "mnemonic": "BTST.B", + "operands": "#6, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17286, + "address_region": "program_or_external", + "bytes": "2706", + "text": "BEQ loc_438E", + "mnemonic": "BEQ", + "operands": "loc_438E", + "kind": "branch", + "targets": [ + 17294 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17288, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 17288, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17294, + "address_region": "program_or_external", + "bytes": "0C030088", + "text": "LDC.W #H'0300, SR", + "mnemonic": "LDC.W", + "operands": "#H'0300, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + ], + "notes": [ + "SR = 0x0300" + ], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17298, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [], + "notes": [], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17299, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17299, + "changes": [], + "notes": [] + } + }, + { + "address": 17300, + "address_region": "program_or_external", + "bytes": "15F7310401", + "text": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "operands": "#H'01, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17305, + "address_region": "program_or_external", + "bytes": "320086", + "text": "BHI loc_4422", + "mnemonic": "BHI", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [], + "notes": [] + } + }, + { + "address": 17308, + "address_region": "program_or_external", + "bytes": "15FB03F7", + "text": "BTST.B #7, @H'FB03", + "mnemonic": "BTST.B", + "operands": "#7, @H'FB03", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64259, + "name": null, + "symbol": "ram_FB03", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17308, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17312, + "address_region": "program_or_external", + "bytes": "36007F", + "text": "BNE loc_4422", + "mnemonic": "BNE", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17308, + "changes": [], + "notes": [] + } + }, + { + "address": 17315, + "address_region": "program_or_external", + "bytes": "1DF73683", + "text": "MOV:G.W @H'F736, R3", + "mnemonic": "MOV:G.W", + "operands": "@H'F736, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63286, + "name": null, + "symbol": "ram_F736", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17315, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 unknown after memory load" + ] + } + }, + { + "address": 17319, + "address_region": "program_or_external", + "bytes": "370078", + "text": "BEQ loc_4422", + "mnemonic": "BEQ", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17315, + "changes": [], + "notes": [] + } + }, + { + "address": 17322, + "address_region": "program_or_external", + "bytes": "1DF69E84", + "text": "MOV:G.W @H'F69E, R4", + "mnemonic": "MOV:G.W", + "operands": "@H'F69E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63134, + "name": null, + "symbol": "ram_F69E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 17326, + "address_region": "program_or_external", + "bytes": "1DF6BE34", + "text": "SUB.W @H'F6BE, R4", + "mnemonic": "SUB.W", + "operands": "@H'F6BE, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63166, + "name": null, + "symbol": "ram_F6BE", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 17330, + "address_region": "program_or_external", + "bytes": "ABDF", + "text": "BCLR.W #15, R3", + "mnemonic": "BCLR.W", + "operands": "#15, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17332, + "address_region": "program_or_external", + "bytes": "2619", + "text": "BNE loc_43CF", + "mnemonic": "BNE", + "operands": "loc_43CF", + "kind": "branch", + "targets": [ + 17359 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [], + "notes": [] + } + }, + { + "address": 17334, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17334, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17336, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_43DB", + "mnemonic": "BNE", + "operands": "loc_43DB", + "kind": "branch", + "targets": [ + 17371 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17334, + "changes": [], + "notes": [] + } + }, + { + "address": 17338, + "address_region": "program_or_external", + "bytes": "ABDD", + "text": "BCLR.W #13, R3", + "mnemonic": "BCLR.W", + "operands": "#13, R3", + "kind": "normal", + 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"block": 17467, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17471, + "address_region": "program_or_external", + "bytes": "5C0002", + "text": "MOV:I.W #H'0002, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0002, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17467, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R4" + } + } + ], + "notes": [ + "R4 = 0x0002" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R4" + } + } + } + } + }, + { + "address": 17474, + "address_region": "program_or_external", + "bytes": "2012", + "text": "BRA loc_4456", + "mnemonic": "BRA", + "operands": "loc_4456", + "kind": "jump", + "targets": [ + 17494 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17467, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 2, + "hex": "0x0002", + "width": 16, + "source": "MOV:I.W #H'0002, R4" + } + } + } + } + }, + { + "address": 17476, + "address_region": "program_or_external", + "bytes": "15F6F70680", + "text": "MOV:G.B #H'80, @H'F6F7", + "mnemonic": "MOV:G.B", + "operands": "#H'80, @H'F6F7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63223, + "name": null, + "symbol": "ram_F6F7", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17476, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17481, + "address_region": "program_or_external", + "bytes": "5C0000", + "text": "MOV:I.W #H'0000, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17476, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R4" + } + } + ], + "notes": [ + "R4 = 0x0000" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "MOV:I.W #H'0000, R4" + } + } + } + } + }, + { + "address": 17484, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA loc_4456", + "mnemonic": "BRA", + "operands": "loc_4456", + "kind": "jump", + "targets": [ + 17494 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction 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"kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17491, + "address_region": "program_or_external", + "bytes": "5C0001", + "text": "MOV:I.W #H'0001, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0001, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17486, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + ], + "notes": [ + "R4 = 0x0001" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + } + } + }, + { + "address": 17494, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17494, + "changes": [], + "notes": [] + } + }, + { + "address": 17495, + "address_region": "program_or_external", + "bytes": "15F7310401", + "text": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "operands": "#H'01, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17495, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17500, + "address_region": "program_or_external", + "bytes": "320086", + "text": "BHI loc_44E5", + "mnemonic": "BHI", + "operands": "loc_44E5", + "kind": "branch", + "targets": [ + 17637 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17495, + "changes": [], + "notes": [] + } + }, + { + "address": 17503, + "address_region": "program_or_external", + "bytes": "15FB03F7", + "text": "BTST.B #7, @H'FB03", + "mnemonic": "BTST.B", + "operands": "#7, @H'FB03", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64259, + "name": null, + "symbol": "ram_FB03", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17503, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17507, + "address_region": "program_or_external", + "bytes": "36007F", + "text": "BNE loc_44E5", + "mnemonic": "BNE", + "operands": "loc_44E5", + "kind": "branch", + "targets": [ + 17637 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17503, + "changes": [], + "notes": [] + } + }, + { + "address": 17510, + "address_region": "program_or_external", + "bytes": "1DF73883", + "text": "MOV:G.W @H'F738, R3", + "mnemonic": "MOV:G.W", + "operands": "@H'F738, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63288, + "name": null, + "symbol": "ram_F738", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17510, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 unknown after memory load" + ] + } + }, + { + "address": 17514, + "address_region": "program_or_external", + "bytes": "370078", + "text": "BEQ loc_44E5", + "mnemonic": "BEQ", + "operands": "loc_44E5", + "kind": "branch", + "targets": [ + 17637 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17510, + "changes": [], + "notes": [] + } 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memory load" + ] + } + }, + { + "address": 17521, + "address_region": "program_or_external", + "bytes": "1DF6BC34", + "text": "SUB.W @H'F6BC, R4", + "mnemonic": "SUB.W", + "operands": "@H'F6BC, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63164, + "name": null, + "symbol": "ram_F6BC", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17517, + "changes": [], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 17525, + "address_region": "program_or_external", + "bytes": "ABDF", + "text": "BCLR.W #15, R3", + "mnemonic": "BCLR.W", + "operands": "#15, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17517, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17527, + "address_region": "program_or_external", + "bytes": "2619", + "text": "BNE loc_4492", + "mnemonic": "BNE", + "operands": "loc_4492", + "kind": "branch", + "targets": [ + 17554 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17517, + "changes": [], + "notes": [] + } + }, + { + "address": 17529, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17531, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_449E", + "mnemonic": "BNE", + "operands": "loc_449E", + "kind": "branch", + "targets": [ + 17566 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [], + "notes": [] + } + }, + { + "address": 17533, + "address_region": "program_or_external", + "bytes": "ABDD", + "text": "BCLR.W #13, R3", + "mnemonic": "BCLR.W", + "operands": "#13, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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@H'E9EC", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 59884, + "name": null, + "symbol": "mem_E9EC", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [], + "notes": [] + } + }, + { + "address": 18721, + "address_region": "program_or_external", + "bytes": "5280", + "text": "MOV:E.B #H'80, R2", + "mnemonic": "MOV:E.B", + "operands": "#H'80, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + } + } + ], + "notes": [ + "R2 = 0x80" + ], + "known_after": { + "registers": { + "R2": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + } + } + } + } + }, + { + "address": 18723, + "address_region": "program_or_external", + "bytes": "5B00F6", + "text": "MOV:I.W #H'00F6, R3", + "mnemonic": "MOV:I.W", + "operands": "#H'00F6, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 246, + "hex": "0x00F6", + "width": 16, + "source": "MOV:I.W #H'00F6, R3" + } + } + ], + "notes": [ + "R3 = 0x00F6" + ], + "known_after": { + "registers": { + "R2": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "R3": { + "known": true, + "value": 246, + "hex": "0x00F6", + "width": 16, + "source": "MOV:I.W #H'00F6, R3" + } + } + } + } + }, + { + "address": 18726, + "address_region": "program_or_external", + "bytes": "1EF52B", + "text": "BSR loc_3E54", + "mnemonic": "BSR", + "operands": "loc_3E54", + "kind": "call", + "targets": [ + 15956 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18709, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:AND.W" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": true, + "value": 128, + "hex": "0x80", + "width": 8, + "source": "MOV:E.B #H'80, R2" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": true, + "value": 246, + "hex": "0x00F6", + "width": 16, + "source": "MOV:I.W #H'00F6, R3" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 18729, + "address_region": "program_or_external", + "bytes": "15F76EF6", + "text": "BTST.B #6, @H'F76E", + "mnemonic": "BTST.B", + "operands": "#6, @H'F76E", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63342, + "name": null, + "symbol": "ram_F76E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18729, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 18733, + "address_region": "program_or_external", + "bytes": "260E", + "text": "BNE loc_493D", + "mnemonic": "BNE", + "operands": "loc_493D", + "kind": "branch", + "targets": [ + 18749 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18729, + "changes": [], + "notes": [] + } + }, + { + "address": 18735, + "address_region": "program_or_external", + "bytes": "15F73280", + "text": "MOV:G.B @H'F732, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F732, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63282, + "name": null, + "symbol": "ram_F732", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 18739, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 18741, + "address_region": "program_or_external", + "bytes": "A01A", + "text": "SHLL.B R0", + "mnemonic": "SHLL.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 18743, + "address_region": "program_or_external", + "bytes": "F8493E80", + "text": "MOV:G.W @(H'493E,R0), R0", + "mnemonic": "MOV:G.W", + "operands": "@(H'493E,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 18747, + "address_region": "program_or_external", + "bytes": "11D8", + "text": "JSR @R0", + "mnemonic": "JSR", + "operands": "@R0", + "kind": "call", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 1, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 3, + "entry_address": 18756, + "target": 25292, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 4, + "entry_address": 18758, + "target": 25268, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 5, + "entry_address": 18760, + "target": 25248, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 6, + "entry_address": 18762, + "target": 25224, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 7, + "entry_address": 18764, + "target": 25205, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 18766, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 9, + "entry_address": 18768, + "target": 33086, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 10, + "entry_address": 18770, + "target": 33062, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 11, + "entry_address": 18772, + "target": 33042, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 12, + "entry_address": 18774, + "target": 33022, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (1/52 decoded targets)" + }, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 18749, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": 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"base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22775, + "changes": [], + "notes": [] + } + }, + { + "address": 22890, + "address_region": "program_or_external", + "bytes": "4000", + "text": "CMP:E #H'00, R0", + "mnemonic": "CMP:E", + "operands": "#H'00, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22890, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 22892, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_5978", + "mnemonic": "BEQ", + "operands": "loc_5978", + "kind": "branch", + "targets": [ + 22904 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22890, + "changes": [], + "notes": [] + } + }, + { + "address": 22894, + "address_region": "program_or_external", + "bytes": "4001", + "text": "CMP:E #H'01, R0", + "mnemonic": "CMP:E", + "operands": "#H'01, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22894, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 22896, + "address_region": "program_or_external", + "bytes": "270B", + "text": "BEQ loc_597D", + "mnemonic": "BEQ", + "operands": "loc_597D", + "kind": "branch", + "targets": [ + 22909 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22894, + "changes": [], + "notes": [] + } + }, + { + "address": 22898, + "address_region": "program_or_external", + "bytes": "4002", + "text": "CMP:E #H'02, R0", + "mnemonic": "CMP:E", + "operands": "#H'02, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22898, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 22900, + "address_region": "program_or_external", + "bytes": "270C", + "text": "BEQ loc_5982", + "mnemonic": "BEQ", + "operands": "loc_5982", + "kind": "branch", + "targets": [ + 22914 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22898, + "changes": [], + "notes": [] + } + }, + { + "address": 22902, + "address_region": "program_or_external", + "bytes": "200F", + "text": "BRA loc_5987", + "mnemonic": "BRA", + "operands": "loc_5987", + "kind": "jump", + "targets": [ + 22919 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22902, + "changes": [], + "notes": [] + } + }, + { + "address": 22904, + "address_region": "program_or_external", + "bytes": "5C0083", + "text": "MOV:I.W #H'0083, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0083, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + 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tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22904, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 131, + "hex": "0x0083", + "width": 16, + "source": "MOV:I.W #H'0083, R4" + } + } + } + } + }, + { + "address": 22909, + "address_region": "program_or_external", + "bytes": "5C00C3", + "text": "MOV:I.W #H'00C3, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'00C3, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22909, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + 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"changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 195, + "hex": "0x00C3", + "width": 16, + "source": "MOV:I.W #H'00C3, R4" + } + } + } + } + }, + { + "address": 22914, + "address_region": "program_or_external", + "bytes": "5C0093", + "text": "MOV:I.W #H'0093, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0093, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22914, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0093" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + } + } + } + }, + { + "address": 22917, + "address_region": "program_or_external", + "bytes": "2003", + "text": "BRA loc_598A", + "mnemonic": "BRA", + "operands": "loc_598A", + "kind": "jump", + "targets": [ + 22922 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22914, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + } + } + } + }, + { + "address": 22919, + "address_region": "program_or_external", + "bytes": "5C00D3", + "text": "MOV:I.W #H'00D3, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'00D3, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22919, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 211, + "hex": "0x00D3", + "width": 16, + "source": "MOV:I.W #H'00D3, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x00D3" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 211, + "hex": "0x00D3", + "width": 16, + "source": "MOV:I.W #H'00D3, R4" + } + } + } + } + }, + { + "address": 22922, + "address_region": "program_or_external", + "bytes": "15F75B24", + "text": "ADD:G.B @H'F75B, R4", + "mnemonic": "ADD:G.B", + "operands": "@H'F75B, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63323, + "name": null, + "symbol": "ram_F75B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 22926, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 22929, + "address_region": "program_or_external", + "bytes": "1EE538", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" 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"known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 22932, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [], + "notes": [] + } + }, + { + "address": 23162, + "address_region": "program_or_external", + "bytes": "15F72616", + "text": "TST.B @H'F726", + "mnemonic": "TST.B", + "operands": "@H'F726", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables 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"register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 37660, + "hex": "0x931C", + "width": 16, + "source": "MOV:I.W #H'931C, R3" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 = 0x931C" + ], + "known_after": { + "registers": { + "R3": { + "known": true, + "value": 37660, + "hex": "0x931C", + "width": 16, + "source": "MOV:I.W #H'931C, R3" + } + } + } + } + }, + { + "address": 37645, + "address_region": "program_or_external", + "bytes": "5404", + "text": "MOV:E.B #H'04, R4", + "mnemonic": "MOV:E.B", + "operands": "#H'04, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37642, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x04", + "width": 8, + "source": "MOV:E.B #H'04, R4" + } + } + ], + "notes": [ + "R4 = 0x04" + ], + "known_after": { + "registers": { + "R3": { + "known": true, + "value": 37660, + "hex": "0x931C", + "width": 16, + "source": "MOV:I.W #H'931C, R3" + }, + "R4": { + "known": true, + "value": 4, + "hex": "0x04", + "width": 8, + "source": "MOV:E.B #H'04, R4" + } + } + } + } + }, + { + "address": 37647, + "address_region": "program_or_external", + "bytes": "1ECCC0", + "text": "BSR loc_5FD2", + "mnemonic": "BSR", + "operands": "loc_5FD2", + "kind": "call", + "targets": [ + 24530 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37642, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": true, + "value": 37660, + "hex": "0x931C", + "width": 16, + "source": "MOV:I.W #H'931C, R3" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 4, + "hex": "0x04", + "width": 8, + "source": "MOV:E.B #H'04, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 37650, + "address_region": "program_or_external", + "bytes": "FC931C84", + "text": "MOV:G.W @(-H'6CE4,R4), R4", + "mnemonic": "MOV:G.W", + "operands": "@(-H'6CE4,R4), R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37642, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 37654, + "address_region": "program_or_external", + "bytes": "11DC", + "text": "JSR @R4", + "mnemonic": "JSR", + "operands": "@R4", + "kind": "call", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 37654, + "instruction": "JSR @R4", + "kind": "call", + "target_register": "R4", + "confidence": "unknown", + "summary": "JSR @R4 uses R4; target not resolved" + }, + "dataflow": { + "block": 37642, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 37656, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 37642, + "changes": [], + "notes": [] + } + }, + { + "address": 47654, + "address_region": "program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47654, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47658, + "address_region": "program_or_external", + "bytes": "26FA", + "text": "BNE loc_BA26", + "mnemonic": "BNE", + "operands": "loc_BA26", + "kind": "branch", + "targets": [ + 47654 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47654, + "changes": [], + "notes": [] + } + }, + { + "address": 47660, + "address_region": "program_or_external", + "bytes": "15F9C00664", + "text": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'64, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47665, + "address_region": "program_or_external", + "bytes": "15F9C40607", + "text": "MOV:G.B #H'07, @H'F9C4", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @H'F9C4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63940, + "name": null, + "symbol": "ram_F9C4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47670, + "address_region": "program_or_external", + "bytes": "1DF85080", + "text": "MOV:G.W @H'F850, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F850, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47674, + "address_region": "program_or_external", + "bytes": "1DF85890", + "text": "MOV:G.W R0, @H'F858", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F858", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47674, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47678, + "address_region": "program_or_external", + "bytes": "1DF85280", + "text": "MOV:G.W @H'F852, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F852, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47682, + "address_region": "program_or_external", + "bytes": "1DF85A90", + "text": "MOV:G.W R0, @H'F85A", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F85A", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47682, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47686, + "address_region": "program_or_external", + "bytes": "15F85480", + "text": "MOV:G.B @H'F854, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F854, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47690, + "address_region": "program_or_external", + "bytes": "15F85C90", + "text": "MOV:G.B R0, @H'F85C", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85C", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47690, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47694, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47694, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_checksum_seed", + "evidence_summary": "candidate TX checksum starts from seed H'005A", + "evidence_addresses": [ + 47694 + ], + "evidence_addresses_hex": [ + "H'BA4E" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 47696, + "address_region": "program_or_external", + "bytes": "15F85860", + "text": "XOR.B @H'F858, R0", + "mnemonic": "XOR.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47700, + "address_region": "program_or_external", + "bytes": "15F85960", + "text": "XOR.B @H'F859, R0", + "mnemonic": "XOR.B", + "operands": "@H'F859, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63577, + "name": null, + "symbol": "ram_F859", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47704, + "address_region": "program_or_external", + "bytes": "15F85A60", + "text": "XOR.B @H'F85A, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47708, + "address_region": "program_or_external", + "bytes": "15F85B60", + "text": "XOR.B @H'F85B, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85B, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63579, + "name": null, + "symbol": "ram_F85B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47712, + "address_region": "program_or_external", + "bytes": "15F85C60", + "text": "XOR.B @H'F85C, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47716, + "address_region": "program_or_external", + "bytes": "15F85D90", + "text": "MOV:G.B R0, @H'F85D", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85D", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63581, + "name": null, + "symbol": "ram_F85D", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "checksum_byte", + "evidence_summary": "candidate checksum byte write targets H'F85D", + "evidence_addresses": [ + 47716 + ], + "evidence_addresses_hex": [ + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47720, + "address_region": "program_or_external", + "bytes": "15FEDCF7", + "text": "BTST.B #7, @SCI1_SSR", + "mnemonic": "BTST.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + } + ], + "board_profile": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47720, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47724, + "address_region": "program_or_external", + "bytes": "27FA", + "text": "BEQ loc_BA68", + "mnemonic": "BEQ", + "operands": "loc_BA68", + "kind": "branch", + "targets": [ + 47720 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + } + ], + "dataflow": { + "block": 47720, + "changes": [], + "notes": [] + } + }, + { + "address": 47726, + "address_region": "program_or_external", + "bytes": "15F85880", + "text": "MOV:G.B @H'F858, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47730, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47730, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47734, + "address_region": "program_or_external", + "bytes": "15F9C20601", + "text": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47734, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_initialized_to_one", + "evidence_summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "evidence_addresses": [ + 47734 + ], + "evidence_addresses_hex": [ + "H'BA76" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47739, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47743, + "address_region": "program_or_external", + "bytes": "15FEDAC7", + "text": "BSET.B #7, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + } + ] + }, + "sci_protocol": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47747, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47748, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47752, + "address_region": "program_or_external", + "bytes": "271F", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [], + "notes": [] + } + }, + { + "address": 47754, + "address_region": "program_or_external", + "bytes": "15FAA5F7", + "text": "BTST.B #7, @H'FAA5", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64165, + "name": null, + "symbol": "ram_FAA5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47758, + "address_region": "program_or_external", + "bytes": "2719", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [], + "notes": [] + } + }, + { + "address": 47760, + "address_region": "program_or_external", + "bytes": "15F9C316", + "text": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47764, + "address_region": "program_or_external", + "bytes": "2713", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [], + "notes": [] + } + }, + { + "address": 47766, + "address_region": "program_or_external", + "bytes": "15FAA2D3", + "text": "BCLR.B #3, @H'FAA2", + "mnemonic": "BCLR.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47770, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47774, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47778, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47783, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BAF1", + "mnemonic": "BRA", + "operands": "loc_BAF1", + "kind": "jump", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47785, + "address_region": "program_or_external", + "bytes": "BF90", + "text": "MOV:G.W R0, @-R7", + "mnemonic": "MOV:G.W", + "operands": "R0, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47787, + "address_region": "program_or_external", + "bytes": "15F9C280", + "text": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47787, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47791, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47793, + "address_region": "program_or_external", + "bytes": "F0F85880", + "text": "MOV:G.B @(-H'07A8,R0), R0", + "mnemonic": "MOV:G.B", + "operands": "@(-H'07A8,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47793, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47797, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47797, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47801, + "address_region": "program_or_external", + "bytes": "CF80", + "text": "MOV:G.W @R7+, R0", + "mnemonic": "MOV:G.W", + "operands": "@R7+, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47803, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47807, + "address_region": "program_or_external", + "bytes": "15F9C208", + "text": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47807, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_increment", + "evidence_summary": "candidate TX ISR increments TX index H'F9C2", + "evidence_addresses": [ + 47807 + ], + "evidence_addresses_hex": [ + "H'BABF" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47811, + "address_region": "program_or_external", + "bytes": "15F9C20406", + "text": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47811, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_compare_frame_length", + "evidence_summary": "candidate TX ISR compares TX index to frame length 6", + "evidence_addresses": [ + 47811 + ], + "evidence_addresses_hex": [ + "H'BAC3" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47816, + "address_region": "program_or_external", + "bytes": "2627", + "text": "BNE loc_BAF1", + "mnemonic": "BNE", + "operands": "loc_BAF1", + "kind": "branch", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47818, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47818, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47822, + "address_region": "program_or_external", + "bytes": "15F795F6", + "text": "BTST.B #6, @H'F795", + "mnemonic": "BTST.B", + "operands": "#6, @H'F795", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63381, + "name": null, + "symbol": "ram_F795", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47826, + "address_region": "program_or_external", + "bytes": "2614", + "text": "BNE loc_BAE8", + "mnemonic": "BNE", + "operands": "loc_BAE8", + "kind": "branch", + "targets": [ + 47848 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47828, + "address_region": "program_or_external", + "bytes": "15F791F7", + "text": "BTST.B #7, @H'F791", + "mnemonic": "BTST.B", + "operands": "#7, @H'F791", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63377, + "name": null, + "symbol": "ram_F791", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47832, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_BAE1", + "mnemonic": "BNE", + "operands": "loc_BAE1", + "kind": "branch", + "targets": [ + 47841 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [], + "notes": [] + } + }, + { + "address": 47834, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47839, + "address_region": "program_or_external", + "bytes": "200C", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [], + "notes": [] + } + }, + { + "address": 47841, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47846, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [], + "notes": [] + } + }, + { + "address": 47848, + "address_region": "program_or_external", + "bytes": "15F9C006F0", + "text": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47848, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47853, + "address_region": "program_or_external", + "bytes": "15F9C113", + "text": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47853, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47857, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47857, + "changes": [], + "notes": [] + } + }, + { + "address": 47858, + "address_region": "program_or_external", + "bytes": "15F9B581", + "text": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9B5, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 47862, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47864, + "address_region": "program_or_external", + "bytes": "15F9B071", + "text": "CMP:G.B @H'F9B0, R1", + "mnemonic": "CMP:G.B", + "operands": "@H'F9B0, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63920, + "name": null, + "symbol": "ram_F9B0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [], + "notes": [] + } + }, + { + "address": 47868, + "address_region": "program_or_external", + "bytes": "2602", + "text": "BNE loc_BB00", + "mnemonic": "BNE", + "operands": "loc_BB00", + "kind": "branch", + "targets": [ + 47872 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [], + "notes": [] + } + }, + { + "address": 47870, + "address_region": "program_or_external", + "bytes": "2056", + "text": "BRA loc_BB56", + "mnemonic": "BRA", + "operands": "loc_BB56", + "kind": "jump", + "targets": [ + 47958 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47870, + "changes": [], + "notes": [] + } + }, + { + "address": 47872, + "address_region": "program_or_external", + "bytes": "15FAA2C3", + "text": "BSET.B #3, @H'FAA2", + "mnemonic": "BSET.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47876, + "address_region": "program_or_external", + "bytes": "A980", + "text": "MOV:G.W R1, R0", + "mnemonic": "MOV:G.W", + "operands": "R1, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R0 unknown after MOV source" + ] + } + }, + { + "address": 47878, + "address_region": "program_or_external", + "bytes": "A81A", + "text": "SHLL.W R0", + "mnemonic": "SHLL.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47880, + "address_region": "program_or_external", + "bytes": "F8F87080", + "text": "MOV:G.W @(-H'0790,R0), R0", + "mnemonic": "MOV:G.W", + "operands": "@(-H'0790,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.W" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47884, + "address_region": "program_or_external", + "bytes": "A885", + "text": "MOV:G.W R0, R5", + "mnemonic": "MOV:G.W", + "operands": "R0, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R5 unknown after MOV source" + ] + } + }, + { + "address": 47886, + "address_region": "program_or_external", + "bytes": "1EA6F5", + "text": "BSR loc_6206", + "mnemonic": "BSR", + "operands": "loc_6206", + "kind": "call", + "targets": [ + 25094 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 47889, + "address_region": "program_or_external", + "bytes": "A881", + "text": "MOV:G.W R0, R1", + "mnemonic": "MOV:G.W", + "operands": "R0, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after MOV source" + ] + } + }, + { + "address": 47891, + "address_region": "program_or_external", + "bytes": "A110", + "text": "SWAP.B R1", + "mnemonic": "SWAP.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47893, + "address_region": "program_or_external", + "bytes": "A11B", + "text": "SHLR.B R1", + "mnemonic": "SHLR.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "unsupported:SHLR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47895, + "address_region": "program_or_external", + "bytes": "A182", + "text": "MOV:G.B R1, R2", + "mnemonic": "MOV:G.B", + "operands": "R1, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R2 unknown after MOV source" + ] + } + }, + { + "address": 47897, + "address_region": "program_or_external", + "bytes": "040751", + "text": "AND.B #H'07, R1", + "mnemonic": "AND.B", + "operands": "#H'07, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:SHLR.B" + }, + "after": { + "known": false, + "reason": "unsupported:AND.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 47900, + "address_region": "program_or_external", + "bytes": "15F85091", + "text": "MOV:G.B R1, @H'F850", + "mnemonic": "MOV:G.B", + "operands": "R1, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47904, + "address_region": "program_or_external", + "bytes": "15F85295", + "text": "MOV:G.B R5, @H'F852", + "mnemonic": "MOV:G.B", + "operands": "R5, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47908, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 47910, + "address_region": "program_or_external", + "bytes": "047852", + "text": "AND.B #H'78, R2", + "mnemonic": "AND.B", + "operands": "#H'78, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:AND.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R2" + ] + } + }, + { + "address": 47913, + "address_region": "program_or_external", + "bytes": "A245", + "text": "OR.B R2, R5", + "mnemonic": "OR.B", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "unsupported:OR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 47915, + "address_region": "program_or_external", + "bytes": "15F85195", + "text": "MOV:G.B R5, @H'F851", + "mnemonic": "MOV:G.B", + "operands": "R5, @H'F851", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63569, + "name": null, + "symbol": "ram_F851", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47919, + "address_region": "program_or_external", + "bytes": "0C01FF50", + "text": "AND.W #H'01FF, R0", + "mnemonic": "AND.W", + "operands": "#H'01FF, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:AND.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47923, + "address_region": "program_or_external", + "bytes": "A81A", + "text": "SHLL.W R0", + "mnemonic": "SHLL.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:AND.W" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47925, + "address_region": "program_or_external", + "bytes": "F8E80084", + "text": "MOV:G.W @(-H'1800,R0), R4", + "mnemonic": "MOV:G.W", + "operands": "@(-H'1800,R0), R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 47929, + "address_region": "program_or_external", + "bytes": "15F85494", + "text": "MOV:G.B R4, @H'F854", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47933, + "address_region": "program_or_external", + "bytes": "A410", + "text": "SWAP.B R4", + "mnemonic": "SWAP.B", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 47935, + "address_region": "program_or_external", + "bytes": "15F85394", + "text": "MOV:G.B R4, @H'F853", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F853", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63571, + "name": null, + "symbol": "ram_F853", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47939, + "address_region": "program_or_external", + "bytes": "1EFEE0", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.W" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:OR.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 47942, + "address_region": "program_or_external", + "bytes": "1DF9C60701F4", + "text": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "operands": "#H'01F4, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47948, + "address_region": "program_or_external", + "bytes": "15F9C80614", + "text": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47953, + "address_region": "program_or_external", + "bytes": "15FAA30680", + "text": "MOV:G.B #H'80, @H'FAA3", + "mnemonic": "MOV:G.B", + "operands": "#H'80, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47958, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47958, + "changes": [], + "notes": [] + } + }, + { + "address": 47959, + "address_region": "program_or_external", + "bytes": "15FAA4C7", + "text": "BSET.B #7, @H'FAA4", + "mnemonic": "BSET.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47959, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "dataflow": { + "block": 47959, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47963, + "address_region": "program_or_external", + "bytes": "15FEDCD5", + "text": "BCLR.B #5, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#5, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear ORER (bit 5) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + } + ], + "serial_reconstruction": [ + { + "address": 47963, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47967, + "address_region": "program_or_external", + "bytes": "15FEDCD4", + "text": "BCLR.B #4, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#4, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear FER (bit 4) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + } + ], + "serial_reconstruction": [ + { + "address": 47967, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47971, + "address_region": "program_or_external", + "bytes": "15FEDCD3", + "text": "BCLR.B #3, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#3, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear PER (bit 3) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + } + ], + "serial_reconstruction": [ + { + "address": 47971, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47975, + "address_region": "program_or_external", + "bytes": "1203", + "text": "STM.W {R0,R1}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R1}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47977, + "address_region": "program_or_external", + "bytes": "15FEDCD6", + "text": "BCLR.B #6, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#6, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear RDRF (bit 6) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + } + ], + "serial_reconstruction": [ + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47981, + "address_region": "program_or_external", + "bytes": "15FEDD80", + "text": "MOV:G.B @SCI1_RDR, R0", + "mnemonic": "MOV:G.B", + "operands": "@SCI1_RDR, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65245, + "name": "SCI1_RDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdr_read", + "evidence_summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "evidence_addresses": [ + 47981 + ], + "evidence_addresses_hex": [ + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47985, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47989, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BB7D", + "mnemonic": "BNE", + "operands": "loc_BB7D", + "kind": "branch", + "targets": [ + 47997 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47991, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47995, + "address_region": "program_or_external", + "bytes": "200D", + "text": "BRA loc_BB8A", + "mnemonic": "BRA", + "operands": "loc_BB8A", + "kind": "jump", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [], + "notes": [] + } + }, + { + "address": 47997, + "address_region": "program_or_external", + "bytes": "15F9C30405", + "text": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'05, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48002, + "address_region": "program_or_external", + "bytes": "2306", + "text": "BLS loc_BB8A", + "mnemonic": "BLS", + "operands": "loc_BB8A", + "kind": "branch", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [], + "notes": [] + } + }, + { + "address": 48004, + "address_region": "program_or_external", + "bytes": "15FAA413", + "text": "CLR.B @H'FAA4", + "mnemonic": "CLR.B", + "operands": "@H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48008, + "address_region": "program_or_external", + "bytes": "2019", + "text": "BRA loc_BBA3", + "mnemonic": "BRA", + "operands": "loc_BBA3", + "kind": "jump", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [], + "notes": [] + } + }, + { + "address": 48010, + "address_region": "program_or_external", + "bytes": "15F9C381", + "text": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C3, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 48014, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 48016, + "address_region": "program_or_external", + "bytes": "F1F86890", + "text": "MOV:G.B R0, @(-H'0798,R1)", + "mnemonic": "MOV:G.B", + "operands": "R0, @(-H'0798,R1)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48016, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_indexed_store", + "evidence_summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "evidence_addresses": [ + 48016 + ], + "evidence_addresses_hex": [ + "H'BB90" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48020, + "address_region": "program_or_external", + "bytes": "A108", + "text": "ADD:Q.B #1, R1", + "mnemonic": "ADD:Q.B", + "operands": "#1, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48020, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 48022, + "address_region": "program_or_external", + "bytes": "15F9C391", + "text": "MOV:G.B R1, @H'F9C3", + "mnemonic": "MOV:G.B", + "operands": "R1, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48022, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48026, + "address_region": "program_or_external", + "bytes": "4106", + "text": "CMP:E #H'06, R1", + "mnemonic": "CMP:E", + "operands": "#H'06, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48026, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_isr_compare_frame_length", + "evidence_summary": "RX ISR compares incremented count to candidate frame length 6", + "evidence_addresses": [ + 48026 + ], + "evidence_addresses_hex": [ + "H'BB9A" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48028, + "address_region": "program_or_external", + "bytes": "2605", + "text": "BNE loc_BBA3", + "mnemonic": "BNE", + "operands": "loc_BBA3", + "kind": "branch", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48030, + "address_region": "program_or_external", + "bytes": "15F9C50614", + "text": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48030, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_complete_timer", + "evidence_summary": "RX ISR sets H'F9C5 after count reaches 6", + "evidence_addresses": [ + 48030 + ], + "evidence_addresses_hex": [ + "H'BB9E" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high" + } + ], + "dataflow": { + "block": 48030, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48035, + "address_region": "program_or_external", + "bytes": "15F9C10605", + "text": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "operands": "#H'05, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48040, + "address_region": "program_or_external", + "bytes": "0203", + "text": "LDM.W @SP+, {R0,R1}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R1}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R1" + ] + } + }, + { + "address": 48042, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [], + "notes": [] + } + }, + { + "address": 48043, + "address_region": "program_or_external", + "bytes": "15F9C30406", + "text": "CMP:G.B #H'06, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48043, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_processor_requires_six_bytes", + "evidence_summary": "RX processing path requires H'F9C3 to equal 6", + "evidence_addresses": [ + 48043 + ], + "evidence_addresses_hex": [ + "H'BBAB" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high" + } + ], + "dataflow": { + "block": 48043, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48048, + "address_region": "program_or_external", + "bytes": "3602BC", + "text": "BNE loc_BE6F", + "mnemonic": "BNE", + "operands": "loc_BE6F", + "kind": "branch", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48043, + "changes": [], + "notes": [] + } + }, + { + "address": 48051, + "address_region": "program_or_external", + "bytes": "1DF86880", + "text": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F868, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63592, + "name": null, + "symbol": "ram_F868", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48051, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48055, + "address_region": "program_or_external", + "bytes": "1DF86090", + "text": "MOV:G.W R0, @H'F860", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F860", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48055, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48059, + "address_region": "program_or_external", + "bytes": "1DF86A80", + "text": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63594, + "name": null, + "symbol": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48059, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48063, + "address_region": "program_or_external", + "bytes": "1DF86290", + "text": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F862", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48063, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48067, + "address_region": "program_or_external", + "bytes": "1DF86C80", + "text": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63596, + "name": null, + "symbol": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48067, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48071, + "address_region": "program_or_external", + "bytes": "1DF86490", + "text": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F864", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48071, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48075, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48079, + "address_region": "program_or_external", + "bytes": "15FAA4F7", + "text": "BTST.B #7, @H'FAA4", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48083, + "address_region": "program_or_external", + "bytes": "360253", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48086, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_checksum_seed", + "evidence_summary": "candidate RX checksum validation starts from seed H'005A", + "evidence_addresses": [ + 48086 + ], + "evidence_addresses_hex": [ + "H'BBD6" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high" + }, + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 48088, + "address_region": "program_or_external", + "bytes": "15F86060", + "text": "XOR.B @H'F860, R0", + "mnemonic": "XOR.B", + "operands": "@H'F860, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48088, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48092, + "address_region": "program_or_external", + "bytes": "15F86160", + "text": "XOR.B @H'F861, R0", + "mnemonic": "XOR.B", + "operands": "@H'F861, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48092, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48096, + "address_region": "program_or_external", + "bytes": "15F86260", + "text": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "operands": "@H'F862, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48096, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48100, + "address_region": "program_or_external", + "bytes": "15F86360", + "text": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "operands": "@H'F863, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63587, + "name": null, + "symbol": "ram_F863", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48100, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48104, + "address_region": "program_or_external", + "bytes": "15F86460", + "text": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "operands": "@H'F864, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48104, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48108, + "address_region": "program_or_external", + "bytes": "15F86570", + "text": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "operands": "@H'F865, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63589, + "name": null, + "symbol": "ram_F865", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48108, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48112, + "address_region": "program_or_external", + "bytes": "360236", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48115, + "address_region": "program_or_external", + "bytes": "15FAA613", + "text": "CLR.B @H'FAA6", + "mnemonic": "CLR.B", + "operands": "@H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48119, + "address_region": "program_or_external", + "bytes": "15F86185", + "text": "MOV:G.B @H'F861, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F861, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48123, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 48125, + "address_region": "program_or_external", + "bytes": "15F86285", + "text": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F862, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48129, + "address_region": "program_or_external", + "bytes": "1EA627", + "text": "BSR loc_622B", + "mnemonic": "BSR", + "operands": "loc_622B", + "kind": "call", + "targets": [ + 25131 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48132, + "address_region": "program_or_external", + "bytes": "AD84", + "text": "MOV:G.W R5, R4", + "mnemonic": "MOV:G.W", + "operands": "R5, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after MOV source" + ] + } + }, + { + "address": 48134, + "address_region": "program_or_external", + "bytes": "AC1A", + "text": "SHLL.W R4", + "mnemonic": "SHLL.W", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 48136, + "address_region": "program_or_external", + "bytes": "15F86080", + "text": "MOV:G.B @H'F860, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F860, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48140, + "address_region": "program_or_external", + "bytes": "040750", + "text": "AND.B #H'07, R0", + "mnemonic": "AND.B", + "operands": "#H'07, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:AND.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48143, + "address_region": "program_or_external", + "bytes": "15FAA216", + "text": "TST.B @H'FAA2", + "mnemonic": "TST.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [], + "notes": [] + } + }, + { + "address": 48147, + "address_region": "program_or_external", + "bytes": "2625", + "text": "BNE loc_BC3A", + "mnemonic": "BNE", + "operands": "loc_BC3A", + "kind": "branch", + "targets": [ + 48186 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [], + "notes": [] + } + }, + { + "address": 48149, + "address_region": "program_or_external", + "bytes": "15FAA2C7", + "text": "BSET.B #7, @H'FAA2", + "mnemonic": "BSET.B", + "operands": "#7, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48149, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48153, + "address_region": "program_or_external", + "bytes": "15F861F7", + "text": "BTST.B #7, @H'F861", + "mnemonic": "BTST.B", + "operands": "#7, @H'F861", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48149, + "changes": [], + "notes": [] + } + }, + { + "address": 48157, + "address_region": "program_or_external", + "bytes": "3600EB", + "text": "BNE loc_BD0B", + "mnemonic": "BNE", + "operands": "loc_BD0B", + "kind": "branch", + "targets": [ + 48395 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48149, + "changes": [], + "notes": [] + } + }, + { + "address": 48160, + "address_region": "program_or_external", + "bytes": "4000", + "text": "CMP:E #H'00, R0", + "mnemonic": "CMP:E", + "operands": "#H'00, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48160, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + 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instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48625, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_BDFB", + "mnemonic": "BEQ", + "operands": "loc_BDFB", + "kind": "branch", + "targets": [ + 48635 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48627, + "address_region": "program_or_external", + "bytes": "15F9B508", + "text": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48631, + "address_region": "program_or_external", + "bytes": "15F9B5D7", + "text": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [], + "notes": [] + } + }, + { + "address": 48635, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48639, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48643, + "address_region": "program_or_external", + "bytes": "206A", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48645, + "address_region": "program_or_external", + "bytes": "1DF85880", + "text": "MOV:G.W @H'F858, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48645, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48649, + "address_region": "program_or_external", + "bytes": "1DF85090", + "text": "MOV:G.W R0, @H'F850", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48653, + "address_region": "program_or_external", + "bytes": "1DF85A80", + "text": "MOV:G.W @H'F85A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48653, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48657, + "address_region": "program_or_external", + "bytes": "1DF85290", + "text": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48661, + "address_region": "program_or_external", + "bytes": "1DF85C80", + "text": "MOV:G.W @H'F85C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48661, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48665, + "address_region": "program_or_external", + "bytes": "1DF85490", + "text": "MOV:G.W R0, @H'F854", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48669, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48674, + "address_region": "program_or_external", + "bytes": "1EFC01", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48677, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48679, + "address_region": "program_or_external", + "bytes": "2046", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48679, + "changes": [], + "notes": [] + } + }, + { + "address": 48681, + "address_region": "program_or_external", + "bytes": "15FAA4D7", + "text": "BCLR.B #7, @H'FAA4", + "mnemonic": "BCLR.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": 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"BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48856, + "address_region": "program_or_external", + "bytes": "200E", + "text": "BRA loc_BEE8", + "mnemonic": "BRA", + "operands": "loc_BEE8", + "kind": "jump", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [], + "notes": [] + } + }, + { + "address": 48868, + "address_region": "program_or_external", + "bytes": "15F9C513", + "text": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "operands": "@H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48868, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48872, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48872, + "changes": [], + "notes": [] + } + }, + { + "address": 48874, + "address_region": "program_or_external", + "bytes": "15FE91D5", + "text": "BCLR.B #5, @FRT1_TCSR", + "mnemonic": "BCLR.B", + "operands": "#5, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear OCFA (bit 5) of FRT1_TCSR", + "valid": true, + "serial_reconstruction": [ + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48878, + "address_region": "program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48878, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48882, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BEF8", + "mnemonic": "BEQ", + "operands": "loc_BEF8", + "kind": "branch", + "targets": [ + 48888 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48884, + "address_region": "program_or_external", + "bytes": "15F9C00C", + "text": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48884, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48884, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48888, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48888, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48888, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48892, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF02", + "mnemonic": "BEQ", + "operands": "loc_BF02", + "kind": "branch", + "targets": [ + 48898 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48888, + "changes": [], + "notes": [] + } + }, + { + "address": 48894, + "address_region": "program_or_external", + "bytes": "15F9C10C", + "text": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48894, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48894, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48898, + "address_region": "program_or_external", + "bytes": "1DF9C616", + "text": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "operands": "@H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48898, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48898, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48902, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF0C", + "mnemonic": "BEQ", + "operands": "loc_BF0C", + "kind": "branch", + "targets": [ + 48908 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48898, + "changes": [], + "notes": [] + } + }, + { + "address": 48904, + "address_region": "program_or_external", + "bytes": "1DF9C60C", + "text": "ADD:Q.W #-1, @H'F9C6", + "mnemonic": "ADD:Q.W", + "operands": "#-1, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48904, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48904, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48908, + "address_region": "program_or_external", + "bytes": "15F6F6F7", + "text": "BTST.B #7, @H'F6F6", + "mnemonic": "BTST.B", + "operands": "#7, @H'F6F6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63222, + "name": null, + "symbol": "ram_F6F6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48908, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + 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"BEQ", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49075, + "changes": [], + "notes": [] + } + }, + { + "address": 49081, + "address_region": "program_or_external", + "bytes": "15F7980C", + "text": "ADD:Q.B #-1, @H'F798", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F798", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63384, + "name": null, + "symbol": "ram_F798", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49085, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_BFC3", + "mnemonic": "BNE", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [], + "notes": [] + } + }, + { + "address": 49087, + "address_region": "program_or_external", + "bytes": "15F731D7", + "text": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49087, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49091, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49091, + "changes": [], + "notes": [] + } + }, + { + "address": 49092, + "address_region": "program_or_external", + "bytes": "15FEECF7", + "text": "BTST.B #7, @WDT_TCSR_R", + "mnemonic": "BTST.B", + "operands": "#7, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49096, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49102, + "address_region": "program_or_external", + "bytes": "15F79408", + "text": "ADD:Q.B #1, @H'F794", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49106, + "address_region": "program_or_external", + "bytes": "15F794040A", + "text": "CMP:G.B #H'0A, @H'F794", + "mnemonic": "CMP:G.B", + "operands": "#H'0A, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49111, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BFDF", + "mnemonic": "BNE", + "operands": "loc_BFDF", + "kind": "branch", + "targets": [ + 49119 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49113, + "address_region": "program_or_external", + "bytes": "1DFEEC07A57F", + "text": "MOV:G.W #H'A57F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A57F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49113, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49119, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49119, + "changes": [], + "notes": [] + } + }, + { + "address": 49120, + "address_region": "program_or_external", + "bytes": "15F840060A", + "text": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "operands": "#H'0A, @H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49120, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49125, + "address_region": "program_or_external", + "bytes": "AD82", + "text": "MOV:G.W R5, R2", + "mnemonic": "MOV:G.W", + "operands": "R5, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after MOV source" + ] + } + }, + { + "address": 49127, + "address_region": "program_or_external", + "bytes": "0E27", + "text": "BSR loc_C010", + "mnemonic": "BSR", + "operands": "loc_C010", + "kind": "call", + "targets": [ + 49168 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49129, + "address_region": "program_or_external", + "bytes": "0E4E", + "text": "BSR loc_C039", + "mnemonic": "BSR", + "operands": "loc_C039", + "kind": "call", + "targets": [ + 49209 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49125, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 49131, + "address_region": "program_or_external", + "bytes": "AA75", + "text": "CMP:G.W R2, R5", + "mnemonic": "CMP:G.W", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip 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"bytes": "15F84016", + "text": "TST.B @H'F840", + "mnemonic": "TST.B", + "operands": "@H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49135, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49139, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BFF9", + "mnemonic": "BEQ", + "operands": "loc_BFF9", + "kind": "branch", + "targets": [ + 49145 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49135, + "changes": [], + "notes": [] + } + }, + { + "address": 49141, + "address_region": "program_or_external", + "bytes": "AA85", + "text": "MOV:G.W R2, R5", + "mnemonic": "MOV:G.W", + "operands": "R2, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49141, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + 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"source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49267, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unknown_operand" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 49271, + "address_region": "program_or_external", + "bytes": "A31A", + "text": "SHLL.B R3", + "mnemonic": "SHLL.B", + "operands": "R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49267, + "changes": [ + { + "kind": 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"address": 49291, + "address_region": "program_or_external", + "bytes": "590007", + "text": "MOV:I.W #H'0007, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49291, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R1" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 = 0x0007" + ], + "known_after": { + "registers": { + "R1": { + "known": true, + "value": 7, + "hex": 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"operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49327, + "changes": [], + "notes": [] + } + }, + { + "address": 49340, + "address_region": "program_or_external", + "bytes": "15FEFFF7", + "text": "BTST.B #7, @P9DR", + "mnemonic": "BTST.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + 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"address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49359, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49363, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": 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"address_region": "program_or_external", + "bytes": "15FEFE0613", + "text": "MOV:G.B #H'13, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'13, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'13", + "valid": true, + "dataflow": { + "block": 49371, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49376, + "address_region": "program_or_external", + "bytes": "590007", + "text": "MOV:I.W #H'0007, R1", + "mnemonic": "MOV:I.W", + "operands": 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"base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49383, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + 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"text": "BEQ loc_C0F5", + "mnemonic": "BEQ", + "operands": "loc_C0F5", + "kind": "branch", + "targets": [ + 49397 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [], + "notes": [] + } + }, + { + "address": 49393, + "address_region": "program_or_external", + "bytes": "A549", + "text": "BSET.B R1, R5", + "mnemonic": "BSET.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49393, + "changes": [ + { + "kind": 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"address": 49397, + "address_region": "program_or_external", + "bytes": "A559", + "text": "BCLR.B R1, R5", + "mnemonic": "BCLR.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49397, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 49399, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": 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"manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49407, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49411, + "address_region": "program_or_external", + "bytes": "01B9DD", + "text": "SCB/F R1, loc_C0E3", + "mnemonic": "SCB/F", + "operands": "R1, loc_C0E3", + "kind": "branch", + "targets": [ + 49379 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49414, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'93", + "valid": true, + "dataflow": { + "block": 49414, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49419, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49414, + "changes": [], + "notes": [] + } + }, + { + "address": 49420, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49424, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49428, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49432, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49436, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49440, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49420, + "changes": [], + "notes": [] + } + }, + { + "address": 49441, + "address_region": "program_or_external", + "bytes": "15FEFFC7", + "text": "BSET.B #7, @P9DR", + "mnemonic": "BSET.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49445, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49449, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49453, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49457, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49461, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49465, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49469, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49473, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49474, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49478, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49482, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49486, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49490, + "address_region": "program_or_external", + "bytes": "15FEFFC7", + "text": "BSET.B #7, @P9DR", + "mnemonic": "BSET.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49494, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49498, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49502, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49506, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + } + ], + "decompiler_consistency": { + "kind": "decompiler_pseudocode_consistency", + "summary": "8 byte-immediate-to-word destination case(s) require explicit zero-extension in pseudocode.", + "checks": [ + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4163, + "address_hex": "H'1043", + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4184, + "address_hex": "H'1058", + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 16487, + "address_hex": "H'4067", + "instruction": "MOV:G.W #H'00, @(-H'0790,R2)", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28924, + "address_hex": "H'70FC", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28935, + "address_hex": "H'7107", + "instruction": "MOV:G.W #H'00, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28946, + "address_hex": "H'7112", + "instruction": "MOV:G.W #H'00, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28951, + "address_hex": "H'7117", + "instruction": "MOV:G.W #H'00, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28956, + "address_hex": "H'711C", + "instruction": "MOV:G.W #H'46, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0046", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + } + ] + }, + "serial_semantics": { + "kind": "serial_semantics", + "protocol_semantics": [ + { + "kind": "serial_semantics", + "scope": "evidence_supported_sci1_6_byte_frame", + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation.", + "frame_candidate": { + "channel": "SCI1", + "rx_frame_start": 63584, + "rx_frame_start_hex": "H'F860", + "rx_frame_end": 63589, + "rx_frame_end_hex": "H'F865", + "tx_staging_start": 63568, + "tx_staging_start_hex": "H'F850", + "tx_staging_end": 63572, + "tx_staging_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "frame_length": 6, + "tx_staging_length": 5, + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "serial_reconstruction_supported": true, + "rx_reconstruction_candidate_id": "sci1_rx_frame_f868_len6_candidate", + "tx_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + "byte_layout": [ + { + "offset": 0, + "rx_address": 63584, + "tx_staging_address": 63568, + "name_candidate": "op_flags", + "semantic": "low three bits select a command; upper bits are preserved or gated in some paths", + "confidence": "medium-high" + }, + { + "offset": 1, + "rx_address": 63585, + "tx_staging_address": 63569, + "name_candidate": "addr_page_flags", + "semantic": "candidate high/page byte for logical point/index; bit 7 is tested as a control flag", + "confidence": "medium" + }, + { + "offset": 2, + "rx_address": 63586, + "tx_staging_address": 63570, + "name_candidate": "addr_offset", + "semantic": "candidate low/offset byte for logical point/index", + "confidence": "medium" + }, + { + "offset": 3, + "rx_address": 63587, + "tx_staging_address": 63571, + "name_candidate": "value_hi", + "semantic": "candidate high byte of a word value", + "confidence": "medium" + }, + { + "offset": 4, + "rx_address": 63588, + "tx_staging_address": 63572, + "name_candidate": "value_lo", + "semantic": "candidate low byte of a word value", + "confidence": "medium" + }, + { + "offset": 5, + "rx_address": 63589, + "tx_staging_address": null, + "name_candidate": "checksum", + "semantic": "0x5A-seeded XOR of bytes 0..4", + "confidence": "high" + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2614 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2646 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2658 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2742 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2661 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2698 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2730 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2742 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "index_decoder": { + "kind": "logical_index_decoder_candidate", + "label": "loc_622B", + "address": 25131, + "address_hex": "H'622B", + "input_fields": [ + "addr_page_flags", + "addr_offset" + ], + "output_register": "R5", + "post_scale_register": "R4", + "post_scale": "R4 = R5 << 1", + "mapping_candidate": [ + { + "page": 0, + "offset_range": "0x00-0x7F", + "index_range": "0x000-0x07F" + }, + { + "page": 1, + "offset_range": "0x00-0xFF", + "index_range": "0x080-0x17F" + }, + { + "page": 2, + "offset_range": "0x00-0x7F", + "index_range": "0x180-0x1FF" + }, + { + "page": "other/overflow", + "index": "0x1FF" + } + ], + "evidence_addresses": [ + 48129 + ], + "evidence_addresses_hex": [ + "H'BC01" + ], + "confidence": "medium", + "caveat": "Mapping is inferred from loc_622B behavior and the nearby R4 = R5 << 1 table-index use." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47841, + "instruction_address_hex": "H'BAE1", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47848, + "instruction_address_hex": "H'BAE8", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "immediate": 240, + "immediate_hex": "H'F0" + }, + { + "instruction_address": 48669, + "instruction_address_hex": "H'BE1D", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48702, + "instruction_address_hex": "H'BE3E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48878, + "instruction_address_hex": "H'BEEE", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "rx_fields": [ + { + "kind": "rx_field_semantic_candidate", + "offset": 0, + "name": "command_low3", + "address": 63584, + "address_hex": "H'F860", + "confidence": "candidate-high", + "caveat": "RX[0] is masked with 0x07 before command comparisons", + "evidence_addresses": [ + 48088, + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "mask": 7, + "mask_hex": "H'07" + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 1, + "name": "likely_id_or_index", + "address": 63585, + "address_hex": "H'F861", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 2, + "name": "likely_id_or_index", + "address": 63586, + "address_hex": "H'F862", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 3, + "name": "likely_value", + "address": 63587, + "address_hex": "H'F863", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 4, + "name": "likely_value", + "address": 63588, + "address_hex": "H'F864", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 5, + "name": "checksum", + "address": 63589, + "address_hex": "H'F865", + "confidence": "candidate-high", + "caveat": "RX[5] is validated by the serial reconstruction checksum evidence", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ] + } + ], + "response_builders": [ + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 47939, + "call_address_hex": "H'BB43", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48674, + "call_address_hex": "H'BE22", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "evidence": [ + { + "kind": "rx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 RX frame candidate", + "candidate_id": "sci1_rx_frame_f868_len6_candidate" + }, + { + "kind": "tx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 TX frame candidate", + "candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + { + "kind": "rx0_masked_command_dispatch", + "summary": "RX[0] is read, masked with 0x07, and compared against command values", + "addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + { + "kind": "responses_stage_f850_f854_before_send", + "summary": "F850-F854 writes are observed before calls to loc_BA26", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378, + 48649, + 48657, + 48665, + 48674, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "response_count": 5 + }, + { + "kind": "bb43_autonomous_tx_report_path", + "summary": "BB43 stages a candidate device-to-host report before loc_BA26; this is separate from RX command dispatch.", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + { + "kind": "rx_payload_bytes_read", + "summary": "RX[1..4] are read in the command-processing region", + "addresses": [ + 48092, + 48096, + 48100, + 48104, + 48119, + 48125, + 48153, + 48190, + 48237, + 48267, + 48273, + 48309, + 48317, + 48325, + 48348, + 48356, + 48402, + 48427, + 48433, + 48603, + 48609, + 48722, + 48730, + 48738 + ], + "addresses_hex": [ + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBF7", + "H'BBFD", + "H'BC19", + "H'BC3E", + "H'BC6D", + "H'BC8B", + "H'BC91", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCDC", + "H'BCE4", + "H'BD12", + "H'BD2B", + "H'BD31", + "H'BDDB", + "H'BDE1", + "H'BE52", + "H'BE5A", + "H'BE62" + ] + } + ] + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2614 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2646 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2658 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2742 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2661 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2698 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2730 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2742 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 24584, + "instruction_address_hex": "H'6008", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "TST.W @(-H'1C00,R1)" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 24584, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'6008", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47841, + "instruction_address_hex": "H'BAE1", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47848, + "instruction_address_hex": "H'BAE8", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "immediate": 240, + "immediate_hex": "H'F0" + }, + { + "instruction_address": 48669, + "instruction_address_hex": "H'BE1D", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48702, + "instruction_address_hex": "H'BE3E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48878, + "instruction_address_hex": "H'BEEE", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation." + } +} \ No newline at end of file diff --git a/build/rom_others_page1.asm b/build/rom_others_page1.asm new file mode 100644 index 0000000..dcb3a97 --- /dev/null +++ b/build/rom_others_page1.asm @@ -0,0 +1,4642 @@ +; H8/536 ROM disassembly +; input: ROM\M27C512@DIP28_1.BIN +; bytes: 65536 +; vector mode: min +; analysis: recursive trace from vectors +; +; Notes from the manual: +; - H8/536 uses the H8/500 CPU instruction set. +; - In minimum mode the reset vector at H'0000-H'0001 is a 16-bit PC. +; - The register field is H'FE80-H'FFFF; names below come from appendix B. +; - @aa:8 short absolute operands use BR as the upper address byte. +; - SCI baud inference uses section 14.2.8 BRR formulas when SMR/BRR are known. +; - LCD inference treats E-clock H'F200/H'F201 accesses as status/control and data candidates. +; - Pass --clock-hz to convert SCI BRR settings into numeric baud rates. +; - Cycle counts use Appendix A tables A-7/A-8 for on-chip access with no external wait states. + +; Memory Map +; H'0000-H'009F exception_vectors vectors +; H'00A0-H'00FF dtc_vectors dtc_vectors +; H'0100-H'F67F program_or_external program +; H'F680-H'FE7F on_chip_ram ram +; H'FE80-H'FFFF register_field registers + +; Vectors +; H'0000 reset -> vec_reset_1000 (H'1000) +; H'0004 invalid_instruction -> vec_reset_1000 (H'1000) +; H'0006 zero_divide -> vec_reset_1000 (H'1000) +; H'0008 trap_vs -> vec_reset_1000 (H'1000) +; H'0010 address_error -> vec_reset_1000 (H'1000) +; H'0012 trace -> vec_reset_1000 (H'1000) +; H'0016 nmi -> vec_nmi_4393 (H'4393) +; H'0020 trapa_0 -> vec_reset_1000 (H'1000) +; H'0022 trapa_1 -> vec_reset_1000 (H'1000) +; H'0024 trapa_2 -> vec_reset_1000 (H'1000) +; H'0026 trapa_3 -> vec_reset_1000 (H'1000) +; H'0028 trapa_4 -> vec_reset_1000 (H'1000) +; H'002A trapa_5 -> vec_reset_1000 (H'1000) +; H'002C trapa_6 -> vec_reset_1000 (H'1000) +; H'002E trapa_7 -> vec_reset_1000 (H'1000) +; H'0030 trapa_8 -> vec_reset_1000 (H'1000) +; H'0032 trapa_9 -> vec_reset_1000 (H'1000) +; H'0034 trapa_a -> vec_reset_1000 (H'1000) +; H'0036 trapa_b -> vec_reset_1000 (H'1000) +; H'0038 trapa_c -> vec_reset_1000 (H'1000) +; H'003A trapa_d -> vec_reset_1000 (H'1000) +; H'003C trapa_e -> vec_reset_1000 (H'1000) +; H'003E trapa_f -> vec_reset_1000 (H'1000) +; H'0040 irq0 -> vec_reset_1000 (H'1000) +; H'0042 interval_timer -> vec_interval_timer_BFC4 (H'BFC4) +; H'0048 irq1 -> vec_reset_1000 (H'1000) +; H'0050 irq2 -> vec_reset_1000 (H'1000) +; H'0052 irq3 -> vec_irq3_3C30 (H'3C30) +; H'0058 irq4 -> vec_irq4_3AC7 (H'3AC7) +; H'005A irq5 -> vec_reset_1000 (H'1000) +; H'0062 frt1_ocia -> vec_frt1_ocia_BEEA (H'BEEA) +; H'006A frt2_ocia -> vec_frt2_ocia_BF23 (H'BF23) +; H'0080 sci1_eri -> vec_sci1_eri_BB57 (H'BB57) +; H'0082 sci1_rxi -> vec_sci1_rxi_BB67 (H'BB67) +; H'0084 sci1_txi -> vec_sci1_txi_BA84 (H'BA84) +; H'0090 ad_adi -> vec_ad_adi_3D99 (H'3D99) + +; Unreached Data Candidates +; string H'2A52 len=11 '78785=5=5=,' +; string H'2BBA len=7 '8*8B8Z8' +; string H'41B2 len=32 '01020304050607080910111213141516' +; string H'57A4 len=7 'Z [ ' +; string H'582A len=6 'Z [ ' +; string H'5B55 len=10 '0123456789' +; string H'5B60 len=40 ' 0 1 2 3 4 5 6 7 8 910111213141516171819' +; string H'60F6 len=16 '0123456789ABCDEF' +; string H'630C len=9 'm*mDm^mxm' +; string H'633E len=6 'vpwhx6' +; string H'63D7 len=10 'OPERATION ' +; string H'63F5 len=10 ' PAINT ' +; string H'6410 len=18 ' ADV~Xd' +; string H'6443 len=10 'OPERATION ' +; string H'6461 len=10 'IRIS/M.BLK' +; string H'6490 len=10 'OPERATION ' +; string H'64AE len=10 ' LOCK ' +; string H'652F len=19 ' DYNA LATITUDE Xe/' +; string H'6551 len=18 'HIGH LOW~XeP' +; string H'6578 len=18 'STD OFF~Xew' +; string H'65C9 len=18 ' BLACK STR Xe' +; string H'6644 len=19 ' BLACK STR XfD' +; string H'6665 len=19 ' STRETCH LEVEL Xfe' +; string H'6683 len=18 'POINT1 POINT2Xf' +; string H'6706 len=18 ' BLACK STR Xg' +; string H'6727 len=19 " COMPRESS LEVEL Xg'" +; string H'6745 len=19 'POINT1 POINT2XgE' +; string H'67E0 len=18 ' TLCS Xg' +; string H'6802 len=17 'ON OFF~Xh' +; string H'681F len=18 ' AGC GAIN AE Xh' +; string H'686A len=136 ' CL F16 F11 F8 F5.6F4 F2.8F2 F1.8F1.4 OP DPR HYP HIGHMID LOW 36dB30dB24dB18dB12dB 9dB 6dB 3dB 0dB-3dB' +; string H'693B len=19 ' AUTO FUNC Xi;' +; string H'695C len=19 ' ATW Xi\\' +; string H'6984 len=17 'ON OFF~Xi' +; string H'6A4F len=19 ' AUTO FUNC XjO' +; string H'6A71 len=18 'STD SPOT.L~Xjp' +; string H'6A8E len=18 ' A.IRIS MODE Xj' +; string H'6AAD len=17 'AI BACK.L~Xj' +; string H'6B3D len=19 ' AUTO FUNC Xk=' +; string H'6B5E len=19 ' AUTO FOCUS Xk^' +; ptrtbl H'1A1E count=4 -> H'F6F8, H'FAFC, H'FDFE, H'FF00 +; ptrtbl H'1EB0 count=4 -> H'F730, H'F727, H'2815, H'F731 +; ptrtbl H'28A8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28B6 count=10 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'28DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'28F2 count=29 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'292E count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'293C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2944 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'294C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2954 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'295C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2964 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'296C count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2974 count=3 -> H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2982 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'29AE count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29B8 count=6 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29DC count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'29FA count=13 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A20 count=8 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2A34 count=15 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A62 count=24 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2A98 count=4 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6 +; ptrtbl H'2AA2 count=18 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2AC8 count=115 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'2BC4 count=113 -> H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6, H'2CA6 ... +; ptrtbl H'33A0 count=3 -> H'FF26, H'11A9, H'F726 +; ptrtbl H'3478 count=3 -> H'F790, H'F727, H'441D +; ptrtbl H'35DC count=3 -> H'FE27, H'1215, H'F717 +; ptrtbl H'4698 count=3 -> H'F750, H'1627, H'10FB +; ptrtbl H'47AE count=3 -> H'F752, H'1627, H'10FB +; ptrtbl H'48AA count=4 -> H'FB03, H'F726, H'1215, H'F6D1 +; ptrtbl H'505A count=3 -> H'1627, H'5515, H'FB03 +; ptrtbl H'62EE count=4 -> H'FCE2, H'FC62, H'FA84, H'11DC +; ptrtbl H'632E count=7 -> H'6EE4, H'6FF0, H'70F6, H'7188, H'7258, H'7328, H'73D8 +; ptrtbl H'74FC count=3 -> H'F772, H'1627, H'12A8 +; ptrtbl H'80F2 count=3 -> H'FC80, H'FC84, H'11DC +; ptrtbl H'9E10 count=3 -> H'FE1E, H'BC7D, H'5500 +; ptrtbl H'B5E0 count=3 -> H'F772, H'1627, H'11A0 + +; Symbols +; mem_1011 H'1011 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_10FB H'10FB program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1161 H'1161 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1170 H'1170 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1179 H'1179 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1188 H'1188 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1197 H'1197 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11A0 H'11A0 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_11A9 H'11A9 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_11DC H'11DC program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1206 H'1206 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1215 H'1215 program_or_external memory r=0 w=0 width=unknown xrefs=3 +; mem_12A8 H'12A8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1314 H'1314 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1617 H'1617 program_or_external memory r=0 w=0 width=unknown xrefs=2 +; mem_1627 H'1627 program_or_external memory r=0 w=0 width=unknown xrefs=6 +; mem_1630 H'1630 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1647 H'1647 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1664 H'1664 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1682 H'1682 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1700 H'1700 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1819 H'1819 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_1A00 H'1A00 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2815 H'2815 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_2CA6 H'2CA6 program_or_external memory r=0 w=0 width=unknown xrefs=429 +; mem_441D H'441D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449C H'449C program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_449E H'449E program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_44A0 H'44A0 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5500 H'5500 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_5515 H'5515 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6EE4 H'6EE4 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_6FF0 H'6FF0 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_70F6 H'70F6 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_7188 H'7188 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_7258 H'7258 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_7328 H'7328 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_73D8 H'73D8 program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_BC7D H'BC7D program_or_external memory r=0 w=0 width=unknown xrefs=1 +; mem_E000 H'E000 program_or_external memory r=0 w=1 width=word +; mem_E004 H'E004 program_or_external memory r=1 w=0 width=word +; mem_E006 H'E006 program_or_external memory r=0 w=1 width=word +; mem_E046 H'E046 program_or_external memory r=0 w=1 width=word +; mem_E080 H'E080 program_or_external memory r=0 w=1 width=word +; mem_E102 H'E102 program_or_external memory r=2 w=0 width=word +; mem_E11E H'E11E program_or_external memory r=2 w=0 width=word +; mem_E124 H'E124 program_or_external memory r=2 w=0 width=word +; mem_E126 H'E126 program_or_external memory r=5 w=0 width=word +; mem_E14E H'E14E program_or_external memory r=1 w=0 width=word +; mem_E16E H'E16E program_or_external memory r=1 w=0 width=word +; mem_E172 H'E172 program_or_external memory r=1 w=0 width=word +; mem_E1EC H'E1EC program_or_external memory r=2 w=0 width=word +; mem_E220 H'E220 program_or_external memory r=1 w=0 width=word +; mem_E51E H'E51E program_or_external memory r=2 w=0 width=word +; mem_E800 H'E800 program_or_external memory r=0 w=1 width=word +; mem_E806 H'E806 program_or_external memory r=0 w=1 width=word +; mem_E880 H'E880 program_or_external memory r=0 w=1 width=word +; mem_E902 H'E902 program_or_external memory r=0 w=1 width=word +; mem_E91E H'E91E program_or_external memory r=0 w=2 width=word +; mem_E924 H'E924 program_or_external memory r=0 w=1 width=word +; mem_E9EC H'E9EC program_or_external memory r=0 w=1 width=word +; mem_F000 H'F000 program_or_external memory r=2 w=0 width=byte +; mem_F001 H'F001 program_or_external memory r=2 w=1 width=byte +; mem_F002 H'F002 program_or_external memory r=2 w=1 width=mixed +; mem_F003 H'F003 program_or_external memory r=1 w=1 width=byte +; mem_F004 H'F004 program_or_external memory r=2 w=1 width=mixed +; mem_F005 H'F005 program_or_external memory r=1 w=1 width=byte +; mem_F006 H'F006 program_or_external memory r=2 w=0 width=mixed +; mem_F007 H'F007 program_or_external memory r=1 w=0 width=byte +; mem_F008 H'F008 program_or_external memory r=2 w=0 width=mixed +; mem_F009 H'F009 program_or_external memory r=1 w=1 width=byte +; mem_F00A H'F00A program_or_external memory r=2 w=1 width=mixed +; mem_F00B H'F00B program_or_external memory r=0 w=1 width=byte +; mem_F00C H'F00C program_or_external memory r=2 w=1 width=mixed +; mem_F00D H'F00D program_or_external memory r=0 w=1 width=byte +; mem_F00E H'F00E program_or_external memory r=0 w=1 width=byte +; mem_F00F H'F00F program_or_external memory r=1 w=1 width=byte +; mem_F100 H'F100 program_or_external memory r=2 w=0 width=byte +; mem_F101 H'F101 program_or_external memory r=2 w=1 width=byte +; mem_F102 H'F102 program_or_external memory r=2 w=1 width=mixed +; ... 241 more symbols omitted from listing header + +; Board Profile +; Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver. +; H8 pin 66 P95/TXD (TXD) -> MAX202 pin 11 +; H8 pin 67 P96/RXD (RXD) -> MAX202 pin 12 +; SCI2 pin routing is disabled by SYSCR2.P9SCI2E=0 in the observed setup. + +; Serial Protocol Reconstruction +; TX candidate: 6 bytes H'F858-H'F85D, checksum H'F85D seeded by H'005A (confidence high 0.95) +; TX path: initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted +; RX candidate: 6 bytes capture H'F868-H'F86D, validate H'F860-H'F865 checksum H'F865 seeded by H'005A (confidence high 0.9) +; caveat: candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet +; Serial RAM role candidates +; H'F9C0: post_tx_report_delay - post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C1: secondary_tx_report_delay - secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it +; H'F9C6: periodic_report_countdown - periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it + +; LCD/Text Scan +; search 'CONNECT': not literal, hits=0 +; near: H'A025 'COMPLETED', H'8E79 'ON CONT1 OFF~X', H'8F55 'ON CONT2 OFF~X', H'94A9 'ON' +; LCD text regions +; region H'63D7-H'6758 count=15 'OPERATION', 'PAINT', 'OPERATION', 'IRIS/M.BLK' +; region H'67E0-H'6831 count=2 'TLCS Xg', 'AGC GAIN AE Xh' +; region H'6A4F-H'6C47 count=8 'AUTO FUNC XjO', 'A.IRIS MODE Xj', 'AI BACK.L~Xj', 'AUTO FUNC Xk=' +; region H'6F84-H'6FC0 count=2 'OTHERS Xo', 'SHUTTER Xo' +; region H'7052-H'7477 count=15 'SET RCP', 'MASTER', 'OTHERS Xp', 'COPY TO SLAVES~Xp' +; region H'757A-H'7824 count=14 'BARS TYPE Xuz', 'SMPTE Xu', 'SPLIT Xu', 'FULLFIELD 75% Xu' +; region H'78B5-H'792F count=4 'OTHERS Xx', 'WHITE BLACK~Xx', 'COMM LINK ITEM-2Xx', 'FLARE Xy' +; region H'819C-H'87A9 count=28 'SHADING X', 'WHITE~X', 'SHADING AUTO SETX', 'BLACK~X' +; region H'883D-H'8959 count=7 'MATRIX X', 'STD FL~X', 'PRESET MATRIX X', 'H.SAT SPCL~X' +; region H'8A0C-H'8BAC count=7 'MATRIX X', 'ON SKIN OFF~X', 'SAT HUE X', 'MATRIX X' +; region H'8CB7-H'8CFD count=2 'FILTER X', '1 2 3 4 X' +; region H'8E57-H'8EA7 count=3 'LENS X', 'ON CONT1 OFF~X', 'FOCUS ZOOM X' +; ... 23 more LCD text regions +; LCD text candidates +; text H'41B0 len=35 medium '01020304050607080910111213141516X' +; text H'5B55 len=10 high '0123456789' xrefs=2 +; text H'60F6 len=16 high '0123456789ABCDEF' +; text H'63D7 len=10 high 'OPERATION' xrefs=1 +; text H'63F5 len=10 high 'PAINT' xrefs=1 +; text H'6443 len=10 high 'OPERATION' xrefs=1 +; text H'6461 len=10 high 'IRIS/M.BLK' xrefs=1 +; text H'6490 len=10 high 'OPERATION' xrefs=1 +; text H'64AE len=10 high 'LOCK' xrefs=1 +; text H'652F len=19 high 'DYNA LATITUDE Xe/' xrefs=1 +; text H'6551 len=18 medium 'HIGH LOW~XeP' xrefs=1 +; text H'65C9 len=18 medium 'BLACK STR Xe' xrefs=1 +; text H'6644 len=19 medium 'BLACK STR XfD' xrefs=1 +; text H'6665 len=19 medium 'STRETCH LEVEL Xfe' xrefs=1 +; text H'6683 len=18 high 'POINT1 POINT2Xf' xrefs=1 +; text H'6706 len=18 medium 'BLACK STR Xg' xrefs=1 +; text H'6727 len=19 medium "COMPRESS LEVEL Xg'" xrefs=1 +; text H'6745 len=19 high 'POINT1 POINT2XgE' xrefs=1 +; text H'67E0 len=18 medium 'TLCS Xg' xrefs=1 +; text H'681F len=18 medium 'AGC GAIN AE Xh' xrefs=1 +; text H'693B len=19 medium 'AUTO FUNC Xi;' xrefs=1 +; text H'6A4F len=19 medium 'AUTO FUNC XjO' xrefs=1 +; text H'6A8E len=18 medium 'A.IRIS MODE Xj' xrefs=1 +; text H'6AAD len=17 medium 'AI BACK.L~Xj' xrefs=1 +; text H'6B3D len=19 medium 'AUTO FUNC Xk=' xrefs=1 +; text H'6B5E len=19 medium 'AUTO FOCUS Xk^' xrefs=1 +; text H'6BEF len=18 medium 'DIAG Xk' xrefs=1 +; text H'6C16 len=18 medium 'DIAG DATA Xl' xrefs=1 +; text H'6C35 len=18 medium 'RESET REQ~Xl4' xrefs=1 +; text H'6F84 len=18 medium 'OTHERS Xo' xrefs=2 +; text H'6FAE len=18 medium 'SHUTTER Xo' xrefs=2 +; text H'7052 len=14 medium 'SET RCP' xrefs=2 +; text H'706F len=14 medium 'MASTER' xrefs=2 +; text H'709F len=18 medium 'OTHERS Xp' xrefs=2 +; text H'70C0 len=18 medium 'COPY TO SLAVES~Xp' xrefs=2 +; text H'7144 len=19 medium 'CAM ID SET~XqD' xrefs=2 +; text H'71C9 len=18 medium 'OTHERS Xq' xrefs=2 +; text H'71F9 len=18 medium 'CAM ID IND Xq' xrefs=2 +; text H'7213 len=18 medium 'TITLE IND Xr' xrefs=2 +; text H'72A5 len=18 medium 'OTHERS Xr' xrefs=2 +; text H'72C7 len=17 medium 'CAM BARS~Xr' xrefs=2 +; text H'72E4 len=18 medium 'CLOCK IND Xr' xrefs=2 +; text H'7369 len=19 medium 'OTHERS Xsi' xrefs=2 +; text H'7393 len=18 high 'CENTER MARKER Xs' xrefs=2 +; text H'7425 len=19 medium 'OTHERS Xt%' xrefs=2 +; text H'7464 len=19 medium 'SAFETY ZONE Xtd' xrefs=2 +; text H'757A len=19 medium 'BARS TYPE Xuz' xrefs=1 +; text H'75A4 len=18 medium 'SMPTE Xu' xrefs=1 +; ... 192 more LCD text candidates + +; LCD Driver Candidates +; H'F200 lcd_status_control status/control register inferred from busy polling and command writes +; H'F201 lcd_data data register inferred from paired data reads/writes +; LCD routines +; routine H'3F40-H'3F74 lcd_wait_and_transfer lcd_command_or_address_write, lcd_data_read, lcd_data_write, lcd_status_read +; LCD busy loops +; loop H'3F4A->H'3F51 LCD busy-flag poll: read H'F200, test bit 7, branch until clear + + +vec_reset_1000: +1000: 5F FE 80 MOV:I.W #H'FE80, R7 ; dataflow R7=H'FE80; cycles=3 +1003: 0C 07 00 88 LDC.W #H'0700, SR ; dataflow SR=H'0700; cycles=6 +1007: 15 FE 80 06 FF MOV:G.B #H'FF, @P1DDR ; P1DDR = H'FF; cycles=9 +100C: 15 FE 82 06 00 MOV:G.B #H'00, @P1DR ; P1DR = H'00; cycles=9 +1011: 15 FE 89 06 F9 MOV:G.B #H'F9, @P6DDR ; P6DDR = H'F9; cycles=9 +1016: 15 FE 8B 06 F1 MOV:G.B #H'F1, @P6DR ; P6DR = H'F1; cycles=9 +101B: 15 FE 8C 06 00 MOV:G.B #H'00, @P7DDR ; P7DDR = H'00; cycles=9 +1020: 15 FE 8E 06 00 MOV:G.B #H'00, @P7DR ; P7DR = H'00; cycles=9 +1025: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +102A: 15 FE FF 06 00 MOV:G.B #H'00, @P9DR ; P9DR = H'00; cycles=9 +102F: 15 FE FC 06 87 MOV:G.B #H'87, @SYSCR1 ; SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled); cycles=9 +1034: 15 FE FD 06 84 MOV:G.B #H'84, @SYSCR2 ; SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM); SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +1039: 15 FE 90 06 02 MOV:G.B #H'02, @FRT1_TCR ; FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +103E: 15 FE 91 06 01 MOV:G.B #H'01, @FRT1_TCSR ; FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1043: 1D FE 92 06 00 MOV:G.W #H'00, @FRT1_FRC_H ; FRT1_FRC_H = H'00; FRT1_FRC word write; TEMP byte-order hazard avoided; cycles=9 +1048: 1D FE 94 07 00 9C MOV:G.W #H'009C, @FRT1_OCRA_H ; FRT1_OCRA_H = H'9C; FRT1_OCRA word write; TEMP byte-order hazard avoided; cycles=11 +104E: 15 FE A0 06 02 MOV:G.B #H'02, @FRT2_TCR ; FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0); cycles=9 +1053: 15 FE A1 06 01 MOV:G.B #H'01, @FRT2_TCSR ; FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1); cycles=9 +1058: 1D FE A2 06 00 MOV:G.W #H'00, @FRT2_FRC_H ; FRT2_FRC_H = H'00; FRT2_FRC word write; TEMP byte-order hazard avoided; cycles=11 +105D: 1D FE A4 07 7A 12 MOV:G.W #H'7A12, @FRT2_OCRA_H ; FRT2_OCRA_H = H'7A12; FRT2_OCRA word write; TEMP byte-order hazard avoided; cycles=9 +1063: 15 FE B0 06 00 MOV:G.B #H'00, @FRT3_TCR ; FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0); cycles=9 +1068: 15 FE B1 06 00 MOV:G.B #H'00, @FRT3_TCSR ; FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0); cycles=9 +106D: 15 FE D0 06 00 MOV:G.B #H'00, @TMR_TCR ; TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1072: 15 FE D1 06 10 MOV:G.B #H'10, @TMR_TCSR ; TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0); cycles=9 +1077: 15 FE C0 06 38 MOV:G.B #H'38, @PWM1_TCR ; PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +107C: 15 FE C1 06 FF MOV:G.B #H'FF, @PWM1_DTR ; PWM1_DTR = H'FF; cycles=9 +1081: 15 FE C4 06 38 MOV:G.B #H'38, @PWM2_TCR ; PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0); cycles=9 +1086: 15 FE C5 06 FF MOV:G.B #H'FF, @PWM2_DTR ; PWM2_DTR = H'FF; cycles=9 +108B: 15 FE C8 06 3B MOV:G.B #H'3B, @PWM3_TCR ; PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1); cycles=9 +1090: 15 FE C9 06 7D MOV:G.B #H'7D, @PWM3_DTR ; PWM3_DTR = H'7D; cycles=9 +1095: 15 FE D8 06 24 MOV:G.B #H'24, @SCI1_SMR ; SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +109A: 15 FE DA 06 3C MOV:G.B #H'3C, @SCI1_SCR ; SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock); disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI1 receive and receive-error interrupts (RIE); enable SCI1 transmitter (TE); enable SCI1 receiver (RE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +109F: 15 FE D9 06 07 MOV:G.B #H'07, @SCI1_BRR ; SCI1_BRR = H'07; SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD); cycles=9 +10A4: 15 FE F0 06 24 MOV:G.B #H'24, @SCI2_SMR ; SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi); SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10A9: 15 FE F2 06 0C MOV:G.B #H'0C, @SCI2_SCR ; SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock); disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE; disable SCI2 receive and receive-error interrupts (RIE); disable SCI2 transmitter (TE); disable SCI2 receiver (RE); SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10AE: 15 FE F1 06 07 MOV:G.B #H'07, @SCI2_BRR ; SCI2_BRR = H'07; SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz; SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96; cycles=9 +10B3: 15 FE E8 06 19 MOV:G.B #H'19, @ADCSR ; ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled); cycles=9 +10B8: 15 FE E9 06 7F MOV:G.B #H'7F, @H'FEE9 ; refs H'FEE9 in register_field; cycles=9 +10BD: 15 FF 10 06 F0 MOV:G.B #H'F0, @WCR ; WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits); cycles=9 +10C2: 15 FF 11 06 FF MOV:G.B #H'FF, @RAMCR ; RAMCR = H'FF (RAME=1; on-chip RAM enabled); cycles=9 +10C7: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=8 +10CB: 30 2E A8 BRA loc_3F76 ; cycles=8 + +loc_10CE: +10CE: 5C 00 40 MOV:I.W #H'0040, R4 ; dataflow R4=H'0040; cycles=3 +10D1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10D4: 1E 2D F5 BSR loc_3ECC ; cycles=13 +10D7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10DA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10DD: 1E 2D EC BSR loc_3ECC ; cycles=14 +10E0: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10E3: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10E6: 1E 2D E3 BSR loc_3ECC ; cycles=13 +10E9: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +10EC: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10EF: 1E 2D DA BSR loc_3ECC ; cycles=14 +10F2: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +10F5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +10F8: 1E 2D D1 BSR loc_3ECC ; cycles=13 +10FB: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +10FE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1101: 1E 2D C8 BSR loc_3ECC ; cycles=14 +1104: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1107: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +110A: 1E 2D BF BSR loc_3ECC ; cycles=13 +110D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1110: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1113: 1E 2D B6 BSR loc_3ECC ; cycles=14 +1116: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1119: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +111C: 1E 2D AD BSR loc_3ECC ; cycles=13 +111F: 5C 00 48 MOV:I.W #H'0048, R4 ; dataflow R4=H'0048; cycles=3 +1122: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1125: 1E 2D A4 BSR loc_3ECC ; cycles=14 +1128: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +112B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +112E: 1E 2D 9B BSR loc_3ECC ; cycles=13 +1131: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1134: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1137: 1E 2D 92 BSR loc_3ECC ; cycles=14 +113A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +113D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1140: 1E 2D 89 BSR loc_3ECC ; cycles=13 +1143: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1146: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1149: 1E 2D 80 BSR loc_3ECC ; cycles=14 +114C: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +114F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1152: 1E 2D 77 BSR loc_3ECC ; cycles=13 +1155: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1158: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +115B: 1E 2D 6E BSR loc_3ECC ; cycles=14 +115E: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1161: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1164: 1E 2D 65 BSR loc_3ECC ; cycles=13 +1167: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +116A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +116D: 1E 2D 5C BSR loc_3ECC ; cycles=14 +1170: 5C 00 50 MOV:I.W #H'0050, R4 ; dataflow R4=H'0050; cycles=3 +1173: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1176: 1E 2D 53 BSR loc_3ECC ; cycles=13 +1179: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +117C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +117F: 1E 2D 4A BSR loc_3ECC ; cycles=14 +1182: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1185: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1188: 1E 2D 41 BSR loc_3ECC ; cycles=13 +118B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +118E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1191: 1E 2D 38 BSR loc_3ECC ; cycles=14 +1194: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +1197: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +119A: 1E 2D 2F BSR loc_3ECC ; cycles=13 +119D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11A3: 1E 2D 26 BSR loc_3ECC ; cycles=14 +11A6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11A9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11AC: 1E 2D 1D BSR loc_3ECC ; cycles=13 +11AF: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11B2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11B5: 1E 2D 14 BSR loc_3ECC ; cycles=14 +11B8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11BB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11BE: 1E 2D 0B BSR loc_3ECC ; cycles=13 +11C1: 5C 00 58 MOV:I.W #H'0058, R4 ; dataflow R4=H'0058; cycles=3 +11C4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11C7: 1E 2D 02 BSR loc_3ECC ; cycles=14 +11CA: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11CD: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D0: 1E 2C F9 BSR loc_3ECC ; cycles=13 +11D3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11D6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11D9: 1E 2C F0 BSR loc_3ECC ; cycles=14 +11DC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +11DF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11E2: 1E 2C E7 BSR loc_3ECC ; cycles=13 +11E5: 5C 02 07 MOV:I.W #H'0207, R4 ; dataflow R4=H'0207; cycles=3 +11E8: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11EB: 1E 2C DE BSR loc_3ECC ; cycles=14 +11EE: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11F1: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11F4: 1E 2C D5 BSR loc_3ECC ; cycles=13 +11F7: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +11FA: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +11FD: 1E 2C CC BSR loc_3ECC ; cycles=14 +1200: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1203: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1206: 1E 2C C3 BSR loc_3ECC ; cycles=13 +1209: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +120C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +120F: 1E 2C BA BSR loc_3ECC ; cycles=14 +1212: 5C 00 60 MOV:I.W #H'0060, R4 ; dataflow R4=H'0060; cycles=3 +1215: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1218: 1E 2C B1 BSR loc_3ECC ; cycles=13 +121B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +121E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1221: 1E 2C A8 BSR loc_3ECC ; cycles=14 +1224: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1227: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +122A: 1E 2C 9F BSR loc_3ECC ; cycles=13 +122D: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1230: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1233: 1E 2C 96 BSR loc_3ECC ; cycles=14 +1236: 5C 02 1B MOV:I.W #H'021B, R4 ; dataflow R4=H'021B; cycles=3 +1239: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +123C: 1E 2C 8D BSR loc_3ECC ; cycles=13 +123F: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1242: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1245: 1E 2C 84 BSR loc_3ECC ; cycles=14 +1248: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +124B: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +124E: 1E 2C 7B BSR loc_3ECC ; cycles=13 +1251: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1254: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1257: 1E 2C 72 BSR loc_3ECC ; cycles=14 +125A: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +125D: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1260: 1E 2C 69 BSR loc_3ECC ; cycles=13 +1263: 5C 00 68 MOV:I.W #H'0068, R4 ; dataflow R4=H'0068; cycles=3 +1266: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1269: 1E 2C 60 BSR loc_3ECC ; cycles=14 +126C: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +126F: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1272: 1E 2C 57 BSR loc_3ECC ; cycles=13 +1275: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1278: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +127B: 1E 2C 4E BSR loc_3ECC ; cycles=14 +127E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1281: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1284: 1E 2C 45 BSR loc_3ECC ; cycles=13 +1287: 5C 02 1C MOV:I.W #H'021C, R4 ; dataflow R4=H'021C; cycles=3 +128A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +128D: 1E 2C 3C BSR loc_3ECC ; cycles=14 +1290: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1293: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1296: 1E 2C 33 BSR loc_3ECC ; cycles=13 +1299: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +129C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +129F: 1E 2C 2A BSR loc_3ECC ; cycles=14 +12A2: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12A5: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12A8: 1E 2C 21 BSR loc_3ECC ; cycles=13 +12AB: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12AE: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12B1: 1E 2C 18 BSR loc_3ECC ; cycles=14 +12B4: 5C 00 70 MOV:I.W #H'0070, R4 ; dataflow R4=H'0070; cycles=3 +12B7: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12BA: 1E 2C 0F BSR loc_3ECC ; cycles=13 +12BD: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C0: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12C3: 1E 2C 06 BSR loc_3ECC ; cycles=14 +12C6: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12C9: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12CC: 1E 2B FD BSR loc_3ECC ; cycles=13 +12CF: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12D2: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12D5: 1E 2B F4 BSR loc_3ECC ; cycles=14 +12D8: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12DB: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12DE: 1E 2B EB BSR loc_3ECC ; cycles=13 +12E1: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12E4: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12E7: 1E 2B E2 BSR loc_3ECC ; cycles=14 +12EA: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +12ED: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F0: 1E 2B D9 BSR loc_3ECC ; cycles=13 +12F3: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12F6: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +12F9: 1E 2B D0 BSR loc_3ECC ; cycles=14 +12FC: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +12FF: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1302: 1E 2B C7 BSR loc_3ECC ; cycles=13 +1305: 5C 00 78 MOV:I.W #H'0078, R4 ; dataflow R4=H'0078; cycles=3 +1308: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +130B: 1E 2B BE BSR loc_3ECC ; cycles=14 +130E: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1311: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1314: 1E 2B B5 BSR loc_3ECC ; cycles=13 +1317: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +131A: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +131D: 1E 2B AC BSR loc_3ECC ; cycles=14 +1320: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +1323: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1326: 1E 2B A3 BSR loc_3ECC ; cycles=13 +1329: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +132C: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +132F: 1E 2B 9A BSR loc_3ECC ; cycles=14 +1332: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1335: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1338: 1E 2B 91 BSR loc_3ECC ; cycles=13 +133B: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +133E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1341: 1E 2B 88 BSR loc_3ECC ; cycles=14 +1344: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1347: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +134A: 1E 2B 7F BSR loc_3ECC ; cycles=13 +134D: 5C 02 04 MOV:I.W #H'0204, R4 ; dataflow R4=H'0204; cycles=3 +1350: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +1353: 1E 2B 76 BSR loc_3ECC ; cycles=14 +1356: 19 RTS ; cycles=12 + +loc_15E0: +15E0: 1E 10 6D BSR loc_2650 ; cycles=13 +15E3: 15 F6 89 D7 BCLR.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=8 +15E7: 27 10 BEQ loc_15F9 ; cycles=3/8 nt/t +15E9: 1D F6 8E 81 MOV:G.W @H'F68E, R1 ; refs ram_F68E in on_chip_ram; cycles=6 +15ED: 1D E9 02 91 MOV:G.W R1, @H'E902 ; refs mem_E902 in program_or_external; cycles=6 +15F1: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +15F3: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +15F6: 1E 28 5B BSR loc_3E54 ; cycles=13 + +loc_15F9: +15F9: 15 F6 F0 16 TST.B @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +15FD: 27 3E BEQ loc_163D ; cycles=3/8 nt/t +15FF: 15 F6 F0 D7 BCLR.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1603: 27 03 BEQ loc_1608 ; cycles=3/8 nt/t +1605: 18 43 94 JSR @loc_4394 ; cycles=14 + +loc_1608: +1608: 15 F6 F0 D6 BCLR.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +160C: 27 03 BEQ loc_1611 ; cycles=3/7 nt/t +160E: 18 44 57 JSR @loc_4457 ; cycles=13 + +loc_1611: +1611: 15 F6 F0 D5 BCLR.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +1615: 27 03 BEQ loc_161A ; cycles=3/8 nt/t +1617: 18 45 1A JSR @loc_451A ; cycles=14 + +loc_161A: +161A: 15 F6 F0 D4 BCLR.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +161E: 15 F6 F0 D3 BCLR.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1622: 27 03 BEQ loc_1627 ; cycles=3/7 nt/t +1624: 18 17 05 JSR @loc_1705 ; cycles=13 + +loc_1627: +1627: 15 F6 F0 D2 BCLR.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +162B: 27 03 BEQ loc_1630 ; cycles=3/8 nt/t +162D: 18 17 4D JSR @loc_174D ; cycles=14 + +loc_1630: +1630: 15 F6 F0 D1 BCLR.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=9 +1634: 27 03 BEQ loc_1639 ; cycles=3/7 nt/t +1636: 18 17 95 JSR @loc_1795 ; cycles=13 + +loc_1639: +1639: 15 F6 F0 D0 BCLR.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 + +loc_163D: +163D: 15 F6 F1 16 TST.B @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=6 +1641: 27 43 BEQ loc_1686 ; cycles=3/8 nt/t +1643: 15 F6 F1 D7 BCLR.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1647: 27 03 BEQ loc_164C ; cycles=3/8 nt/t +1649: 18 17 C9 JSR @loc_17C9 ; cycles=14 + +loc_164C: +164C: 15 F6 F1 D6 BCLR.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1650: 27 03 BEQ loc_1655 ; cycles=3/7 nt/t +1652: 18 17 FB JSR @loc_17FB ; cycles=13 + +loc_1655: +1655: 15 F6 F1 D5 BCLR.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +1659: 27 03 BEQ loc_165E ; cycles=3/8 nt/t +165B: 18 18 2D JSR @loc_182D ; cycles=14 + +loc_165E: +165E: 15 F6 F1 D4 BCLR.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1662: 27 03 BEQ loc_1667 ; cycles=3/7 nt/t +1664: 18 18 91 JSR @loc_1891 ; cycles=13 + +loc_1667: +1667: 15 F6 F1 D3 BCLR.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +166B: 27 03 BEQ loc_1670 ; cycles=3/8 nt/t +166D: 18 18 E7 JSR @loc_18E7 ; cycles=14 + +loc_1670: +1670: 15 F6 F1 D2 BCLR.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +1674: 27 03 BEQ loc_1679 ; cycles=3/7 nt/t +1676: 18 19 4A JSR @loc_194A ; cycles=13 + +loc_1679: +1679: 15 F6 F1 D1 BCLR.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=8 +167D: 27 03 BEQ loc_1682 ; cycles=3/8 nt/t +167F: 18 19 79 JSR @loc_1979 ; cycles=14 + +loc_1682: +1682: 15 F6 F1 D0 BCLR.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 + +loc_1686: +1686: 15 F6 F2 16 TST.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=7 +168A: 27 48 BEQ loc_16D4 ; cycles=3/7 nt/t +168C: 15 F6 F2 D7 BCLR.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +1690: 27 03 BEQ loc_1695 ; cycles=3/7 nt/t +1692: 18 1B 2D JSR @loc_1B2D ; cycles=13 + +loc_1695: +1695: 15 F6 F2 D6 BCLR.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +1699: 27 03 BEQ loc_169E ; cycles=3/8 nt/t +169B: 18 1B 44 JSR @loc_1B44 ; cycles=14 + +loc_169E: +169E: 15 F6 F2 D5 BCLR.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16A2: 27 03 BEQ loc_16A7 ; cycles=3/7 nt/t +16A4: 18 1B 5B JSR @loc_1B5B ; cycles=13 + +loc_16A7: +16A7: 15 F6 F2 D4 BCLR.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16AB: 27 03 BEQ loc_16B0 ; cycles=3/8 nt/t +16AD: 18 1B A0 JSR @loc_1BA0 ; cycles=14 + +loc_16B0: +16B0: 15 F6 F2 D3 BCLR.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16B4: 27 03 BEQ loc_16B9 ; cycles=3/7 nt/t +16B6: 18 1B B6 JSR @loc_1BB6 ; cycles=13 + +loc_16B9: +16B9: 15 F6 F2 D2 BCLR.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16BD: 27 03 BEQ loc_16C2 ; cycles=3/8 nt/t +16BF: 18 1B CC JSR @loc_1BCC ; cycles=14 + +loc_16C2: +16C2: 15 F6 F2 D1 BCLR.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=9 +16C6: 27 03 BEQ loc_16CB ; cycles=3/7 nt/t +16C8: 18 1B 72 JSR @loc_1B72 ; cycles=13 + +loc_16CB: +16CB: 15 F6 F2 D0 BCLR.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +16CF: 27 03 BEQ loc_16D4 ; cycles=3/8 nt/t +16D1: 18 1B 89 JSR @loc_1B89 ; cycles=14 + +loc_16D4: +16D4: 15 F6 F3 16 TST.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=7 +16D8: 27 2A BEQ loc_1704 ; cycles=3/7 nt/t +16DA: 15 F6 F3 D7 BCLR.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16DE: 15 F6 F3 D6 BCLR.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E2: 15 F6 F3 D5 BCLR.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16E6: 15 F6 F3 D4 BCLR.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16EA: 27 03 BEQ loc_16EF ; cycles=3/7 nt/t +16EC: 18 1B E2 JSR @loc_1BE2 ; cycles=13 + +loc_16EF: +16EF: 15 F6 F3 D3 BCLR.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=8 +16F3: 27 03 BEQ loc_16F8 ; cycles=3/8 nt/t +16F5: 18 1B F8 JSR @loc_1BF8 ; cycles=14 + +loc_16F8: +16F8: 15 F6 F3 D2 BCLR.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +16FC: 15 F6 F3 D1 BCLR.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +1700: 15 F6 F3 D0 BCLR.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 + +loc_1704: +1704: 19 RTS ; cycles=12 + +loc_1705: +1705: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +170A: 22 38 BHI loc_1744 ; cycles=3/7 nt/t +170C: 1D E1 4E FF BTST.W #15, @H'E14E ; refs mem_E14E in program_or_external; cycles=7 +1710: 26 24 BNE loc_1736 ; cycles=3/7 nt/t +1712: 15 F7 30 F6 BTST.B #6, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1716: 26 1E BNE loc_1736 ; cycles=3/7 nt/t +1718: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +171C: 26 08 BNE loc_1726 ; cycles=3/7 nt/t +171E: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +1722: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_1726: +1726: 1D F7 32 07 1C 07 MOV:G.W #H'1C07, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +172C: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1731: 1E 31 C6 BSR loc_48FA ; cycles=14 +1734: 20 0E BRA loc_1744 ; cycles=7 + +loc_1736: +1736: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +173A: 1D F6 B6 34 SUB.W @H'F6B6, R4 ; refs ram_F6B6 in on_chip_ram; cycles=7 +173E: 5B 00 A9 MOV:I.W #H'00A9, R3 ; dataflow R3=H'00A9; cycles=3 +1741: 1E 02 5E BSR loc_19A2 ; cycles=14 + +loc_1744: +1744: 1D F6 96 84 MOV:G.W @H'F696, R4 ; refs ram_F696 in on_chip_ram; cycles=7 +1748: 1D F6 B6 94 MOV:G.W R4, @H'F6B6 ; refs ram_F6B6 in on_chip_ram; cycles=7 +174C: 19 RTS ; cycles=12 + +loc_174D: +174D: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1752: 22 38 BHI loc_178C ; cycles=3/7 nt/t +1754: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=7 +1758: 27 32 BEQ loc_178C ; cycles=3/7 nt/t +175A: 1D E1 6E FD BTST.W #13, @H'E16E ; refs mem_E16E in program_or_external; cycles=7 +175E: 26 1E BNE loc_177E ; cycles=3/7 nt/t +1760: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +1764: 26 08 BNE loc_176E ; cycles=3/7 nt/t +1766: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=7 +176A: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=7 + +loc_176E: +176E: 1D F7 32 07 1C 06 MOV:G.W #H'1C06, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=11 +1774: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +1779: 1E 31 7E BSR loc_48FA ; cycles=14 +177C: 20 0E BRA loc_178C ; cycles=7 + +loc_177E: +177E: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1782: 1D F6 B4 34 SUB.W @H'F6B4, R4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1786: 5B 00 C5 MOV:I.W #H'00C5, R3 ; dataflow R3=H'00C5; cycles=3 +1789: 1E 02 16 BSR loc_19A2 ; cycles=14 + +loc_178C: +178C: 1D F6 94 84 MOV:G.W @H'F694, R4 ; refs ram_F694 in on_chip_ram; cycles=7 +1790: 1D F6 B4 94 MOV:G.W R4, @H'F6B4 ; refs ram_F6B4 in on_chip_ram; cycles=7 +1794: 19 RTS ; cycles=12 + +loc_1795: +1795: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +179A: 22 24 BHI loc_17C0 ; cycles=3/7 nt/t +179C: 1D E1 72 FD BTST.W #13, @H'E172 ; refs mem_E172 in program_or_external; cycles=7 +17A0: 26 05 BNE loc_17A7 ; cycles=3/7 nt/t +17A2: 1E 09 82 BSR loc_2127 ; cycles=13 +17A5: 20 19 BRA loc_17C0 ; cycles=8 + +loc_17A7: +17A7: 1D E2 20 FF BTST.W #15, @H'E220 ; refs mem_E220 in program_or_external; cycles=6 +17AB: 27 05 BEQ loc_17B2 ; cycles=3/8 nt/t +17AD: 1E 09 77 BSR loc_2127 ; cycles=14 +17B0: 20 0E BRA loc_17C0 ; cycles=7 + +loc_17B2: +17B2: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17B6: 1D F6 B2 34 SUB.W @H'F6B2, R4 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17BA: 5B 00 BC MOV:I.W #H'00BC, R3 ; dataflow R3=H'00BC; cycles=3 +17BD: 1E 01 E2 BSR loc_19A2 ; cycles=14 + +loc_17C0: +17C0: 1D F6 92 84 MOV:G.W @H'F692, R4 ; refs ram_F692 in on_chip_ram; cycles=7 +17C4: 1D F6 B2 94 MOV:G.W R4, @H'F6B2 ; refs ram_F6B2 in on_chip_ram; cycles=7 +17C8: 19 RTS ; cycles=12 + +loc_17C9: +17C9: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +17CE: 22 22 BHI loc_17F2 ; cycles=3/7 nt/t +17D0: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +17D4: 27 1C BEQ loc_17F2 ; cycles=3/7 nt/t +17D6: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17DA: 1D F6 CE 34 SUB.W @H'F6CE, R4 ; refs ram_F6CE in on_chip_ram; cycles=7 +17DE: 5B 00 A3 MOV:I.W #H'00A3, R3 ; dataflow R3=H'00A3; cycles=3 +17E1: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +17E5: 27 08 BEQ loc_17EF ; cycles=3/8 nt/t +17E7: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +17EB: 27 02 BEQ loc_17EF ; cycles=3/8 nt/t +17ED: AB CE BSET.W #14, R3 ; cycles=3 + +loc_17EF: +17EF: 1E 01 B0 BSR loc_19A2 ; cycles=14 + +loc_17F2: +17F2: 1D F6 AE 84 MOV:G.W @H'F6AE, R4 ; refs ram_F6AE in on_chip_ram; cycles=7 +17F6: 1D F6 CE 94 MOV:G.W R4, @H'F6CE ; refs ram_F6CE in on_chip_ram; cycles=7 +17FA: 19 RTS ; cycles=12 + +loc_17FB: +17FB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1800: 22 22 BHI loc_1824 ; cycles=3/7 nt/t +1802: 1D E1 26 FC BTST.W #12, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +1806: 27 1C BEQ loc_1824 ; cycles=3/7 nt/t +1808: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +180C: 1D F6 CC 34 SUB.W @H'F6CC, R4 ; refs ram_F6CC in on_chip_ram; cycles=7 +1810: 5B 00 A4 MOV:I.W #H'00A4, R3 ; dataflow R3=H'00A4; cycles=3 +1813: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1817: 27 08 BEQ loc_1821 ; cycles=3/8 nt/t +1819: 15 F4 04 F3 BTST.B #3, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +181D: 27 02 BEQ loc_1821 ; cycles=3/8 nt/t +181F: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1821: +1821: 1E 01 7E BSR loc_19A2 ; cycles=14 + +loc_1824: +1824: 1D F6 AC 84 MOV:G.W @H'F6AC, R4 ; refs ram_F6AC in on_chip_ram; cycles=7 +1828: 1D F6 CC 94 MOV:G.W R4, @H'F6CC ; refs ram_F6CC in on_chip_ram; cycles=7 +182C: 19 RTS ; cycles=12 + +loc_182D: +182D: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1831: 26 32 BNE loc_1865 ; cycles=3/8 nt/t +1833: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1838: 22 22 BHI loc_185C ; cycles=3/7 nt/t +183A: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +183E: 27 1C BEQ loc_185C ; cycles=3/7 nt/t +1840: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1844: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1848: 5B 00 A5 MOV:I.W #H'00A5, R3 ; dataflow R3=H'00A5; cycles=3 +184B: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +184F: 27 08 BEQ loc_1859 ; cycles=3/8 nt/t +1851: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1855: 27 02 BEQ loc_1859 ; cycles=3/8 nt/t +1857: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1859: +1859: 1E 01 46 BSR loc_19A2 ; cycles=14 + +loc_185C: +185C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1860: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1864: 19 RTS ; cycles=12 + +loc_1865: +1865: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +186A: 22 1C BHI loc_1888 ; cycles=3/7 nt/t +186C: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +1870: 1D F6 CA 34 SUB.W @H'F6CA, R4 ; refs ram_F6CA in on_chip_ram; cycles=7 +1874: 5B 00 D8 MOV:I.W #H'00D8, R3 ; dataflow R3=H'00D8; cycles=3 +1877: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +187B: 27 08 BEQ loc_1885 ; cycles=3/8 nt/t +187D: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +1881: 27 02 BEQ loc_1885 ; cycles=3/8 nt/t +1883: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1885: +1885: 1E 01 1A BSR loc_19A2 ; cycles=14 + +loc_1888: +1888: 1D F6 AA 84 MOV:G.W @H'F6AA, R4 ; refs ram_F6AA in on_chip_ram; cycles=7 +188C: 1D F6 CA 94 MOV:G.W R4, @H'F6CA ; refs ram_F6CA in on_chip_ram; cycles=7 +1890: 19 RTS ; cycles=12 + +loc_1891: +1891: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +1895: 26 24 BNE loc_18BB ; cycles=3/8 nt/t +1897: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +189C: 22 14 BHI loc_18B2 ; cycles=3/7 nt/t +189E: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18A2: 27 0E BEQ loc_18B2 ; cycles=3/7 nt/t +18A4: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18A8: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18AC: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +18AF: 1E 00 F0 BSR loc_19A2 ; cycles=14 + +loc_18B2: +18B2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18B6: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18BA: 19 RTS ; cycles=12 + +loc_18BB: +18BB: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18C0: 22 1C BHI loc_18DE ; cycles=3/7 nt/t +18C2: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18C6: 1D F6 C8 34 SUB.W @H'F6C8, R4 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18CA: 5B 00 D9 MOV:I.W #H'00D9, R3 ; dataflow R3=H'00D9; cycles=3 +18CD: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +18D1: 27 08 BEQ loc_18DB ; cycles=3/8 nt/t +18D3: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +18D7: 27 02 BEQ loc_18DB ; cycles=3/8 nt/t +18D9: AB CE BSET.W #14, R3 ; cycles=3 + +loc_18DB: +18DB: 1E 00 C4 BSR loc_19A2 ; cycles=14 + +loc_18DE: +18DE: 1D F6 A8 84 MOV:G.W @H'F6A8, R4 ; refs ram_F6A8 in on_chip_ram; cycles=7 +18E2: 1D F6 C8 94 MOV:G.W R4, @H'F6C8 ; refs ram_F6C8 in on_chip_ram; cycles=7 +18E6: 19 RTS ; cycles=12 + +loc_18E7: +18E7: 15 F7 17 F2 BTST.B #2, @H'F717 ; refs ram_F717 in on_chip_ram; cycles=6 +18EB: 26 32 BNE loc_191F ; cycles=3/8 nt/t +18ED: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +18F2: 22 22 BHI loc_1916 ; cycles=3/7 nt/t +18F4: 1D E1 26 F5 BTST.W #5, @H'E126 ; refs mem_E126 in program_or_external; cycles=7 +18F8: 27 1C BEQ loc_1916 ; cycles=3/7 nt/t +18FA: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +18FE: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +1902: 5B 00 A6 MOV:I.W #H'00A6, R3 ; dataflow R3=H'00A6; cycles=3 +1905: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1909: 27 08 BEQ loc_1913 ; cycles=3/8 nt/t +190B: 15 F4 04 F2 BTST.B #2, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +190F: 27 02 BEQ loc_1913 ; cycles=3/8 nt/t +1911: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1913: +1913: 1E 00 8C BSR loc_19A2 ; cycles=14 + +loc_1916: +1916: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +191A: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=7 +191E: 19 RTS ; cycles=12 + +loc_191F: +191F: 15 F7 31 04 02 CMP:G.B #H'02, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +1924: 22 1B BHI loc_1941 ; cycles=3/7 nt/t +1926: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=7 +192A: 1D F6 C6 34 SUB.W @H'F6C6, R4 ; refs ram_F6C6 in on_chip_ram; cycles=7 +192E: 5B 00 DA MOV:I.W #H'00DA, R3 ; dataflow R3=H'00DA; cycles=3 +1931: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1935: 27 08 BEQ loc_193F ; cycles=3/8 nt/t +1937: 15 F4 04 F1 BTST.B #1, @H'F404 ; refs mem_F404 in program_or_external; cycles=6 +193B: 27 02 BEQ loc_193F ; cycles=3/8 nt/t +193D: AB CE BSET.W #14, R3 ; cycles=3 + +loc_193F: +193F: 0E 61 BSR loc_19A2 ; cycles=14 + +loc_1941: +1941: 1D F6 A6 84 MOV:G.W @H'F6A6, R4 ; refs ram_F6A6 in on_chip_ram; cycles=6 +1945: 1D F6 C6 94 MOV:G.W R4, @H'F6C6 ; refs ram_F6C6 in on_chip_ram; cycles=6 +1949: 19 RTS ; cycles=13 + +loc_194A: +194A: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +194F: 22 1F BHI loc_1970 ; cycles=3/8 nt/t +1951: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=6 +1955: 1D F6 C4 34 SUB.W @H'F6C4, R4 ; refs ram_F6C4 in on_chip_ram; cycles=6 +1959: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +195D: 26 00 BNE loc_195F ; cycles=3/8 nt/t + +loc_195F: +195F: 5B 00 80 MOV:I.W #H'0080, R3 ; dataflow R3=H'0080; cycles=3 +1962: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +1966: 27 02 BEQ loc_196A ; cycles=3/7 nt/t +1968: AB CE BSET.W #14, R3 ; cycles=3 + +loc_196A: +196A: 0E 36 BSR loc_19A2 ; cycles=13 +196C: 15 F7 6D C7 BSET.B #7, @H'F76D ; refs ram_F76D in on_chip_ram; cycles=9 + +loc_1970: +1970: 1D F6 A4 84 MOV:G.W @H'F6A4, R4 ; refs ram_F6A4 in on_chip_ram; cycles=7 +1974: 1D F6 C4 94 MOV:G.W R4, @H'F6C4 ; refs ram_F6C4 in on_chip_ram; cycles=7 +1978: 19 RTS ; cycles=12 + +loc_1979: +1979: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +197E: 22 19 BHI loc_1999 ; cycles=3/7 nt/t +1980: 1D F6 A2 80 MOV:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +1984: 1D F6 C2 30 SUB.W @H'F6C2, R0 ; refs ram_F6C2 in on_chip_ram; cycles=7 +1988: 1D F6 8C A8 MULXU.W @H'F68C, R0 ; refs ram_F68C in on_chip_ram; cycles=26 +198C: 5B 00 81 MOV:I.W #H'0081, R3 ; dataflow R3=H'0081; cycles=3 +198F: 15 F7 91 F5 BTST.B #5, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +1993: 27 02 BEQ loc_1997 ; cycles=3/8 nt/t +1995: AB CE BSET.W #14, R3 ; cycles=3 + +loc_1997: +1997: 0E 42 BSR loc_19DB ; cycles=14 + +loc_1999: +1999: 1D F6 A2 84 MOV:G.W @H'F6A2, R4 ; refs ram_F6A2 in on_chip_ram; cycles=6 +199D: 1D F6 C2 94 MOV:G.W R4, @H'F6C2 ; refs ram_F6C2 in on_chip_ram; cycles=6 +19A1: 19 RTS ; cycles=13 + +loc_19A2: +19A2: AB 85 MOV:G.W R3, R5 ; cycles=3 +19A4: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19A8: AB 1A SHLL.W R3 ; cycles=3 +19AA: FB E4 00 80 MOV:G.W @(-H'1C00,R3), R0 ; cycles=7 +19AE: 48 FC 00 CMP:I #H'FC00, R0 ; cycles=3 +19B1: 22 03 BHI loc_19B6 ; cycles=3/8 nt/t +19B3: 58 FE 00 MOV:I.W #H'FE00, R0 ; dataflow R0=H'FE00; cycles=3 + +loc_19B6: +19B6: A8 15 NOT.W R0 ; cycles=3 +19B8: A8 08 ADD:Q.W #1, R0 ; cycles=4 +19BA: 4C 00 0F CMP:I #H'000F, R4 ; cycles=3 +19BD: 23 14 BLS loc_19D3 ; cycles=3/8 nt/t +19BF: 4C FF F0 CMP:I #H'FFF0, R4 ; cycles=3 +19C2: 24 0F BCC loc_19D3 ; cycles=3/7 nt/t +19C4: 4C 80 00 CMP:I #H'8000, R4 ; cycles=3 +19C7: 24 05 BCC loc_19CE ; cycles=3/8 nt/t +19C9: 5C 00 1A MOV:I.W #H'001A, R4 ; dataflow R4=H'001A; cycles=3 +19CC: 20 09 BRA loc_19D7 ; cycles=7 + +loc_19CE: +19CE: 5C FF 1C MOV:I.W #H'FF1C, R4 ; dataflow R4=H'FF1C; cycles=3 +19D1: 20 04 BRA loc_19D7 ; cycles=8 + +loc_19D3: +19D3: F4 1A 25 84 MOV:G.B @(H'1A25,R4), R4 ; cycles=6 + +loc_19D7: +19D7: AC A8 MULXU.W R4, R0 ; cycles=25 +19D9: 20 08 BRA loc_19E3 ; cycles=8 + +loc_19DB: +19DB: AB 85 MOV:G.W R3, R5 ; cycles=3 +19DD: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +19E1: AB 1A SHLL.W R3 ; cycles=3 + +loc_19E3: +19E3: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +19E7: A8 21 ADD:G.W R0, R1 ; cycles=3 +19E9: A9 82 MOV:G.W R1, R2 ; cycles=3 +19EB: 25 0C BCS loc_19F9 ; cycles=3/8 nt/t +19ED: A8 32 SUB.W R0, R2 ; cycles=3 +19EF: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +19F2: 23 0F BLS loc_1A03 ; cycles=3/7 nt/t +19F4: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +19F7: 20 0A BRA loc_1A03 ; cycles=8 + +loc_19F9: +19F9: AA 30 SUB.W R2, R0 ; cycles=3 +19FB: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +19FE: 23 03 BLS loc_1A03 ; cycles=3/7 nt/t +1A00: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_1A03: +1A03: FB E0 00 71 CMP:G.W @(-H'2000,R3), R1 ; cycles=6 +1A07: 27 0B BEQ loc_1A14 ; cycles=3/8 nt/t +1A09: FB E8 00 91 MOV:G.W R1, @(-H'1800,R3) ; cycles=6 +1A0D: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A0F: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A11: 1E 24 40 BSR loc_3E54 ; cycles=14 + +loc_1A14: +1A14: 19 RTS ; cycles=12 + +loc_1A35: +1A35: AB 85 MOV:G.W R3, R5 ; cycles=3 +1A37: 0C 01 FF 53 AND.W #H'01FF, R3 ; cycles=4 +1A3B: AB 1A SHLL.W R3 ; cycles=3 +1A3D: FB E0 00 80 MOV:G.W @(-H'2000,R3), R0 ; cycles=6 +1A41: 27 3A BEQ loc_1A7D ; cycles=3/8 nt/t +1A43: 0E 48 BSR loc_1A8D ; cycles=14 + +loc_1A45: +1A45: AC 16 TST.W R4 ; cycles=3 +1A47: 26 10 BNE loc_1A59 ; cycles=3/8 nt/t +1A49: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A4B: +1A4B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A4F: A8 1B SHLR.W R0 ; cycles=3 +1A51: 27 16 BEQ loc_1A69 ; cycles=3/8 nt/t +1A53: A8 51 AND.W R0, R1 ; cycles=3 +1A55: 27 F4 BEQ loc_1A4B ; cycles=3/8 nt/t +1A57: 20 12 BRA loc_1A6B ; cycles=8 + +loc_1A59: +1A59: A8 82 MOV:G.W R0, R2 ; cycles=3 + +loc_1A5B: +1A5B: FB E4 00 81 MOV:G.W @(-H'1C00,R3), R1 ; cycles=6 +1A5F: A8 1A SHLL.W R0 ; cycles=3 +1A61: 27 06 BEQ loc_1A69 ; cycles=3/8 nt/t +1A63: A8 51 AND.W R0, R1 ; cycles=3 +1A65: 27 F4 BEQ loc_1A5B ; cycles=3/8 nt/t +1A67: 20 02 BRA loc_1A6B ; cycles=8 + +loc_1A69: +1A69: AA 80 MOV:G.W R2, R0 ; cycles=3 + +loc_1A6B: +1A6B: FB E0 00 70 CMP:G.W @(-H'2000,R3), R0 ; cycles=6 +1A6F: 27 0B BEQ loc_1A7C ; cycles=3/8 nt/t +1A71: FB E8 00 90 MOV:G.W R0, @(-H'1800,R3) ; cycles=6 +1A75: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +1A77: AD 83 MOV:G.W R5, R3 ; cycles=3 +1A79: 1E 23 D8 BSR loc_3E54 ; cycles=14 + +loc_1A7C: +1A7C: 19 RTS ; cycles=12 + +loc_1A7D: +1A7D: A8 CF BSET.W #15, R0 ; cycles=3 + +loc_1A7F: +1A7F: A8 81 MOV:G.W R0, R1 ; cycles=3 +1A81: FB E4 00 51 AND.W @(-H'1C00,R3), R1 ; cycles=6 +1A85: 26 04 BNE loc_1A8B ; cycles=3/8 nt/t +1A87: A8 1B SHLR.W R0 ; cycles=3 +1A89: 20 F4 BRA loc_1A7F ; cycles=8 + +loc_1A8B: +1A8B: 20 B8 BRA loc_1A45 ; cycles=8 + +loc_1A8D: +1A8D: 59 00 0F MOV:I.W #H'000F, R1 ; dataflow R1=H'000F; cycles=3 + +loc_1A90: +1A90: A8 79 BTST.W R1, R0 ; cycles=3 +1A92: 26 03 BNE loc_1A97 ; cycles=3/7 nt/t +1A94: 01 B9 F9 SCB/F R1, loc_1A90 ; cycles=3/4/8 false/-1/t + +loc_1A97: +1A97: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +1A99: A8 49 BSET.W R1, R0 ; cycles=3 +1A9B: 19 RTS ; cycles=13 + +loc_1A9C: +1A9C: AB 16 TST.W R3 ; cycles=3 +1A9E: 27 32 BEQ loc_1AD2 ; cycles=3/7 nt/t +1AA0: AB 1A SHLL.W R3 ; cycles=3 +1AA2: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +1AA6: A0 15 NOT.B R0 ; cycles=2 +1AA8: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AAB: AC 16 TST.W R4 ; cycles=3 +1AAD: 26 0D BNE loc_1ABC ; cycles=3/8 nt/t + +loc_1AAF: +1AAF: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1AB1: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AB4: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=7 +1AB8: 27 F5 BEQ loc_1AAF ; cycles=3/7 nt/t +1ABA: 20 0B BRA loc_1AC7 ; cycles=7 + +loc_1ABC: +1ABC: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1ABE: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1AC1: FB E4 00 78 BTST.W R0, @(-H'1C00,R3) ; cycles=6 +1AC5: 27 F5 BEQ loc_1ABC ; cycles=3/8 nt/t + +loc_1AC7: +1AC7: A0 15 NOT.B R0 ; cycles=2 +1AC9: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +1ACC: 15 F7 33 90 MOV:G.B R0, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=7 +1AD0: 20 0E BRA loc_1AE0 ; cycles=7 + +loc_1AD2: +1AD2: AC 16 TST.W R4 ; cycles=3 +1AD4: 26 06 BNE loc_1ADC ; cycles=3/7 nt/t +1AD6: 15 F7 33 08 ADD:Q.B #1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 +1ADA: 20 04 BRA loc_1AE0 ; cycles=7 + +loc_1ADC: +1ADC: 15 F7 33 0C ADD:Q.B #-1, @H'F733 ; refs ram_F733 in on_chip_ram; cycles=9 + +loc_1AE0: +1AE0: 1E 2E 17 BSR loc_48FA ; cycles=13 +1AE3: 19 RTS ; cycles=13 + +loc_1AE4: +1AE4: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=7 +1AE8: A0 12 EXTU.B R0 ; cycles=3 +1AEA: F0 F7 5D 81 MOV:G.B @(-H'08A3,R0), R1 ; cycles=7 +1AEE: AC 16 TST.W R4 ; cycles=3 +1AF0: 26 0A BNE loc_1AFC ; cycles=3/7 nt/t +1AF2: A1 08 ADD:Q.B #1, R1 ; cycles=4 +1AF4: 41 2E CMP:E #H'2E, R1 ; cycles=2 +1AF6: 23 0B BLS loc_1B03 ; cycles=3/7 nt/t +1AF8: 51 00 MOV:E.B #H'00, R1 ; dataflow R1=H'00; cycles=2 +1AFA: 20 07 BRA loc_1B03 ; cycles=7 + +loc_1AFC: +1AFC: 04 01 31 SUB.B #H'01, R1 ; cycles=3 +1AFF: 24 02 BCC loc_1B03 ; cycles=3/8 nt/t +1B01: 51 2E MOV:E.B #H'2E, R1 ; dataflow R1=H'2E; cycles=2 + +loc_1B03: +1B03: F0 F7 5D 91 MOV:G.B R1, @(-H'08A3,R0) ; cycles=6 +1B07: 1E 2D F0 BSR loc_48FA ; cycles=14 +1B0A: 19 RTS ; cycles=12 + +loc_1B0B: +1B0B: 15 F7 5B 80 MOV:G.B @H'F75B, R0 ; refs ram_F75B in on_chip_ram; cycles=6 +1B0F: AC 16 TST.W R4 ; cycles=3 +1B11: 26 0A BNE loc_1B1D ; cycles=3/8 nt/t +1B13: A0 08 ADD:Q.B #1, R0 ; cycles=4 +1B15: 40 08 CMP:E #H'08, R0 ; cycles=2 +1B17: 23 0C BLS loc_1B25 ; cycles=3/8 nt/t +1B19: 50 08 MOV:E.B #H'08, R0 ; dataflow R0=H'08; cycles=2 +1B1B: 20 08 BRA loc_1B25 ; cycles=8 + +loc_1B1D: +1B1D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +1B1F: 40 01 CMP:E #H'01, R0 ; cycles=2 +1B21: 24 02 BCC loc_1B25 ; cycles=3/8 nt/t +1B23: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_1B25: +1B25: 15 F7 5B 90 MOV:G.B R0, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=6 +1B29: 1E 2D CE BSR loc_48FA ; cycles=14 +1B2C: 19 RTS ; cycles=12 + +loc_1B2D: +1B2D: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B31: 15 F6 E7 64 XOR.B @H'F6E7, R4 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B35: 5D 00 7E MOV:I.W #H'007E, R5 ; dataflow R5=H'007E; cycles=3 +1B38: 1E 00 D3 BSR loc_1C0E ; cycles=13 +1B3B: 15 F6 D7 84 MOV:G.B @H'F6D7, R4 ; refs ram_F6D7 in on_chip_ram; cycles=6 +1B3F: 15 F6 E7 94 MOV:G.B R4, @H'F6E7 ; refs ram_F6E7 in on_chip_ram; cycles=6 +1B43: 19 RTS ; cycles=13 + +loc_1B44: +1B44: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B48: 15 F6 E6 64 XOR.B @H'F6E6, R4 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B4C: 5D 00 6E MOV:I.W #H'006E, R5 ; dataflow R5=H'006E; cycles=3 +1B4F: 1E 00 BC BSR loc_1C0E ; cycles=14 +1B52: 15 F6 D6 84 MOV:G.B @H'F6D6, R4 ; refs ram_F6D6 in on_chip_ram; cycles=7 +1B56: 15 F6 E6 94 MOV:G.B R4, @H'F6E6 ; refs ram_F6E6 in on_chip_ram; cycles=7 +1B5A: 19 RTS ; cycles=12 + +loc_1B5B: +1B5B: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B5F: 15 F6 E5 64 XOR.B @H'F6E5, R4 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B63: 5D 00 5E MOV:I.W #H'005E, R5 ; dataflow R5=H'005E; cycles=3 +1B66: 1E 00 A5 BSR loc_1C0E ; cycles=13 +1B69: 15 F6 D5 84 MOV:G.B @H'F6D5, R4 ; refs ram_F6D5 in on_chip_ram; cycles=6 +1B6D: 15 F6 E5 94 MOV:G.B R4, @H'F6E5 ; refs ram_F6E5 in on_chip_ram; cycles=6 +1B71: 19 RTS ; cycles=13 + +loc_1B72: +1B72: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B76: 15 F6 E1 64 XOR.B @H'F6E1, R4 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B7A: 5D 00 1E MOV:I.W #H'001E, R5 ; dataflow R5=H'001E; cycles=3 +1B7D: 1E 00 8E BSR loc_1C0E ; cycles=14 +1B80: 15 F6 D1 84 MOV:G.B @H'F6D1, R4 ; refs ram_F6D1 in on_chip_ram; cycles=7 +1B84: 15 F6 E1 94 MOV:G.B R4, @H'F6E1 ; refs ram_F6E1 in on_chip_ram; cycles=7 +1B88: 19 RTS ; cycles=12 + +loc_1B89: +1B89: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B8D: 15 F6 E0 64 XOR.B @H'F6E0, R4 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B91: 5D 00 0E MOV:I.W #H'000E, R5 ; dataflow R5=H'000E; cycles=3 +1B94: 1E 00 77 BSR loc_1C0E ; cycles=13 +1B97: 15 F6 D0 84 MOV:G.B @H'F6D0, R4 ; refs ram_F6D0 in on_chip_ram; cycles=6 +1B9B: 15 F6 E0 94 MOV:G.B R4, @H'F6E0 ; refs ram_F6E0 in on_chip_ram; cycles=6 +1B9F: 19 RTS ; cycles=13 + +loc_1BA0: +1BA0: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=7 +1BA4: 15 F6 E4 64 XOR.B @H'F6E4, R4 ; refs ram_F6E4 in on_chip_ram; cycles=7 +1BA8: 5D 00 4E MOV:I.W #H'004E, R5 ; dataflow R5=H'004E; cycles=3 +1BAB: 0E 61 BSR loc_1C0E ; cycles=14 +1BAD: 15 F6 D4 84 MOV:G.B @H'F6D4, R4 ; refs ram_F6D4 in on_chip_ram; cycles=6 +1BB1: 15 F6 E4 94 MOV:G.B R4, @H'F6E4 ; refs ram_F6E4 in on_chip_ram; cycles=6 +1BB5: 19 RTS ; cycles=13 + +loc_1BB6: +1BB6: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=7 +1BBA: 15 F6 E3 64 XOR.B @H'F6E3, R4 ; refs ram_F6E3 in on_chip_ram; cycles=7 +1BBE: 5D 00 3E MOV:I.W #H'003E, R5 ; dataflow R5=H'003E; cycles=3 +1BC1: 0E 4B BSR loc_1C0E ; cycles=14 +1BC3: 15 F6 D3 84 MOV:G.B @H'F6D3, R4 ; refs ram_F6D3 in on_chip_ram; cycles=6 +1BC7: 15 F6 E3 94 MOV:G.B R4, @H'F6E3 ; refs ram_F6E3 in on_chip_ram; cycles=6 +1BCB: 19 RTS ; cycles=13 + +loc_1BCC: +1BCC: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=7 +1BD0: 15 F6 E2 64 XOR.B @H'F6E2, R4 ; refs ram_F6E2 in on_chip_ram; cycles=7 +1BD4: 5D 00 2E MOV:I.W #H'002E, R5 ; dataflow R5=H'002E; cycles=3 +1BD7: 0E 35 BSR loc_1C0E ; cycles=14 +1BD9: 15 F6 D2 84 MOV:G.B @H'F6D2, R4 ; refs ram_F6D2 in on_chip_ram; cycles=6 +1BDD: 15 F6 E2 94 MOV:G.B R4, @H'F6E2 ; refs ram_F6E2 in on_chip_ram; cycles=6 +1BE1: 19 RTS ; cycles=13 + +loc_1BE2: +1BE2: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=7 +1BE6: 15 F6 EC 64 XOR.B @H'F6EC, R4 ; refs ram_F6EC in on_chip_ram; cycles=7 +1BEA: 5D 00 CE MOV:I.W #H'00CE, R5 ; dataflow R5=H'00CE; cycles=3 +1BED: 0E 1F BSR loc_1C0E ; cycles=14 +1BEF: 15 F6 DC 84 MOV:G.B @H'F6DC, R4 ; refs ram_F6DC in on_chip_ram; cycles=6 +1BF3: 15 F6 EC 94 MOV:G.B R4, @H'F6EC ; refs ram_F6EC in on_chip_ram; cycles=6 +1BF7: 19 RTS ; cycles=13 + +loc_1BF8: +1BF8: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=7 +1BFC: 15 F6 EB 64 XOR.B @H'F6EB, R4 ; refs ram_F6EB in on_chip_ram; cycles=7 +1C00: 5D 00 BE MOV:I.W #H'00BE, R5 ; dataflow R5=H'00BE; cycles=3 +1C03: 0E 09 BSR loc_1C0E ; cycles=14 +1C05: 15 F6 DB 84 MOV:G.B @H'F6DB, R4 ; refs ram_F6DB in on_chip_ram; cycles=6 +1C09: 15 F6 EB 94 MOV:G.B R4, @H'F6EB ; refs ram_F6EB in on_chip_ram; cycles=6 +1C0D: 19 RTS ; cycles=13 + +loc_1C0E: +1C0E: A4 1A SHLL.B R4 ; cycles=2 +1C10: 24 0A BCC loc_1C1C ; cycles=3/7 nt/t +1C12: FD 27 06 80 MOV:G.W @(H'2706,R5), R0 ; cycles=7 +1C16: 12 30 STM.W {R4,R5}, @-SP ; cycles=12 +1C18: 11 D8 JSR @R0 ; JSR @R0 uses R0; target not resolved; cycles=13 +1C1A: 02 30 LDM.W @SP+, {R4,R5} ; cycles=14 + +loc_1C1C: +1C1C: A4 16 TST.B R4 ; cycles=2 +1C1E: 27 04 BEQ loc_1C24 ; cycles=3/7 nt/t +1C20: AD 0D ADD:Q.W #-2, R5 ; cycles=4 +1C22: 20 EA BRA loc_1C0E ; cycles=7 + +loc_1C24: +1C24: 19 RTS ; cycles=12 + +loc_2127: +2127: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=8 +212B: 26 08 BNE loc_2135 ; cycles=3/8 nt/t +212D: 1D F7 32 81 MOV:G.W @H'F732, R1 ; refs ram_F732 in on_chip_ram; cycles=6 +2131: 1D F7 34 91 MOV:G.W R1, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=6 + +loc_2135: +2135: 1D F7 32 07 1C 03 MOV:G.W #H'1C03, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +213B: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +2140: 1E 27 B7 BSR loc_48FA ; cycles=13 +2143: 19 RTS ; cycles=13 + +loc_2650: +2650: 15 F6 F6 D5 BCLR.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +2654: 37 00 68 BEQ loc_26BF ; cycles=3/7 nt/t +2657: 1D E1 24 80 MOV:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +265B: A8 1A SHLL.W R0 ; cycles=3 +265D: A0 10 SWAP.B R0 ; cycles=3 +265F: 15 F6 F6 F6 BTST.B #6, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=6 +2663: 26 08 BNE loc_266D ; cycles=3/8 nt/t +2665: A0 08 ADD:Q.B #1, R0 ; cycles=4 +2667: 24 1A BCC loc_2683 ; cycles=3/8 nt/t +2669: 50 FF MOV:E.B #H'FF, R0 ; dataflow R0=H'FF; cycles=2 +266B: 20 16 BRA loc_2683 ; cycles=8 + +loc_266D: +266D: A0 0C ADD:Q.B #-1, R0 ; cycles=4 +266F: 1D E0 04 FD BTST.W #13, @H'E004 ; refs mem_E004 in program_or_external; cycles=6 +2673: 26 08 BNE loc_267D ; cycles=3/8 nt/t +2675: 40 49 CMP:E #H'49, R0 ; cycles=2 +2677: 24 0A BCC loc_2683 ; cycles=3/8 nt/t +2679: 50 49 MOV:E.B #H'49, R0 ; dataflow R0=H'49; cycles=2 +267B: 20 06 BRA loc_2683 ; cycles=8 + +loc_267D: +267D: 40 16 CMP:E #H'16, R0 ; cycles=2 +267F: 24 02 BCC loc_2683 ; cycles=3/8 nt/t +2681: 50 16 MOV:E.B #H'16, R0 ; dataflow R0=H'16; cycles=2 + +loc_2683: +2683: A0 12 EXTU.B R0 ; cycles=3 +2685: A0 10 SWAP.B R0 ; cycles=3 +2687: A8 1B SHLR.W R0 ; cycles=3 +2689: A8 CF BSET.W #15, R0 ; cycles=3 +268B: 1D E1 24 70 CMP:G.W @H'E124, R0 ; refs mem_E124 in program_or_external; cycles=6 +268F: 27 2E BEQ loc_26BF ; cycles=3/8 nt/t +2691: 1D E9 24 90 MOV:G.W R0, @H'E924 ; refs mem_E924 in program_or_external; cycles=6 +2695: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +2697: 5B 00 92 MOV:I.W #H'0092, R3 ; dataflow R3=H'0092; cycles=3 +269A: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +269E: 27 08 BEQ loc_26A8 ; cycles=3/7 nt/t +26A0: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs mem_F404 in program_or_external; cycles=7 +26A4: 27 02 BEQ loc_26A8 ; cycles=3/7 nt/t +26A6: AB CE BSET.W #14, R3 ; cycles=3 + +loc_26A8: +26A8: 1E 17 A9 BSR loc_3E54 ; cycles=13 +26AB: 15 F6 F6 C0 BSET.B #0, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=8 +26AF: 26 08 BNE loc_26B9 ; cycles=3/8 nt/t +26B1: 1D F6 F4 07 07 D0 MOV:G.W #H'07D0, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 +26B7: 20 06 BRA loc_26BF ; cycles=8 + +loc_26B9: +26B9: 1D F6 F4 07 00 C8 MOV:G.W #H'00C8, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_26BF: +26BF: 19 RTS ; cycles=13 + +loc_2806: +2806: 15 F9 B9 81 MOV:G.B @H'F9B9, R1 ; refs ram_F9B9 in on_chip_ram; cycles=7 +280A: A1 12 EXTU.B R1 ; cycles=3 +280C: 15 F9 B4 71 CMP:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +2810: 26 03 BNE loc_2815 ; cycles=3/7 nt/t +2812: 30 04 91 BRA loc_2CA6 ; cycles=7 + +loc_2815: +2815: A9 80 MOV:G.W R1, R0 ; cycles=3 +2817: A8 1A SHLL.W R0 ; cycles=3 +2819: F8 F9 70 80 MOV:G.W @(-H'0690,R0), R0 ; cycles=6 +281D: A1 08 ADD:Q.B #1, R1 ; cycles=4 +281F: 04 1F 51 AND.B #H'1F, R1 ; cycles=3 +2822: 15 F9 B9 91 MOV:G.B R1, @H'F9B9 ; refs ram_F9B9 in on_chip_ram; cycles=7 +2826: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +282A: A8 85 MOV:G.W R0, R5 ; cycles=3 +282C: 1E 39 D7 BSR loc_6206 ; cycles=13 +282F: A8 84 MOV:G.W R0, R4 ; cycles=3 +2831: AC 1A SHLL.W R4 ; cycles=3 +2833: A8 16 TST.W R0 ; cycles=3 +2835: 27 68 BEQ loc_289F ; cycles=3/8 nt/t +2837: 1D F7 36 81 MOV:G.W @H'F736, R1 ; refs ram_F736 in on_chip_ram; cycles=6 +283B: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +283F: A9 70 CMP:G.W R1, R0 ; cycles=3 +2841: 37 04 67 BEQ loc_2CAB ; cycles=3/8 nt/t +2844: 1D F7 38 81 MOV:G.W @H'F738, R1 ; refs ram_F738 in on_chip_ram; cycles=7 +2848: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +284C: A9 70 CMP:G.W R1, R0 ; cycles=3 +284E: 37 04 5A BEQ loc_2CAB ; cycles=3/7 nt/t +2851: 1D F7 3A 81 MOV:G.W @H'F73A, R1 ; refs ram_F73A in on_chip_ram; cycles=6 +2855: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2859: A9 70 CMP:G.W R1, R0 ; cycles=3 +285B: 37 04 4D BEQ loc_2CAB ; cycles=3/8 nt/t +285E: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs ram_F73C in on_chip_ram; cycles=7 +2862: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2866: A9 70 CMP:G.W R1, R0 ; cycles=3 +2868: 37 04 40 BEQ loc_2CAB ; cycles=3/7 nt/t +286B: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +286F: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2873: A9 70 CMP:G.W R1, R0 ; cycles=3 +2875: 37 04 33 BEQ loc_2CAB ; cycles=3/8 nt/t +2878: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs ram_F740 in on_chip_ram; cycles=7 +287C: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +2880: A9 70 CMP:G.W R1, R0 ; cycles=3 +2882: 37 04 26 BEQ loc_2CAB ; cycles=3/7 nt/t +2885: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +2889: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +288D: A9 70 CMP:G.W R1, R0 ; cycles=3 +288F: 37 04 19 BEQ loc_2CAB ; cycles=3/8 nt/t +2892: 1D F7 54 81 MOV:G.W @H'F754, R1 ; refs ram_F754 in on_chip_ram; cycles=7 +2896: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +289A: A9 70 CMP:G.W R1, R0 ; cycles=3 +289C: 37 04 0C BEQ loc_2CAB ; cycles=3/7 nt/t + +loc_289F: +289F: FC 28 A6 81 MOV:G.W @(H'28A6,R4), R1 ; cycles=6 +28A3: 11 D1 JMP @R1 ; JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets); cycles=7 + +loc_2CA6: +2CA6: 15 F7 69 D7 BCLR.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CAA: 19 RTS ; cycles=12 + +loc_2CAB: +2CAB: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +2CAD: 1E 1C 4A BSR loc_48FA ; cycles=14 +2CB0: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 +2CB2: 15 F7 69 C7 BSET.B #7, @H'F769 ; refs ram_F769 in on_chip_ram; cycles=9 +2CB6: 30 FB E6 BRA loc_289F ; cycles=7 + +loc_3930: +3930: 58 00 07 MOV:I.W #H'0007, R0 ; dataflow R0=H'0007; cycles=3 + +loc_3933: +3933: 15 FE 8E 78 BTST.B R0, @P7DR ; refs P7DR in register_field; cycles=6 +3937: 27 0A BEQ loc_3943 ; cycles=3/8 nt/t +3939: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 +393D: F0 F6 80 C0 BSET.B #0, @(-H'0980,R0) ; cycles=8 +3941: 20 04 BRA loc_3947 ; cycles=8 + +loc_3943: +3943: F0 F6 80 1A SHLL.B @(-H'0980,R0) ; cycles=8 + +loc_3947: +3947: F0 F6 80 04 FF CMP:G.B #H'FF, @(-H'0980,R0) ; cycles=6 +394C: 26 06 BNE loc_3954 ; cycles=3/7 nt/t +394E: 15 F6 88 48 BSET.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=9 +3952: 20 0B BRA loc_395F ; cycles=7 + +loc_3954: +3954: F0 F6 80 04 00 CMP:G.B #H'00, @(-H'0980,R0) ; cycles=7 +3959: 26 04 BNE loc_395F ; cycles=3/8 nt/t +395B: 15 F6 88 58 BCLR.B R0, @H'F688 ; refs ram_F688 in on_chip_ram; cycles=8 + +loc_395F: +395F: 01 B8 D1 SCB/F R0, loc_3933 ; cycles=3/4/9 false/-1/t +3962: 15 F7 22 08 ADD:Q.B #1, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=9 +3966: 15 F7 22 04 3C CMP:G.B #H'3C, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +396B: 27 0F BEQ loc_397C ; cycles=3/8 nt/t +396D: 15 F7 22 04 78 CMP:G.B #H'78, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=6 +3972: 27 0B BEQ loc_397F ; cycles=3/7 nt/t +3974: 15 F7 22 04 B4 CMP:G.B #H'B4, @H'F722 ; refs ram_F722 in on_chip_ram; cycles=7 +3979: 27 08 BEQ loc_3983 ; cycles=3/8 nt/t +397B: 19 RTS ; cycles=13 + +loc_397C: +397C: 0E 17 BSR loc_3995 ; cycles=13 +397E: 19 RTS ; cycles=12 + +loc_397F: +397F: 1E 00 AC BSR loc_3A2E ; cycles=14 +3982: 19 RTS ; cycles=12 + +loc_3983: +3983: 0E 05 BSR loc_398A ; cycles=14 +3985: 15 F7 22 13 CLR.B @H'F722 ; refs ram_F722 in on_chip_ram; cycles=8 +3989: 19 RTS ; cycles=13 + +loc_398A: +398A: 15 FE E8 F7 BTST.B #7, @ADCSR ; refs ADCSR in register_field; cycles=7 +398E: 26 04 BNE loc_3994 ; cycles=3/7 nt/t +3990: 15 FE E8 C5 BSET.B #5, @ADCSR ; set ADST (bit 5) of ADCSR; cycles=9 + +loc_3994: +3994: 19 RTS ; cycles=12 + +loc_3995: +3995: 15 F7 20 16 TST.B @H'F720 ; refs ram_F720 in on_chip_ram; cycles=6 +3999: 36 00 91 BNE loc_3A2D ; cycles=3/8 nt/t +399C: 15 F1 01 06 A0 MOV:G.B #H'A0, @H'F101 ; refs mem_F101 in program_or_external; cycles=9 +39A1: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +39A5: 37 00 85 BEQ loc_3A2D ; cycles=3/8 nt/t +39A8: 15 F7 1B 80 MOV:G.B @H'F71B, R0 ; refs ram_F71B in on_chip_ram; cycles=7 +39AC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39B0: 15 F7 13 50 AND.B @H'F713, R0 ; refs ram_F713 in on_chip_ram; cycles=7 +39B4: 15 F1 02 90 MOV:G.B R0, @H'F102 ; refs mem_F102 in program_or_external; cycles=7 +39B8: 15 F7 1A 80 MOV:G.B @H'F71A, R0 ; refs ram_F71A in on_chip_ram; cycles=7 +39BC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39C0: 15 F7 12 50 AND.B @H'F712, R0 ; refs ram_F712 in on_chip_ram; cycles=7 +39C4: 15 F1 03 90 MOV:G.B R0, @H'F103 ; refs mem_F103 in program_or_external; cycles=7 +39C8: 15 F7 19 80 MOV:G.B @H'F719, R0 ; refs ram_F719 in on_chip_ram; cycles=7 +39CC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39D0: 15 F7 11 50 AND.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=7 +39D4: 15 F1 04 90 MOV:G.B R0, @H'F104 ; refs mem_F104 in program_or_external; cycles=7 +39D8: 15 F7 18 80 MOV:G.B @H'F718, R0 ; refs ram_F718 in on_chip_ram; cycles=7 +39DC: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=7 +39E0: 15 F7 10 50 AND.B @H'F710, R0 ; refs ram_F710 in on_chip_ram; cycles=7 +39E4: 15 F1 05 90 MOV:G.B R0, @H'F105 ; refs mem_F105 in program_or_external; cycles=7 +39E8: 15 F7 02 80 MOV:G.B @H'F702, R0 ; refs ram_F702 in on_chip_ram; cycles=7 +39EC: 15 F1 09 90 MOV:G.B R0, @H'F109 ; refs mem_F109 in program_or_external; cycles=7 +39F0: 15 F7 03 80 MOV:G.B @H'F703, R0 ; refs ram_F703 in on_chip_ram; cycles=7 +39F4: 15 F1 0A 90 MOV:G.B R0, @H'F10A ; refs mem_F10A in program_or_external; cycles=7 +39F8: 15 F7 04 80 MOV:G.B @H'F704, R0 ; refs ram_F704 in on_chip_ram; cycles=7 +39FC: 15 F1 0B 90 MOV:G.B R0, @H'F10B ; refs mem_F10B in program_or_external; cycles=7 +3A00: 15 F7 05 80 MOV:G.B @H'F705, R0 ; refs ram_F705 in on_chip_ram; cycles=7 +3A04: 15 F1 0C 90 MOV:G.B R0, @H'F10C ; refs mem_F10C in program_or_external; cycles=7 +3A08: 15 F7 00 80 MOV:G.B @H'F700, R0 ; refs ram_F700 in on_chip_ram; cycles=7 +3A0C: 15 F1 0D 90 MOV:G.B R0, @H'F10D ; refs mem_F10D in program_or_external; cycles=7 +3A10: 15 F7 01 80 MOV:G.B @H'F701, R0 ; refs ram_F701 in on_chip_ram; cycles=7 +3A14: 15 F1 0E 90 MOV:G.B R0, @H'F10E ; refs mem_F10E in program_or_external; cycles=7 +3A18: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=7 +3A1C: A0 15 NOT.B R0 ; cycles=2 +3A1E: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3A21: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3A24: 15 F1 0F 90 MOV:G.B R0, @H'F10F ; refs mem_F10F in program_or_external; cycles=7 +3A28: 15 F7 20 06 03 MOV:G.B #H'03, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=9 + +loc_3A2D: +3A2D: 19 RTS ; cycles=13 + +loc_3A2E: +3A2E: 15 F7 21 16 TST.B @H'F721 ; refs ram_F721 in on_chip_ram; cycles=7 +3A32: 36 00 91 BNE loc_3AC6 ; cycles=3/7 nt/t +3A35: 15 F0 01 06 A0 MOV:G.B #H'A0, @H'F001 ; refs mem_F001 in program_or_external; cycles=9 +3A3A: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3A3E: 37 00 85 BEQ loc_3AC6 ; cycles=3/7 nt/t +3A41: 15 F7 1F 80 MOV:G.B @H'F71F, R0 ; refs ram_F71F in on_chip_ram; cycles=6 +3A45: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A49: 15 F7 17 50 AND.B @H'F717, R0 ; refs ram_F717 in on_chip_ram; cycles=6 +3A4D: 15 F0 02 90 MOV:G.B R0, @H'F002 ; refs mem_F002 in program_or_external; cycles=6 +3A51: 15 F7 1E 80 MOV:G.B @H'F71E, R0 ; refs ram_F71E in on_chip_ram; cycles=6 +3A55: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A59: 15 F7 16 50 AND.B @H'F716, R0 ; refs ram_F716 in on_chip_ram; cycles=6 +3A5D: 15 F0 03 90 MOV:G.B R0, @H'F003 ; refs mem_F003 in program_or_external; cycles=6 +3A61: 15 F7 1D 80 MOV:G.B @H'F71D, R0 ; refs ram_F71D in on_chip_ram; cycles=6 +3A65: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A69: 15 F7 15 50 AND.B @H'F715, R0 ; refs ram_F715 in on_chip_ram; cycles=6 +3A6D: 15 F0 04 90 MOV:G.B R0, @H'F004 ; refs mem_F004 in program_or_external; cycles=6 +3A71: 15 F7 1C 80 MOV:G.B @H'F71C, R0 ; refs ram_F71C in on_chip_ram; cycles=6 +3A75: 15 F7 23 40 OR.B @H'F723, R0 ; refs ram_F723 in on_chip_ram; cycles=6 +3A79: 15 F7 14 50 AND.B @H'F714, R0 ; refs ram_F714 in on_chip_ram; cycles=6 +3A7D: 15 F0 05 90 MOV:G.B R0, @H'F005 ; refs mem_F005 in program_or_external; cycles=6 +3A81: 15 F7 08 80 MOV:G.B @H'F708, R0 ; refs ram_F708 in on_chip_ram; cycles=6 +3A85: 15 F0 09 90 MOV:G.B R0, @H'F009 ; refs mem_F009 in program_or_external; cycles=6 +3A89: 15 F7 09 80 MOV:G.B @H'F709, R0 ; refs ram_F709 in on_chip_ram; cycles=6 +3A8D: 15 F0 0A 90 MOV:G.B R0, @H'F00A ; refs mem_F00A in program_or_external; cycles=6 +3A91: 15 F7 0A 80 MOV:G.B @H'F70A, R0 ; refs ram_F70A in on_chip_ram; cycles=6 +3A95: 15 F0 0B 90 MOV:G.B R0, @H'F00B ; refs mem_F00B in program_or_external; cycles=6 +3A99: 15 F7 0B 80 MOV:G.B @H'F70B, R0 ; refs ram_F70B in on_chip_ram; cycles=6 +3A9D: 15 F0 0C 90 MOV:G.B R0, @H'F00C ; refs mem_F00C in program_or_external; cycles=6 +3AA1: 15 F7 06 80 MOV:G.B @H'F706, R0 ; refs ram_F706 in on_chip_ram; cycles=6 +3AA5: 15 F0 0D 90 MOV:G.B R0, @H'F00D ; refs mem_F00D in program_or_external; cycles=6 +3AA9: 15 F7 07 80 MOV:G.B @H'F707, R0 ; refs ram_F707 in on_chip_ram; cycles=6 +3AAD: 15 F0 0E 90 MOV:G.B R0, @H'F00E ; refs mem_F00E in program_or_external; cycles=6 +3AB1: 15 FE 8E 80 MOV:G.B @P7DR, R0 ; refs P7DR in register_field; cycles=6 +3AB5: A0 15 NOT.B R0 ; cycles=2 +3AB7: 04 03 50 AND.B #H'03, R0 ; cycles=3 +3ABA: 04 A0 40 OR.B #H'A0, R0 ; cycles=3 +3ABD: 15 F0 0F 90 MOV:G.B R0, @H'F00F ; refs mem_F00F in program_or_external; cycles=6 +3AC1: 15 F7 21 06 03 MOV:G.B #H'03, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3AC6: +3AC6: 19 RTS ; cycles=12 + +vec_irq4_3AC7: +3AC7: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +3AC9: 15 F1 00 F1 BTST.B #1, @H'F100 ; refs mem_F100 in program_or_external; cycles=6 +3ACD: 36 01 5D BNE loc_3C2D ; cycles=3/8 nt/t +3AD0: 15 F1 0F 80 MOV:G.B @H'F10F, R0 ; refs mem_F10F in program_or_external; cycles=7 +3AD4: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3AD6: 27 08 BEQ loc_3AE0 ; cycles=3/7 nt/t +3AD8: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3ADA: 37 00 85 BEQ loc_3B62 ; cycles=3/7 nt/t +3ADD: 30 01 4D BRA loc_3C2D ; cycles=8 + +loc_3AE0: +3AE0: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3AE4: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3AE7: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3AEB: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3AEF: 1D F6 9A 70 CMP:G.W @H'F69A, R0 ; refs ram_F69A in on_chip_ram; cycles=6 +3AF3: 27 08 BEQ loc_3AFD ; cycles=3/8 nt/t +3AF5: 15 F6 F0 C5 BSET.B #5, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3AF9: 1D F6 9A 90 MOV:G.W R0, @H'F69A ; refs ram_F69A in on_chip_ram; cycles=6 + +loc_3AFD: +3AFD: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B01: 1D F6 98 70 CMP:G.W @H'F698, R0 ; refs ram_F698 in on_chip_ram; cycles=6 +3B05: 27 08 BEQ loc_3B0F ; cycles=3/8 nt/t +3B07: 15 F6 F0 C4 BSET.B #4, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B0B: 1D F6 98 90 MOV:G.W R0, @H'F698 ; refs ram_F698 in on_chip_ram; cycles=6 + +loc_3B0F: +3B0F: 1D F1 08 80 MOV:G.W @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3B13: 1D F6 96 70 CMP:G.W @H'F696, R0 ; refs ram_F696 in on_chip_ram; cycles=6 +3B17: 27 08 BEQ loc_3B21 ; cycles=3/8 nt/t +3B19: 15 F6 F0 C3 BSET.B #3, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B1D: 1D F6 96 90 MOV:G.W R0, @H'F696 ; refs ram_F696 in on_chip_ram; cycles=6 + +loc_3B21: +3B21: 1D F1 06 80 MOV:G.W @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3B25: 1D F6 94 70 CMP:G.W @H'F694, R0 ; refs ram_F694 in on_chip_ram; cycles=6 +3B29: 27 08 BEQ loc_3B33 ; cycles=3/8 nt/t +3B2B: 15 F6 F0 C2 BSET.B #2, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B2F: 1D F6 94 90 MOV:G.W R0, @H'F694 ; refs ram_F694 in on_chip_ram; cycles=6 + +loc_3B33: +3B33: 1D F1 04 80 MOV:G.W @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3B37: 1D F6 92 70 CMP:G.W @H'F692, R0 ; refs ram_F692 in on_chip_ram; cycles=6 +3B3B: 27 08 BEQ loc_3B45 ; cycles=3/8 nt/t +3B3D: 15 F6 F0 C1 BSET.B #1, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B41: 1D F6 92 90 MOV:G.W R0, @H'F692 ; refs ram_F692 in on_chip_ram; cycles=6 + +loc_3B45: +3B45: 1D F1 02 80 MOV:G.W @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3B49: 1D F6 90 70 CMP:G.W @H'F690, R0 ; refs ram_F690 in on_chip_ram; cycles=6 +3B4D: 27 08 BEQ loc_3B57 ; cycles=3/8 nt/t +3B4F: 15 F6 F0 C0 BSET.B #0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B53: 1D F6 90 90 MOV:G.W R0, @H'F690 ; refs ram_F690 in on_chip_ram; cycles=6 + +loc_3B57: +3B57: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3B5B: 15 F7 20 D0 BCLR.B #0, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 +3B5F: 30 00 CB BRA loc_3C2D ; cycles=8 + +loc_3B62: +3B62: 15 F6 F0 80 MOV:G.B @H'F6F0, R0 ; refs ram_F6F0 in on_chip_ram; cycles=7 +3B66: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3B69: 15 F6 F0 90 MOV:G.B R0, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=6 +3B6D: 15 F6 F2 13 CLR.B @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3B71: 1D F1 0C 80 MOV:G.W @H'F10C, R0 ; refs mem_F10C in program_or_external; cycles=6 +3B75: 1D F6 9E 70 CMP:G.W @H'F69E, R0 ; refs ram_F69E in on_chip_ram; cycles=6 +3B79: 27 08 BEQ loc_3B83 ; cycles=3/8 nt/t +3B7B: 15 F6 F0 C7 BSET.B #7, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B7F: 1D F6 9E 90 MOV:G.W R0, @H'F69E ; refs ram_F69E in on_chip_ram; cycles=6 + +loc_3B83: +3B83: 1D F1 0A 80 MOV:G.W @H'F10A, R0 ; refs mem_F10A in program_or_external; cycles=6 +3B87: 1D F6 9C 70 CMP:G.W @H'F69C, R0 ; refs ram_F69C in on_chip_ram; cycles=6 +3B8B: 27 08 BEQ loc_3B95 ; cycles=3/8 nt/t +3B8D: 15 F6 F0 C6 BSET.B #6, @H'F6F0 ; refs ram_F6F0 in on_chip_ram; cycles=8 +3B91: 1D F6 9C 90 MOV:G.W R0, @H'F69C ; refs ram_F69C in on_chip_ram; cycles=6 + +loc_3B95: +3B95: 15 F1 09 80 MOV:G.B @H'F109, R0 ; refs mem_F109 in program_or_external; cycles=6 +3B99: 15 F6 D0 70 CMP:G.B @H'F6D0, R0 ; refs ram_F6D0 in on_chip_ram; cycles=6 +3B9D: 27 08 BEQ loc_3BA7 ; cycles=3/8 nt/t +3B9F: 15 F6 F2 C0 BSET.B #0, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BA3: 15 F6 D0 90 MOV:G.B R0, @H'F6D0 ; refs ram_F6D0 in on_chip_ram; cycles=6 + +loc_3BA7: +3BA7: 15 F1 08 80 MOV:G.B @H'F108, R0 ; refs mem_F108 in program_or_external; cycles=6 +3BAB: 15 F6 D1 70 CMP:G.B @H'F6D1, R0 ; refs ram_F6D1 in on_chip_ram; cycles=6 +3BAF: 27 08 BEQ loc_3BB9 ; cycles=3/8 nt/t +3BB1: 15 F6 F2 C1 BSET.B #1, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BB5: 15 F6 D1 90 MOV:G.B R0, @H'F6D1 ; refs ram_F6D1 in on_chip_ram; cycles=6 + +loc_3BB9: +3BB9: 15 F1 07 80 MOV:G.B @H'F107, R0 ; refs mem_F107 in program_or_external; cycles=6 +3BBD: 15 F6 D2 70 CMP:G.B @H'F6D2, R0 ; refs ram_F6D2 in on_chip_ram; cycles=6 +3BC1: 27 08 BEQ loc_3BCB ; cycles=3/8 nt/t +3BC3: 15 F6 F2 C2 BSET.B #2, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BC7: 15 F6 D2 90 MOV:G.B R0, @H'F6D2 ; refs ram_F6D2 in on_chip_ram; cycles=6 + +loc_3BCB: +3BCB: 15 F1 06 80 MOV:G.B @H'F106, R0 ; refs mem_F106 in program_or_external; cycles=6 +3BCF: 15 F6 D3 70 CMP:G.B @H'F6D3, R0 ; refs ram_F6D3 in on_chip_ram; cycles=6 +3BD3: 27 08 BEQ loc_3BDD ; cycles=3/8 nt/t +3BD5: 15 F6 F2 C3 BSET.B #3, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BD9: 15 F6 D3 90 MOV:G.B R0, @H'F6D3 ; refs ram_F6D3 in on_chip_ram; cycles=6 + +loc_3BDD: +3BDD: 15 F1 05 80 MOV:G.B @H'F105, R0 ; refs mem_F105 in program_or_external; cycles=6 +3BE1: 15 F6 D4 70 CMP:G.B @H'F6D4, R0 ; refs ram_F6D4 in on_chip_ram; cycles=6 +3BE5: 27 08 BEQ loc_3BEF ; cycles=3/8 nt/t +3BE7: 15 F6 F2 C4 BSET.B #4, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BEB: 15 F6 D4 90 MOV:G.B R0, @H'F6D4 ; refs ram_F6D4 in on_chip_ram; cycles=6 + +loc_3BEF: +3BEF: 15 F1 04 80 MOV:G.B @H'F104, R0 ; refs mem_F104 in program_or_external; cycles=6 +3BF3: 15 F6 D5 70 CMP:G.B @H'F6D5, R0 ; refs ram_F6D5 in on_chip_ram; cycles=6 +3BF7: 27 08 BEQ loc_3C01 ; cycles=3/8 nt/t +3BF9: 15 F6 F2 C5 BSET.B #5, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3BFD: 15 F6 D5 90 MOV:G.B R0, @H'F6D5 ; refs ram_F6D5 in on_chip_ram; cycles=6 + +loc_3C01: +3C01: 15 F1 03 80 MOV:G.B @H'F103, R0 ; refs mem_F103 in program_or_external; cycles=6 +3C05: 15 F6 D6 70 CMP:G.B @H'F6D6, R0 ; refs ram_F6D6 in on_chip_ram; cycles=6 +3C09: 27 08 BEQ loc_3C13 ; cycles=3/8 nt/t +3C0B: 15 F6 F2 C6 BSET.B #6, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C0F: 15 F6 D6 90 MOV:G.B R0, @H'F6D6 ; refs ram_F6D6 in on_chip_ram; cycles=6 + +loc_3C13: +3C13: 15 F1 02 80 MOV:G.B @H'F102, R0 ; refs mem_F102 in program_or_external; cycles=6 +3C17: 15 F6 D7 70 CMP:G.B @H'F6D7, R0 ; refs ram_F6D7 in on_chip_ram; cycles=6 +3C1B: 27 08 BEQ loc_3C25 ; cycles=3/8 nt/t +3C1D: 15 F6 F2 C7 BSET.B #7, @H'F6F2 ; refs ram_F6F2 in on_chip_ram; cycles=8 +3C21: 15 F6 D7 90 MOV:G.B R0, @H'F6D7 ; refs ram_F6D7 in on_chip_ram; cycles=6 + +loc_3C25: +3C25: 15 F1 01 80 MOV:G.B @H'F101, R0 ; refs mem_F101 in program_or_external; cycles=6 +3C29: 15 F7 20 D1 BCLR.B #1, @H'F720 ; refs ram_F720 in on_chip_ram; cycles=8 + +loc_3C2D: +3C2D: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +3C2F: 0A RTE ; cycles=14 + +vec_irq3_3C30: +3C30: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +3C32: 15 F0 00 F1 BTST.B #1, @H'F000 ; refs mem_F000 in program_or_external; cycles=7 +3C36: 36 01 5D BNE loc_3D96 ; cycles=3/7 nt/t +3C39: 15 F0 0F 80 MOV:G.B @H'F00F, R0 ; refs mem_F00F in program_or_external; cycles=6 +3C3D: 40 A9 CMP:E #H'A9, R0 ; cycles=2 +3C3F: 27 08 BEQ loc_3C49 ; cycles=3/8 nt/t +3C41: 40 A8 CMP:E #H'A8, R0 ; cycles=2 +3C43: 37 00 85 BEQ loc_3CCB ; cycles=3/8 nt/t +3C46: 30 01 4D BRA loc_3D96 ; cycles=7 + +loc_3C49: +3C49: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3C4D: 04 C0 50 AND.B #H'C0, R0 ; cycles=3 +3C50: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3C54: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3C58: 1D F6 AA 70 CMP:G.W @H'F6AA, R0 ; refs ram_F6AA in on_chip_ram; cycles=7 +3C5C: 27 08 BEQ loc_3C66 ; cycles=3/7 nt/t +3C5E: 15 F6 F1 C5 BSET.B #5, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C62: 1D F6 AA 90 MOV:G.W R0, @H'F6AA ; refs ram_F6AA in on_chip_ram; cycles=7 + +loc_3C66: +3C66: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3C6A: 1D F6 A8 70 CMP:G.W @H'F6A8, R0 ; refs ram_F6A8 in on_chip_ram; cycles=7 +3C6E: 27 08 BEQ loc_3C78 ; cycles=3/7 nt/t +3C70: 15 F6 F1 C4 BSET.B #4, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C74: 1D F6 A8 90 MOV:G.W R0, @H'F6A8 ; refs ram_F6A8 in on_chip_ram; cycles=7 + +loc_3C78: +3C78: 1D F0 08 80 MOV:G.W @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3C7C: 1D F6 A6 70 CMP:G.W @H'F6A6, R0 ; refs ram_F6A6 in on_chip_ram; cycles=7 +3C80: 27 08 BEQ loc_3C8A ; cycles=3/7 nt/t +3C82: 15 F6 F1 C3 BSET.B #3, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C86: 1D F6 A6 90 MOV:G.W R0, @H'F6A6 ; refs ram_F6A6 in on_chip_ram; cycles=7 + +loc_3C8A: +3C8A: 1D F0 06 80 MOV:G.W @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3C8E: 1D F6 A4 70 CMP:G.W @H'F6A4, R0 ; refs ram_F6A4 in on_chip_ram; cycles=7 +3C92: 27 08 BEQ loc_3C9C ; cycles=3/7 nt/t +3C94: 15 F6 F1 C2 BSET.B #2, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3C98: 1D F6 A4 90 MOV:G.W R0, @H'F6A4 ; refs ram_F6A4 in on_chip_ram; cycles=7 + +loc_3C9C: +3C9C: 1D F0 04 80 MOV:G.W @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3CA0: 1D F6 A2 70 CMP:G.W @H'F6A2, R0 ; refs ram_F6A2 in on_chip_ram; cycles=7 +3CA4: 27 08 BEQ loc_3CAE ; cycles=3/7 nt/t +3CA6: 15 F6 F1 C1 BSET.B #1, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CAA: 1D F6 A2 90 MOV:G.W R0, @H'F6A2 ; refs ram_F6A2 in on_chip_ram; cycles=7 + +loc_3CAE: +3CAE: 1D F0 02 80 MOV:G.W @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3CB2: 1D F6 A0 70 CMP:G.W @H'F6A0, R0 ; refs ram_F6A0 in on_chip_ram; cycles=7 +3CB6: 27 08 BEQ loc_3CC0 ; cycles=3/7 nt/t +3CB8: 15 F6 F1 C0 BSET.B #0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CBC: 1D F6 A0 90 MOV:G.W R0, @H'F6A0 ; refs ram_F6A0 in on_chip_ram; cycles=7 + +loc_3CC0: +3CC0: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3CC4: 15 F7 21 D0 BCLR.B #0, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 +3CC8: 30 00 CB BRA loc_3D96 ; cycles=7 + +loc_3CCB: +3CCB: 15 F6 F1 80 MOV:G.B @H'F6F1, R0 ; refs ram_F6F1 in on_chip_ram; cycles=6 +3CCF: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3CD2: 15 F6 F1 90 MOV:G.B R0, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=7 +3CD6: 15 F6 F3 13 CLR.B @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3CDA: 1D F0 0C 80 MOV:G.W @H'F00C, R0 ; refs mem_F00C in program_or_external; cycles=7 +3CDE: 1D F6 AE 70 CMP:G.W @H'F6AE, R0 ; refs ram_F6AE in on_chip_ram; cycles=7 +3CE2: 27 08 BEQ loc_3CEC ; cycles=3/7 nt/t +3CE4: 15 F6 F1 C7 BSET.B #7, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CE8: 1D F6 AE 90 MOV:G.W R0, @H'F6AE ; refs ram_F6AE in on_chip_ram; cycles=7 + +loc_3CEC: +3CEC: 1D F0 0A 80 MOV:G.W @H'F00A, R0 ; refs mem_F00A in program_or_external; cycles=7 +3CF0: 1D F6 AC 70 CMP:G.W @H'F6AC, R0 ; refs ram_F6AC in on_chip_ram; cycles=7 +3CF4: 27 08 BEQ loc_3CFE ; cycles=3/7 nt/t +3CF6: 15 F6 F1 C6 BSET.B #6, @H'F6F1 ; refs ram_F6F1 in on_chip_ram; cycles=9 +3CFA: 1D F6 AC 90 MOV:G.W R0, @H'F6AC ; refs ram_F6AC in on_chip_ram; cycles=7 + +loc_3CFE: +3CFE: 15 F0 09 80 MOV:G.B @H'F009, R0 ; refs mem_F009 in program_or_external; cycles=7 +3D02: 15 F6 D8 70 CMP:G.B @H'F6D8, R0 ; refs ram_F6D8 in on_chip_ram; cycles=7 +3D06: 27 08 BEQ loc_3D10 ; cycles=3/7 nt/t +3D08: 15 F6 F3 C0 BSET.B #0, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D0C: 15 F6 D8 90 MOV:G.B R0, @H'F6D8 ; refs ram_F6D8 in on_chip_ram; cycles=7 + +loc_3D10: +3D10: 15 F0 08 80 MOV:G.B @H'F008, R0 ; refs mem_F008 in program_or_external; cycles=7 +3D14: 15 F6 D9 70 CMP:G.B @H'F6D9, R0 ; refs ram_F6D9 in on_chip_ram; cycles=7 +3D18: 27 08 BEQ loc_3D22 ; cycles=3/7 nt/t +3D1A: 15 F6 F3 C1 BSET.B #1, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D1E: 15 F6 D9 90 MOV:G.B R0, @H'F6D9 ; refs ram_F6D9 in on_chip_ram; cycles=7 + +loc_3D22: +3D22: 15 F0 07 80 MOV:G.B @H'F007, R0 ; refs mem_F007 in program_or_external; cycles=7 +3D26: 15 F6 DA 70 CMP:G.B @H'F6DA, R0 ; refs ram_F6DA in on_chip_ram; cycles=7 +3D2A: 27 08 BEQ loc_3D34 ; cycles=3/7 nt/t +3D2C: 15 F6 F3 C2 BSET.B #2, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D30: 15 F6 DA 90 MOV:G.B R0, @H'F6DA ; refs ram_F6DA in on_chip_ram; cycles=7 + +loc_3D34: +3D34: 15 F0 06 80 MOV:G.B @H'F006, R0 ; refs mem_F006 in program_or_external; cycles=7 +3D38: 15 F6 DB 70 CMP:G.B @H'F6DB, R0 ; refs ram_F6DB in on_chip_ram; cycles=7 +3D3C: 27 08 BEQ loc_3D46 ; cycles=3/7 nt/t +3D3E: 15 F6 F3 C3 BSET.B #3, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D42: 15 F6 DB 90 MOV:G.B R0, @H'F6DB ; refs ram_F6DB in on_chip_ram; cycles=7 + +loc_3D46: +3D46: 15 F0 05 80 MOV:G.B @H'F005, R0 ; refs mem_F005 in program_or_external; cycles=7 +3D4A: 15 F6 DC 70 CMP:G.B @H'F6DC, R0 ; refs ram_F6DC in on_chip_ram; cycles=7 +3D4E: 27 08 BEQ loc_3D58 ; cycles=3/7 nt/t +3D50: 15 F6 F3 C4 BSET.B #4, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D54: 15 F6 DC 90 MOV:G.B R0, @H'F6DC ; refs ram_F6DC in on_chip_ram; cycles=7 + +loc_3D58: +3D58: 15 F0 04 80 MOV:G.B @H'F004, R0 ; refs mem_F004 in program_or_external; cycles=7 +3D5C: 15 F6 DD 70 CMP:G.B @H'F6DD, R0 ; refs ram_F6DD in on_chip_ram; cycles=7 +3D60: 27 08 BEQ loc_3D6A ; cycles=3/7 nt/t +3D62: 15 F6 F3 C5 BSET.B #5, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D66: 15 F6 DD 90 MOV:G.B R0, @H'F6DD ; refs ram_F6DD in on_chip_ram; cycles=7 + +loc_3D6A: +3D6A: 15 F0 03 80 MOV:G.B @H'F003, R0 ; refs mem_F003 in program_or_external; cycles=7 +3D6E: 15 F6 DE 70 CMP:G.B @H'F6DE, R0 ; refs ram_F6DE in on_chip_ram; cycles=7 +3D72: 27 08 BEQ loc_3D7C ; cycles=3/7 nt/t +3D74: 15 F6 F3 C6 BSET.B #6, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D78: 15 F6 DE 90 MOV:G.B R0, @H'F6DE ; refs ram_F6DE in on_chip_ram; cycles=7 + +loc_3D7C: +3D7C: 15 F0 02 80 MOV:G.B @H'F002, R0 ; refs mem_F002 in program_or_external; cycles=7 +3D80: 15 F6 DF 70 CMP:G.B @H'F6DF, R0 ; refs ram_F6DF in on_chip_ram; cycles=7 +3D84: 27 08 BEQ loc_3D8E ; cycles=3/7 nt/t +3D86: 15 F6 F3 C7 BSET.B #7, @H'F6F3 ; refs ram_F6F3 in on_chip_ram; cycles=9 +3D8A: 15 F6 DF 90 MOV:G.B R0, @H'F6DF ; refs ram_F6DF in on_chip_ram; cycles=7 + +loc_3D8E: +3D8E: 15 F0 01 80 MOV:G.B @H'F001, R0 ; refs mem_F001 in program_or_external; cycles=7 +3D92: 15 F7 21 D1 BCLR.B #1, @H'F721 ; refs ram_F721 in on_chip_ram; cycles=9 + +loc_3D96: +3D96: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +3D98: 0A RTE ; cycles=13 + +vec_ad_adi_3D99: +3D99: 15 FE E8 D5 BCLR.B #5, @ADCSR ; clear ADST (bit 5) of ADCSR; cycles=8 +3D9D: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +3D9F: 15 F6 8A 80 MOV:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DA3: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3DA6: 1D FE E0 81 MOV:G.W @ADDRA_H, R1 ; ADDRA word read; TEMP byte-order hazard avoided; refs ADDRA_H in register_field; cycles=7 +3DAA: A1 10 SWAP.B R1 ; cycles=3 +3DAC: A1 12 EXTU.B R1 ; cycles=3 +3DAE: F1 CF B6 81 MOV:G.B @(-H'304A,R1), R1 ; cycles=7 +3DB2: A9 20 ADD:G.W R1, R0 ; cycles=3 +3DB4: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3DB7: 15 F6 8A 70 CMP:G.B @H'F68A, R0 ; refs ram_F68A in on_chip_ram; cycles=6 +3DBB: 27 4B BEQ loc_3E08 ; cycles=3/8 nt/t +3DBD: 15 F6 8A 82 MOV:G.B @H'F68A, R2 ; refs ram_F68A in on_chip_ram; cycles=6 +3DC1: 15 F6 8A 90 MOV:G.B R0, @H'F68A ; refs ram_F68A in on_chip_ram; cycles=6 +3DC5: 15 F7 31 04 03 CMP:G.B #H'03, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +3DCA: 22 3C BHI loc_3E08 ; cycles=3/7 nt/t +3DCC: A0 12 EXTU.B R0 ; cycles=3 +3DCE: A2 12 EXTU.B R2 ; cycles=3 +3DD0: 0C 01 01 A8 MULXU.W #H'0101, R0 ; cycles=25 +3DD4: 0C 01 01 AA MULXU.W #H'0101, R2 ; cycles=25 +3DD8: AB 31 SUB.W R3, R1 ; cycles=3 +3DDA: 1D E1 02 80 MOV:G.W @H'E102, R0 ; refs mem_E102 in program_or_external; cycles=7 +3DDE: A8 21 ADD:G.W R0, R1 ; cycles=3 +3DE0: A9 82 MOV:G.W R1, R2 ; cycles=3 +3DE2: 25 0C BCS loc_3DF0 ; cycles=3/7 nt/t +3DE4: A8 32 SUB.W R0, R2 ; cycles=3 +3DE6: 4A 80 00 CMP:I #H'8000, R2 ; cycles=3 +3DE9: 23 0F BLS loc_3DFA ; cycles=3/8 nt/t +3DEB: 59 00 00 MOV:I.W #H'0000, R1 ; dataflow R1=H'0000; cycles=3 +3DEE: 20 0A BRA loc_3DFA ; cycles=7 + +loc_3DF0: +3DF0: AA 30 SUB.W R2, R0 ; cycles=3 +3DF2: 48 80 00 CMP:I #H'8000, R0 ; cycles=3 +3DF5: 23 03 BLS loc_3DFA ; cycles=3/8 nt/t +3DF7: 59 FF FF MOV:I.W #H'FFFF, R1 ; dataflow R1=H'FFFF; cycles=3 + +loc_3DFA: +3DFA: 1D E1 02 71 CMP:G.W @H'E102, R1 ; refs mem_E102 in program_or_external; cycles=7 +3DFE: 27 08 BEQ loc_3E08 ; cycles=3/7 nt/t +3E00: 1D F6 8E 91 MOV:G.W R1, @H'F68E ; refs ram_F68E in on_chip_ram; cycles=7 +3E04: 15 F6 89 C7 BSET.B #7, @H'F689 ; refs ram_F689 in on_chip_ram; cycles=9 + +loc_3E08: +3E08: 15 F6 8B 80 MOV:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E0C: 04 14 A8 MULXU.B #H'14, R0 ; cycles=19 +3E0F: 1D FE E2 81 MOV:G.W @ADDRB_H, R1 ; ADDRB word read; TEMP byte-order hazard avoided; refs ADDRB_H in register_field; cycles=6 +3E13: A1 10 SWAP.B R1 ; cycles=3 +3E15: A1 12 EXTU.B R1 ; cycles=3 +3E17: A9 20 ADD:G.W R1, R0 ; cycles=3 +3E19: 04 15 B8 DIVXU.B #H'15, R0 ; cycles=23 +3E1C: 1D F6 8C 16 TST.W @H'F68C ; refs ram_F68C in on_chip_ram; cycles=7 +3E20: 27 06 BEQ loc_3E28 ; cycles=3/7 nt/t +3E22: 15 F6 8B 70 CMP:G.B @H'F68B, R0 ; refs ram_F68B in on_chip_ram; cycles=7 +3E26: 27 25 BEQ loc_3E4D ; cycles=3/7 nt/t + +loc_3E28: +3E28: 15 F6 8B 90 MOV:G.B R0, @H'F68B ; refs ram_F68B in on_chip_ram; cycles=7 +3E2C: A0 12 EXTU.B R0 ; cycles=3 +3E2E: A8 83 MOV:G.W R0, R3 ; cycles=3 +3E30: A3 AB MULXU.B R3, R3 ; cycles=18 +3E32: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +3E34: 0C 00 C8 BA DIVXU.W #H'00C8, R2 ; cycles=29 +3E38: 04 04 A8 MULXU.B #H'04, R0 ; cycles=19 +3E3B: 0C 00 AB 20 ADD:G.W #H'00AB, R0 ; cycles=4 +3E3F: AB 20 ADD:G.W R3, R0 ; cycles=3 +3E41: 15 FE 8E F4 BTST.B #4, @P7DR ; refs P7DR in register_field; cycles=6 +3E45: 26 02 BNE loc_3E49 ; cycles=3/8 nt/t +3E47: A8 1B SHLR.W R0 ; cycles=3 + +loc_3E49: +3E49: 1D F6 8C 90 MOV:G.W R0, @H'F68C ; refs ram_F68C in on_chip_ram; cycles=6 + +loc_3E4D: +3E4D: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 +3E4F: 15 FE E8 D7 BCLR.B #7, @ADCSR ; clear ADF (bit 7) of ADCSR; cycles=8 +3E53: 0A RTE ; cycles=14 + +loc_3E54: +3E54: A2 F7 BTST.B #7, R2 ; cycles=2 +3E56: 27 42 BEQ loc_3E9A ; cycles=3/7 nt/t +3E58: 15 F9 B5 80 MOV:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=7 +3E5C: A0 12 EXTU.B R0 ; cycles=3 +3E5E: A8 1A SHLL.W R0 ; cycles=3 +3E60: 15 F9 B0 81 MOV:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E64: A1 12 EXTU.B R1 ; cycles=3 +3E66: A9 1A SHLL.W R1 ; cycles=3 + +loc_3E68: +3E68: A0 71 CMP:G.B R0, R1 ; cycles=2 +3E6A: 27 0A BEQ loc_3E76 ; cycles=3/7 nt/t +3E6C: F8 F8 70 73 CMP:G.W @(-H'0790,R0), R3 ; cycles=7 +3E70: 27 28 BEQ loc_3E9A ; cycles=3/7 nt/t +3E72: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3E74: 20 F2 BRA loc_3E68 ; cycles=7 + +loc_3E76: +3E76: F9 F8 70 93 MOV:G.W R3, @(-H'0790,R1) ; cycles=7 +3E7A: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +3E7E: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_3E82: +3E82: 15 F9 B0 80 MOV:G.B @H'F9B0, R0 ; refs ram_F9B0 in on_chip_ram; cycles=7 +3E86: A0 08 ADD:Q.B #1, R0 ; cycles=4 +3E88: 04 7F 50 AND.B #H'7F, R0 ; cycles=3 +3E8B: 15 F9 B5 70 CMP:G.B @H'F9B5, R0 ; refs ram_F9B5 in on_chip_ram; cycles=6 +3E8F: 26 09 BNE loc_3E9A ; cycles=3/8 nt/t +3E91: 12 0C STM.W {R2,R3}, @-SP ; cycles=12 +3E93: 1E 01 3D BSR loc_3FD3 ; cycles=14 +3E96: 02 0C LDM.W @SP+, {R2,R3} ; cycles=14 +3E98: 20 E8 BRA loc_3E82 ; cycles=7 + +loc_3E9A: +3E9A: A2 F6 BTST.B #6, R2 ; cycles=2 +3E9C: 27 2D BEQ loc_3ECB ; cycles=3/7 nt/t +3E9E: 15 F9 B9 80 MOV:G.B @H'F9B9, R0 ; refs ram_F9B9 in on_chip_ram; cycles=7 +3EA2: A0 12 EXTU.B R0 ; cycles=3 +3EA4: A8 1A SHLL.W R0 ; cycles=3 +3EA6: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +3EAA: A1 12 EXTU.B R1 ; cycles=3 +3EAC: A9 1A SHLL.W R1 ; cycles=3 + +loc_3EAE: +3EAE: A0 71 CMP:G.B R0, R1 ; cycles=2 +3EB0: 27 0D BEQ loc_3EBF ; cycles=3/7 nt/t +3EB2: F8 F9 70 73 CMP:G.W @(-H'0690,R0), R3 ; cycles=7 +3EB6: 27 13 BEQ loc_3ECB ; cycles=3/7 nt/t +3EB8: A0 09 ADD:Q.B #2, R0 ; cycles=4 +3EBA: 04 3F 50 AND.B #H'3F, R0 ; cycles=3 +3EBD: 20 EF BRA loc_3EAE ; cycles=8 + +loc_3EBF: +3EBF: F9 F9 70 93 MOV:G.W R3, @(-H'0690,R1) ; cycles=6 +3EC3: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +3EC7: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_3ECB: +3ECB: 19 RTS ; cycles=13 + +loc_3ECC: +3ECC: 12 1F STM.W {R0,R1,R2,R3,R4}, @-SP ; cycles=21 +3ECE: A5 12 EXTU.B R5 ; cycles=3 +3ED0: 45 03 CMP:E #H'03, R5 ; cycles=2 +3ED2: 23 05 BLS loc_3ED9 ; cycles=3/7 nt/t +3ED4: 1E 00 69 BSR loc_3F40 ; cycles=13 +3ED7: 20 4C BRA loc_3F25 ; cycles=8 + +loc_3ED9: +3ED9: A5 83 MOV:G.B R5, R3 ; cycles=2 +3EDB: 45 00 CMP:E #H'00, R5 ; cycles=2 +3EDD: 27 0A BEQ loc_3EE9 ; cycles=3/8 nt/t +3EDF: 45 01 CMP:E #H'01, R5 ; cycles=2 +3EE1: 27 0B BEQ loc_3EEE ; cycles=3/8 nt/t +3EE3: 45 02 CMP:E #H'02, R5 ; cycles=2 +3EE5: 27 0C BEQ loc_3EF3 ; cycles=3/8 nt/t +3EE7: 20 0F BRA loc_3EF8 ; cycles=8 + +loc_3EE9: +3EE9: 5D 00 80 MOV:I.W #H'0080, R5 ; dataflow R5=H'0080; cycles=3 +3EEC: 20 0D BRA loc_3EFB ; cycles=7 + +loc_3EEE: +3EEE: 5D 00 C0 MOV:I.W #H'00C0, R5 ; dataflow R5=H'00C0; cycles=3 +3EF1: 20 08 BRA loc_3EFB ; cycles=8 + +loc_3EF3: +3EF3: 5D 00 90 MOV:I.W #H'0090, R5 ; dataflow R5=H'0090; cycles=3 +3EF6: 20 03 BRA loc_3EFB ; cycles=7 + +loc_3EF8: +3EF8: 5D 00 D0 MOV:I.W #H'00D0, R5 ; dataflow R5=H'00D0; cycles=3 + +loc_3EFB: +3EFB: 04 10 AB MULXU.B #H'10, R3 ; cycles=19 +3EFE: 0C FA B0 23 ADD:G.W #H'FAB0, R3 ; cycles=4 +3F02: A9 13 CLR.W R1 ; dataflow R1=H'0000; cycles=3 + +loc_3F04: +3F04: F1 FA F0 82 MOV:G.B @(-H'0510,R1), R2 ; cycles=7 +3F08: D3 72 CMP:G.B @R3, R2 ; cycles=6 +3F0A: 27 04 BEQ loc_3F10 ; cycles=3/7 nt/t +3F0C: D3 92 MOV:G.B R2, @R3 ; cycles=6 +3F0E: 0E 18 BSR loc_3F28 ; cycles=13 + +loc_3F10: +3F10: A1 08 ADD:Q.B #1, R1 ; cycles=4 +3F12: A3 08 ADD:Q.B #1, R3 ; cycles=4 +3F14: 41 10 CMP:E #H'10, R1 ; cycles=2 +3F16: 27 02 BEQ loc_3F1A ; cycles=3/7 nt/t +3F18: 20 EA BRA loc_3F04 ; cycles=7 + +loc_3F1A: +3F1A: 1D FB 00 07 00 E0 MOV:G.W #H'00E0, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=11 +3F20: 5C 00 E0 MOV:I.W #H'00E0, R4 ; dataflow R4=H'00E0; cycles=3 +3F23: 0E 1B BSR loc_3F40 ; cycles=14 + +loc_3F25: +3F25: 02 1F LDM.W @SP+, {R0,R1,R2,R3,R4} ; cycles=26 +3F27: 19 RTS ; cycles=13 + +loc_3F28: +3F28: AD 84 MOV:G.W R5, R4 ; cycles=3 +3F2A: A1 24 ADD:G.B R1, R4 ; cycles=2 +3F2C: 1D FB 00 74 CMP:G.W @H'FB00, R4 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F30: 27 06 BEQ loc_3F38 ; cycles=3/7 nt/t +3F32: 1D FB 00 94 MOV:G.W R4, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=7 +3F36: 0E 08 BSR loc_3F40 ; cycles=13 + +loc_3F38: +3F38: 5C 02 00 MOV:I.W #H'0200, R4 ; dataflow R4=H'0200; cycles=3 +3F3B: A2 24 ADD:G.B R2, R4 ; cycles=2 +3F3D: 0E 01 BSR loc_3F40 ; cycles=14 +3F3F: 19 RTS ; cycles=13 + +loc_3F40: +3F40: BF 98 STC.W SR, @-R7 ; cycles=8 +3F42: 0C 00 FF 58 ANDC.W #H'00FF, SR ; cycles=4 +3F46: 0C 06 00 48 ORC.W #H'0600, SR ; cycles=4 + +loc_3F4A: +3F4A: 15 F2 00 00 80 MOVFPE.B @H'F200, R0 ; LCD status read from E-clock H'F200; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; refs mem_F200 in program_or_external; cycles=13 +3F4F: A0 F7 BTST.B #7, R0 ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=2 +3F51: 26 F7 BNE loc_3F4A ; LCD busy-flag poll: read H'F200, test bit 7, branch until clear; cycles=3/8 nt/t +3F53: AC F8 BTST.W #8, R4 ; cycles=3 +3F55: 26 16 BNE loc_3F6D ; cycles=3/8 nt/t +3F57: AC F9 BTST.W #9, R4 ; cycles=3 +3F59: 26 07 BNE loc_3F62 ; cycles=3/8 nt/t +3F5B: 15 F2 00 00 94 MOVTPE.B R4, @H'F200 ; LCD command/address write to E-clock H'F200; refs mem_F200 in program_or_external; cycles=13 +3F60: 20 10 BRA loc_3F72 ; cycles=7 + +loc_3F62: +3F62: 15 F2 01 00 94 MOVTPE.B R4, @H'F201 ; LCD data write to E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 +3F67: 1D FB 00 08 ADD:Q.W #1, @H'FB00 ; refs ram_FB00 in on_chip_ram; cycles=8 +3F6B: 20 05 BRA loc_3F72 ; cycles=8 + +loc_3F6D: +3F6D: 15 F2 01 00 84 MOVFPE.B @H'F201, R4 ; LCD data read from E-clock H'F201; refs mem_F201 in program_or_external; cycles=13 + +loc_3F72: +3F72: CF 88 LDC.W @R7+, SR ; cycles=7 +3F74: 19 RTS ; cycles=12 + +loc_3F76: +3F76: 58 27 10 MOV:I.W #H'2710, R0 ; dataflow R0=H'2710; cycles=3 +3F79: 59 C3 50 MOV:I.W #H'C350, R1 ; dataflow R1=H'C350; cycles=3 + +loc_3F7C: +3F7C: 15 FE 82 D7 BCLR.B #7, @P1DR ; clear bit 7 of P1DR; cycles=9 +3F80: 01 B8 F9 SCB/F R0, loc_3F7C ; cycles=3/4/8 false/-1/t + +loc_3F83: +3F83: 15 FE 82 C7 BSET.B #7, @P1DR ; set bit 7 of P1DR; cycles=8 +3F87: 01 B9 F9 SCB/F R1, loc_3F83 ; cycles=3/4/9 false/-1/t +3F8A: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_3F8C: +3F8C: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=9 +3F90: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=9 +3F94: F8 F6 80 13 CLR.W @(-H'0980,R0) ; cycles=9 +3F98: A8 09 ADD:Q.W #2, R0 ; cycles=4 +3F9A: 48 08 00 CMP:I #H'0800, R0 ; cycles=3 +3F9D: 26 ED BNE loc_3F8C ; cycles=3/8 nt/t +3F9F: 1E 03 6A BSR loc_430C ; cycles=14 +3FA2: 1E 03 7F BSR loc_4324 ; cycles=13 +3FA5: 1E 00 EE BSR loc_4096 ; cycles=14 +3FA8: 1E 01 10 BSR loc_40BB ; cycles=13 +3FAB: 1E 02 69 BSR loc_4217 ; cycles=14 +3FAE: 1E 03 9B BSR loc_434C ; cycles=13 + +loc_3FB1: +3FB1: 1D FE EC 07 5A 00 MOV:G.W #H'5A00, @WDT_TCSR_R ; WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00); cycles=9 +3FB7: 15 F7 94 13 CLR.B @H'F794 ; refs ram_F794 in on_chip_ram; cycles=8 +3FBB: 0E 16 BSR loc_3FD3 ; cycles=14 +3FBD: 1E 7B EB BSR loc_BBAB ; cycles=14 +3FC0: 0E 2D BSR loc_3FEF ; cycles=13 +3FC2: 1E 00 81 BSR loc_4046 ; cycles=13 +3FC5: 1E 7E D6 BSR loc_BE9E ; cycles=14 +3FC8: 1E E8 3B BSR loc_2806 ; cycles=13 +3FCB: 1E F9 62 BSR loc_3930 ; cycles=14 +3FCE: 1E D6 0F BSR loc_15E0 ; cycles=13 +3FD1: 20 DE BRA loc_3FB1 ; cycles=8 + +loc_3FD3: +3FD3: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +3FD7: 26 15 BNE loc_3FEE ; cycles=3/8 nt/t +3FD9: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +3FDD: 27 06 BEQ loc_3FE5 ; cycles=3/8 nt/t +3FDF: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +3FE3: 26 09 BNE loc_3FEE ; cycles=3/8 nt/t + +loc_3FE5: +3FE5: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=6 +3FE9: 26 03 BNE loc_3FEE ; cycles=3/8 nt/t +3FEB: 1E 7B 04 BSR loc_BAF2 ; cycles=14 + +loc_3FEE: +3FEE: 19 RTS ; cycles=12 + +loc_3FEF: +3FEF: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +3FF3: 26 12 BNE loc_4007 ; cycles=3/8 nt/t +3FF5: 15 F9 B5 13 CLR.B @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +3FF9: 15 F9 B0 13 CLR.B @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=8 +3FFD: 15 FA A5 D7 BCLR.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 +4001: 27 08 BEQ loc_400B ; cycles=3/8 nt/t +4003: 0E 07 BSR loc_400C ; cycles=14 +4005: 20 04 BRA loc_400B ; cycles=8 + +loc_4007: +4007: 15 FA A5 C7 BSET.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=8 + +loc_400B: +400B: 19 RTS ; cycles=13 + +loc_400C: +400C: 15 F7 30 13 CLR.B @H'F730 ; refs ram_F730 in on_chip_ram; cycles=9 +4010: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=9 +4014: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=9 +4018: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=9 +401C: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=9 +4020: 1D F7 32 13 CLR.W @H'F732 ; refs ram_F732 in on_chip_ram; cycles=9 +4024: 1D F7 5C 13 CLR.W @H'F75C ; refs ram_F75C in on_chip_ram; cycles=9 +4028: 15 FB 03 13 CLR.B @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +402C: 1D E0 46 13 CLR.W @H'E046 ; refs mem_E046 in program_or_external; cycles=9 +4030: 1D F7 6A 13 CLR.W @H'F76A ; refs ram_F76A in on_chip_ram; cycles=9 +4034: 15 F7 91 13 CLR.B @H'F791 ; refs ram_F791 in on_chip_ram; cycles=9 +4038: 15 F7 95 13 CLR.B @H'F795 ; refs ram_F795 in on_chip_ram; cycles=9 +403C: 15 F7 6E 13 CLR.B @H'F76E ; refs ram_F76E in on_chip_ram; cycles=9 +4040: 0E 33 BSR loc_4075 ; cycles=13 +4042: 1E 01 D2 BSR loc_4217 ; cycles=13 +4045: 19 RTS ; cycles=13 + +loc_4046: +4046: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=7 +404A: 26 0C BNE loc_4058 ; cycles=3/7 nt/t +404C: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +4050: 27 07 BEQ loc_4059 ; cycles=3/7 nt/t +4052: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +4056: 27 01 BEQ loc_4059 ; cycles=3/7 nt/t + +loc_4058: +4058: 19 RTS ; cycles=12 + +loc_4059: +4059: 15 F9 B0 82 MOV:G.B @H'F9B0, R2 ; refs ram_F9B0 in on_chip_ram; cycles=6 +405D: A2 12 EXTU.B R2 ; cycles=3 +405F: 15 F9 B5 72 CMP:G.B @H'F9B5, R2 ; refs ram_F9B5 in on_chip_ram; cycles=6 +4063: 26 0F BNE loc_4074 ; cycles=3/8 nt/t +4065: A2 1A SHLL.B R2 ; cycles=2 +4067: FA F8 70 06 00 MOV:G.W #H'00, @(-H'0790,R2) ; cycles=11 +406C: 15 F9 B0 08 ADD:Q.B #1, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 +4070: 15 F9 B0 D7 BCLR.B #7, @H'F9B0 ; refs ram_F9B0 in on_chip_ram; cycles=9 + +loc_4074: +4074: 19 RTS ; cycles=12 + +loc_4075: +4075: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 + +loc_4077: +4077: F8 E0 00 13 CLR.W @(-H'2000,R0) ; cycles=8 +407B: F8 E4 00 13 CLR.W @(-H'1C00,R0) ; cycles=8 +407F: F8 E8 00 13 CLR.W @(-H'1800,R0) ; cycles=8 +4083: 48 02 00 CMP:I #H'0200, R0 ; cycles=3 +4086: 24 04 BCC loc_408C ; cycles=3/7 nt/t +4088: F8 EC 00 13 CLR.W @(-H'1400,R0) ; cycles=9 + +loc_408C: +408C: A8 09 ADD:Q.W #2, R0 ; cycles=4 +408E: 48 04 00 CMP:I #H'0400, R0 ; cycles=3 +4091: 26 E4 BNE loc_4077 ; cycles=3/8 nt/t +4093: 0E 01 BSR loc_4096 ; cycles=14 +4095: 19 RTS ; cycles=13 + +loc_4096: +4096: 1D E0 00 07 00 80 MOV:G.W #H'0080, @H'E000 ; refs mem_E000 in program_or_external; cycles=11 +409C: 1D E0 06 07 80 00 MOV:G.W #H'8000, @H'E006 ; refs mem_E006 in program_or_external; cycles=11 +40A2: 1D E0 80 07 FF FF MOV:G.W #H'FFFF, @H'E080 ; refs mem_E080 in program_or_external; cycles=11 +40A8: 1D E8 00 07 00 80 MOV:G.W #H'0080, @H'E800 ; refs mem_E800 in program_or_external; cycles=11 +40AE: 1D E8 06 07 80 00 MOV:G.W #H'8000, @H'E806 ; refs mem_E806 in program_or_external; cycles=11 +40B4: 1D E8 80 07 FF FF MOV:G.W #H'FFFF, @H'E880 ; refs mem_E880 in program_or_external; cycles=11 +40BA: 19 RTS ; cycles=12 + +loc_40BB: +40BB: 58 00 40 MOV:I.W #H'0040, R0 ; dataflow R0=H'0040; cycles=3 + +loc_40BE: +40BE: F8 F8 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0792,R0) ; cycles=9 +40C4: F8 F8 AE 07 FF FF MOV:G.W #H'FFFF, @(-H'0752,R0) ; cycles=9 +40CA: F8 F8 EE 07 FF FF MOV:G.W #H'FFFF, @(-H'0712,R0) ; cycles=9 +40D0: F8 F9 2E 07 FF FF MOV:G.W #H'FFFF, @(-H'06D2,R0) ; cycles=9 +40D6: F8 F9 6E 07 FF FF MOV:G.W #H'FFFF, @(-H'0692,R0) ; cycles=9 +40DC: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +40DE: 26 DE BNE loc_40BE ; cycles=3/7 nt/t +40E0: 15 F9 C4 06 14 MOV:G.B #H'14, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +40E5: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +40EA: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +40EF: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +40F4: 15 FE 8E F7 BTST.B #7, @P7DR ; refs P7DR in register_field; cycles=7 +40F8: 27 09 BEQ loc_4103 ; cycles=3/7 nt/t +40FA: 1D F4 02 05 6B 6F CMP:G.W #H'6B6F, @H'F402 ; refs mem_F402 in program_or_external; cycles=7 +4100: 37 00 AD BEQ loc_41B0 ; cycles=3/7 nt/t + +loc_4103: +4103: 58 01 00 MOV:I.W #H'0100, R0 ; dataflow R0=H'0100; cycles=3 + +loc_4106: +4106: A8 0D ADD:Q.W #-2, R0 ; cycles=4 +4108: F8 C9 64 85 MOV:G.W @(-H'369C,R0), R5 ; cycles=7 +410C: F8 F4 00 95 MOV:G.W R5, @(-H'0C00,R0) ; cycles=7 +4110: BF 90 MOV:G.W R0, @-R7 ; cycles=6 +4112: A8 84 MOV:G.W R0, R4 ; cycles=3 +4114: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4117: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +411B: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +411E: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4122: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4125: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4129: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +412C: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4130: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4133: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4137: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +413A: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +413E: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4141: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4145: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4148: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +414C: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +414F: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4153: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4156: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +415A: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +415D: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4161: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4164: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4168: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +416B: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +416F: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4172: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +4176: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4179: 0C 01 00 24 ADD:G.W #H'0100, R4 ; cycles=4 +417D: 18 BF E0 JSR @loc_BFE0 ; cycles=14 +4180: CF 80 MOV:G.W @R7+, R0 ; cycles=5 +4182: 26 82 BNE loc_4106 ; cycles=3/7 nt/t +4184: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_4187: +4187: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +4189: A8 84 MOV:G.W R0, R4 ; cycles=3 +418B: A4 10 SWAP.B R4 ; cycles=3 +418D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4190: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +4193: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4195: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +4198: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +419B: AC 09 ADD:Q.W #2, R4 ; cycles=4 +419D: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A0: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41A3: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41A5: 5D 20 20 MOV:I.W #H'2020, R5 ; dataflow R5=H'2020; cycles=3 +41A8: 18 BF E0 JSR @loc_BFE0 ; cycles=13 +41AB: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +41AD: 01 B8 D7 SCB/F R0, loc_4187 ; cycles=3/4/9 false/-1/t + +loc_41B0: +41B0: 20 20 BRA loc_41D2 ; cycles=7 + +loc_41D2: +41D2: 58 00 0F MOV:I.W #H'000F, R0 ; dataflow R0=H'000F; cycles=3 + +loc_41D5: +41D5: A8 81 MOV:G.W R0, R1 ; cycles=3 +41D7: A1 1A SHLL.B R1 ; cycles=2 +41D9: A1 1A SHLL.B R1 ; cycles=2 +41DB: A1 1A SHLL.B R1 ; cycles=2 +41DD: A8 84 MOV:G.W R0, R4 ; cycles=3 +41DF: A4 10 SWAP.B R4 ; cycles=3 +41E1: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41E3: 18 BF FE JSR @loc_BFFE ; cycles=14 +41E6: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41E8: F9 F7 B0 95 MOV:G.W R5, @(-H'0850,R1) ; cycles=7 +41EC: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41EE: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41F0: 18 BF FE JSR @loc_BFFE ; cycles=13 +41F3: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +41F5: F9 F7 B2 95 MOV:G.W R5, @(-H'084E,R1) ; cycles=6 +41F9: AC 09 ADD:Q.W #2, R4 ; cycles=4 +41FB: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +41FD: 18 BF FE JSR @loc_BFFE ; cycles=14 +4200: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +4202: F9 F7 B4 95 MOV:G.W R5, @(-H'084C,R1) ; cycles=7 +4206: AC 09 ADD:Q.W #2, R4 ; cycles=4 +4208: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +420A: 18 BF FE JSR @loc_BFFE ; cycles=13 +420D: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +420F: F9 F7 B6 95 MOV:G.W R5, @(-H'084A,R1) ; cycles=6 +4213: 01 B8 BF SCB/F R0, loc_41D5 ; cycles=3/4/9 false/-1/t +4216: 19 RTS ; cycles=12 + +loc_4217: +4217: 15 F7 98 13 CLR.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +421B: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +421F: 15 FE 82 D2 BCLR.B #2, @P1DR ; clear bit 2 of P1DR; cycles=8 +4223: 1D F7 00 07 24 24 MOV:G.W #H'2424, @H'F700 ; refs ram_F700 in on_chip_ram; cycles=9 +4229: 1D F7 02 07 24 24 MOV:G.W #H'2424, @H'F702 ; refs ram_F702 in on_chip_ram; cycles=9 +422F: 1D F7 04 07 24 24 MOV:G.W #H'2424, @H'F704 ; refs ram_F704 in on_chip_ram; cycles=9 +4235: 1D F7 06 07 24 24 MOV:G.W #H'2424, @H'F706 ; refs ram_F706 in on_chip_ram; cycles=9 +423B: 15 F7 08 06 7F MOV:G.B #H'7F, @H'F708 ; refs ram_F708 in on_chip_ram; cycles=9 +4240: 15 F7 09 06 24 MOV:G.B #H'24, @H'F709 ; refs ram_F709 in on_chip_ram; cycles=9 +4245: 1D F7 0A 07 24 24 MOV:G.W #H'2424, @H'F70A ; refs ram_F70A in on_chip_ram; cycles=9 +424B: 15 F7 10 13 CLR.B @H'F710 ; refs ram_F710 in on_chip_ram; cycles=8 +424F: 15 F7 11 13 CLR.B @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +4253: 15 F7 12 13 CLR.B @H'F712 ; refs ram_F712 in on_chip_ram; cycles=8 +4257: 15 F7 13 13 CLR.B @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +425B: 15 F7 14 13 CLR.B @H'F714 ; refs ram_F714 in on_chip_ram; cycles=8 +425F: 15 F7 15 13 CLR.B @H'F715 ; refs ram_F715 in on_chip_ram; cycles=8 +4263: 15 F7 16 13 CLR.B @H'F716 ; refs ram_F716 in on_chip_ram; cycles=8 +4267: 15 F7 17 13 CLR.B @H'F717 ; refs ram_F717 in on_chip_ram; cycles=8 +426B: 15 F7 18 06 FF MOV:G.B #H'FF, @H'F718 ; refs ram_F718 in on_chip_ram; cycles=9 +4270: 15 F7 19 06 FF MOV:G.B #H'FF, @H'F719 ; refs ram_F719 in on_chip_ram; cycles=9 +4275: 15 F7 1A 06 FF MOV:G.B #H'FF, @H'F71A ; refs ram_F71A in on_chip_ram; cycles=9 +427A: 15 F7 1B 06 FF MOV:G.B #H'FF, @H'F71B ; refs ram_F71B in on_chip_ram; cycles=9 +427F: 15 F7 1C 06 FF MOV:G.B #H'FF, @H'F71C ; refs ram_F71C in on_chip_ram; cycles=9 +4284: 15 F7 1D 06 FF MOV:G.B #H'FF, @H'F71D ; refs ram_F71D in on_chip_ram; cycles=9 +4289: 15 F7 1E 06 FF MOV:G.B #H'FF, @H'F71E ; refs ram_F71E in on_chip_ram; cycles=9 +428E: 15 F7 1F 06 FF MOV:G.B #H'FF, @H'F71F ; refs ram_F71F in on_chip_ram; cycles=9 +4293: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +4299: 1D FA F2 07 4F 4E MOV:G.W #H'4F4E, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +429F: 1D FA F4 07 4E 45 MOV:G.W #H'4E45, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42A5: 1D FA F6 07 43 54 MOV:G.W #H'4354, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42AB: 1D FA F8 07 3A 4E MOV:G.W #H'3A4E, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42B1: 1D FA FA 07 4F 54 MOV:G.W #H'4F54, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42B7: 1D FA FC 07 20 41 MOV:G.W #H'2041, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42BD: 1D FA FE 07 43 54 MOV:G.W #H'4354, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42C3: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +42C6: 1E FC 03 BSR loc_3ECC ; cycles=13 +42C9: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +42CF: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +42D5: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +42DB: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +42E1: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +42E7: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +42ED: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +42F3: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +42F9: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +42FC: 1E FB CD BSR loc_3ECC ; cycles=13 +42FF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +4302: 1E FB C7 BSR loc_3ECC ; cycles=13 +4305: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +4308: 1E FB C1 BSR loc_3ECC ; cycles=13 +430B: 19 RTS ; cycles=13 + +loc_430C: +430C: 15 FE 8B D0 BCLR.B #0, @P6DR ; clear bit 0 of P6DR; cycles=9 +4310: 15 F5 55 06 AA MOV:G.B #H'AA, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +4315: 15 F4 AA 06 55 MOV:G.B #H'55, @H'F4AA ; refs mem_F4AA in program_or_external; cycles=9 +431A: 15 F5 55 06 CC MOV:G.B #H'CC, @H'F555 ; refs mem_F555 in program_or_external; cycles=9 +431F: 15 FE 8B C0 BSET.B #0, @P6DR ; set bit 0 of P6DR; cycles=8 +4323: 19 RTS ; cycles=13 + +loc_4324: +4324: 5C 00 38 MOV:I.W #H'0038, R4 ; dataflow R4=H'0038; cycles=3 +4327: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +432A: 1E FB 9F BSR loc_3ECC ; cycles=13 +432D: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 +4330: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4333: 1E FB 96 BSR loc_3ECC ; cycles=14 +4336: 5C 00 0E MOV:I.W #H'000E, R4 ; dataflow R4=H'000E; cycles=3 +4339: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +433C: 1E FB 8D BSR loc_3ECC ; cycles=13 +433F: 5C 00 06 MOV:I.W #H'0006, R4 ; dataflow R4=H'0006; cycles=3 +4342: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +4345: 1E FB 84 BSR loc_3ECC ; cycles=14 +4348: 1E CD 83 BSR loc_10CE ; cycles=13 +434B: 19 RTS ; cycles=13 + +loc_434C: +434C: 15 FF 00 06 70 MOV:G.B #H'70, @IPRA ; IPRA = H'70 (irq0 priority=7; irq1 priority=0); cycles=9 +4351: 15 FF 01 06 44 MOV:G.B #H'44, @IPRB ; IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4); cycles=9 +4356: 15 FF 02 06 66 MOV:G.B #H'66, @IPRC ; IPRC = H'66 (FRT1 priority=6; FRT2 priority=6); cycles=9 +435B: 15 FF 03 06 00 MOV:G.B #H'00, @IPRD ; IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0); cycles=9 +4360: 15 FF 04 06 50 MOV:G.B #H'50, @IPRE ; IPRE = H'50 (SCI1 priority=5; SCI2 priority=0); cycles=9 +4365: 15 FF 05 06 40 MOV:G.B #H'40, @IPRF ; IPRF = H'40 (A/D priority=4); cycles=9 +436A: 15 FE DA C6 BSET.B #6, @SCI1_SCR ; set RIE (bit 6) of SCI1_SCR; enable SCI1 receive and receive-error interrupts (RIE); SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +436E: 15 FE 90 C5 BSET.B #5, @FRT1_TCR ; set OCIEA (bit 5) of FRT1_TCR; cycles=9 +4372: 15 FE A0 C5 BSET.B #5, @FRT2_TCR ; set OCIEA (bit 5) of FRT2_TCR; cycles=9 +4376: 15 FE E8 C6 BSET.B #6, @ADCSR ; set ADIE (bit 6) of ADCSR; cycles=9 +437A: 15 FE FD C4 BSET.B #4, @SYSCR2 ; set IRQ3E (bit 4) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +437E: 15 FE FD C5 BSET.B #5, @SYSCR2 ; set IRQ4E (bit 5) of SYSCR2; SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96; cycles=9 +4382: 15 FE 8E F6 BTST.B #6, @P7DR ; refs P7DR in register_field; cycles=7 +4386: 27 06 BEQ loc_438E ; cycles=3/7 nt/t +4388: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 + +loc_438E: +438E: 0C 03 00 88 LDC.W #H'0300, SR ; dataflow SR=H'0300; cycles=6 +4392: 19 RTS ; cycles=12 + +vec_nmi_4393: +4393: 0A RTE ; cycles=14 + +loc_4394: +4394: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +4399: 32 00 86 BHI loc_4422 ; cycles=3/8 nt/t +439C: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +43A0: 36 00 7F BNE loc_4422 ; cycles=3/7 nt/t +43A3: 1D F7 36 83 MOV:G.W @H'F736, R3 ; refs ram_F736 in on_chip_ram; cycles=6 +43A7: 37 00 78 BEQ loc_4422 ; cycles=3/8 nt/t +43AA: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +43AE: 1D F6 BE 34 SUB.W @H'F6BE, R4 ; refs ram_F6BE in on_chip_ram; cycles=7 +43B2: AB DF BCLR.W #15, R3 ; cycles=3 +43B4: 26 19 BNE loc_43CF ; cycles=3/7 nt/t +43B6: AB DE BCLR.W #14, R3 ; cycles=3 +43B8: 26 21 BNE loc_43DB ; cycles=3/7 nt/t +43BA: AB DD BCLR.W #13, R3 ; cycles=3 +43BC: 26 29 BNE loc_43E7 ; cycles=3/7 nt/t +43BE: AB DC BCLR.W #12, R3 ; cycles=3 +43C0: 26 31 BNE loc_43F3 ; cycles=3/7 nt/t +43C2: AB DB BCLR.W #11, R3 ; cycles=3 +43C4: 26 39 BNE loc_43FF ; cycles=3/7 nt/t +43C6: AB DA BCLR.W #10, R3 ; cycles=3 +43C8: 26 43 BNE loc_440D ; cycles=3/7 nt/t +43CA: 1E D5 D5 BSR loc_19A2 ; cycles=13 +43CD: 20 53 BRA loc_4422 ; cycles=8 + +loc_43CF: +43CF: 0E 5E BSR loc_442F ; cycles=14 +43D1: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43D4: 27 03 BEQ loc_43D9 ; cycles=3/7 nt/t +43D6: 1E D6 5C BSR loc_1A35 ; cycles=13 + +loc_43D9: +43D9: 20 47 BRA loc_4422 ; cycles=8 + +loc_43DB: +43DB: 0E 52 BSR loc_442F ; cycles=14 +43DD: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43E0: 27 03 BEQ loc_43E5 ; cycles=3/7 nt/t +43E2: 1E D6 B7 BSR loc_1A9C ; cycles=13 + +loc_43E5: +43E5: 20 3B BRA loc_4422 ; cycles=8 + +loc_43E7: +43E7: 0E 46 BSR loc_442F ; cycles=14 +43E9: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43EC: 27 03 BEQ loc_43F1 ; cycles=3/7 nt/t +43EE: 1E D6 F3 BSR loc_1AE4 ; cycles=13 + +loc_43F1: +43F1: 20 2F BRA loc_4422 ; cycles=8 + +loc_43F3: +43F3: 0E 3A BSR loc_442F ; cycles=14 +43F5: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +43F8: 27 03 BEQ loc_43FD ; cycles=3/7 nt/t +43FA: 1E D7 0E BSR loc_1B0B ; cycles=13 + +loc_43FD: +43FD: 20 23 BRA loc_4422 ; cycles=8 + +loc_43FF: +43FF: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4404: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +4408: 1E 04 EF BSR loc_48FA ; cycles=13 +440B: 20 15 BRA loc_4422 ; cycles=8 + +loc_440D: +440D: 0E 20 BSR loc_442F ; cycles=14 +440F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4412: 27 0C BEQ loc_4420 ; cycles=3/7 nt/t +4414: 15 F7 70 06 80 MOV:G.B #H'80, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +4419: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +441D: 1E 04 DA BSR loc_48FA ; cycles=14 + +loc_4420: +4420: 20 00 BRA loc_4422 ; cycles=7 + +loc_4422: +4422: 1D F6 9E 84 MOV:G.W @H'F69E, R4 ; refs ram_F69E in on_chip_ram; cycles=7 +4426: 1D F6 BE 94 MOV:G.W R4, @H'F6BE ; refs ram_F6BE in on_chip_ram; cycles=7 +442A: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +442E: 19 RTS ; cycles=12 + +loc_442F: +442F: 15 F6 F7 24 ADD:G.B @H'F6F7, R4 ; refs ram_F6F7 in on_chip_ram; cycles=6 +4433: 44 88 CMP:E #H'88, R4 ; cycles=2 +4435: 24 0D BCC loc_4444 ; cycles=3/8 nt/t +4437: 44 78 CMP:E #H'78, R4 ; cycles=2 +4439: 23 13 BLS loc_444E ; cycles=3/8 nt/t +443B: 15 F6 F7 94 MOV:G.B R4, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=6 +443F: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4442: 20 12 BRA loc_4456 ; cycles=7 + +loc_4444: +4444: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4449: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +444C: 20 08 BRA loc_4456 ; cycles=7 + +loc_444E: +444E: 15 F6 F7 06 80 MOV:G.B #H'80, @H'F6F7 ; refs ram_F6F7 in on_chip_ram; cycles=9 +4453: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4456: +4456: 19 RTS ; cycles=12 + +loc_4457: +4457: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=6 +445C: 32 00 86 BHI loc_44E5 ; cycles=3/7 nt/t +445F: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=6 +4463: 36 00 7F BNE loc_44E5 ; cycles=3/8 nt/t +4466: 1D F7 38 83 MOV:G.W @H'F738, R3 ; refs ram_F738 in on_chip_ram; cycles=7 +446A: 37 00 78 BEQ loc_44E5 ; cycles=3/7 nt/t +446D: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +4471: 1D F6 BC 34 SUB.W @H'F6BC, R4 ; refs ram_F6BC in on_chip_ram; cycles=6 +4475: AB DF BCLR.W #15, R3 ; cycles=3 +4477: 26 19 BNE loc_4492 ; cycles=3/8 nt/t +4479: AB DE BCLR.W #14, R3 ; cycles=3 +447B: 26 21 BNE loc_449E ; cycles=3/8 nt/t +447D: AB DD BCLR.W #13, R3 ; cycles=3 +447F: 26 29 BNE loc_44AA ; cycles=3/8 nt/t +4481: AB DC BCLR.W #12, R3 ; cycles=3 +4483: 26 31 BNE loc_44B6 ; cycles=3/8 nt/t +4485: AB DB BCLR.W #11, R3 ; cycles=3 +4487: 26 39 BNE loc_44C2 ; cycles=3/8 nt/t +4489: AB DA BCLR.W #10, R3 ; cycles=3 +448B: 26 43 BNE loc_44D0 ; cycles=3/8 nt/t +448D: 1E D5 12 BSR loc_19A2 ; cycles=14 +4490: 20 53 BRA loc_44E5 ; cycles=7 + +loc_4492: +4492: 0E 5E BSR loc_44F2 ; cycles=13 +4494: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4497: 27 03 BEQ loc_449C ; cycles=3/8 nt/t +4499: 1E D5 99 BSR loc_1A35 ; cycles=14 + +loc_449C: +449C: 20 47 BRA loc_44E5 ; cycles=7 + +loc_449E: +449E: 0E 52 BSR loc_44F2 ; cycles=13 +44A0: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44A3: 27 03 BEQ loc_44A8 ; cycles=3/8 nt/t +44A5: 1E D5 F4 BSR loc_1A9C ; cycles=14 + +loc_44A8: +44A8: 20 3B BRA loc_44E5 ; cycles=7 + +loc_44AA: +44AA: 0E 46 BSR loc_44F2 ; cycles=13 +44AC: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44AF: 27 03 BEQ loc_44B4 ; cycles=3/8 nt/t +44B1: 1E D6 30 BSR loc_1AE4 ; cycles=14 + +loc_44B4: +44B4: 20 2F BRA loc_44E5 ; cycles=7 + +loc_44B6: +44B6: 0E 3A BSR loc_44F2 ; cycles=13 +44B8: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44BB: 27 03 BEQ loc_44C0 ; cycles=3/8 nt/t +44BD: 1E D6 4B BSR loc_1B0B ; cycles=14 + +loc_44C0: +44C0: 20 23 BRA loc_44E5 ; cycles=7 + +loc_44C2: +44C2: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44C7: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +44CB: 1E 04 2C BSR loc_48FA ; cycles=14 +44CE: 20 15 BRA loc_44E5 ; cycles=7 + +loc_44D0: +44D0: 0E 20 BSR loc_44F2 ; cycles=13 +44D2: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +44D5: 27 0C BEQ loc_44E3 ; cycles=3/8 nt/t +44D7: 15 F7 70 06 40 MOV:G.B #H'40, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +44DC: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +44E0: 1E 04 17 BSR loc_48FA ; cycles=13 + +loc_44E3: +44E3: 20 00 BRA loc_44E5 ; cycles=8 + +loc_44E5: +44E5: 1D F6 9C 84 MOV:G.W @H'F69C, R4 ; refs ram_F69C in on_chip_ram; cycles=6 +44E9: 1D F6 BC 94 MOV:G.W R4, @H'F6BC ; refs ram_F6BC in on_chip_ram; cycles=6 +44ED: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=8 +44F1: 19 RTS ; cycles=13 + +loc_44F2: +44F2: 15 F6 F8 24 ADD:G.B @H'F6F8, R4 ; refs ram_F6F8 in on_chip_ram; cycles=7 +44F6: 44 88 CMP:E #H'88, R4 ; cycles=2 +44F8: 24 0D BCC loc_4507 ; cycles=3/7 nt/t +44FA: 44 78 CMP:E #H'78, R4 ; cycles=2 +44FC: 23 13 BLS loc_4511 ; cycles=3/7 nt/t +44FE: 15 F6 F8 94 MOV:G.B R4, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=7 +4502: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +4505: 20 12 BRA loc_4519 ; cycles=8 + +loc_4507: +4507: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +450C: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +450F: 20 08 BRA loc_4519 ; cycles=8 + +loc_4511: +4511: 15 F6 F8 06 80 MOV:G.B #H'80, @H'F6F8 ; refs ram_F6F8 in on_chip_ram; cycles=9 +4516: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_4519: +4519: 19 RTS ; cycles=13 + +loc_451A: +451A: 15 F7 31 04 01 CMP:G.B #H'01, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +451F: 32 00 86 BHI loc_45A8 ; cycles=3/8 nt/t +4522: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +4526: 36 00 7F BNE loc_45A8 ; cycles=3/7 nt/t +4529: 1D F7 3A 83 MOV:G.W @H'F73A, R3 ; refs ram_F73A in on_chip_ram; cycles=6 +452D: 37 00 78 BEQ loc_45A8 ; cycles=3/8 nt/t +4530: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +4534: 1D F6 BA 34 SUB.W @H'F6BA, R4 ; refs ram_F6BA in on_chip_ram; cycles=7 +4538: AB DF BCLR.W #15, R3 ; cycles=3 +453A: 26 19 BNE loc_4555 ; cycles=3/7 nt/t +453C: AB DE BCLR.W #14, R3 ; cycles=3 +453E: 26 21 BNE loc_4561 ; cycles=3/7 nt/t +4540: AB DD BCLR.W #13, R3 ; cycles=3 +4542: 26 29 BNE loc_456D ; cycles=3/7 nt/t +4544: AB DC BCLR.W #12, R3 ; cycles=3 +4546: 26 31 BNE loc_4579 ; cycles=3/7 nt/t +4548: AB DB BCLR.W #11, R3 ; cycles=3 +454A: 26 39 BNE loc_4585 ; cycles=3/7 nt/t +454C: AB DA BCLR.W #10, R3 ; cycles=3 +454E: 26 43 BNE loc_4593 ; cycles=3/7 nt/t +4550: 1E D4 4F BSR loc_19A2 ; cycles=13 +4553: 20 53 BRA loc_45A8 ; cycles=8 + +loc_4555: +4555: 0E 5E BSR loc_45B5 ; cycles=14 +4557: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +455A: 27 03 BEQ loc_455F ; cycles=3/7 nt/t +455C: 1E D4 D6 BSR loc_1A35 ; cycles=13 + +loc_455F: +455F: 20 47 BRA loc_45A8 ; cycles=8 + +loc_4561: +4561: 0E 52 BSR loc_45B5 ; cycles=14 +4563: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4566: 27 03 BEQ loc_456B ; cycles=3/7 nt/t +4568: 1E D5 31 BSR loc_1A9C ; cycles=13 + +loc_456B: +456B: 20 3B BRA loc_45A8 ; cycles=8 + +loc_456D: +456D: 0E 46 BSR loc_45B5 ; cycles=14 +456F: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4572: 27 03 BEQ loc_4577 ; cycles=3/7 nt/t +4574: 1E D5 6D BSR loc_1AE4 ; cycles=13 + +loc_4577: +4577: 20 2F BRA loc_45A8 ; cycles=8 + +loc_4579: +4579: 0E 3A BSR loc_45B5 ; cycles=14 +457B: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +457E: 27 03 BEQ loc_4583 ; cycles=3/7 nt/t +4580: 1E D5 88 BSR loc_1B0B ; cycles=13 + +loc_4583: +4583: 20 23 BRA loc_45A8 ; cycles=8 + +loc_4585: +4585: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +458A: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=7 +458E: 1E 03 69 BSR loc_48FA ; cycles=13 +4591: 20 15 BRA loc_45A8 ; cycles=8 + +loc_4593: +4593: 0E 20 BSR loc_45B5 ; cycles=14 +4595: 4C 00 02 CMP:I #H'0002, R4 ; cycles=3 +4598: 27 0C BEQ loc_45A6 ; cycles=3/7 nt/t +459A: 15 F7 70 06 20 MOV:G.B #H'20, @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +459F: 1D F7 72 94 MOV:G.W R4, @H'F772 ; refs ram_F772 in on_chip_ram; cycles=6 +45A3: 1E 03 54 BSR loc_48FA ; cycles=14 + +loc_45A6: +45A6: 20 00 BRA loc_45A8 ; cycles=7 + +loc_45A8: +45A8: 1D F6 9A 84 MOV:G.W @H'F69A, R4 ; refs ram_F69A in on_chip_ram; cycles=7 +45AC: 1D F6 BA 94 MOV:G.W R4, @H'F6BA ; refs ram_F6BA in on_chip_ram; cycles=7 +45B0: 15 FB 02 13 CLR.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +45B4: 19 RTS ; cycles=12 + +loc_45B5: +45B5: 15 F6 F9 24 ADD:G.B @H'F6F9, R4 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45B9: 44 88 CMP:E #H'88, R4 ; cycles=2 +45BB: 24 0D BCC loc_45CA ; cycles=3/8 nt/t +45BD: 44 78 CMP:E #H'78, R4 ; cycles=2 +45BF: 23 13 BLS loc_45D4 ; cycles=3/8 nt/t +45C1: 15 F6 F9 94 MOV:G.B R4, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=6 +45C5: 5C 00 02 MOV:I.W #H'0002, R4 ; dataflow R4=H'0002; cycles=3 +45C8: 20 12 BRA loc_45DC ; cycles=7 + +loc_45CA: +45CA: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45CF: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +45D2: 20 08 BRA loc_45DC ; cycles=7 + +loc_45D4: +45D4: 15 F6 F9 06 80 MOV:G.B #H'80, @H'F6F9 ; refs ram_F6F9 in on_chip_ram; cycles=9 +45D9: 5C 00 01 MOV:I.W #H'0001, R4 ; dataflow R4=H'0001; cycles=3 + +loc_45DC: +45DC: 19 RTS ; cycles=12 + +loc_48EF: +48EF: 1D F7 34 80 MOV:G.W @H'F734, R0 ; refs ram_F734 in on_chip_ram; cycles=6 +48F3: 1D F7 32 90 MOV:G.W R0, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +48F7: 0E 01 BSR loc_48FA ; cycles=14 +48F9: 19 RTS ; cycles=13 + +loc_48FA: +48FA: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +48FE: 26 29 BNE loc_4929 ; cycles=3/7 nt/t +4900: 15 F7 32 04 1A CMP:G.B #H'1A, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=7 +4905: 27 22 BEQ loc_4929 ; cycles=3/8 nt/t +4907: 1D F7 32 05 19 00 CMP:G.W #H'1900, @H'F732 ; refs ram_F732 in on_chip_ram; cycles=6 +490D: 27 1A BEQ loc_4929 ; cycles=3/8 nt/t +490F: 1D E1 EC FD BTST.W #13, @H'E1EC ; refs mem_E1EC in program_or_external; cycles=6 +4913: 27 14 BEQ loc_4929 ; cycles=3/8 nt/t +4915: 1D E1 EC 80 MOV:G.W @H'E1EC, R0 ; refs mem_E1EC in program_or_external; cycles=6 +4919: 0C 9F FF 50 AND.W #H'9FFF, R0 ; cycles=4 +491D: 1D E9 EC 90 MOV:G.W R0, @H'E9EC ; refs mem_E9EC in program_or_external; cycles=6 +4921: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +4923: 5B 00 F6 MOV:I.W #H'00F6, R3 ; dataflow R3=H'00F6; cycles=3 +4926: 1E F5 2B BSR loc_3E54 ; cycles=13 + +loc_4929: +4929: 15 F7 6E F6 BTST.B #6, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +492D: 26 0E BNE loc_493D ; cycles=3/8 nt/t +492F: 15 F7 32 80 MOV:G.B @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +4933: A0 12 EXTU.B R0 ; cycles=3 +4935: A0 1A SHLL.B R0 ; cycles=2 +4937: F8 49 3E 80 MOV:G.W @(H'493E,R0), R0 ; cycles=6 +493B: 11 D8 JSR @R0 ; JSR @R0 uses R0 loaded from pointer table H'493E via R0 (0/52 decoded targets); cycles=14 + +loc_493D: +493D: 19 RTS ; cycles=13 + +loc_5500: +5500: 15 F7 95 F7 BTST.B #7, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +5504: 36 00 A6 BNE loc_55AD ; cycles=3/7 nt/t +5507: 15 F7 6E 82 MOV:G.B @H'F76E, R2 ; refs ram_F76E in on_chip_ram; cycles=6 +550B: 0C 00 0F 52 AND.W #H'000F, R2 ; cycles=4 +550F: AA 83 MOV:G.W R2, R3 ; cycles=3 +5511: A3 1A SHLL.B R3 ; cycles=2 +5513: A3 1A SHLL.B R3 ; cycles=2 +5515: A3 1A SHLL.B R3 ; cycles=2 +5517: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5519: 15 F7 5E 84 MOV:G.B @H'F75E, R4 ; refs ram_F75E in on_chip_ram; cycles=6 +551D: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5521: A5 10 SWAP.B R5 ; cycles=3 +5523: 15 F7 5F 84 MOV:G.B @H'F75F, R4 ; refs ram_F75F in on_chip_ram; cycles=6 +5527: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +552B: FB F7 B0 95 MOV:G.W R5, @(-H'0850,R3) ; cycles=6 +552F: AA 84 MOV:G.W R2, R4 ; cycles=3 +5531: A4 10 SWAP.B R4 ; cycles=3 +5533: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5535: 1E 6A A8 BSR loc_BFE0 ; cycles=14 +5538: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +553A: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +553C: 15 F7 60 84 MOV:G.B @H'F760, R4 ; refs ram_F760 in on_chip_ram; cycles=7 +5540: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5544: A5 10 SWAP.B R5 ; cycles=3 +5546: 15 F7 61 84 MOV:G.B @H'F761, R4 ; refs ram_F761 in on_chip_ram; cycles=7 +554A: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +554E: FB F7 B2 95 MOV:G.W R5, @(-H'084E,R3) ; cycles=7 +5552: AA 84 MOV:G.W R2, R4 ; cycles=3 +5554: A4 10 SWAP.B R4 ; cycles=3 +5556: AC 09 ADD:Q.W #2, R4 ; cycles=4 +5558: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +555A: 1E 6A 83 BSR loc_BFE0 ; cycles=13 +555D: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +555F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5561: 15 F7 62 84 MOV:G.B @H'F762, R4 ; refs ram_F762 in on_chip_ram; cycles=6 +5565: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5569: A5 10 SWAP.B R5 ; cycles=3 +556B: 15 F7 63 84 MOV:G.B @H'F763, R4 ; refs ram_F763 in on_chip_ram; cycles=6 +556F: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=6 +5573: FB F7 B4 95 MOV:G.W R5, @(-H'084C,R3) ; cycles=6 +5577: AA 84 MOV:G.W R2, R4 ; cycles=3 +5579: A4 10 SWAP.B R4 ; cycles=3 +557B: 0C 00 04 24 ADD:G.W #H'0004, R4 ; cycles=4 +557F: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +5581: 1E 6A 5C BSR loc_BFE0 ; cycles=14 +5584: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 +5586: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +5588: 15 F7 64 84 MOV:G.B @H'F764, R4 ; refs ram_F764 in on_chip_ram; cycles=7 +558C: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +5590: A5 10 SWAP.B R5 ; cycles=3 +5592: 15 F7 65 84 MOV:G.B @H'F765, R4 ; refs ram_F765 in on_chip_ram; cycles=7 +5596: F4 CE 7C 85 MOV:G.B @(-H'3184,R4), R5 ; cycles=7 +559A: FB F7 B6 95 MOV:G.W R5, @(-H'084A,R3) ; cycles=7 +559E: AA 84 MOV:G.W R2, R4 ; cycles=3 +55A0: A4 10 SWAP.B R4 ; cycles=3 +55A2: 0C 00 06 24 ADD:G.W #H'0006, R4 ; cycles=4 +55A6: 12 3C STM.W {R2,R3,R4,R5}, @-SP ; cycles=18 +55A8: 1E 6A 35 BSR loc_BFE0 ; cycles=13 +55AB: 02 3C LDM.W @SP+, {R2,R3,R4,R5} ; cycles=22 + +loc_55AD: +55AD: AD 13 CLR.W R5 ; dataflow R5=H'0000; cycles=3 + +loc_55AF: +55AF: FD C5 64 84 MOV:G.W @(-H'3A9C,R5), R4 ; cycles=6 +55B3: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=6 +55B7: 27 06 BEQ loc_55BF ; cycles=3/8 nt/t +55B9: AC FE BTST.W #14, R4 ; cycles=3 +55BB: 27 13 BEQ loc_55D0 ; cycles=3/8 nt/t +55BD: 20 04 BRA loc_55C3 ; cycles=8 + +loc_55BF: +55BF: AC FD BTST.W #13, R4 ; cycles=3 +55C1: 27 0D BEQ loc_55D0 ; cycles=3/8 nt/t + +loc_55C3: +55C3: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55C5: AD 83 MOV:G.W R5, R3 ; cycles=3 +55C7: AB 1B SHLR.W R3 ; cycles=3 +55C9: 0C 02 00 43 OR.W #H'0200, R3 ; cycles=4 +55CD: 1E E8 84 BSR loc_3E54 ; cycles=14 + +loc_55D0: +55D0: AD 09 ADD:Q.W #2, R5 ; cycles=4 +55D2: 4D 04 00 CMP:I #H'0400, R5 ; cycles=3 +55D5: 25 D8 BCS loc_55AF ; cycles=3/8 nt/t +55D7: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +55D9: 5B 00 6C MOV:I.W #H'006C, R3 ; dataflow R3=H'006C; cycles=3 +55DC: 1E E8 75 BSR loc_3E54 ; cycles=13 +55DF: 15 F7 56 13 CLR.B @H'F756 ; refs ram_F756 in on_chip_ram; cycles=8 +55E3: 15 F7 57 13 CLR.B @H'F757 ; refs ram_F757 in on_chip_ram; cycles=8 +55E7: 15 F7 58 13 CLR.B @H'F758 ; refs ram_F758 in on_chip_ram; cycles=8 +55EB: 15 F7 59 13 CLR.B @H'F759 ; refs ram_F759 in on_chip_ram; cycles=8 +55EF: 19 RTS ; cycles=13 + +loc_58F7: +58F7: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +58FD: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5903: AA 13 CLR.W R2 ; dataflow R2=H'0000; cycles=3 +5905: 15 F7 5E 82 MOV:G.B @H'F75E, R2 ; refs ram_F75E in on_chip_ram; cycles=6 +5909: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +590D: A1 10 SWAP.B R1 ; cycles=3 +590F: 15 F7 5F 82 MOV:G.B @H'F75F, R2 ; refs ram_F75F in on_chip_ram; cycles=6 +5913: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5917: 1D FA F4 91 MOV:G.W R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=6 +591B: 15 F7 60 82 MOV:G.B @H'F760, R2 ; refs ram_F760 in on_chip_ram; cycles=6 +591F: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5923: A1 10 SWAP.B R1 ; cycles=3 +5925: 15 F7 61 82 MOV:G.B @H'F761, R2 ; refs ram_F761 in on_chip_ram; cycles=6 +5929: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +592D: 1D FA F6 91 MOV:G.W R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=6 +5931: 15 F7 62 82 MOV:G.B @H'F762, R2 ; refs ram_F762 in on_chip_ram; cycles=6 +5935: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5939: A1 10 SWAP.B R1 ; cycles=3 +593B: 15 F7 63 82 MOV:G.B @H'F763, R2 ; refs ram_F763 in on_chip_ram; cycles=6 +593F: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5943: 1D FA F8 91 MOV:G.W R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=6 +5947: 15 F7 64 82 MOV:G.B @H'F764, R2 ; refs ram_F764 in on_chip_ram; cycles=6 +594B: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +594F: A1 10 SWAP.B R1 ; cycles=3 +5951: 15 F7 65 82 MOV:G.B @H'F765, R2 ; refs ram_F765 in on_chip_ram; cycles=6 +5955: F2 CE 7C 81 MOV:G.B @(-H'3184,R2), R1 ; cycles=6 +5959: 1D FA FA 91 MOV:G.W R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=6 +595D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5963: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5969: 19 RTS ; cycles=13 + +loc_596A: +596A: 40 00 CMP:E #H'00, R0 ; cycles=2 +596C: 27 0A BEQ loc_5978 ; cycles=3/7 nt/t +596E: 40 01 CMP:E #H'01, R0 ; cycles=2 +5970: 27 0B BEQ loc_597D ; cycles=3/7 nt/t +5972: 40 02 CMP:E #H'02, R0 ; cycles=2 +5974: 27 0C BEQ loc_5982 ; cycles=3/7 nt/t +5976: 20 0F BRA loc_5987 ; cycles=7 + +loc_5978: +5978: 5C 00 83 MOV:I.W #H'0083, R4 ; dataflow R4=H'0083; cycles=3 +597B: 20 0D BRA loc_598A ; cycles=8 + +loc_597D: +597D: 5C 00 C3 MOV:I.W #H'00C3, R4 ; dataflow R4=H'00C3; cycles=3 +5980: 20 08 BRA loc_598A ; cycles=7 + +loc_5982: +5982: 5C 00 93 MOV:I.W #H'0093, R4 ; dataflow R4=H'0093; cycles=3 +5985: 20 03 BRA loc_598A ; cycles=8 + +loc_5987: +5987: 5C 00 D3 MOV:I.W #H'00D3, R4 ; dataflow R4=H'00D3; cycles=3 + +loc_598A: +598A: 15 F7 5B 24 ADD:G.B @H'F75B, R4 ; refs ram_F75B in on_chip_ram; cycles=7 +598E: 5D 00 04 MOV:I.W #H'0004, R5 ; dataflow R5=H'0004; cycles=3 +5991: 1E E5 38 BSR loc_3ECC ; cycles=14 +5994: 19 RTS ; cycles=12 + +loc_5A04: +5A04: 15 F7 13 F6 BTST.B #6, @H'F713 ; refs ram_F713 in on_chip_ram; cycles=7 +5A08: 26 04 BNE loc_5A0E ; cycles=3/7 nt/t +5A0A: 15 F7 26 13 CLR.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=9 + +loc_5A0E: +5A0E: 58 00 07 MOV:I.W #H'0007, R0 ; dataflow R0=H'0007; cycles=3 + +loc_5A11: +5A11: A8 0C ADD:Q.W #-1, R0 ; cycles=4 +5A13: F8 F7 3C 81 MOV:G.W @(-H'08C4,R0), R1 ; cycles=6 +5A17: 27 4C BEQ loc_5A65 ; cycles=3/8 nt/t +5A19: A9 82 MOV:G.W R1, R2 ; cycles=3 +5A1B: 0C FE 00 52 AND.W #H'FE00, R2 ; cycles=4 +5A1F: 26 44 BNE loc_5A65 ; cycles=3/8 nt/t +5A21: A9 1A SHLL.W R1 ; cycles=3 +5A23: F8 F7 4C 16 TST.W @(-H'08B4,R0) ; cycles=6 +5A27: 27 10 BEQ loc_5A39 ; cycles=3/8 nt/t +5A29: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5A2D: F8 F7 4C 52 AND.W @(-H'08B4,R0), R2 ; cycles=6 +5A31: F8 F7 4C 72 CMP:G.W @(-H'08B4,R0), R2 ; cycles=6 +5A35: 27 12 BEQ loc_5A49 ; cycles=3/8 nt/t +5A37: 20 2C BRA loc_5A65 ; cycles=8 + +loc_5A39: +5A39: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5A3D: F8 F7 44 52 AND.W @(-H'08BC,R0), R2 ; cycles=6 +5A41: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5A45: 27 1E BEQ loc_5A65 ; cycles=3/8 nt/t +5A47: 20 00 BRA loc_5A49 ; cycles=8 + +loc_5A49: +5A49: F9 E0 00 81 MOV:G.W @(-H'2000,R1), R1 ; cycles=6 +5A4D: F8 F7 44 82 MOV:G.W @(-H'08BC,R0), R2 ; cycles=6 +5A51: AA 15 NOT.W R2 ; cycles=3 +5A53: AA 51 AND.W R2, R1 ; cycles=3 +5A55: F8 F7 4C 71 CMP:G.W @(-H'08B4,R0), R1 ; cycles=6 +5A59: 26 0A BNE loc_5A65 ; cycles=3/8 nt/t +5A5B: F8 5A 72 81 MOV:G.W @(H'5A72,R0), R1 ; cycles=6 +5A5F: 15 F7 11 49 BSET.B R1, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +5A63: 20 08 BRA loc_5A6D ; cycles=8 + +loc_5A65: +5A65: F8 5A 72 81 MOV:G.W @(H'5A72,R0), R1 ; cycles=6 +5A69: 15 F7 11 59 BCLR.B R1, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 + +loc_5A6D: +5A6D: 01 B8 A1 SCB/F R0, loc_5A11 ; cycles=3/4/9 false/-1/t +5A70: 19 RTS ; cycles=12 + +loc_5A7A: +5A7A: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=7 +5A7E: 26 10 BNE loc_5A90 ; cycles=3/7 nt/t +5A80: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A84: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A88: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +5A8C: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 + +loc_5A90: +5A90: 19 RTS ; cycles=12 + +loc_5A91: +5A91: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5A94: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5A98: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5A9B: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5A9F: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5AA2: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5AA6: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5AA9: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5AAD: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5AB0: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5AB4: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5AB7: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5ABB: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5ABE: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5AC2: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5AC5: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5AC9: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5ACC: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5AD0: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5AD3: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5AD7: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5ADA: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5ADE: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5AE1: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5AE5: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5AE8: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5AEC: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5AEF: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5AF3: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5AF6: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5AFA: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5AFD: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5B01: 19 RTS ; cycles=13 + +loc_5B02: +5B02: 15 F7 2E 80 MOV:G.B @H'F72E, R0 ; refs ram_F72E in on_chip_ram; cycles=7 +5B06: A0 12 EXTU.B R0 ; cycles=3 +5B08: 40 01 CMP:E #H'01, R0 ; cycles=2 +5B0A: 23 48 BLS loc_5B54 ; cycles=3/7 nt/t +5B0C: 40 09 CMP:E #H'09, R0 ; cycles=2 +5B0E: 22 1D BHI loc_5B2D ; cycles=3/7 nt/t +5B10: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=7 +5B14: 15 FA FF 90 MOV:G.B R0, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=7 +5B18: 15 FA FE 06 2F MOV:G.B #H'2F, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +5B1D: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=6 +5B21: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B23: F0 5B 55 80 MOV:G.B @(H'5B55,R0), R0 ; LCD text xref H'5B55 '0123456789'; cycles=6 +5B27: 15 FA FD 90 MOV:G.B R0, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5B2B: 20 27 BRA loc_5B54 ; cycles=8 + +loc_5B2D: +5B2D: A0 1A SHLL.B R0 ; cycles=2 +5B2F: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=6 +5B33: 1D FA FE 90 MOV:G.W R0, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=6 +5B37: 15 FA FD 06 2F MOV:G.B #H'2F, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=9 +5B3C: 15 F7 33 80 MOV:G.B @H'F733, R0 ; refs ram_F733 in on_chip_ram; cycles=7 +5B40: A0 12 EXTU.B R0 ; cycles=3 +5B42: A0 08 ADD:Q.B #1, R0 ; cycles=4 +5B44: A0 1A SHLL.B R0 ; cycles=2 +5B46: F8 5B 60 80 MOV:G.W @(H'5B60,R0), R0 ; cycles=7 +5B4A: 15 FA FC 90 MOV:G.B R0, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5B4E: A0 10 SWAP.B R0 ; cycles=3 +5B50: 15 FA FB 90 MOV:G.B R0, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=7 + +loc_5B54: +5B54: 19 RTS ; cycles=12 + +loc_5B88: +5B88: 1D F7 3C 81 MOV:G.W @H'F73C, R1 ; refs ram_F73C in on_chip_ram; cycles=7 +5B8C: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5B90: 27 62 BEQ loc_5BF4 ; cycles=3/7 nt/t +5B92: A9 1A SHLL.W R1 ; cycles=3 +5B94: 1D F7 4C 16 TST.W @H'F74C ; refs ram_F74C in on_chip_ram; cycles=7 +5B98: 27 10 BEQ loc_5BAA ; cycles=3/7 nt/t +5B9A: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=7 +5B9E: 1D F7 4C 52 AND.W @H'F74C, R2 ; refs ram_F74C in on_chip_ram; cycles=7 +5BA2: 1D F7 4C 72 CMP:G.W @H'F74C, R2 ; refs ram_F74C in on_chip_ram; cycles=7 +5BA6: 27 12 BEQ loc_5BBA ; cycles=3/7 nt/t +5BA8: 20 4A BRA loc_5BF4 ; cycles=7 + +loc_5BAA: +5BAA: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=7 +5BAE: 1D F7 44 52 AND.W @H'F744, R2 ; refs ram_F744 in on_chip_ram; cycles=7 +5BB2: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=7 +5BB6: 27 3C BEQ loc_5BF4 ; cycles=3/7 nt/t +5BB8: 20 00 BRA loc_5BBA ; cycles=7 + +loc_5BBA: +5BBA: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=7 +5BBD: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=6 +5BC1: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=6 +5BC4: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=7 +5BC8: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=7 +5BCB: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=6 +5BCF: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=6 +5BD2: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=7 +5BD6: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=7 +5BD9: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=6 +5BDD: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=6 +5BE0: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=7 +5BE4: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=7 +5BE7: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=6 +5BEB: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=6 +5BEE: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=7 +5BF2: 20 18 BRA loc_5C0C ; cycles=7 + +loc_5BF4: +5BF4: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=11 +5BFA: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=11 +5C00: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=11 +5C06: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=11 + +loc_5C0C: +5C0C: 1D F7 40 81 MOV:G.W @H'F740, R1 ; refs ram_F740 in on_chip_ram; cycles=7 +5C10: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5C14: 27 62 BEQ loc_5C78 ; cycles=3/7 nt/t +5C16: A9 1A SHLL.W R1 ; cycles=3 +5C18: 1D F7 50 16 TST.W @H'F750 ; refs ram_F750 in on_chip_ram; cycles=7 +5C1C: 27 10 BEQ loc_5C2E ; cycles=3/7 nt/t +5C1E: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=7 +5C22: 1D F7 50 52 AND.W @H'F750, R2 ; refs ram_F750 in on_chip_ram; cycles=7 +5C26: 1D F7 50 72 CMP:G.W @H'F750, R2 ; refs ram_F750 in on_chip_ram; cycles=7 +5C2A: 27 12 BEQ loc_5C3E ; cycles=3/7 nt/t +5C2C: 20 4A BRA loc_5C78 ; cycles=7 + +loc_5C2E: +5C2E: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=7 +5C32: 1D F7 48 52 AND.W @H'F748, R2 ; refs ram_F748 in on_chip_ram; cycles=7 +5C36: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=7 +5C3A: 27 3C BEQ loc_5C78 ; cycles=3/7 nt/t +5C3C: 20 00 BRA loc_5C3E ; cycles=7 + +loc_5C3E: +5C3E: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=7 +5C41: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=6 +5C45: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=6 +5C48: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=7 +5C4C: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=7 +5C4F: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=6 +5C53: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=6 +5C56: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=7 +5C5A: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=7 +5C5D: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=6 +5C61: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=6 +5C64: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=7 +5C68: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=7 +5C6B: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=6 +5C6F: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=6 +5C72: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=7 +5C76: 20 18 BRA loc_5C90 ; cycles=7 + +loc_5C78: +5C78: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=11 +5C7E: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=11 +5C84: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=11 +5C8A: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=11 + +loc_5C90: +5C90: 19 RTS ; cycles=12 + +loc_5C91: +5C91: 1D F7 3E 81 MOV:G.W @H'F73E, R1 ; refs ram_F73E in on_chip_ram; cycles=6 +5C95: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5C99: 27 62 BEQ loc_5CFD ; cycles=3/8 nt/t +5C9B: A9 1A SHLL.W R1 ; cycles=3 +5C9D: 1D F7 4E 16 TST.W @H'F74E ; refs ram_F74E in on_chip_ram; cycles=6 +5CA1: 27 10 BEQ loc_5CB3 ; cycles=3/8 nt/t +5CA3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CA7: 1D F7 4E 52 AND.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAB: 1D F7 4E 72 CMP:G.W @H'F74E, R2 ; refs ram_F74E in on_chip_ram; cycles=6 +5CAF: 27 12 BEQ loc_5CC3 ; cycles=3/8 nt/t +5CB1: 20 4A BRA loc_5CFD ; cycles=8 + +loc_5CB3: +5CB3: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CB7: 1D F7 46 52 AND.W @H'F746, R2 ; refs ram_F746 in on_chip_ram; cycles=6 +5CBB: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5CBF: 27 3C BEQ loc_5CFD ; cycles=3/8 nt/t +5CC1: 20 00 BRA loc_5CC3 ; cycles=8 + +loc_5CC3: +5CC3: E0 00 81 MOV:G.B @(H'00,R0), R1 ; cycles=6 +5CC6: 15 FA F0 91 MOV:G.B R1, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=7 +5CCA: E0 01 81 MOV:G.B @(H'01,R0), R1 ; cycles=7 +5CCD: 15 FA F1 91 MOV:G.B R1, @H'FAF1 ; refs ram_FAF1 in on_chip_ram; cycles=6 +5CD1: E0 02 81 MOV:G.B @(H'02,R0), R1 ; cycles=6 +5CD4: 15 FA F2 91 MOV:G.B R1, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=7 +5CD8: E0 03 81 MOV:G.B @(H'03,R0), R1 ; cycles=7 +5CDB: 15 FA F3 91 MOV:G.B R1, @H'FAF3 ; refs ram_FAF3 in on_chip_ram; cycles=6 +5CDF: E0 04 81 MOV:G.B @(H'04,R0), R1 ; cycles=6 +5CE2: 15 FA F4 91 MOV:G.B R1, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=7 +5CE6: E0 05 81 MOV:G.B @(H'05,R0), R1 ; cycles=7 +5CE9: 15 FA F5 91 MOV:G.B R1, @H'FAF5 ; refs ram_FAF5 in on_chip_ram; cycles=6 +5CED: E0 06 81 MOV:G.B @(H'06,R0), R1 ; cycles=6 +5CF0: 15 FA F6 91 MOV:G.B R1, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=7 +5CF4: E0 07 81 MOV:G.B @(H'07,R0), R1 ; cycles=7 +5CF7: 15 FA F7 91 MOV:G.B R1, @H'FAF7 ; refs ram_FAF7 in on_chip_ram; cycles=6 +5CFB: 20 18 BRA loc_5D15 ; cycles=8 + +loc_5CFD: +5CFD: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +5D03: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +5D09: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +5D0F: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 + +loc_5D15: +5D15: 1D F7 42 81 MOV:G.W @H'F742, R1 ; refs ram_F742 in on_chip_ram; cycles=6 +5D19: 0C 01 FF 51 AND.W #H'01FF, R1 ; cycles=4 +5D1D: 27 62 BEQ loc_5D81 ; cycles=3/8 nt/t +5D1F: A9 1A SHLL.W R1 ; cycles=3 +5D21: 1D F7 52 16 TST.W @H'F752 ; refs ram_F752 in on_chip_ram; cycles=6 +5D25: 27 10 BEQ loc_5D37 ; cycles=3/8 nt/t +5D27: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D2B: 1D F7 52 52 AND.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D2F: 1D F7 52 72 CMP:G.W @H'F752, R2 ; refs ram_F752 in on_chip_ram; cycles=6 +5D33: 27 12 BEQ loc_5D47 ; cycles=3/8 nt/t +5D35: 20 4A BRA loc_5D81 ; cycles=8 + +loc_5D37: +5D37: F9 E4 00 82 MOV:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D3B: 1D F7 4A 52 AND.W @H'F74A, R2 ; refs ram_F74A in on_chip_ram; cycles=6 +5D3F: F9 E4 00 72 CMP:G.W @(-H'1C00,R1), R2 ; cycles=6 +5D43: 27 3C BEQ loc_5D81 ; cycles=3/8 nt/t +5D45: 20 00 BRA loc_5D47 ; cycles=8 + +loc_5D47: +5D47: E0 08 81 MOV:G.B @(H'08,R0), R1 ; cycles=6 +5D4A: 15 FA F8 91 MOV:G.B R1, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=7 +5D4E: E0 09 81 MOV:G.B @(H'09,R0), R1 ; cycles=7 +5D51: 15 FA F9 91 MOV:G.B R1, @H'FAF9 ; refs ram_FAF9 in on_chip_ram; cycles=6 +5D55: E0 0A 81 MOV:G.B @(H'0A,R0), R1 ; cycles=6 +5D58: 15 FA FA 91 MOV:G.B R1, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=7 +5D5C: E0 0B 81 MOV:G.B @(H'0B,R0), R1 ; cycles=7 +5D5F: 15 FA FB 91 MOV:G.B R1, @H'FAFB ; refs ram_FAFB in on_chip_ram; cycles=6 +5D63: E0 0C 81 MOV:G.B @(H'0C,R0), R1 ; cycles=6 +5D66: 15 FA FC 91 MOV:G.B R1, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=7 +5D6A: E0 0D 81 MOV:G.B @(H'0D,R0), R1 ; cycles=7 +5D6D: 15 FA FD 91 MOV:G.B R1, @H'FAFD ; refs ram_FAFD in on_chip_ram; cycles=6 +5D71: E0 0E 81 MOV:G.B @(H'0E,R0), R1 ; cycles=6 +5D74: 15 FA FE 91 MOV:G.B R1, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=7 +5D78: E0 0F 81 MOV:G.B @(H'0F,R0), R1 ; cycles=7 +5D7B: 15 FA FF 91 MOV:G.B R1, @H'FAFF ; refs ram_FAFF in on_chip_ram; cycles=6 +5D7F: 20 18 BRA loc_5D99 ; cycles=8 + +loc_5D81: +5D81: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +5D87: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +5D8D: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +5D93: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 + +loc_5D99: +5D99: 19 RTS ; cycles=13 + +loc_606B: +606B: 1D F7 32 80 MOV:G.W @H'F732, R0 ; refs ram_F732 in on_chip_ram; cycles=6 +606F: 1D F7 5C 70 CMP:G.W @H'F75C, R0 ; refs ram_F75C in on_chip_ram; cycles=6 +6073: 27 65 BEQ loc_60DA ; cycles=3/8 nt/t +6075: 1D F7 5C 90 MOV:G.W R0, @H'F75C ; refs ram_F75C in on_chip_ram; cycles=6 +6079: A9 1A SHLL.W R1 ; cycles=3 +607B: A8 13 CLR.W R0 ; dataflow R0=H'0000; cycles=3 +607D: F1 E0 00 80 MOV:G.B @(-H'2000,R1), R0 ; cycles=6 +6081: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +6085: A2 10 SWAP.B R2 ; cycles=3 +6087: F1 E0 01 80 MOV:G.B @(-H'1FFF,R1), R0 ; cycles=6 +608B: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +608F: 1D F7 5E 92 MOV:G.W R2, @H'F75E ; refs ram_F75E in on_chip_ram; cycles=6 +6093: F1 E0 02 80 MOV:G.B @(-H'1FFE,R1), R0 ; cycles=6 +6097: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +609B: A2 10 SWAP.B R2 ; cycles=3 +609D: F1 E0 03 80 MOV:G.B @(-H'1FFD,R1), R0 ; cycles=6 +60A1: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60A5: 1D F7 60 92 MOV:G.W R2, @H'F760 ; refs ram_F760 in on_chip_ram; cycles=6 +60A9: F1 E0 04 80 MOV:G.B @(-H'1FFC,R1), R0 ; cycles=6 +60AD: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60B1: A2 10 SWAP.B R2 ; cycles=3 +60B3: F1 E0 05 80 MOV:G.B @(-H'1FFB,R1), R0 ; cycles=6 +60B7: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60BB: 1D F7 62 92 MOV:G.W R2, @H'F762 ; refs ram_F762 in on_chip_ram; cycles=6 +60BF: F1 E0 06 80 MOV:G.B @(-H'1FFA,R1), R0 ; cycles=6 +60C3: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60C7: A2 10 SWAP.B R2 ; cycles=3 +60C9: F1 E0 07 80 MOV:G.B @(-H'1FF9,R1), R0 ; cycles=6 +60CD: F0 CE B6 82 MOV:G.B @(-H'314A,R0), R2 ; cycles=6 +60D1: 1D F7 64 92 MOV:G.W R2, @H'F764 ; refs ram_F764 in on_chip_ram; cycles=6 +60D5: 15 F7 5B 06 01 MOV:G.B #H'01, @H'F75B ; refs ram_F75B in on_chip_ram; cycles=9 + +loc_60DA: +60DA: 19 RTS ; cycles=12 + +loc_6106: +6106: 1D FA F0 06 01 MOV:G.W #H'01, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=11 +610B: 1D FA F2 07 01 01 MOV:G.W #H'0101, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +6111: 1D FA F4 07 01 01 MOV:G.W #H'0101, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +6117: 1D FA F6 07 01 01 MOV:G.W #H'0101, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +611D: 1D FA F8 07 01 01 MOV:G.W #H'0101, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +6123: 1D FA FA 07 01 01 MOV:G.W #H'0101, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +6129: 1D FA FC 07 01 01 MOV:G.W #H'0101, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +612F: 1D FA FE 07 01 02 MOV:G.W #H'0102, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +6135: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +6138: 1E DD 91 BSR loc_3ECC ; cycles=13 +613B: 19 RTS ; cycles=13 + +loc_613C: +613C: 1D FA F0 07 03 04 MOV:G.W #H'0304, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=11 +6142: 1D FA F2 07 04 04 MOV:G.W #H'0404, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=11 +6148: 1D FA F4 07 04 04 MOV:G.W #H'0404, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=11 +614E: 1D FA F6 07 04 04 MOV:G.W #H'0404, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=11 +6154: 1D FA F8 07 04 04 MOV:G.W #H'0404, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=11 +615A: 1D FA FA 07 04 04 MOV:G.W #H'0404, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=11 +6160: 1D FA FC 07 04 04 MOV:G.W #H'0404, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=11 +6166: 1D FA FE 07 04 05 MOV:G.W #H'0405, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=11 +616C: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +616F: 1E DD 5A BSR loc_3ECC ; cycles=14 +6172: 19 RTS ; cycles=12 + +loc_6173: +6173: 1D FA F0 07 20 20 MOV:G.W #H'2020, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +6179: 1D FA F2 07 20 20 MOV:G.W #H'2020, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +617F: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +6185: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +618B: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +6191: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +6197: 1D FA FC 07 20 20 MOV:G.W #H'2020, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +619D: 1D FA FE 07 20 20 MOV:G.W #H'2020, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +61A3: 19 RTS ; cycles=13 + +loc_61D5: +61D5: 1D FA F0 07 20 43 MOV:G.W #H'2043, @H'FAF0 ; refs ram_FAF0 in on_chip_ram; cycles=9 +61DB: 1D FA F2 07 55 52 MOV:G.W #H'5552, @H'FAF2 ; refs ram_FAF2 in on_chip_ram; cycles=9 +61E1: 1D FA F4 07 20 20 MOV:G.W #H'2020, @H'FAF4 ; refs ram_FAF4 in on_chip_ram; cycles=9 +61E7: 1D FA F6 07 20 20 MOV:G.W #H'2020, @H'FAF6 ; refs ram_FAF6 in on_chip_ram; cycles=9 +61ED: 1D FA F8 07 20 20 MOV:G.W #H'2020, @H'FAF8 ; refs ram_FAF8 in on_chip_ram; cycles=9 +61F3: 1D FA FA 07 20 20 MOV:G.W #H'2020, @H'FAFA ; refs ram_FAFA in on_chip_ram; cycles=9 +61F9: 1D FA FC 07 43 48 MOV:G.W #H'4348, @H'FAFC ; refs ram_FAFC in on_chip_ram; cycles=9 +61FF: 1D FA FE 07 52 20 MOV:G.W #H'5220, @H'FAFE ; refs ram_FAFE in on_chip_ram; cycles=9 +6205: 19 RTS ; cycles=13 + +loc_6206: +6206: 0C 01 FF 55 AND.W #H'01FF, R5 ; cycles=4 +620A: 4D 00 7F CMP:I #H'007F, R5 ; cycles=3 +620D: 23 07 BLS loc_6216 ; cycles=3/8 nt/t +620F: 4D 01 7F CMP:I #H'017F, R5 ; cycles=3 +6212: 23 04 BLS loc_6218 ; cycles=3/7 nt/t +6214: 20 0C BRA loc_6222 ; cycles=7 + +loc_6216: +6216: 20 12 BRA loc_622A ; cycles=7 + +loc_6218: +6218: 0C 00 80 35 SUB.W #H'0080, R5 ; cycles=4 +621C: 0C 01 00 25 ADD:G.W #H'0100, R5 ; cycles=4 +6220: 20 08 BRA loc_622A ; cycles=7 + +loc_6222: +6222: 0C 01 80 35 SUB.W #H'0180, R5 ; cycles=4 +6226: 0C 02 00 25 ADD:G.W #H'0200, R5 ; cycles=4 + +loc_622A: +622A: 19 RTS ; cycles=12 + +loc_622B: +622B: AD 84 MOV:G.W R5, R4 ; cycles=3 +622D: A5 12 EXTU.B R5 ; cycles=3 +622F: A4 10 SWAP.B R4 ; cycles=3 +6231: 04 07 54 AND.B #H'07, R4 ; cycles=3 +6234: 44 00 CMP:E #H'00, R4 ; cycles=2 +6236: 27 0C BEQ loc_6244 ; cycles=3/7 nt/t +6238: 44 01 CMP:E #H'01, R4 ; cycles=2 +623A: 27 11 BEQ loc_624D ; cycles=3/7 nt/t +623C: 44 02 CMP:E #H'02, R4 ; cycles=2 +623E: 27 16 BEQ loc_6256 ; cycles=3/7 nt/t +6240: 44 03 CMP:E #H'03, R4 ; cycles=2 +6242: 27 1B BEQ loc_625F ; cycles=3/7 nt/t + +loc_6244: +6244: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6246: 22 17 BHI loc_625F ; cycles=3/7 nt/t +6248: 5C 00 00 MOV:I.W #H'0000, R4 ; dataflow R4=H'0000; cycles=3 +624B: 20 17 BRA loc_6264 ; cycles=8 + +loc_624D: +624D: 45 FF CMP:E #H'FF, R5 ; cycles=2 +624F: 22 0E BHI loc_625F ; cycles=3/8 nt/t +6251: 5C 00 80 MOV:I.W #H'0080, R4 ; dataflow R4=H'0080; cycles=3 +6254: 20 0E BRA loc_6264 ; cycles=7 + +loc_6256: +6256: 45 7F CMP:E #H'7F, R5 ; cycles=2 +6258: 22 05 BHI loc_625F ; cycles=3/7 nt/t +625A: 5C 01 80 MOV:I.W #H'0180, R4 ; dataflow R4=H'0180; cycles=3 +625D: 20 05 BRA loc_6264 ; cycles=8 + +loc_625F: +625F: AC 13 CLR.W R4 ; dataflow R4=H'0000; cycles=3 +6261: 5D 01 FF MOV:I.W #H'01FF, R5 ; dataflow R5=H'01FF; cycles=3 + +loc_6264: +6264: AC 25 ADD:G.W R4, R5 ; cycles=3 +6266: 19 RTS ; cycles=12 +6EE4: 1D F7 36 06 00 MOV:G.W #H'00, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +6EE9: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=9 +6EEE: 1D F7 3A 06 00 MOV:G.W #H'00, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=11 +6EF3: 1D F7 3C 06 00 MOV:G.W #H'00, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +6EF8: 1D F7 40 06 00 MOV:G.W #H'00, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +6EFD: 1D F7 3E 07 08 8F MOV:G.W #H'088F, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=9 +6F03: 1D F7 46 07 07 FF MOV:G.W #H'07FF, @H'F746 ; refs ram_F746 in on_chip_ram; cycles=9 +6F09: 1D F7 4E 07 08 00 MOV:G.W #H'0800, @H'F74E ; refs ram_F74E in on_chip_ram; cycles=9 +6F0F: 1D F7 42 07 08 8F MOV:G.W #H'088F, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=9 +6F15: 1D F7 4A 07 07 FF MOV:G.W #H'07FF, @H'F74A ; refs ram_F74A in on_chip_ram; cycles=9 +6F1B: 1D F7 52 07 10 00 MOV:G.W #H'1000, @H'F752 ; refs ram_F752 in on_chip_ram; cycles=9 +6F21: 1D F7 54 06 00 MOV:G.W #H'00, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=9 +6F26: 15 F7 70 80 MOV:G.B @H'F770, R0 ; refs ram_F770 in on_chip_ram; cycles=7 +6F2A: 15 F7 70 13 CLR.B @H'F770 ; refs ram_F770 in on_chip_ram; cycles=9 +6F2E: 04 03 50 AND.B #H'03, R0 ; cycles=3 +6F31: 27 34 BEQ loc_6F67 ; cycles=3/8 nt/t +6F33: A0 F1 BTST.B #1, R0 ; cycles=2 +6F35: 27 0E BEQ loc_6F45 ; cycles=3/8 nt/t +6F37: 1D E5 1E FB BTST.W #11, @H'E51E ; refs mem_E51E in program_or_external; cycles=6 +6F3B: 27 2A BEQ loc_6F67 ; cycles=3/8 nt/t +6F3D: 1D E9 1E 07 08 00 MOV:G.W #H'0800, @H'E91E ; refs mem_E91E in program_or_external; cycles=9 +6F43: 20 0C BRA loc_6F51 ; cycles=8 + +loc_6F45: +6F45: 1D E5 1E FC BTST.W #12, @H'E51E ; refs mem_E51E in program_or_external; cycles=6 +6F49: 27 1C BEQ loc_6F67 ; cycles=3/8 nt/t +6F4B: 1D E9 1E 07 10 00 MOV:G.W #H'1000, @H'E91E ; refs mem_E91E in program_or_external; cycles=9 + +loc_6F51: +6F51: 52 80 MOV:E.B #H'80, R2 ; dataflow R2=H'80; cycles=2 +6F53: 5B 00 8F MOV:I.W #H'008F, R3 ; dataflow R3=H'008F; cycles=3 +6F56: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +6F5A: 27 08 BEQ loc_6F64 ; cycles=3/7 nt/t +6F5C: 15 F4 04 F4 BTST.B #4, @H'F404 ; refs mem_F404 in program_or_external; cycles=7 +6F60: 27 02 BEQ loc_6F64 ; cycles=3/7 nt/t +6F62: AB CE BSET.W #14, R3 ; cycles=3 + +loc_6F64: +6F64: 1E CE ED BSR loc_3E54 ; cycles=13 + +loc_6F67: +6F67: 15 F7 11 80 MOV:G.B @H'F711, R0 ; refs ram_F711 in on_chip_ram; cycles=6 +6F6B: 04 0F 50 AND.B #H'0F, R0 ; cycles=3 +6F6E: 1D E1 1E FB BTST.W #11, @H'E11E ; refs mem_E11E in program_or_external; cycles=7 +6F72: 27 02 BEQ loc_6F76 ; cycles=3/7 nt/t +6F74: A0 C6 BSET.B #6, R0 ; cycles=2 + +loc_6F76: +6F76: 1D E1 1E FC BTST.W #12, @H'E11E ; refs mem_E11E in program_or_external; cycles=7 +6F7A: 27 02 BEQ loc_6F7E ; cycles=3/7 nt/t +6F7C: A0 C4 BSET.B #4, R0 ; cycles=2 + +loc_6F7E: +6F7E: 15 F7 11 90 MOV:G.B R0, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=7 +6F82: 20 10 BRA loc_6F94 ; cycles=7 + +loc_6F94: +6F94: 58 6F 84 MOV:I.W #H'6F84, R0 ; LCD text xref H'6F84 'OTHERS Xo'; dataflow R0=H'6F84; cycles=3 +6F97: 1E EA F7 BSR loc_5A91 ; cycles=14 +6F9A: 1E EB 65 BSR loc_5B02 ; cycles=13 +6F9D: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +6FA0: 1E CF 29 BSR loc_3ECC ; cycles=13 +6FA3: 1E F1 CD BSR loc_6173 ; cycles=14 +6FA6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +6FA9: 1E CF 20 BSR loc_3ECC ; cycles=14 +6FAC: 20 10 BRA loc_6FBE ; cycles=7 + +loc_6FBE: +6FBE: 58 6F AE MOV:I.W #H'6FAE, R0 ; LCD text xref H'6FAE 'SHUTTER Xo'; dataflow R0=H'6FAE; cycles=3 +6FC1: 1E EA CD BSR loc_5A91 ; cycles=14 +6FC4: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +6FC7: 1E CF 02 BSR loc_3ECC ; cycles=14 +6FCA: 20 10 BRA loc_6FDC ; cycles=7 + +loc_6FDC: +6FDC: 58 6F CC MOV:I.W #H'6FCC, R0 ; dataflow R0=H'6FCC; cycles=3 +6FDF: 1E EC AF BSR loc_5C91 ; cycles=14 +6FE2: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +6FE5: 1E CE E4 BSR loc_3ECC ; cycles=14 +6FE8: 19 RTS ; cycles=12 +6FF0: 1D F7 36 06 00 MOV:G.W #H'00, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +6FF5: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=9 +6FFA: 1D F7 3A 06 00 MOV:G.W #H'00, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=11 +6FFF: 1D F7 3C 06 00 MOV:G.W #H'00, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +7004: 1D F7 40 07 08 00 MOV:G.W #H'0800, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +700A: 1D F7 3E 06 00 MOV:G.W #H'00, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=11 +700F: 1D F7 42 06 00 MOV:G.W #H'00, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=9 +7014: 1D F7 54 06 00 MOV:G.W #H'00, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +7019: 15 F7 70 80 MOV:G.B @H'F770, R0 ; refs ram_F770 in on_chip_ram; cycles=6 +701D: 15 F7 70 13 CLR.B @H'F770 ; refs ram_F770 in on_chip_ram; cycles=8 +7021: 04 04 50 AND.B #H'04, R0 ; cycles=3 +7024: 37 00 76 BEQ loc_709D ; cycles=3/7 nt/t +7027: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=6 +702B: 27 1F BEQ loc_704C ; cycles=3/8 nt/t +702D: 15 F7 6E C6 BSET.B #6, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=8 +7031: 15 F7 95 C7 BSET.B #7, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=8 +7035: 15 F7 31 C7 BSET.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +7039: 15 F7 98 06 C8 MOV:G.B #H'C8, @H'F798 ; refs ram_F798 in on_chip_ram; cycles=9 +703E: 15 F7 11 C7 BSET.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=9 +7042: 15 F7 26 06 64 MOV:G.B #H'64, @H'F726 ; refs ram_F726 in on_chip_ram; cycles=9 +7047: 1E E4 B6 BSR loc_5500 ; cycles=14 +704A: 20 51 BRA loc_709D ; cycles=7 + +loc_704C: +704C: 1E F0 B7 BSR loc_6106 ; cycles=13 +704F: 20 10 BRA loc_7061 ; cycles=8 + +loc_7061: +7061: 58 70 51 MOV:I.W #H'7051, R0 ; LCD text xref H'7052 'SET RCP'; dataflow R0=H'7051; cycles=3 +7064: 1E EA 2A BSR loc_5A91 ; cycles=13 +7067: 55 01 MOV:E.B #H'01, R5 ; dataflow R5=H'01; cycles=2 +7069: 1E CE 60 BSR loc_3ECC ; cycles=14 +706C: 20 10 BRA loc_707E ; cycles=7 + +loc_707E: +707E: 58 70 6E MOV:I.W #H'706E, R0 ; LCD text xref H'706F 'MASTER'; dataflow R0=H'706E; cycles=3 +7081: 1E EA 0D BSR loc_5A91 ; cycles=14 +7084: 55 02 MOV:E.B #H'02, R5 ; dataflow R5=H'02; cycles=2 +7086: 1E CE 43 BSR loc_3ECC ; cycles=13 +7089: 1E F0 B0 BSR loc_613C ; cycles=14 +708C: 1D F7 34 07 01 01 MOV:G.W #H'0101, @H'F734 ; refs ram_F734 in on_chip_ram; cycles=11 +7092: 15 FB 03 C7 BSET.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +7096: 15 FB 02 06 14 MOV:G.B #H'14, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +709B: 20 4E BRA loc_70EB ; cycles=8 + +loc_709D: +709D: 20 10 BRA loc_70AF ; cycles=8 + +loc_70AF: +70AF: 58 70 9F MOV:I.W #H'709F, R0 ; LCD text xref H'709F 'OTHERS Xp'; dataflow R0=H'709F; cycles=3 +70B2: 1E E9 DC BSR loc_5A91 ; cycles=13 +70B5: 1E EA 4A BSR loc_5B02 ; cycles=14 +70B8: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +70BB: 1E CE 0E BSR loc_3ECC ; cycles=14 +70BE: 20 10 BRA loc_70D0 ; cycles=7 + +loc_70D0: +70D0: 58 70 C0 MOV:I.W #H'70C0, R0 ; LCD text xref H'70C0 'COPY TO SLAVES~Xp'; dataflow R0=H'70C0; cycles=3 +70D3: 1E E9 BB BSR loc_5A91 ; cycles=14 +70D6: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +70D9: 1E CD F0 BSR loc_3ECC ; cycles=14 +70DC: 1E F0 94 BSR loc_6173 ; cycles=13 +70DF: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +70E2: 1E CD E7 BSR loc_3ECC ; cycles=13 +70E5: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +70E8: 1E CD E1 BSR loc_3ECC ; cycles=13 + +loc_70EB: +70EB: 1E E9 8C BSR loc_5A7A ; cycles=14 +70EE: 19 RTS ; cycles=12 +70F6: 1D F7 36 07 10 43 MOV:G.W #H'1043, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +70FC: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=11 +7101: 1D F7 3A 07 20 43 MOV:G.W #H'2043, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=9 +7107: 1D F7 3C 06 00 MOV:G.W #H'00, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +710C: 1D F7 40 07 20 43 MOV:G.W #H'2043, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +7112: 1D F7 3E 06 00 MOV:G.W #H'00, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=11 +7117: 1D F7 42 06 00 MOV:G.W #H'00, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=9 +711C: 1D F7 54 06 46 MOV:G.W #H'46, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +7121: 20 10 BRA loc_7133 ; cycles=8 + +loc_7133: +7133: 58 71 23 MOV:I.W #H'7123, R0 ; dataflow R0=H'7123; cycles=3 +7136: 1E E9 58 BSR loc_5A91 ; cycles=13 +7139: 1E E9 C6 BSR loc_5B02 ; cycles=14 +713C: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +713F: 1E CD 8A BSR loc_3ECC ; cycles=14 +7142: 20 10 BRA loc_7154 ; cycles=7 + +loc_7154: +7154: 58 71 44 MOV:I.W #H'7144, R0 ; LCD text xref H'7144 'CAM ID SET~XqD'; dataflow R0=H'7144; cycles=3 +7157: 1E E9 37 BSR loc_5A91 ; cycles=14 +715A: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +715D: 1E CD 6C BSR loc_3ECC ; cycles=14 +7160: 59 00 43 MOV:I.W #H'0043, R1 ; dataflow R1=H'0043; cycles=3 +7163: 1E EF 05 BSR loc_606B ; cycles=14 +7166: 1E E7 8E BSR loc_58F7 ; cycles=13 +7169: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +716C: 1E CD 5D BSR loc_3ECC ; cycles=13 +716F: 1E F0 63 BSR loc_61D5 ; cycles=14 +7172: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +7175: 1E CD 54 BSR loc_3ECC ; cycles=14 +7178: 58 00 02 MOV:I.W #H'0002, R0 ; dataflow R0=H'0002; cycles=3 +717B: 1E E7 EC BSR loc_596A ; cycles=14 +717E: 1E E8 F9 BSR loc_5A7A ; cycles=13 +7181: 19 RTS ; cycles=13 +7188: 1D F7 36 06 00 MOV:G.W #H'00, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +718D: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=9 +7192: 1D F7 3A 06 00 MOV:G.W #H'00, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=11 +7197: 1D F7 3C 06 00 MOV:G.W #H'00, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +719C: 1D F7 40 06 00 MOV:G.W #H'00, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +71A1: 1D F7 3E 06 37 MOV:G.W #H'37, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=9 +71A6: 1D F7 46 07 F7 FF MOV:G.W #H'F7FF, @H'F746 ; refs ram_F746 in on_chip_ram; cycles=11 +71AC: 1D F7 4E 07 08 00 MOV:G.W #H'0800, @H'F74E ; refs ram_F74E in on_chip_ram; cycles=11 +71B2: 1D F7 42 06 37 MOV:G.W #H'37, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=11 +71B7: 1D F7 4A 07 F7 FF MOV:G.W #H'F7FF, @H'F74A ; refs ram_F74A in on_chip_ram; cycles=9 +71BD: 1D F7 52 06 00 MOV:G.W #H'00, @H'F752 ; refs ram_F752 in on_chip_ram; cycles=9 +71C2: 1D F7 54 06 00 MOV:G.W #H'00, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +71C7: 20 10 BRA loc_71D9 ; cycles=8 + +loc_71D9: +71D9: 58 71 C9 MOV:I.W #H'71C9, R0 ; LCD text xref H'71C9 'OTHERS Xq'; dataflow R0=H'71C9; cycles=3 +71DC: 1E E8 B2 BSR loc_5A91 ; cycles=13 +71DF: 1E E9 20 BSR loc_5B02 ; cycles=14 +71E2: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +71E5: 1E CC E4 BSR loc_3ECC ; cycles=14 +71E8: 1E EF 88 BSR loc_6173 ; cycles=13 +71EB: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +71EE: 1E CC DB BSR loc_3ECC ; cycles=13 +71F1: 15 F7 30 F7 BTST.B #7, @H'F730 ; refs ram_F730 in on_chip_ram; cycles=6 +71F5: 27 1A BEQ loc_7211 ; cycles=3/8 nt/t +71F7: 20 10 BRA loc_7209 ; cycles=8 + +loc_7209: +7209: 58 71 F9 MOV:I.W #H'71F9, R0 ; LCD text xref H'71F9 'CAM ID IND Xq'; dataflow R0=H'71F9; cycles=3 +720C: 1E E8 82 BSR loc_5A91 ; cycles=13 +720F: 20 18 BRA loc_7229 ; cycles=8 + +loc_7211: +7211: 20 10 BRA loc_7223 ; cycles=8 + +loc_7223: +7223: 58 72 13 MOV:I.W #H'7213, R0 ; LCD text xref H'7213 'TITLE IND Xr'; dataflow R0=H'7213; cycles=3 +7226: 1E E8 68 BSR loc_5A91 ; cycles=13 + +loc_7229: +7229: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +722C: 1E CC 9D BSR loc_3ECC ; cycles=13 +722F: 20 10 BRA loc_7241 ; cycles=8 + +loc_7241: +7241: 58 72 31 MOV:I.W #H'7231, R0 ; dataflow R0=H'7231; cycles=3 +7244: 1E EA 4A BSR loc_5C91 ; cycles=13 +7247: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +724A: 1E CC 7F BSR loc_3ECC ; cycles=13 +724D: 1E E7 B4 BSR loc_5A04 ; cycles=14 +7250: 19 RTS ; cycles=12 +7258: 1D F7 36 06 00 MOV:G.W #H'00, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +725D: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=9 +7262: 1D F7 3A 06 00 MOV:G.W #H'00, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=11 +7267: 1D F7 3C 06 38 MOV:G.W #H'38, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +726C: 1D F7 44 07 3F FF MOV:G.W #H'3FFF, @H'F744 ; refs ram_F744 in on_chip_ram; cycles=11 +7272: 1D F7 4C 07 80 00 MOV:G.W #H'8000, @H'F74C ; refs ram_F74C in on_chip_ram; cycles=11 +7278: 1D F7 40 06 38 MOV:G.W #H'38, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +727D: 1D F7 48 07 3F FF MOV:G.W #H'3FFF, @H'F748 ; refs ram_F748 in on_chip_ram; cycles=9 +7283: 1D F7 50 07 40 00 MOV:G.W #H'4000, @H'F750 ; refs ram_F750 in on_chip_ram; cycles=9 +7289: 1D F7 3E 06 00 MOV:G.W #H'00, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=9 +728E: 1D F7 42 06 38 MOV:G.W #H'38, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=11 +7293: 1D F7 4A 07 3F FF MOV:G.W #H'3FFF, @H'F74A ; refs ram_F74A in on_chip_ram; cycles=9 +7299: 1D F7 52 06 00 MOV:G.W #H'00, @H'F752 ; refs ram_F752 in on_chip_ram; cycles=9 +729E: 1D F7 54 06 00 MOV:G.W #H'00, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +72A3: 20 10 BRA loc_72B5 ; cycles=8 + +loc_72B5: +72B5: 58 72 A5 MOV:I.W #H'72A5, R0 ; LCD text xref H'72A5 'OTHERS Xr'; dataflow R0=H'72A5; cycles=3 +72B8: 1E E7 D6 BSR loc_5A91 ; cycles=13 +72BB: 1E E8 44 BSR loc_5B02 ; cycles=14 +72BE: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +72C1: 1E CC 08 BSR loc_3ECC ; cycles=14 +72C4: 20 10 BRA loc_72D6 ; cycles=7 + +loc_72D6: +72D6: 58 72 C6 MOV:I.W #H'72C6, R0 ; LCD text xref H'72C7 'CAM BARS~Xr'; dataflow R0=H'72C6; cycles=3 +72D9: 1E E8 AC BSR loc_5B88 ; cycles=14 +72DC: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +72DF: 1E CB EA BSR loc_3ECC ; cycles=14 +72E2: 20 10 BRA loc_72F4 ; cycles=7 + +loc_72F4: +72F4: 58 72 E4 MOV:I.W #H'72E4, R0 ; LCD text xref H'72E4 'CLOCK IND Xr'; dataflow R0=H'72E4; cycles=3 +72F7: 1E E7 97 BSR loc_5A91 ; cycles=14 +72FA: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +72FD: 1E CB CC BSR loc_3ECC ; cycles=14 +7300: 20 10 BRA loc_7312 ; cycles=7 + +loc_7312: +7312: 58 73 02 MOV:I.W #H'7302, R0 ; dataflow R0=H'7302; cycles=3 +7315: 1E E9 79 BSR loc_5C91 ; cycles=14 +7318: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +731B: 1E CB AE BSR loc_3ECC ; cycles=14 +731E: 1E E6 E3 BSR loc_5A04 ; cycles=13 +7321: 19 RTS ; cycles=13 +7328: 1D F7 36 06 00 MOV:G.W #H'00, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +732D: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=9 +7332: 1D F7 3A 06 00 MOV:G.W #H'00, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=11 +7337: 1D F7 3C 06 00 MOV:G.W #H'00, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +733C: 1D F7 40 06 00 MOV:G.W #H'00, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +7341: 1D F7 3E 06 27 MOV:G.W #H'27, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=9 +7346: 1D F7 46 07 7F FF MOV:G.W #H'7FFF, @H'F746 ; refs ram_F746 in on_chip_ram; cycles=11 +734C: 1D F7 4E 07 80 00 MOV:G.W #H'8000, @H'F74E ; refs ram_F74E in on_chip_ram; cycles=11 +7352: 1D F7 42 06 27 MOV:G.W #H'27, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=11 +7357: 1D F7 4A 07 7F FF MOV:G.W #H'7FFF, @H'F74A ; refs ram_F74A in on_chip_ram; cycles=9 +735D: 1D F7 52 06 00 MOV:G.W #H'00, @H'F752 ; refs ram_F752 in on_chip_ram; cycles=9 +7362: 1D F7 54 06 00 MOV:G.W #H'00, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +7367: 20 10 BRA loc_7379 ; cycles=8 + +loc_7379: +7379: 58 73 69 MOV:I.W #H'7369, R0 ; LCD text xref H'7369 'OTHERS Xsi'; dataflow R0=H'7369; cycles=3 +737C: 1E E7 12 BSR loc_5A91 ; cycles=13 +737F: 1E E7 80 BSR loc_5B02 ; cycles=14 +7382: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +7385: 1E CB 44 BSR loc_3ECC ; cycles=14 +7388: 1E ED E8 BSR loc_6173 ; cycles=13 +738B: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +738E: 1E CB 3B BSR loc_3ECC ; cycles=13 +7391: 20 10 BRA loc_73A3 ; cycles=8 + +loc_73A3: +73A3: 58 73 93 MOV:I.W #H'7393, R0 ; LCD text xref H'7393 'CENTER MARKER Xs'; dataflow R0=H'7393; cycles=3 +73A6: 1E E6 E8 BSR loc_5A91 ; cycles=13 +73A9: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +73AC: 1E CB 1D BSR loc_3ECC ; cycles=13 +73AF: 20 10 BRA loc_73C1 ; cycles=8 + +loc_73C1: +73C1: 58 73 B1 MOV:I.W #H'73B1, R0 ; dataflow R0=H'73B1; cycles=3 +73C4: 1E E8 CA BSR loc_5C91 ; cycles=13 +73C7: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +73CA: 1E CA FF BSR loc_3ECC ; cycles=13 +73CD: 1E E6 34 BSR loc_5A04 ; cycles=14 +73D0: 19 RTS ; cycles=12 +73D8: 1D F7 36 06 00 MOV:G.W #H'00, @H'F736 ; refs ram_F736 in on_chip_ram; cycles=11 +73DD: 1D F7 38 06 00 MOV:G.W #H'00, @H'F738 ; refs ram_F738 in on_chip_ram; cycles=9 +73E2: 1D F7 3A 06 00 MOV:G.W #H'00, @H'F73A ; refs ram_F73A in on_chip_ram; cycles=11 +73E7: 1D F7 3C 06 27 MOV:G.W #H'27, @H'F73C ; refs ram_F73C in on_chip_ram; cycles=9 +73EC: 1D F7 44 07 CF FF MOV:G.W #H'CFFF, @H'F744 ; refs ram_F744 in on_chip_ram; cycles=11 +73F2: 1D F7 4C 07 20 00 MOV:G.W #H'2000, @H'F74C ; refs ram_F74C in on_chip_ram; cycles=11 +73F8: 1D F7 40 06 27 MOV:G.W #H'27, @H'F740 ; refs ram_F740 in on_chip_ram; cycles=11 +73FD: 1D F7 48 07 CF FF MOV:G.W #H'CFFF, @H'F748 ; refs ram_F748 in on_chip_ram; cycles=9 +7403: 1D F7 50 07 10 00 MOV:G.W #H'1000, @H'F750 ; refs ram_F750 in on_chip_ram; cycles=9 +7409: 1D F7 3E 06 00 MOV:G.W #H'00, @H'F73E ; refs ram_F73E in on_chip_ram; cycles=9 +740E: 1D F7 42 06 27 MOV:G.W #H'27, @H'F742 ; refs ram_F742 in on_chip_ram; cycles=11 +7413: 1D F7 4A 07 CF FF MOV:G.W #H'CFFF, @H'F74A ; refs ram_F74A in on_chip_ram; cycles=9 +7419: 1D F7 52 06 00 MOV:G.W #H'00, @H'F752 ; refs ram_F752 in on_chip_ram; cycles=9 +741E: 1D F7 54 06 00 MOV:G.W #H'00, @H'F754 ; refs ram_F754 in on_chip_ram; cycles=11 +7423: 20 10 BRA loc_7435 ; cycles=8 + +loc_7435: +7435: 58 74 25 MOV:I.W #H'7425, R0 ; LCD text xref H'7425 'OTHERS Xt%'; dataflow R0=H'7425; cycles=3 +7438: 1E E6 56 BSR loc_5A91 ; cycles=13 +743B: 1E E6 C4 BSR loc_5B02 ; cycles=14 +743E: 5D 00 00 MOV:I.W #H'0000, R5 ; dataflow R5=H'0000; cycles=3 +7441: 1E CA 88 BSR loc_3ECC ; cycles=14 +7444: 20 10 BRA loc_7456 ; cycles=7 + +loc_7456: +7456: 58 74 46 MOV:I.W #H'7446, R0 ; dataflow R0=H'7446; cycles=3 +7459: 1E E7 2C BSR loc_5B88 ; cycles=14 +745C: 5D 00 01 MOV:I.W #H'0001, R5 ; dataflow R5=H'0001; cycles=3 +745F: 1E CA 6A BSR loc_3ECC ; cycles=14 +7462: 20 10 BRA loc_7474 ; cycles=7 + +loc_7474: +7474: 58 74 64 MOV:I.W #H'7464, R0 ; LCD text xref H'7464 'SAFETY ZONE Xtd'; dataflow R0=H'7464; cycles=3 +7477: 1E E6 17 BSR loc_5A91 ; cycles=14 +747A: 5D 00 02 MOV:I.W #H'0002, R5 ; dataflow R5=H'0002; cycles=3 +747D: 1E CA 4C BSR loc_3ECC ; cycles=14 +7480: 20 10 BRA loc_7492 ; cycles=7 + +loc_7492: +7492: 58 74 82 MOV:I.W #H'7482, R0 ; dataflow R0=H'7482; cycles=3 +7495: 1E E7 F9 BSR loc_5C91 ; cycles=14 +7498: 5D 00 03 MOV:I.W #H'0003, R5 ; dataflow R5=H'0003; cycles=3 +749B: 1E CA 2E BSR loc_3ECC ; cycles=14 +749E: 1E E5 63 BSR loc_5A04 ; cycles=13 +74A1: 19 RTS ; cycles=13 + +loc_BA26: +BA26: 15 F9 C0 16 TST.B @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=7 +BA2A: 26 FA BNE loc_BA26 ; cycles=3/7 nt/t +BA2C: 15 F9 C0 06 64 MOV:G.B #H'64, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BA31: 15 F9 C4 06 07 MOV:G.B #H'07, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=9 +BA36: 1D F8 50 80 MOV:G.W @H'F850, R0 ; refs ram_F850 in on_chip_ram; cycles=7 +BA3A: 1D F8 58 90 MOV:G.W R0, @H'F858 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA3E: 1D F8 52 80 MOV:G.W @H'F852, R0 ; refs ram_F852 in on_chip_ram; cycles=7 +BA42: 1D F8 5A 90 MOV:G.W R0, @H'F85A ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA46: 15 F8 54 80 MOV:G.B @H'F854, R0 ; refs ram_F854 in on_chip_ram; cycles=7 +BA4A: 15 F8 5C 90 MOV:G.B R0, @H'F85C ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA4E: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high; dataflow R0=H'5A; cycles=2 +BA50: 15 F8 58 60 XOR.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA54: 15 F8 59 60 XOR.B @H'F859, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F859 in on_chip_ram; cycles=7 +BA58: 15 F8 5A 60 XOR.B @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85A in on_chip_ram; cycles=7 +BA5C: 15 F8 5B 60 XOR.B @H'F85B, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85B in on_chip_ram; cycles=7 +BA60: 15 F8 5C 60 XOR.B @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85C in on_chip_ram; cycles=7 +BA64: 15 F8 5D 90 MOV:G.B R0, @H'F85D ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high; refs ram_F85D in on_chip_ram; cycles=7 + +loc_BA68: +BA68: 15 FE DC F7 BTST.B #7, @SCI1_SSR ; wait for SCI1 transmit data register empty (TDRE=1); SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; refs SCI1_SSR in register_field; cycles=7 +BA6C: 27 FA BEQ loc_BA68 ; repeat SCI1 transmit-empty wait while TDRE=0; cycles=3/7 nt/t +BA6E: 15 F8 58 80 MOV:G.B @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; refs ram_F858 in on_chip_ram; cycles=7 +BA72: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=7 +BA76: 15 F9 C2 06 01 MOV:G.B #H'01, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high; refs ram_F9C2 in on_chip_ram; cycles=9 +BA7B: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BA7F: 15 FE DA C7 BSET.B #7, @SCI1_SCR ; set TIE (bit 7) of SCI1_SCR; enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=8 +BA83: 19 RTS ; cycles=13 + +vec_sci1_txi_BA84: +BA84: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BA88: 27 1F BEQ loc_BAA9 ; cycles=3/7 nt/t +BA8A: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BA8E: 27 19 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA90: 15 F9 C3 16 TST.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BA94: 27 13 BEQ loc_BAA9 ; cycles=3/7 nt/t +BA96: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BA9A: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BA9E: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BAA2: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAA7: 20 48 BRA loc_BAF1 ; cycles=8 + +loc_BAA9: +BAA9: BF 90 MOV:G.W R0, @-R7 ; cycles=5 +BAAB: 15 F9 C2 80 MOV:G.B @H'F9C2, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAAF: A0 12 EXTU.B R0 ; cycles=3 +BAB1: F0 F8 58 80 MOV:G.B @(-H'07A8,R0), R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; cycles=6 +BAB5: 15 FE DB 90 MOV:G.B R0, @SCI1_TDR ; SCI1_TDR; write RS232/SCI byte to SCI1 TDR for transmission; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high; SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11; cycles=6 +BAB9: CF 80 MOV:G.W @R7+, R0 ; cycles=6 +BABB: 15 FE DC D7 BCLR.B #7, @SCI1_SSR ; clear TDRE (bit 7) of SCI1_SSR; clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BABF: 15 F9 C2 08 ADD:Q.B #1, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high; refs ram_F9C2 in on_chip_ram; cycles=8 +BAC3: 15 F9 C2 04 06 CMP:G.B #H'06, @H'F9C2 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high; refs ram_F9C2 in on_chip_ram; cycles=6 +BAC8: 26 27 BNE loc_BAF1 ; cycles=3/7 nt/t +BACA: 15 FE DA D7 BCLR.B #7, @SCI1_SCR ; clear TIE (bit 7) of SCI1_SCR; disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE; SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12); cycles=9 +BACE: 15 F7 95 F6 BTST.B #6, @H'F795 ; refs ram_F795 in on_chip_ram; cycles=7 +BAD2: 26 14 BNE loc_BAE8 ; cycles=3/7 nt/t +BAD4: 15 F7 91 F7 BTST.B #7, @H'F791 ; refs ram_F791 in on_chip_ram; cycles=7 +BAD8: 26 07 BNE loc_BAE1 ; cycles=3/7 nt/t +BADA: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BADF: 20 0C BRA loc_BAED ; cycles=8 + +loc_BAE1: +BAE1: 15 F9 C0 06 09 MOV:G.B #H'09, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BAE6: 20 05 BRA loc_BAED ; cycles=7 + +loc_BAE8: +BAE8: 15 F9 C0 06 F0 MOV:G.B #H'F0, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BAED: +BAED: 15 F9 C1 13 CLR.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=8 + +loc_BAF1: +BAF1: 0A RTE ; cycles=14 + +loc_BAF2: +BAF2: 15 F9 B5 81 MOV:G.B @H'F9B5, R1 ; refs ram_F9B5 in on_chip_ram; cycles=7 +BAF6: A1 12 EXTU.B R1 ; cycles=3 +BAF8: 15 F9 B0 71 CMP:G.B @H'F9B0, R1 ; refs ram_F9B0 in on_chip_ram; cycles=7 +BAFC: 26 02 BNE loc_BB00 ; cycles=3/7 nt/t +BAFE: 20 56 BRA loc_BB56 ; cycles=7 + +loc_BB00: +BB00: 15 FA A2 C3 BSET.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BB04: A9 80 MOV:G.W R1, R0 ; cycles=3 +BB06: A8 1A SHLL.W R0 ; cycles=3 +BB08: F8 F8 70 80 MOV:G.W @(-H'0790,R0), R0 ; cycles=7 +BB0C: A8 85 MOV:G.W R0, R5 ; cycles=3 +BB0E: 1E A6 F5 BSR loc_6206 ; cycles=13 +BB11: A8 81 MOV:G.W R0, R1 ; cycles=3 +BB13: A1 10 SWAP.B R1 ; cycles=3 +BB15: A1 1B SHLR.B R1 ; cycles=2 +BB17: A1 82 MOV:G.B R1, R2 ; cycles=2 +BB19: 04 07 51 AND.B #H'07, R1 ; cycles=3 +BB1C: 15 F8 50 91 MOV:G.B R1, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=7 +BB20: 15 F8 52 95 MOV:G.B R5, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BB24: A5 10 SWAP.B R5 ; cycles=3 +BB26: 04 78 52 AND.B #H'78, R2 ; cycles=3 +BB29: A2 45 OR.B R2, R5 ; cycles=2 +BB2B: 15 F8 51 95 MOV:G.B R5, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BB2F: 0C 01 FF 50 AND.W #H'01FF, R0 ; cycles=4 +BB33: A8 1A SHLL.W R0 ; cycles=3 +BB35: F8 E8 00 84 MOV:G.W @(-H'1800,R0), R4 ; cycles=6 +BB39: 15 F8 54 94 MOV:G.B R4, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BB3D: A4 10 SWAP.B R4 ; cycles=3 +BB3F: 15 F8 53 94 MOV:G.B R4, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=6 +BB43: 1E FE E0 BSR loc_BA26 ; cycles=14 +BB46: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=11 +BB4C: 15 F9 C8 06 14 MOV:G.B #H'14, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=9 +BB51: 15 FA A3 06 80 MOV:G.B #H'80, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 + +loc_BB56: +BB56: 19 RTS ; cycles=12 + +vec_sci1_eri_BB57: +BB57: 15 FA A4 C7 BSET.B #7, @H'FAA4 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; refs ram_FAA4 in on_chip_ram; cycles=8 +BB5B: 15 FE DC D5 BCLR.B #5, @SCI1_SSR ; clear ORER (bit 5) of SCI1_SSR; clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB5F: 15 FE DC D4 BCLR.B #4, @SCI1_SSR ; clear FER (bit 4) of SCI1_SSR; clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB63: 15 FE DC D3 BCLR.B #3, @SCI1_SSR ; clear PER (bit 3) of SCI1_SSR; clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 + +vec_sci1_rxi_BB67: +BB67: 12 03 STM.W {R0,R1}, @-SP ; cycles=12 +BB69: 15 FE DC D6 BCLR.B #6, @SCI1_SSR ; clear RDRF (bit 6) of SCI1_SSR; clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use; cycles=8 +BB6D: 15 FE DD 80 MOV:G.B @SCI1_RDR, R0 ; read SCI1 received byte from RDR; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high; SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD; refs SCI1_RDR in register_field; cycles=6 +BB71: 15 F9 C1 16 TST.B @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=6 +BB75: 26 06 BNE loc_BB7D ; cycles=3/8 nt/t +BB77: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BB7B: 20 0D BRA loc_BB8A ; cycles=8 + +loc_BB7D: +BB7D: 15 F9 C3 04 05 CMP:G.B #H'05, @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=6 +BB82: 23 06 BLS loc_BB8A ; cycles=3/7 nt/t +BB84: 15 FA A4 13 CLR.B @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=9 +BB88: 20 19 BRA loc_BBA3 ; cycles=7 + +loc_BB8A: +BB8A: 15 F9 C3 81 MOV:G.B @H'F9C3, R1 ; refs ram_F9C3 in on_chip_ram; cycles=7 +BB8E: A1 12 EXTU.B R1 ; cycles=3 +BB90: F1 F8 68 90 MOV:G.B R0, @(-H'0798,R1) ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high; cycles=7 +BB94: A1 08 ADD:Q.B #1, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; cycles=4 +BB96: 15 F9 C3 91 MOV:G.B R1, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high; refs ram_F9C3 in on_chip_ram; cycles=7 +BB9A: 41 06 CMP:E #H'06, R1 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high; cycles=2 +BB9C: 26 05 BNE loc_BBA3 ; cycles=3/7 nt/t +BB9E: 15 F9 C5 06 14 MOV:G.B #H'14, @H'F9C5 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BBA3: +BBA3: 15 F9 C1 06 05 MOV:G.B #H'05, @H'F9C1 ; refs ram_F9C1 in on_chip_ram; cycles=9 +BBA8: 02 03 LDM.W @SP+, {R0,R1} ; cycles=14 +BBAA: 0A RTE ; cycles=13 + +loc_BBAB: +BBAB: 15 F9 C3 04 06 CMP:G.B #H'06, @H'F9C3 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high; refs ram_F9C3 in on_chip_ram; cycles=6 +BBB0: 36 02 BC BNE loc_BE6F ; cycles=3/7 nt/t +BBB3: 1D F8 68 80 MOV:G.W @H'F868, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F868 in on_chip_ram; cycles=6 +BBB7: 1D F8 60 90 MOV:G.W R0, @H'F860 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=6 +BBBB: 1D F8 6A 80 MOV:G.W @H'F86A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86A in on_chip_ram; cycles=6 +BBBF: 1D F8 62 90 MOV:G.W R0, @H'F862 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=6 +BBC3: 1D F8 6C 80 MOV:G.W @H'F86C, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F86C in on_chip_ram; cycles=6 +BBC7: 1D F8 64 90 MOV:G.W R0, @H'F864 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=6 +BBCB: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BBCF: 15 FA A4 F7 BTST.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=6 +BBD3: 36 02 53 BNE loc_BE29 ; cycles=3/8 nt/t +BBD6: 50 5A MOV:E.B #H'5A, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; dataflow R0=H'5A; cycles=2 +BBD8: 15 F8 60 60 XOR.B @H'F860, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F860 in on_chip_ram; cycles=7 +BBDC: 15 F8 61 60 XOR.B @H'F861, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F861 in on_chip_ram; cycles=7 +BBE0: 15 F8 62 60 XOR.B @H'F862, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F862 in on_chip_ram; cycles=7 +BBE4: 15 F8 63 60 XOR.B @H'F863, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F863 in on_chip_ram; cycles=7 +BBE8: 15 F8 64 60 XOR.B @H'F864, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F864 in on_chip_ram; cycles=7 +BBEC: 15 F8 65 70 CMP:G.B @H'F865, R0 ; candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high; refs ram_F865 in on_chip_ram; cycles=7 +BBF0: 36 02 36 BNE loc_BE29 ; cycles=3/7 nt/t +BBF3: 15 FA A6 13 CLR.B @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BBF7: 15 F8 61 85 MOV:G.B @H'F861, R5 ; refs ram_F861 in on_chip_ram; cycles=6 +BBFB: A5 10 SWAP.B R5 ; cycles=3 +BBFD: 15 F8 62 85 MOV:G.B @H'F862, R5 ; refs ram_F862 in on_chip_ram; cycles=6 +BC01: 1E A6 27 BSR loc_622B ; cycles=14 +BC04: AD 84 MOV:G.W R5, R4 ; cycles=3 +BC06: AC 1A SHLL.W R4 ; cycles=3 +BC08: 15 F8 60 80 MOV:G.B @H'F860, R0 ; refs ram_F860 in on_chip_ram; cycles=7 +BC0C: 04 07 50 AND.B #H'07, R0 ; cycles=3 +BC0F: 15 FA A2 16 TST.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BC13: 26 25 BNE loc_BC3A ; cycles=3/8 nt/t + +loc_BC15: +BC15: 15 FA A2 C7 BSET.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC19: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=6 +BC1D: 36 00 EB BNE loc_BD0B ; cycles=3/8 nt/t +BC20: 40 00 CMP:E #H'00, R0 ; cycles=2 +BC22: 27 45 BEQ loc_BC69 ; cycles=3/7 nt/t +BC24: 40 01 CMP:E #H'01, R0 ; cycles=2 +BC26: 37 00 AE BEQ loc_BCD7 ; cycles=3/7 nt/t +BC29: 40 02 CMP:E #H'02, R0 ; cycles=2 +BC2B: 37 00 D6 BEQ loc_BD04 ; cycles=3/8 nt/t +BC2E: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC30: 37 01 D2 BEQ loc_BE05 ; cycles=3/7 nt/t +BC33: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BC37: 30 02 35 BRA loc_BE6F ; cycles=8 + +loc_BC3A: +BC3A: A0 F2 BTST.B #2, R0 ; cycles=2 +BC3C: 27 1E BEQ loc_BC5C ; cycles=3/7 nt/t +BC3E: 15 F8 61 F7 BTST.B #7, @H'F861 ; refs ram_F861 in on_chip_ram; cycles=7 +BC42: 36 01 E2 BNE loc_BE27 ; cycles=3/7 nt/t +BC45: 40 04 CMP:E #H'04, R0 ; cycles=2 +BC47: 37 00 C4 BEQ loc_BD0E ; cycles=3/8 nt/t +BC4A: 40 05 CMP:E #H'05, R0 ; cycles=2 +BC4C: 37 01 31 BEQ loc_BD80 ; cycles=3/7 nt/t +BC4F: 40 06 CMP:E #H'06, R0 ; cycles=2 +BC51: 37 01 87 BEQ loc_BDDB ; cycles=3/8 nt/t +BC54: 40 07 CMP:E #H'07, R0 ; cycles=2 +BC56: 37 01 AC BEQ loc_BE05 ; cycles=3/7 nt/t +BC59: 30 02 13 BRA loc_BE6F ; cycles=8 + +loc_BC5C: +BC5C: 15 FA A2 D3 BCLR.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BC60: 37 02 0C BEQ loc_BE6F ; cycles=3/7 nt/t +BC63: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BC67: 20 AC BRA loc_BC15 ; cycles=8 + +loc_BC69: +BC69: AD 16 TST.W R5 ; cycles=3 +BC6B: 26 1E BNE loc_BC8B ; cycles=3/8 nt/t +BC6D: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC71: A0 10 SWAP.B R0 ; cycles=3 +BC73: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BC75: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC79: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC7D: 15 F8 64 06 80 MOV:G.B #H'80, @H'F864 ; refs ram_F864 in on_chip_ram; cycles=9 +BC82: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BC86: 1E 01 E7 BSR loc_BE70 ; cycles=13 +BC89: 20 25 BRA loc_BCB0 ; cycles=8 + +loc_BC8B: +BC8B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BC8F: A0 10 SWAP.B R0 ; cycles=3 +BC91: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BC95: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BC99: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=6 +BC9D: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BCA1: FC C5 64 81 MOV:G.W @(-H'3A9C,R4), R1 ; cycles=6 +BCA5: A1 12 EXTU.B R1 ; cycles=3 +BCA7: 27 04 BEQ loc_BCAD ; cycles=3/8 nt/t +BCA9: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 + +loc_BCAD: +BCAD: 1E 01 C0 BSR loc_BE70 ; cycles=14 + +loc_BCB0: +BCB0: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCB5: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=6 +BCB9: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=6 +BCBD: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=6 +BCC1: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BCC5: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BCC9: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BCCD: 1E FD 56 BSR loc_BA26 ; cycles=14 +BCD0: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BCD4: 30 01 98 BRA loc_BE6F ; cycles=7 + +loc_BCD7: +BCD7: 15 F8 50 06 04 MOV:G.B #H'04, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BCDC: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BCE0: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCE4: 15 F8 62 80 MOV:G.B @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BCE8: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BCEC: FC E0 00 80 MOV:G.W @(-H'2000,R4), R0 ; cycles=7 +BCF0: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BCF4: A0 10 SWAP.B R0 ; cycles=3 +BCF6: 15 F8 53 90 MOV:G.B R0, @H'F853 ; refs ram_F853 in on_chip_ram; cycles=7 +BCFA: 1E FD 29 BSR loc_BA26 ; cycles=13 +BCFD: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD01: 30 01 6B BRA loc_BE6F ; cycles=8 + +loc_BD04: +BD04: 15 FA A2 D7 BCLR.B #7, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BD08: 30 01 64 BRA loc_BE6F ; cycles=7 + +loc_BD0B: +BD0B: 30 01 61 BRA loc_BE6F ; cycles=8 + +loc_BD0E: +BD0E: AD 16 TST.W R5 ; cycles=3 +BD10: 26 19 BNE loc_BD2B ; cycles=3/7 nt/t +BD12: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=7 +BD16: A0 10 SWAP.B R0 ; cycles=3 +BD18: 50 80 MOV:E.B #H'80, R0 ; dataflow R0=H'80; cycles=2 +BD1A: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=7 +BD1E: FC E8 00 90 MOV:G.W R0, @(-H'1800,R4) ; cycles=7 +BD22: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=9 +BD26: 1E 01 47 BSR loc_BE70 ; cycles=13 +BD29: 20 3C BRA loc_BD67 ; cycles=8 + +loc_BD2B: +BD2B: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BD2F: A0 10 SWAP.B R0 ; cycles=3 +BD31: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BD35: FC E0 00 90 MOV:G.W R0, @(-H'2000,R4) ; cycles=6 +BD39: F5 EC 00 C7 BSET.B #7, @(-H'1400,R5) ; cycles=8 +BD3D: F4 C5 65 81 MOV:G.B @(-H'3A9B,R4), R1 ; cycles=6 +BD41: A1 12 EXTU.B R1 ; cycles=3 +BD43: 27 1F BEQ loc_BD64 ; cycles=3/8 nt/t +BD45: F9 F4 00 90 MOV:G.W R0, @(-H'0C00,R1) ; cycles=6 +BD49: 15 F7 6E F7 BTST.B #7, @H'F76E ; refs ram_F76E in on_chip_ram; cycles=6 +BD4D: 27 15 BEQ loc_BD64 ; cycles=3/8 nt/t +BD4F: 12 31 STM.W {R0,R4,R5}, @-SP ; cycles=15 +BD51: 15 F7 6E 84 MOV:G.B @H'F76E, R4 ; refs ram_F76E in on_chip_ram; cycles=6 +BD55: A4 10 SWAP.B R4 ; cycles=3 +BD57: A1 84 MOV:G.B R1, R4 ; cycles=2 +BD59: 0C 0F FE 54 AND.W #H'0FFE, R4 ; cycles=4 +BD5D: A8 85 MOV:G.W R0, R5 ; cycles=3 +BD5F: 1E 02 7E BSR loc_BFE0 ; cycles=14 +BD62: 02 31 LDM.W @SP+, {R0,R4,R5} ; cycles=18 + +loc_BD64: +BD64: 1E 01 09 BSR loc_BE70 ; cycles=13 + +loc_BD67: +BD67: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BD6B: 27 08 BEQ loc_BD75 ; cycles=3/8 nt/t +BD6D: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BD71: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BD75: +BD75: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BD79: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BD7D: 30 00 EF BRA loc_BE6F ; cycles=8 + +loc_BD80: +BD80: 4D 00 6C CMP:I #H'006C, R5 ; cycles=3 +BD83: 27 3A BEQ loc_BDBF ; cycles=3/8 nt/t +BD85: 4D 00 6D CMP:I #H'006D, R5 ; cycles=3 +BD88: 27 35 BEQ loc_BDBF ; cycles=3/7 nt/t +BD8A: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD8D: 27 30 BEQ loc_BDBF ; cycles=3/8 nt/t +BD8F: 4D 00 6E CMP:I #H'006E, R5 ; cycles=3 +BD92: 27 2B BEQ loc_BDBF ; cycles=3/7 nt/t +BD94: 15 F7 31 F7 BTST.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=7 +BD98: 27 28 BEQ loc_BDC2 ; cycles=3/7 nt/t +BD9A: 4D 00 6B CMP:I #H'006B, R5 ; cycles=3 +BD9D: 27 16 BEQ loc_BDB5 ; cycles=3/8 nt/t +BD9F: 4D 00 96 CMP:I #H'0096, R5 ; cycles=3 +BDA2: 27 11 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDA4: 4D 00 97 CMP:I #H'0097, R5 ; cycles=3 +BDA7: 27 0C BEQ loc_BDB5 ; cycles=3/8 nt/t +BDA9: 4D 00 C6 CMP:I #H'00C6, R5 ; cycles=3 +BDAC: 27 07 BEQ loc_BDB5 ; cycles=3/7 nt/t +BDAE: 4D 00 F8 CMP:I #H'00F8, R5 ; cycles=3 +BDB1: 27 02 BEQ loc_BDB5 ; cycles=3/8 nt/t +BDB3: 20 0D BRA loc_BDC2 ; cycles=8 + +loc_BDB5: +BDB5: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 +BDB9: 15 F7 90 D7 BCLR.B #7, @H'F790 ; refs ram_F790 in on_chip_ram; cycles=8 +BDBD: 20 03 BRA loc_BDC2 ; cycles=8 + +loc_BDBF: +BDBF: 1E 00 AE BSR loc_BE70 ; cycles=14 + +loc_BDC2: +BDC2: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=7 +BDC6: 27 08 BEQ loc_BDD0 ; cycles=3/7 nt/t +BDC8: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 +BDCC: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=9 + +loc_BDD0: +BDD0: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=9 +BDD4: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=9 +BDD8: 30 00 94 BRA loc_BE6F ; cycles=7 + +loc_BDDB: +BDDB: 15 F8 63 80 MOV:G.B @H'F863, R0 ; refs ram_F863 in on_chip_ram; cycles=6 +BDDF: A0 10 SWAP.B R0 ; cycles=3 +BDE1: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=6 +BDE5: FC E4 00 90 MOV:G.W R0, @(-H'1C00,R4) ; cycles=6 +BDE9: F5 EC 00 C6 BSET.B #6, @(-H'1400,R5) ; cycles=8 +BDED: 15 FA A2 F3 BTST.B #3, @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=6 +BDF1: 27 08 BEQ loc_BDFB ; cycles=3/8 nt/t +BDF3: 15 F9 B5 08 ADD:Q.B #1, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 +BDF7: 15 F9 B5 D7 BCLR.B #7, @H'F9B5 ; refs ram_F9B5 in on_chip_ram; cycles=8 + +loc_BDFB: +BDFB: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BDFF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE03: 20 6A BRA loc_BE6F ; cycles=8 + +loc_BE05: +BE05: 1D F8 58 80 MOV:G.W @H'F858, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F858 in on_chip_ram; cycles=6 +BE09: 1D F8 50 90 MOV:G.W R0, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=6 +BE0D: 1D F8 5A 80 MOV:G.W @H'F85A, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85A in on_chip_ram; cycles=6 +BE11: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=6 +BE15: 1D F8 5C 80 MOV:G.W @H'F85C, R0 ; candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high; refs ram_F85C in on_chip_ram; cycles=6 +BE19: 1D F8 54 90 MOV:G.W R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=6 +BE1D: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE22: 1E FC 01 BSR loc_BA26 ; cycles=13 +BE25: 20 48 BRA loc_BE6F ; cycles=8 + +loc_BE27: +BE27: 20 46 BRA loc_BE6F ; cycles=8 + +loc_BE29: +BE29: 15 FA A4 D7 BCLR.B #7, @H'FAA4 ; refs ram_FAA4 in on_chip_ram; cycles=8 +BE2D: 15 FA A5 F7 BTST.B #7, @H'FAA5 ; refs ram_FAA5 in on_chip_ram; cycles=6 +BE31: 27 3A BEQ loc_BE6D ; cycles=3/8 nt/t +BE33: 15 FA A6 08 ADD:Q.B #1, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=8 +BE37: 15 FA A6 04 02 CMP:G.B #H'02, @H'FAA6 ; refs ram_FAA6 in on_chip_ram; cycles=6 +BE3C: 25 0F BCS loc_BE4D ; cycles=3/7 nt/t +BE3E: 15 F9 C0 06 1F MOV:G.B #H'1F, @H'F9C0 ; refs ram_F9C0 in on_chip_ram; cycles=9 +BE43: 15 FA A3 13 CLR.B @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=8 +BE47: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BE4B: 20 20 BRA loc_BE6D ; cycles=8 + +loc_BE4D: +BE4D: 15 F8 50 06 07 MOV:G.B #H'07, @H'F850 ; refs ram_F850 in on_chip_ram; cycles=9 +BE52: 15 F8 61 80 MOV:G.B @H'F861, R0 ; refs ram_F861 in on_chip_ram; cycles=7 +BE56: 15 F8 51 90 MOV:G.B R0, @H'F851 ; refs ram_F851 in on_chip_ram; cycles=7 +BE5A: 1D F8 62 80 MOV:G.W @H'F862, R0 ; refs ram_F862 in on_chip_ram; cycles=7 +BE5E: 1D F8 52 90 MOV:G.W R0, @H'F852 ; refs ram_F852 in on_chip_ram; cycles=7 +BE62: 15 F8 64 80 MOV:G.B @H'F864, R0 ; refs ram_F864 in on_chip_ram; cycles=7 +BE66: 15 F8 54 90 MOV:G.B R0, @H'F854 ; refs ram_F854 in on_chip_ram; cycles=7 +BE6A: 1E FB B9 BSR loc_BA26 ; cycles=13 + +loc_BE6D: +BE6D: 20 00 BRA loc_BE6F ; cycles=8 + +loc_BE6F: +BE6F: 19 RTS ; cycles=13 + +loc_BE70: +BE70: 15 F9 B9 83 MOV:G.B @H'F9B9, R3 ; refs ram_F9B9 in on_chip_ram; cycles=7 +BE74: A3 12 EXTU.B R3 ; cycles=3 +BE76: AB 1A SHLL.W R3 ; cycles=3 +BE78: 15 F9 B4 81 MOV:G.B @H'F9B4, R1 ; refs ram_F9B4 in on_chip_ram; cycles=7 +BE7C: A1 12 EXTU.B R1 ; cycles=3 +BE7E: A9 1A SHLL.W R1 ; cycles=3 + +loc_BE80: +BE80: A3 71 CMP:G.B R3, R1 ; cycles=2 +BE82: 27 0D BEQ loc_BE91 ; cycles=3/7 nt/t +BE84: FB F9 70 75 CMP:G.W @(-H'0690,R3), R5 ; cycles=7 +BE88: 27 13 BEQ loc_BE9D ; cycles=3/7 nt/t +BE8A: A3 09 ADD:Q.B #2, R3 ; cycles=4 +BE8C: 04 3F 53 AND.B #H'3F, R3 ; cycles=3 +BE8F: 20 EF BRA loc_BE80 ; cycles=8 + +loc_BE91: +BE91: F9 F9 70 95 MOV:G.W R5, @(-H'0690,R1) ; cycles=6 +BE95: 15 F9 B4 08 ADD:Q.B #1, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 +BE99: 15 F9 B4 D5 BCLR.B #5, @H'F9B4 ; refs ram_F9B4 in on_chip_ram; cycles=8 + +loc_BE9D: +BE9D: 19 RTS ; cycles=13 + +loc_BE9E: +BE9E: 15 FA A5 80 MOV:G.B @H'FAA5, R0 ; refs ram_FAA5 in on_chip_ram; cycles=7 +BEA2: 04 80 50 AND.B #H'80, R0 ; cycles=3 +BEA5: 15 FA A3 50 AND.B @H'FAA3, R0 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEA9: 15 FA A3 90 MOV:G.B R0, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BEAD: 26 06 BNE loc_BEB5 ; cycles=3/8 nt/t +BEAF: 15 FA A2 13 CLR.B @H'FAA2 ; refs ram_FAA2 in on_chip_ram; cycles=8 +BEB3: 20 33 BRA loc_BEE8 ; cycles=8 + +loc_BEB5: +BEB5: 1D F9 C6 16 TST.W @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=6 +BEB9: 26 2D BNE loc_BEE8 ; cycles=3/8 nt/t +BEBB: 15 F9 C8 16 TST.B @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=6 +BEBF: 27 23 BEQ loc_BEE4 ; cycles=3/8 nt/t +BEC1: 15 F9 C8 0C ADD:Q.B #-1, @H'F9C8 ; refs ram_F9C8 in on_chip_ram; cycles=8 +BEC5: 1D F9 C6 07 01 F4 MOV:G.W #H'01F4, @H'F9C6 ; refs ram_F9C6 in on_chip_ram; cycles=9 +BECB: 15 FA A3 F7 BTST.B #7, @H'FAA3 ; refs ram_FAA3 in on_chip_ram; cycles=6 +BECF: 27 17 BEQ loc_BEE8 ; cycles=3/8 nt/t +BED1: 15 F9 C3 13 CLR.B @H'F9C3 ; refs ram_F9C3 in on_chip_ram; cycles=8 +BED5: 1E FB 4E BSR loc_BA26 ; cycles=14 +BED8: 20 0E BRA loc_BEE8 ; cycles=7 + +loc_BEE4: +BEE4: 15 F9 C5 13 CLR.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=9 + +loc_BEE8: +BEE8: 19 RTS ; cycles=12 + +vec_frt1_ocia_BEEA: +BEEA: 15 FE 91 D5 BCLR.B #5, @FRT1_TCSR ; clear OCFA (bit 5) of FRT1_TCSR; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported; cycles=9 +BEEE: 15 F9 C0 16 TST.B @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=7 +BEF2: 27 04 BEQ loc_BEF8 ; cycles=3/7 nt/t +BEF4: 15 F9 C0 0C ADD:Q.B #-1, @H'F9C0 ; candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C0 in on_chip_ram; cycles=9 + +loc_BEF8: +BEF8: 15 F9 C1 16 TST.B @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=7 +BEFC: 27 04 BEQ loc_BF02 ; cycles=3/7 nt/t +BEFE: 15 F9 C1 0C ADD:Q.B #-1, @H'F9C1 ; candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C1 in on_chip_ram; cycles=9 + +loc_BF02: +BF02: 1D F9 C6 16 TST.W @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=7 +BF06: 27 04 BEQ loc_BF0C ; cycles=3/7 nt/t +BF08: 1D F9 C6 0C ADD:Q.W #-1, @H'F9C6 ; candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported; refs ram_F9C6 in on_chip_ram; cycles=9 + +loc_BF0C: +BF0C: 15 F6 F6 F7 BTST.B #7, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=7 +BF10: 27 10 BEQ loc_BF22 ; cycles=3/7 nt/t +BF12: 1D F6 F4 16 TST.W @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=7 +BF16: 26 06 BNE loc_BF1E ; cycles=3/7 nt/t +BF18: 15 F6 F6 C5 BSET.B #5, @H'F6F6 ; refs ram_F6F6 in on_chip_ram; cycles=9 +BF1C: 20 04 BRA loc_BF22 ; cycles=7 + +loc_BF1E: +BF1E: 1D F6 F4 0C ADD:Q.W #-1, @H'F6F4 ; refs ram_F6F4 in on_chip_ram; cycles=9 + +loc_BF22: +BF22: 0A RTE ; cycles=13 + +vec_frt2_ocia_BF23: +BF23: 15 FE A1 D5 BCLR.B #5, @FRT2_TCSR ; clear OCFA (bit 5) of FRT2_TCSR; cycles=8 +BF27: 15 F9 C4 16 TST.B @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=6 +BF2B: 27 04 BEQ loc_BF31 ; cycles=3/8 nt/t +BF2D: 15 F9 C4 0C ADD:Q.B #-1, @H'F9C4 ; refs ram_F9C4 in on_chip_ram; cycles=8 + +loc_BF31: +BF31: 15 F9 C5 16 TST.B @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=6 +BF35: 27 04 BEQ loc_BF3B ; cycles=3/8 nt/t +BF37: 15 F9 C5 0C ADD:Q.B #-1, @H'F9C5 ; refs ram_F9C5 in on_chip_ram; cycles=8 + +loc_BF3B: +BF3B: 15 F7 24 16 TST.B @H'F724 ; refs ram_F724 in on_chip_ram; cycles=6 +BF3F: 27 06 BEQ loc_BF47 ; cycles=3/8 nt/t +BF41: 15 F7 24 0C ADD:Q.B #-1, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=8 +BF45: 20 09 BRA loc_BF50 ; cycles=8 + +loc_BF47: +BF47: 15 F7 24 06 03 MOV:G.B #H'03, @H'F724 ; refs ram_F724 in on_chip_ram; cycles=9 +BF4C: 15 F7 23 15 NOT.B @H'F723 ; refs ram_F723 in on_chip_ram; cycles=9 + +loc_BF50: +BF50: 15 FB 03 F7 BTST.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=7 +BF54: 27 17 BEQ loc_BF6D ; cycles=3/7 nt/t +BF56: 15 FB 02 16 TST.B @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=7 +BF5A: 27 06 BEQ loc_BF62 ; cycles=3/7 nt/t +BF5C: 15 FB 02 0C ADD:Q.B #-1, @H'FB02 ; refs ram_FB02 in on_chip_ram; cycles=9 +BF60: 20 0B BRA loc_BF6D ; cycles=7 + +loc_BF62: +BF62: 15 FB 03 D7 BCLR.B #7, @H'FB03 ; refs ram_FB03 in on_chip_ram; cycles=9 +BF66: 12 3F STM.W {R0,R1,R2,R3,R4,R5}, @-SP ; cycles=24 +BF68: 1E 89 84 BSR loc_48EF ; cycles=13 +BF6B: 02 3F LDM.W @SP+, {R0,R1,R2,R3,R4,R5} ; cycles=30 + +loc_BF6D: +BF6D: 15 F7 6C 16 TST.B @H'F76C ; refs ram_F76C in on_chip_ram; cycles=6 +BF71: 27 04 BEQ loc_BF77 ; cycles=3/8 nt/t +BF73: 15 F7 6C 0C ADD:Q.B #-1, @H'F76C ; refs ram_F76C in on_chip_ram; cycles=8 + +loc_BF77: +BF77: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BF7B: 27 04 BEQ loc_BF81 ; cycles=3/8 nt/t +BF7D: 15 F8 40 0C ADD:Q.B #-1, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=8 + +loc_BF81: +BF81: 15 F7 26 16 TST.B @H'F726 ; refs ram_F726 in on_chip_ram; cycles=6 +BF85: 27 1C BEQ loc_BFA3 ; cycles=3/8 nt/t +BF87: 15 F7 26 0C ADD:Q.B #-1, @H'F726 ; refs ram_F726 in on_chip_ram; cycles=8 +BF8B: 26 16 BNE loc_BFA3 ; cycles=3/8 nt/t +BF8D: 15 F7 13 D6 BCLR.B #6, @H'F713 ; refs ram_F713 in on_chip_ram; cycles=8 +BF91: 26 10 BNE loc_BFA3 ; cycles=3/8 nt/t +BF93: 15 F7 11 D7 BCLR.B #7, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF97: 15 F7 11 D6 BCLR.B #6, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9B: 15 F7 11 D5 BCLR.B #5, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 +BF9F: 15 F7 11 D4 BCLR.B #4, @H'F711 ; refs ram_F711 in on_chip_ram; cycles=8 + +loc_BFA3: +BFA3: 15 F7 97 16 TST.B @H'F797 ; refs ram_F797 in on_chip_ram; cycles=6 +BFA7: 27 0A BEQ loc_BFB3 ; cycles=3/8 nt/t +BFA9: 15 F7 97 0C ADD:Q.B #-1, @H'F797 ; refs ram_F797 in on_chip_ram; cycles=8 +BFAD: 26 04 BNE loc_BFB3 ; cycles=3/8 nt/t +BFAF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFB3: +BFB3: 15 F7 98 16 TST.B @H'F798 ; refs ram_F798 in on_chip_ram; cycles=6 +BFB7: 27 0A BEQ loc_BFC3 ; cycles=3/8 nt/t +BFB9: 15 F7 98 0C ADD:Q.B #-1, @H'F798 ; refs ram_F798 in on_chip_ram; cycles=8 +BFBD: 26 04 BNE loc_BFC3 ; cycles=3/8 nt/t +BFBF: 15 F7 31 D7 BCLR.B #7, @H'F731 ; refs ram_F731 in on_chip_ram; cycles=8 + +loc_BFC3: +BFC3: 0A RTE ; cycles=14 + +vec_interval_timer_BFC4: +BFC4: 15 FE EC F7 BTST.B #7, @WDT_TCSR_R ; refs WDT_TCSR_R in register_field; cycles=7 +BFC8: 1D FE EC 07 A5 3F MOV:G.W #H'A53F, @WDT_TCSR_R ; WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096); cycles=11 +BFCE: 15 F7 94 08 ADD:Q.B #1, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=9 +BFD2: 15 F7 94 04 0A CMP:G.B #H'0A, @H'F794 ; refs ram_F794 in on_chip_ram; cycles=7 +BFD7: 26 06 BNE loc_BFDF ; cycles=3/8 nt/t +BFD9: 1D FE EC 07 A5 7F MOV:G.W #H'A57F, @WDT_TCSR_R ; WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096); cycles=9 + +loc_BFDF: +BFDF: 0A RTE ; cycles=14 + +loc_BFE0: +BFE0: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 + +loc_BFE5: +BFE5: AD 82 MOV:G.W R5, R2 ; cycles=3 +BFE7: 0E 27 BSR loc_C010 ; cycles=14 +BFE9: 0E 4E BSR loc_C039 ; cycles=14 +BFEB: AA 75 CMP:G.W R2, R5 ; cycles=3 +BFED: 27 0E BEQ loc_BFFD ; cycles=3/8 nt/t +BFEF: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +BFF3: 27 04 BEQ loc_BFF9 ; cycles=3/8 nt/t +BFF5: AA 85 MOV:G.W R2, R5 ; cycles=3 +BFF7: 20 EC BRA loc_BFE5 ; cycles=8 + +loc_BFF9: +BFF9: 15 F8 41 C7 BSET.B #7, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_BFFD: +BFFD: 19 RTS ; cycles=13 + +loc_BFFE: +BFFE: 15 F8 40 06 0A MOV:G.B #H'0A, @H'F840 ; refs ram_F840 in on_chip_ram; cycles=9 +C003: 0E 34 BSR loc_C039 ; cycles=14 +C005: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C009: 26 04 BNE loc_C00F ; cycles=3/8 nt/t +C00B: 15 F8 41 C6 BSET.B #6, @H'F841 ; refs ram_F841 in on_chip_ram; cycles=8 + +loc_C00F: +C00F: 19 RTS ; cycles=13 + +loc_C010: +C010: 0E 58 BSR loc_C06A ; cycles=13 + +loc_C012: +C012: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=7 +C016: 27 20 BEQ loc_C038 ; cycles=3/7 nt/t +C018: 1E 01 06 BSR loc_C121 ; cycles=13 +C01B: A3 80 MOV:G.B R3, R0 ; cycles=2 +C01D: 0E 6C BSR loc_C08B ; cycles=14 +C01F: 27 F1 BEQ loc_C012 ; cycles=3/8 nt/t +C021: A4 80 MOV:G.B R4, R0 ; cycles=2 +C023: 0E 66 BSR loc_C08B ; cycles=14 +C025: 27 EB BEQ loc_C012 ; cycles=3/8 nt/t +C027: AD 80 MOV:G.W R5, R0 ; cycles=3 +C029: A0 10 SWAP.B R0 ; cycles=3 +C02B: 0E 5E BSR loc_C08B ; cycles=14 +C02D: 27 E3 BEQ loc_C012 ; cycles=3/8 nt/t +C02F: A5 80 MOV:G.B R5, R0 ; cycles=2 +C031: 0E 58 BSR loc_C08B ; cycles=14 +C033: 27 DD BEQ loc_C012 ; cycles=3/8 nt/t +C035: 1E 01 0A BSR loc_C142 ; cycles=14 + +loc_C038: +C038: 19 RTS ; cycles=12 + +loc_C039: +C039: 0E 2F BSR loc_C06A ; cycles=14 + +loc_C03B: +C03B: 15 F8 40 16 TST.B @H'F840 ; refs ram_F840 in on_chip_ram; cycles=6 +C03F: 27 28 BEQ loc_C069 ; cycles=3/8 nt/t +C041: 1E 00 DD BSR loc_C121 ; cycles=14 +C044: A3 80 MOV:G.B R3, R0 ; cycles=2 +C046: 0E 43 BSR loc_C08B ; cycles=13 +C048: 27 F1 BEQ loc_C03B ; cycles=3/7 nt/t +C04A: A4 80 MOV:G.B R4, R0 ; cycles=2 +C04C: 0E 3D BSR loc_C08B ; cycles=13 +C04E: 27 EB BEQ loc_C03B ; cycles=3/7 nt/t +C050: 1E 00 CE BSR loc_C121 ; cycles=13 +C053: A3 80 MOV:G.B R3, R0 ; cycles=2 +C055: A0 C0 BSET.B #0, R0 ; cycles=2 +C057: 0E 32 BSR loc_C08B ; cycles=14 +C059: 27 E0 BEQ loc_C03B ; cycles=3/8 nt/t +C05B: 1E 00 7D BSR loc_C0DB ; cycles=14 +C05E: A5 10 SWAP.B R5 ; cycles=3 +C060: 1E 00 A9 BSR loc_C10C ; cycles=13 +C063: 1E 00 75 BSR loc_C0DB ; cycles=14 +C066: 1E 00 D9 BSR loc_C142 ; cycles=13 + +loc_C069: +C069: 19 RTS ; cycles=13 + +loc_C06A: +C06A: 0C 0F FF 54 AND.W #H'0FFF, R4 ; cycles=4 +C06E: 4C 08 00 CMP:I #H'0800, R4 ; cycles=3 +C071: 24 0B BCC loc_C07E ; cycles=3/8 nt/t +C073: AC 83 MOV:G.W R4, R3 ; cycles=3 +C075: A3 10 SWAP.B R3 ; cycles=3 +C077: A3 1A SHLL.B R3 ; cycles=2 +C079: 04 A0 43 OR.B #H'A0, R3 ; cycles=3 +C07C: 20 0C BRA loc_C08A ; cycles=7 + +loc_C07E: +C07E: AC 83 MOV:G.W R4, R3 ; cycles=3 +C080: A3 10 SWAP.B R3 ; cycles=3 +C082: A3 1A SHLL.B R3 ; cycles=2 +C084: 04 0E 53 AND.B #H'0E, R3 ; cycles=3 +C087: 04 E0 43 OR.B #H'E0, R3 ; cycles=3 + +loc_C08A: +C08A: 19 RTS ; cycles=12 + +loc_C08B: +C08B: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C08E: +C08E: A0 1A SHLL.B R0 ; cycles=2 +C090: 24 06 BCC loc_C098 ; cycles=3/7 nt/t +C092: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C096: 20 04 BRA loc_C09C ; cycles=7 + +loc_C098: +C098: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 + +loc_C09C: +C09C: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A0: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0A8: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0AC: 01 B9 DF SCB/F R1, loc_C08E ; cycles=3/4/8 false/-1/t +C0AF: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0B4: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0B8: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C0BC: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=7 +C0C0: 27 0D BEQ loc_C0CF ; cycles=3/7 nt/t +C0C2: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C0C6: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0CB: 50 00 MOV:E.B #H'00, R0 ; dataflow R0=H'00; cycles=2 +C0CD: 20 0B BRA loc_C0DA ; cycles=8 + +loc_C0CF: +C0CF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0D3: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C0D8: 50 01 MOV:E.B #H'01, R0 ; dataflow R0=H'01; cycles=2 + +loc_C0DA: +C0DA: 19 RTS ; cycles=12 + +loc_C0DB: +C0DB: 15 FE FE 06 13 MOV:G.B #H'13, @P9DDR ; P9DDR = H'13; cycles=9 +C0E0: 59 00 07 MOV:I.W #H'0007, R1 ; dataflow R1=H'0007; cycles=3 + +loc_C0E3: +C0E3: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0E7: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C0EB: 15 FE FF F7 BTST.B #7, @P9DR ; refs P9DR in register_field; cycles=6 +C0EF: 27 04 BEQ loc_C0F5 ; cycles=3/8 nt/t +C0F1: A5 49 BSET.B R1, R5 ; cycles=2 +C0F3: 20 02 BRA loc_C0F7 ; cycles=8 + +loc_C0F5: +C0F5: A5 59 BCLR.B R1, R5 ; cycles=2 + +loc_C0F7: +C0F7: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FB: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C0FF: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C103: 01 B9 DD SCB/F R1, loc_C0E3 ; cycles=3/4/9 false/-1/t +C106: 15 FE FE 06 93 MOV:G.B #H'93, @P9DDR ; P9DDR = H'93; cycles=9 +C10B: 19 RTS ; cycles=13 + +loc_C10C: +C10C: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C110: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C114: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C118: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C11C: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C120: 19 RTS ; cycles=12 + +loc_C121: +C121: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=8 +C125: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C129: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C12D: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C131: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=8 +C135: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C139: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=8 +C13D: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=8 +C141: 19 RTS ; cycles=13 + +loc_C142: +C142: 15 FE FF D7 BCLR.B #7, @P9DR ; clear bit 7 of P9DR; cycles=9 +C146: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C14E: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C152: 15 FE FF C7 BSET.B #7, @P9DR ; set bit 7 of P9DR; cycles=9 +C156: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15A: 15 FE FF C1 BSET.B #1, @P9DR ; set bit 1 of P9DR; cycles=9 +C15E: 15 FE FF D1 BCLR.B #1, @P9DR ; clear bit 1 of P9DR; cycles=9 +C162: 19 RTS ; cycles=12 diff --git a/build/rom_others_page1.json b/build/rom_others_page1.json new file mode 100644 index 0000000..553b91c --- /dev/null +++ b/build/rom_others_page1.json @@ -0,0 +1,239015 @@ +{ + "vectors": [ + { + "address": 0, + "name": "reset", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 4, + "name": "invalid_instruction", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 6, + "name": "zero_divide", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 8, + "name": "trap_vs", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 16, + "name": "address_error", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 18, + "name": "trace", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 22, + "name": "nmi", + "target": 17299, + "target_label": "vec_nmi_4393" + }, + { + "address": 32, + "name": "trapa_0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 34, + "name": "trapa_1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 36, + "name": "trapa_2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 38, + "name": "trapa_3", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 40, + "name": "trapa_4", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 42, + "name": "trapa_5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 44, + "name": "trapa_6", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 46, + "name": "trapa_7", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 48, + "name": "trapa_8", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 50, + "name": "trapa_9", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 52, + "name": "trapa_a", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 54, + "name": "trapa_b", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 56, + "name": "trapa_c", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 58, + "name": "trapa_d", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 60, + "name": "trapa_e", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 62, + "name": "trapa_f", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 64, + "name": "irq0", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 66, + "name": "interval_timer", + "target": 49092, + "target_label": "vec_interval_timer_BFC4" + }, + { + "address": 72, + "name": "irq1", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 80, + "name": "irq2", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 82, + "name": "irq3", + "target": 15408, + "target_label": "vec_irq3_3C30" + }, + { + "address": 88, + "name": "irq4", + "target": 15047, + "target_label": "vec_irq4_3AC7" + }, + { + "address": 90, + "name": "irq5", + "target": 4096, + "target_label": "vec_reset_1000" + }, + { + "address": 98, + "name": "frt1_ocia", + "target": 48874, + "target_label": "vec_frt1_ocia_BEEA" + }, + { + "address": 106, + "name": "frt2_ocia", + "target": 48931, + "target_label": "vec_frt2_ocia_BF23" + }, + { + "address": 128, + "name": "sci1_eri", + "target": 47959, + "target_label": "vec_sci1_eri_BB57" + }, + { + "address": 130, + "name": "sci1_rxi", + "target": 47975, + "target_label": "vec_sci1_rxi_BB67" + }, + { + "address": 132, + "name": "sci1_txi", + "target": 47748, + "target_label": "vec_sci1_txi_BA84" + }, + { + "address": 144, + "name": "ad_adi", + "target": 15769, + "target_label": "vec_ad_adi_3D99" + } + ], + "dtc_vectors": [], + "memory_regions": [ + { + "name": "exception_vectors", + "start": 0, + "end": 159, + "kind": "vectors", + "manual": "section 2 address space" + }, + { + "name": "dtc_vectors", + "start": 160, + "end": 255, + "kind": "dtc_vectors", + "manual": "section 2 address space" + }, + { + "name": "program_or_external", + "start": 256, + "end": 63103, + "kind": "program", + "manual": "section 2/17 mode-dependent ROM or external space" + }, + { + "name": "on_chip_ram", + "start": 63104, + "end": 65151, + "kind": "ram", + "manual": "section 16 RAM" + }, + { + "name": "register_field", + "start": 65152, + "end": 65535, + "kind": "registers", + "manual": "appendix B register map" + } + ], + "data_candidates": { + "strings": [ + { + "address": 10834, + "length": 11, + "text": "78785=5=5=,", + "terminated": false + }, + { + "address": 11194, + "length": 7, + "text": "8*8B8Z8", + "terminated": false + }, + { + "address": 16818, + "length": 32, + "text": "01020304050607080910111213141516", + "terminated": false + }, + { + "address": 22436, + "length": 7, + "text": "Z [ ", + "terminated": false + }, + { + "address": 22570, + "length": 6, + "text": "Z [ ", + "terminated": false + }, + { + "address": 23381, + "length": 10, + "text": "0123456789", + "terminated": true + }, + { + "address": 23392, + "length": 40, + "text": " 0 1 2 3 4 5 6 7 8 910111213141516171819", + "terminated": false + }, + { + "address": 24822, + "length": 16, + "text": "0123456789ABCDEF", + "terminated": false + }, + { + "address": 25356, + "length": 9, + "text": "m*mDm^mxm", + "terminated": false + }, + { + "address": 25406, + "length": 6, + "text": "vpwhx6", + "terminated": true + }, + { + "address": 25559, + "length": 10, + "text": "OPERATION ", + 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"from_label": "loc_451A", + "to": 6923, + "to_label": "loc_1B0B", + "call_site": 17792 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 17845, + "to_label": "loc_45B5", + "call_site": 17749 + }, + { + "from": 17690, + "from_label": "loc_451A", + "to": 18682, + "to_label": "loc_48FA", + "call_site": 17806 + }, + { + "from": 18671, + "from_label": "loc_48EF", + "to": 18682, + "to_label": "loc_48FA", + "call_site": 18679 + }, + { + "from": 18682, + "from_label": "loc_48FA", + "to": 15956, + "to_label": "loc_3E54", + "call_site": 18726 + }, + { + "from": 21760, + "from_label": "loc_5500", + "to": 15956, + "to_label": "loc_3E54", + "call_site": 21965 + }, + { + "from": 21760, + "from_label": "loc_5500", + "to": 49120, + "to_label": "loc_BFE0", + "call_site": 21813 + }, + { + "from": 22890, + "from_label": "loc_596A", + "to": 16076, + "to_label": "loc_3ECC", + "call_site": 22929 + }, + { + "from": 24838, + "from_label": "loc_6106", + "to": 16076, + "to_label": "loc_3ECC", + "call_site": 24888 + }, + { + "from": 24892, + "from_label": "loc_613C", + "to": 16076, + "to_label": "loc_3ECC", + "call_site": 24943 + }, + { + "from": 47858, + "from_label": "loc_BAF2", + "to": 25094, + "to_label": "loc_6206", + "call_site": 47886 + }, + { + "from": 47858, + "from_label": "loc_BAF2", + "to": 47654, + "to_label": "loc_BA26", + "call_site": 47939 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 25131, + "to_label": "loc_622B", + "call_site": 48129 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 47654, + "to_label": "loc_BA26", + "call_site": 48378 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 48752, + "to_label": "loc_BE70", + "call_site": 48262 + }, + { + "from": 48043, + "from_label": "loc_BBAB", + "to": 49120, + "to_label": "loc_BFE0", + "call_site": 48479 + }, + { + "from": 48798, + "from_label": "loc_BE9E", + "to": 47654, + "to_label": "loc_BA26", + "call_site": 48853 + }, + { + "from": 48931, + "from_label": "vec_frt2_ocia_BF23", + "to": 18671, + "to_label": "loc_48EF", + "call_site": 49000 + }, + { + "from": 49120, + "from_label": "loc_BFE0", + "to": 49168, + "to_label": "loc_C010", + "call_site": 49127 + }, + { + "from": 49120, + "from_label": "loc_BFE0", + "to": 49209, + "to_label": "loc_C039", + "call_site": 49129 + }, + { + "from": 49150, + "from_label": "loc_BFFE", + "to": 49209, + "to_label": "loc_C039", + "call_site": 49155 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49258, + "to_label": "loc_C06A", + "call_site": 49168 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49291, + "to_label": "loc_C08B", + "call_site": 49181 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49441, + "to_label": "loc_C121", + "call_site": 49176 + }, + { + "from": 49168, + "from_label": "loc_C010", + "to": 49474, + "to_label": "loc_C142", + "call_site": 49205 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49258, + "to_label": "loc_C06A", + "call_site": 49209 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49291, + "to_label": "loc_C08B", + "call_site": 49222 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49371, + "to_label": "loc_C0DB", + "call_site": 49243 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49420, + "to_label": "loc_C10C", + "call_site": 49248 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49441, + "to_label": "loc_C121", + "call_site": 49217 + }, + { + "from": 49209, + "from_label": "loc_C039", + "to": 49474, + "to_label": "loc_C142", + "call_site": 49254 + } + ] + }, + "timing_summary": { + "blocks": [], + "loops": [] + }, + "sci": { + "clock_hz": null, + "formulas": { + "async": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))" + }, + "manual_references": [ + "Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source", + "Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source", + "Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator", + "Manual/0900766b802125d0.md:16303 asynchronous BRR formula", + "Manual/0900766b802125d0.md:16379 synchronous BRR formula", + "Manual/0900766b802125d0.md:16410 SCI clock source selection tables" + ], + "channels": { + "SCI1": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ], + "configurations": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "SCI2": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "configurations": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + } + } + }, + "sci_protocol": { + "manual_references": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "channels": { + "SCI1": { + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "SCI2": { + "events": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ] + } + }, + "events": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + }, + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ] + }, + "serial_reconstruction": { + "kind": "serial_reconstruction", + "candidates": [ + { + "id": "sci1_tx_frame_f858_len6_candidate", + "kind": "candidate_sci1_tx_frame", + "channel": "SCI1", + "frame_length": 6, + "buffer_start": 63576, + "buffer_start_hex": "H'F858", + "buffer_end": 63581, + "buffer_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "tx_index_address": 63938, + "tx_index_address_hex": "H'F9C2", + "tdr_address": 65243, + "tdr_address_hex": "H'FEDB", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "roles": [ + { + "name": "tx_frame", + "address": 63576, + "address_hex": "H'F858", + "end_address": 63581, + "end_address_hex": "H'F85D", + "summary": "evidence-supported candidate SCI1 TX frame buffer" + }, + { + "name": "tx_checksum", + "address": 63581, + "address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "summary": "evidence-supported candidate SCI1 TX XOR checksum byte" + }, + { + "name": "tx_index", + "address": 63938, + "address_hex": "H'F9C2", + "summary": "evidence-supported candidate SCI1 TX frame index" + } + ], + "tx_path": { + "kind": "interrupt_driven_txi", + "initial_tdr_write_address": 47730, + "initial_tdr_write_address_hex": "H'BA72", + "txi_indexed_tdr_write_address": 47797, + "txi_indexed_tdr_write_address_hex": "H'BAB5", + "summary": "initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted", + "tdre_caveat": "TDRE reassertion is hardware/emulator timing context; static evidence is the indexed TXI send path." + }, + "confidence": "high", + "confidence_score": 0.95, + "confidence_reason": "all required independent evidence groups were observed", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "missing_evidence": [], + "evidence_addresses": { + "tx_buffer_region": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "tx_checksum_seed": [ + 47694 + ], + "checksum_byte": [ + 47716 + ], + "xor_checksum_chain": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "initial_send_from_buffer_start": [ + 47726, + 47730 + ], + "tx_index_initialized_to_one": [ + 47734 + ], + "tx_isr_indexed_send": [ + 47787, + 47793, + 47797 + ], + "tx_index_increment": [ + 47807 + ], + "tx_index_compare_frame_length": [ + 47811 + ] + }, + "evidence_addresses_hex": { + "tx_buffer_region": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "tx_checksum_seed": [ + "H'BA4E" + ], + "checksum_byte": [ + "H'BA64" + ], + "xor_checksum_chain": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "initial_send_from_buffer_start": [ + "H'BA6E", + "H'BA72" + ], + "tx_index_initialized_to_one": [ + "H'BA76" + ], + "tx_isr_indexed_send": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "tx_index_increment": [ + "H'BABF" + ], + "tx_index_compare_frame_length": [ + "H'BAC3" + ] + }, + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + } + ], + "short_comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis using buffer H'F858-H'F85D with checksum byte H'F85D seeded by H'005A" + }, + { + "id": "sci1_rx_frame_f868_len6_candidate", + "kind": "candidate_sci1_rx_frame", + "channel": "SCI1", + "frame_length": 6, + "capture_buffer_start": 63592, + "capture_buffer_start_hex": "H'F868", + "capture_buffer_end": 63597, + "capture_buffer_end_hex": "H'F86D", + "validation_buffer_start": 63584, + "validation_buffer_start_hex": "H'F860", + "validation_buffer_end": 63589, + "validation_buffer_end_hex": "H'F865", + "checksum_address": 63589, + "checksum_address_hex": "H'F865", + "rx_index_address": 63939, + "rx_index_address_hex": "H'F9C3", + "rdr_address": 65245, + "rdr_address_hex": "H'FEDD", + "interbyte_timeout_address": 63937, + "interbyte_timeout_address_hex": "H'F9C1", + "complete_timer_address": 63941, + "complete_timer_address_hex": "H'F9C5", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "confidence": "high", + "confidence_score": 0.9, + "confidence_reason": "RX count, copy, and checksum-validation evidence were observed; no explicit header/sync byte was identified", + "caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet", + "required_evidence_count": 9, + "observed_evidence_count": 9, + "optional_evidence_count": 2, + "missing_evidence": [], + "evidence_addresses": { + "rx_rdr_read": [ + 47981 + ], + "rx_indexed_store": [ + 48016 + ], + "rx_index_increment_store": [ + 48020, + 48022 + ], + "rx_isr_compare_frame_length": [ + 48026 + ], + "rx_complete_timer": [ + 48030 + ], + "rx_processor_requires_six_bytes": [ + 48043 + ], + "rx_copy_capture_to_frame_buffer": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "rx_checksum_seed": [ + 48086 + ], + "rx_xor_checksum_validation": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "rx_rdrf_clear_before_rdr_read": [ + 47977, + 47981 + ], + "rx_eri_falls_through_to_rxi": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ] + }, + "evidence_addresses_hex": { + "rx_rdr_read": [ + "H'BB6D" + ], + "rx_indexed_store": [ + "H'BB90" + ], + "rx_index_increment_store": [ + "H'BB94", + "H'BB96" + ], + "rx_isr_compare_frame_length": [ + "H'BB9A" + ], + "rx_complete_timer": [ + "H'BB9E" + ], + "rx_processor_requires_six_bytes": [ + "H'BBAB" + ], + "rx_copy_capture_to_frame_buffer": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "rx_checksum_seed": [ + "H'BBD6" + ], + "rx_xor_checksum_validation": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "rx_rdrf_clear_before_rdr_read": [ + "H'BB69", + "H'BB6D" + ], + "rx_eri_falls_through_to_rxi": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ] + }, + "evidence": [ + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + } + ], + "rx_error_handling": { + "kind": "sci1_rx_error_handling_candidate", + "error_latch_address": 64164, + "error_latch_address_hex": "H'FAA4", + "error_latch_bit": 7, + "fallthrough_to_rx_byte_path": true, + "rdrf_clear_before_rdr_read": true, + "summary": "SCI1 ERI appears to mark a physical receive error and continue into the RXI byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order.", + "manual_caveat": "Manual text distinguishes ORER from FER/PER data transfer into RDR and describes the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order.", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "candidate-medium" + }, + "short_comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A", + "comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A" + } + ], + "ram_roles": [ + { + "kind": "candidate_ram_role", + "name": "post_tx_report_delay", + "address": 63936, + "address_hex": "H'F9C0", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "post_tx_report_delay_tick_decrement": [ + 48878, + 48884 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "post_tx_report_delay_tick_decrement": [ + "H'BEEE", + "H'BEF4" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "secondary_tx_report_delay", + "address": 63937, + "address_hex": "H'F9C1", + "width_bits": 8, + "confidence": "candidate/evidence-supported", + "summary": "secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "secondary_tx_report_delay_tick_decrement": [ + 48888, + 48894 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "secondary_tx_report_delay_tick_decrement": [ + "H'BEF8", + "H'BEFE" + ] + } + }, + { + "kind": "candidate_ram_role", + "name": "periodic_report_countdown", + "address": 63942, + "address_hex": "H'F9C6", + "width_bits": 16, + "confidence": "candidate/evidence-supported", + "summary": "periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it", + "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol", + "evidence": [ + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "evidence_addresses": { + "frt1_ocia_periodic_tick_isr": [ + 48874 + ], + "periodic_report_countdown_tick_decrement": [ + 48898, + 48904 + ] + }, + "evidence_addresses_hex": { + "frt1_ocia_periodic_tick_isr": [ + "H'BEEA" + ], + "periodic_report_countdown_tick_decrement": [ + "H'BF02", + "H'BF08" + ] + } + } + ], + "evidence": [ + { + "kind": "tx_buffer_region", + "summary": "TX buffer-region references cluster around H'F858-H'F85D", + "addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "instructions": [ + "MOV:G.W R0, @H'F858", + "MOV:G.W R0, @H'F85A", + "MOV:G.B R0, @H'F85C", + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D", + "MOV:G.B @H'F858, R0", + "MOV:G.W @H'F858, R0", + "MOV:G.W @H'F85A, R0", + "MOV:G.W @H'F85C, R0" + ], + "distinct_buffer_addresses": [ + 63576, + 63577, + 63578, + 63579, + 63580, + 63581 + ], + "distinct_buffer_addresses_hex": [ + "H'F858", + "H'F859", + "H'F85A", + "H'F85B", + "H'F85C", + "H'F85D" + ] + }, + { + "kind": "tx_checksum_seed", + "summary": "candidate TX checksum starts from seed H'005A", + "addresses": [ + 47694 + ], + "addresses_hex": [ + "H'BA4E" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "checksum_byte", + "summary": "candidate checksum byte write targets H'F85D", + "addresses": [ + 47716 + ], + "addresses_hex": [ + "H'BA64" + ], + "instructions": [ + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "xor_checksum_chain", + "summary": "XOR chain appears to feed the H'F85D checksum byte", + "addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "instructions": [ + "XOR.B @H'F858, R0", + "XOR.B @H'F859, R0", + "XOR.B @H'F85A, R0", + "XOR.B @H'F85B, R0", + "XOR.B @H'F85C, R0", + "MOV:G.B R0, @H'F85D" + ] + }, + { + "kind": "initial_send_from_buffer_start", + "summary": "initial SCI1 TDR send is supported by a read from H'F858", + "addresses": [ + 47726, + 47730 + ], + "addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "instructions": [ + "MOV:G.B @H'F858, R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_initialized_to_one", + "summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "addresses": [ + 47734 + ], + "addresses_hex": [ + "H'BA76" + ], + "instructions": [ + "MOV:G.B #H'01, @H'F9C2" + ] + }, + { + "kind": "tx_isr_indexed_send", + "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "addresses": [ + 47787, + 47793, + 47797 + ], + "addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "instructions": [ + "MOV:G.B @H'F9C2, R0", + "MOV:G.B @(-H'07A8,R0), R0", + "MOV:G.B R0, @SCI1_TDR" + ] + }, + { + "kind": "tx_index_increment", + "summary": "candidate TX ISR increments TX index H'F9C2", + "addresses": [ + 47807 + ], + "addresses_hex": [ + "H'BABF" + ], + "instructions": [ + "ADD:Q.B #1, @H'F9C2" + ] + }, + { + "kind": "tx_index_compare_frame_length", + "summary": "candidate TX ISR compares TX index to frame length 6", + "addresses": [ + 47811 + ], + "addresses_hex": [ + "H'BAC3" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C2" + ] + }, + { + "kind": "rx_rdr_read", + "summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "addresses": [ + 47981 + ], + "addresses_hex": [ + "H'BB6D" + ], + "instructions": [ + "MOV:G.B @SCI1_RDR, R0" + ] + }, + { + "kind": "rx_rdrf_clear_before_rdr_read", + "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "addresses": [ + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF", + "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence" + ] + }, + { + "kind": "rx_eri_falls_through_to_rxi", + "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "instructions": [ + "BSET.B #7, @H'FAA4", + "BCLR.B #5, @SCI1_SSR", + "BCLR.B #4, @SCI1_SSR", + "BCLR.B #3, @SCI1_SSR", + "BCLR.B #6, @SCI1_SSR", + "MOV:G.B @SCI1_RDR, R0" + ], + "manual_references": [ + "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not", + "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER" + ] + }, + { + "kind": "rx_indexed_store", + "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "addresses": [ + 48016 + ], + "addresses_hex": [ + "H'BB90" + ], + "instructions": [ + "MOV:G.B R0, @(-H'0798,R1)" + ] + }, + { + "kind": "rx_index_increment_store", + "summary": "RX byte count/index is incremented and stored at H'F9C3", + "addresses": [ + 48020, + 48022 + ], + "addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "instructions": [ + "ADD:Q.B #1, R1", + "MOV:G.B R1, @H'F9C3" + ] + }, + { + "kind": "rx_isr_compare_frame_length", + "summary": "RX ISR compares incremented count to candidate frame length 6", + "addresses": [ + 48026 + ], + "addresses_hex": [ + "H'BB9A" + ], + "instructions": [ + "CMP:E #H'06, R1" + ] + }, + { + "kind": "rx_complete_timer", + "summary": "RX ISR sets H'F9C5 after count reaches 6", + "addresses": [ + 48030 + ], + "addresses_hex": [ + "H'BB9E" + ], + "instructions": [ + "MOV:G.B #H'14, @H'F9C5" + ] + }, + { + "kind": "rx_processor_requires_six_bytes", + "summary": "RX processing path requires H'F9C3 to equal 6", + "addresses": [ + 48043 + ], + "addresses_hex": [ + "H'BBAB" + ], + "instructions": [ + "CMP:G.B #H'06, @H'F9C3" + ] + }, + { + "kind": "rx_copy_capture_to_frame_buffer", + "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "instructions": [ + "MOV:G.W @H'F868, R0", + "MOV:G.W @H'F86A, R0", + "MOV:G.W @H'F86C, R0", + "MOV:G.W R0, @H'F860", + "MOV:G.W R0, @H'F862", + "MOV:G.W R0, @H'F864" + ] + }, + { + "kind": "rx_checksum_seed", + "summary": "candidate RX checksum validation starts from seed H'005A", + "addresses": [ + 48086 + ], + "addresses_hex": [ + "H'BBD6" + ], + "instructions": [ + "MOV:E.B #H'5A, R0" + ] + }, + { + "kind": "rx_xor_checksum_validation", + "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "instructions": [ + "MOV:E.B #H'5A, R0", + "XOR.B @H'F860, R0", + "XOR.B @H'F861, R0", + "XOR.B @H'F862, R0", + "XOR.B @H'F863, R0", + "XOR.B @H'F864, R0", + "CMP:G.B @H'F865, R0" + ] + }, + { + "kind": "frt1_ocia_periodic_tick_isr", + "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "addresses": [ + 48874 + ], + "addresses_hex": [ + "H'BEEA" + ], + "instructions": [ + "BCLR.B #5, @FRT1_TCSR" + ], + "vector_address": 98, + "vector_address_hex": "H'0062", + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "post_tx_report_delay_tick_decrement", + "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48878, + 48884 + ], + "addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "instructions": [ + "TST.B @H'F9C0", + "ADD:Q.B #-1, @H'F9C0" + ], + "role_name": "post_tx_report_delay", + "ram_address": 63936, + "ram_address_hex": "H'F9C0", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "secondary_tx_report_delay_tick_decrement", + "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48888, + 48894 + ], + "addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "instructions": [ + "TST.B @H'F9C1", + "ADD:Q.B #-1, @H'F9C1" + ], + "role_name": "secondary_tx_report_delay", + "ram_address": 63937, + "ram_address_hex": "H'F9C1", + "width_bits": 8, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + }, + { + "kind": "periodic_report_countdown_tick_decrement", + "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "addresses": [ + 48898, + 48904 + ], + "addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "instructions": [ + "TST.W @H'F9C6", + "ADD:Q.W #-1, @H'F9C6" + ], + "role_name": "periodic_report_countdown", + "ram_address": 63942, + "ram_address_hex": "H'F9C6", + "width_bits": 16, + "isr_address": 48874, + "isr_address_hex": "H'BEEA" + } + ], + "required_evidence": { + "tx": [ + "tx_buffer_region", + "tx_checksum_seed", + "checksum_byte", + "xor_checksum_chain", + "initial_send_from_buffer_start", + "tx_index_initialized_to_one", + "tx_isr_indexed_send", + "tx_index_increment", + "tx_index_compare_frame_length" + ], + "rx": [ + "rx_rdr_read", + "rx_indexed_store", + "rx_index_increment_store", + "rx_isr_compare_frame_length", + "rx_complete_timer", + "rx_processor_requires_six_bytes", + "rx_copy_capture_to_frame_buffer", + "rx_checksum_seed", + "rx_xor_checksum_validation" + ] + } + }, + "board_profile": { + "board": "sony_rcp_tx7", + "name": "Sony RCP-TX7", + "summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.", + "manual_references": [ + "Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD", + "Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD", + "Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals", + "Manual/0900766b802125d0.md:11201 P96 is RXD1 input", + "Manual/0900766b802125d0.md:11202 P95 is TXD1 output", + "Manual/0900766b802125d0.md:15725 SCI1 RXD input pin", + "Manual/0900766b802125d0.md:15726 SCI1 TXD output pin", + "Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR", + "Manual/0900766b802125d0.md:15794 RDR receive data register", + "Manual/0900766b802125d0.md:15823 TDR transmit data register", + "Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions", + "Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output", + "Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input", + "Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags", + "Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions", + "Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94" + ], + "traces": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "channels": { + "SCI1": { + "traced_to_max202": true, + "path": "RS232/MAX202", + "pins": [ + { + "channel": "SCI1", + "signal": "TXD", + "h8_pin": 66, + "h8_pin_name": "P95/TXD", + "h8_function": "TXD1", + "max202_pin": 11, + "evidence": "MAX202 pin 11 traces to H8 pin 66" + }, + { + "channel": "SCI1", + "signal": "RXD", + "h8_pin": 67, + "h8_pin_name": "P96/RXD", + "h8_function": "RXD1", + "max202_pin": 12, + "evidence": "MAX202 pin 12 traces to H8 pin 67" + } + ], + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + }, + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + }, + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + }, + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ] + }, + "SCI2": { + "traced_to_max202": false, + "path": null, + "note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.", + "p9sci2e": false, + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + }, + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ] + } + }, + "instructions": { + "4148": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "4245": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4250": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "4255": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "4260": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4265": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "4270": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "17258": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "17274": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "17278": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "47720": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47730": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47739": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47743": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47774": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47797": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "47803": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47818": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "47963": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47967": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47971": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47977": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "47981": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + }, + "state": { + "SYSCR2": { + "value": 180, + "value_hex": "H'B4" + }, + "P9SCI2E": false + } + }, + "peripheral_access": { + "manual_references": [ + "Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access", + "Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte", + "Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP", + "Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP", + "Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte" + ], + "warnings": [] + }, + "indirect_flow": { + "sites": [ + { + "address": 7192, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "unknown", + "summary": "JSR @R0 uses R0; target not resolved" + }, + { + "address": 10403, + "instruction": "JMP @R1", + "kind": "jump", + "target_register": "R1", + "confidence": "table_load", + "table": { + "base": 10406, + "index_register": "R4", + "target_register": "R1", + "load_address": 10399, + "load_instruction": "MOV:G.W @(H'28A6,R4), R1", + "entry_size": 2, + "entry_count": 128, + "decoded_target_count": 103, + "entries": [ + { + "index": 0, + "entry_address": 10406, + "target": 11449, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 10408, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 2, + "entry_address": 10410, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 3, + "entry_address": 10412, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 4, + "entry_address": 10414, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 5, + "entry_address": 10416, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 6, + "entry_address": 10418, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 7, + "entry_address": 10420, + "target": 11715, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 10422, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 9, + "entry_address": 10424, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 10, + "entry_address": 10426, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 11, + "entry_address": 10428, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 12, + "entry_address": 10430, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 13, + "entry_address": 10432, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 14, + "entry_address": 10434, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 15, + "entry_address": 10436, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 16, + "entry_address": 10438, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 17, + "entry_address": 10440, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 18, + "entry_address": 10442, + "target": 11779, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 10444, + "target": 11782, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 10446, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 21, + "entry_address": 10448, + "target": 11833, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 10450, + "target": 11866, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 10452, + "target": 11909, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 10454, + "target": 11887, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 10456, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 26, + "entry_address": 10458, + "target": 11972, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 10460, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 28, + "entry_address": 10462, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 29, + "entry_address": 10464, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 30, + "entry_address": 10466, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 31, + "entry_address": 10468, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 32, + "entry_address": 10470, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 33, + "entry_address": 10472, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 34, + "entry_address": 10474, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 35, + "entry_address": 10476, + "target": 12006, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 10478, + "target": 12044, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 10480, + "target": 12060, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 10482, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 39, + "entry_address": 10484, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 40, + "entry_address": 10486, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 41, + "entry_address": 10488, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 42, + "entry_address": 10490, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 43, + "entry_address": 10492, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 44, + "entry_address": 10494, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 45, + "entry_address": 10496, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 46, + "entry_address": 10498, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 47, + "entry_address": 10500, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 48, + "entry_address": 10502, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 49, + "entry_address": 10504, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 50, + "entry_address": 10506, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 51, + "entry_address": 10508, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 52, + "entry_address": 10510, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 53, + "entry_address": 10512, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 54, + "entry_address": 10514, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 55, + "entry_address": 10516, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 56, + "entry_address": 10518, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 57, + "entry_address": 10520, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 58, + "entry_address": 10522, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 59, + "entry_address": 10524, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 60, + "entry_address": 10526, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 61, + "entry_address": 10528, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 62, + "entry_address": 10530, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 63, + "entry_address": 10532, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 64, + "entry_address": 10534, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 65, + "entry_address": 10536, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 66, + "entry_address": 10538, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 67, + "entry_address": 10540, + "target": 12106, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 68, + "entry_address": 10542, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 69, + "entry_address": 10544, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 70, + "entry_address": 10546, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 71, + "entry_address": 10548, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 72, + "entry_address": 10550, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 73, + "entry_address": 10552, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 74, + "entry_address": 10554, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 75, + "entry_address": 10556, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 76, + "entry_address": 10558, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 77, + "entry_address": 10560, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 78, + "entry_address": 10562, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 79, + "entry_address": 10564, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 80, + "entry_address": 10566, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 81, + "entry_address": 10568, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 82, + "entry_address": 10570, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 83, + "entry_address": 10572, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 84, + "entry_address": 10574, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true 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"entry_address": 10588, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 92, + "entry_address": 10590, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 93, + "entry_address": 10592, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 94, + "entry_address": 10594, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 95, + "entry_address": 10596, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 96, + "entry_address": 10598, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 97, + "entry_address": 10600, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 98, + "entry_address": 10602, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 99, + "entry_address": 10604, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 100, + "entry_address": 10606, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 101, + "entry_address": 10608, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 102, + "entry_address": 10610, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 103, + "entry_address": 10612, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 104, + "entry_address": 10614, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 105, + "entry_address": 10616, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 106, + "entry_address": 10618, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 107, + "entry_address": 10620, + "target": 12146, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 108, + "entry_address": 10622, + "target": 12207, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 109, + "entry_address": 10624, + "target": 12309, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 110, + "entry_address": 10626, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 0, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 3, + "entry_address": 18756, + "target": 25292, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 4, + "entry_address": 18758, + "target": 25268, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 5, + "entry_address": 18760, + "target": 25248, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 6, + "entry_address": 18762, + "target": 25224, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 7, + "entry_address": 18764, + "target": 25205, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 18766, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 9, + "entry_address": 18768, + "target": 33086, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 10, + "entry_address": 18770, + "target": 33062, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 11, + "entry_address": 18772, + "target": 33042, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 12, + "entry_address": 18774, + "target": 33022, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (0/52 decoded targets)" + } + ] + }, + "dataflow": { + "blocks": [ + { + "start": 4096, + "instructions": [ + 4096, + 4099, + 4103, + 4108, + 4113, + 4118, + 4123, + 4128, + 4133, + 4138, + 4143, + 4148, + 4153, + 4158, + 4163, + 4168, + 4174, + 4179, + 4184, + 4189, + 4195, + 4200, + 4205, + 4210, + 4215, + 4220, + 4225, + 4230, + 4235, + 4240, + 4245, + 4250, + 4255, + 4260, + 4265, + 4270, + 4275, + 4280, + 4285, + 4290, + 4295, + 4299 + ], + "end": 4299, + "end_exclusive": 4302 + }, + { + "start": 4302, + "instructions": [ + 4302, + 4305, + 4308, + 4311, + 4314, + 4317, + 4320, + 4323, + 4326, + 4329, + 4332, + 4335, + 4338, + 4341, + 4344, + 4347, + 4350, + 4353, + 4356, + 4359, + 4362, + 4365, + 4368, + 4371, + 4374, + 4377, + 4380, + 4383, + 4386, + 4389, + 4392, + 4395, + 4398, + 4401, + 4404, + 4407, + 4410, + 4413, + 4416, + 4419, + 4422, + 4425, + 4428, + 4431, + 4434, + 4437, + 4440, + 4443, + 4446, + 4449, + 4452, + 4455, + 4458, + 4461, + 4464, + 4467, + 4470, + 4473, + 4476, + 4479, + 4482, + 4485, + 4488, + 4491, + 4494, + 4497, + 4500, + 4503, + 4506, + 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"address": 61707, + "name": "mem_F10B", + "region": "program_or_external", + "kind": "memory", + "access_count": 1, + "read_count": 0, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14844, + "last_access": 14844, + "accesses": [ + { + "address": 61707, + "instruction_address": 14844, + "instruction": "MOV:G.B R0, @H'F10B", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F10B", + "operand_index": 1 + } + ] + }, + { + "address": 61708, + "name": "mem_F10C", + "region": "program_or_external", + "kind": "memory", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 14852, + "last_access": 15217, + "accesses": [ + { + "address": 61708, + "instruction_address": 14852, + "instruction": "MOV:G.B R0, @H'F10C", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + 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] + }, + { + "address": 61953, + "name": "mem_F201", + "region": "program_or_external", + "kind": "memory", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16226, + "last_access": 16237, + "accesses": [ + { + "address": 61953, + "instruction_address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "mnemonic": "MOVTPE.B", + "direction": "write", + "width": "byte", + "operand": "@H'F201", + "operand_index": 1 + }, + { + "address": 61953, + "instruction_address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "mnemonic": "MOVFPE.B", + "direction": "read", + "width": "byte", + "operand": "@H'F201", + "operand_index": 0 + } + ] + }, + { + "address": 62466, + "name": "mem_F402", + "region": "program_or_external", + "kind": "memory", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 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"direction": "write", + "width": "byte", + "operand": "@H'F6E6", + "operand_index": 1 + } + ] + }, + { + "address": 63207, + "name": "ram_F6E7", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 6961, + "last_access": 6975, + "accesses": [ + { + "address": 63207, + "instruction_address": 6961, + "instruction": "XOR.B @H'F6E7, R4", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6E7", + "operand_index": 0 + }, + { + "address": 63207, + "instruction_address": 6975, + "instruction": "MOV:G.B R4, @H'F6E7", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6E7", + "operand_index": 1 + } + ] + }, + { + "address": 63211, + "name": "ram_F6EB", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7164, + "last_access": 7177, + "accesses": [ + { + "address": 63211, + "instruction_address": 7164, + "instruction": "XOR.B @H'F6EB, R4", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6EB", + "operand_index": 0 + }, + { + "address": 63211, + "instruction_address": 7177, + "instruction": "MOV:G.B R4, @H'F6EB", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6EB", + "operand_index": 1 + } + ] + }, + { + "address": 63212, + "name": "ram_F6EC", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 7142, + "last_access": 7155, + "accesses": [ + { + "address": 63212, + "instruction_address": 7142, + "instruction": "XOR.B @H'F6EC, R4", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6EC", + "operand_index": 0 + }, + { + "address": 63212, + "instruction_address": 7155, + "instruction": "MOV:G.B R4, @H'F6EC", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6EC", + "operand_index": 1 + } + ] + }, + { + "address": 63216, + "name": "ram_F6F0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 21, + "read_count": 19, + "write_count": 18, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5625, + "last_access": 15245, + "accesses": [ + { + "address": 63216, + "instruction_address": 5625, + "instruction": "TST.B @H'F6F0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 0 + }, + { + "address": 63216, + "instruction_address": 5631, + "instruction": "BCLR.B #7, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5640, + "instruction": "BCLR.B #6, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5649, + "instruction": "BCLR.B #5, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5658, + "instruction": "BCLR.B #4, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5662, + "instruction": "BCLR.B #3, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5671, + "instruction": "BCLR.B #2, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5680, + "instruction": "BCLR.B #1, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 5689, + "instruction": "BCLR.B #0, @H'F6F0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15072, + "instruction": "MOV:G.B @H'F6F0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 0 + }, + { + "address": 63216, + "instruction_address": 15079, + "instruction": "MOV:G.B R0, @H'F6F0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15093, + "instruction": "BSET.B #5, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15111, + "instruction": "BSET.B #4, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15129, + "instruction": "BSET.B #3, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15147, + "instruction": "BSET.B #2, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15165, + "instruction": "BSET.B #1, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15183, + "instruction": "BSET.B #0, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15202, + "instruction": "MOV:G.B @H'F6F0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 0 + }, + { + "address": 63216, + "instruction_address": 15209, + "instruction": "MOV:G.B R0, @H'F6F0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15227, + "instruction": "BSET.B #7, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + }, + { + "address": 63216, + "instruction_address": 15245, + "instruction": "BSET.B #6, @H'F6F0", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F0", + "operand_index": 1 + } + ] + }, + { + "address": 63217, + "name": "ram_F6F1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 21, + "read_count": 19, + "write_count": 18, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5693, + "last_access": 15606, + "accesses": [ + { + "address": 63217, + "instruction_address": 5693, + "instruction": "TST.B @H'F6F1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 0 + }, + { + "address": 63217, + "instruction_address": 5699, + "instruction": "BCLR.B #7, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5708, + "instruction": "BCLR.B #6, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + 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"BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 5762, + "instruction": "BCLR.B #0, @H'F6F1", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15433, + "instruction": "MOV:G.B @H'F6F1, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 0 + }, + { + "address": 63217, + "instruction_address": 15440, + "instruction": "MOV:G.B R0, @H'F6F1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15454, + "instruction": "BSET.B #5, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15472, + "instruction": "BSET.B #4, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15490, + "instruction": "BSET.B #3, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15508, + "instruction": "BSET.B #2, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15526, + "instruction": "BSET.B #1, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F1", + "operand_index": 1 + }, + { + "address": 63217, + "instruction_address": 15544, + "instruction": "BSET.B #0, @H'F6F1", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": 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"instruction": "BCLR.B #0, @H'F6F2", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15213, + "instruction": "CLR.B @H'F6F2", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 0 + }, + { + "address": 63218, + "instruction_address": 15263, + "instruction": "BSET.B #0, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15281, + "instruction": "BSET.B #1, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + "operand_index": 1 + }, + { + "address": 63218, + "instruction_address": 15299, + "instruction": "BSET.B #2, @H'F6F2", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F6F2", + 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"BCLR.B #4, @H'F711", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F711", + "operand_index": 1 + } + ] + }, + { + "address": 63250, + "name": "ram_F712", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 2, + "read_count": 1, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14784, + "last_access": 16979, + "accesses": [ + { + "address": 63250, + "instruction_address": 14784, + "instruction": "AND.B @H'F712, R0", + "mnemonic": "AND.B", + "direction": "read", + "width": "byte", + "operand": "@H'F712", + "operand_index": 0 + }, + { + "address": 63250, + "instruction_address": 16979, + "instruction": "CLR.B @H'F712", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F712", + "operand_index": 0 + } + ] + }, + { + "address": 63251, + "name": "ram_F713", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + 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"address": 63263, + "instruction_address": 14913, + "instruction": "MOV:G.B @H'F71F, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F71F", + "operand_index": 0 + }, + { + "address": 63263, + "instruction_address": 17038, + "instruction": "MOV:G.B #H'FF, @H'F71F", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F71F", + "operand_index": 1 + } + ] + }, + { + "address": 63264, + "name": "ram_F720", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14741, + "last_access": 15401, + "accesses": [ + { + "address": 63264, + "instruction_address": 14741, + "instruction": "TST.B @H'F720", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F720", + "operand_index": 0 + }, + { + "address": 63264, + "instruction_address": 14888, + "instruction": "MOV:G.B #H'03, @H'F720", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F720", + "operand_index": 1 + }, + { + "address": 63264, + "instruction_address": 15195, + "instruction": "BCLR.B #0, @H'F720", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F720", + "operand_index": 1 + }, + { + "address": 63264, + "instruction_address": 15401, + "instruction": "BCLR.B #1, @H'F720", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F720", + "operand_index": 1 + } + ] + }, + { + "address": 63265, + "name": "ram_F721", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14894, + "last_access": 15762, + "accesses": [ + { + "address": 63265, + "instruction_address": 14894, + "instruction": "TST.B @H'F721", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F721", + "operand_index": 0 + }, + { + "address": 63265, + "instruction_address": 15041, + "instruction": "MOV:G.B #H'03, @H'F721", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F721", + "operand_index": 1 + }, + { + "address": 63265, + "instruction_address": 15556, + "instruction": "BCLR.B #0, @H'F721", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F721", + "operand_index": 1 + }, + { + "address": 63265, + "instruction_address": 15762, + "instruction": "BCLR.B #1, @H'F721", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F721", + "operand_index": 1 + } + ] + }, + { + "address": 63266, + "name": "ram_F722", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 4, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14690, + "last_access": 14725, + "accesses": [ + { + "address": 63266, + "instruction_address": 14690, + "instruction": "ADD:Q.B #1, @H'F722", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F722", + "operand_index": 1 + }, + { + "address": 63266, + "instruction_address": 14694, + "instruction": "CMP:G.B #H'3C, @H'F722", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F722", + "operand_index": 1 + }, + { + "address": 63266, + "instruction_address": 14701, + "instruction": "CMP:G.B #H'78, @H'F722", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F722", + "operand_index": 1 + }, + { + "address": 63266, + "instruction_address": 14708, + "instruction": "CMP:G.B #H'B4, @H'F722", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F722", + "operand_index": 1 + }, + { + "address": 63266, + "instruction_address": 14725, + "instruction": "CLR.B @H'F722", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F722", + "operand_index": 0 + } + ] + }, + { + "address": 63267, + "name": "ram_F723", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 9, + "read_count": 9, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 14764, + "last_access": 48972, + "accesses": [ + { + "address": 63267, + "instruction_address": 14764, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14780, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14796, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14812, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14917, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14933, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14949, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 14965, + "instruction": "OR.B @H'F723, R0", + "mnemonic": "OR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + }, + { + "address": 63267, + "instruction_address": 48972, + "instruction": "NOT.B @H'F723", + "mnemonic": "NOT.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F723", + "operand_index": 0 + } + ] + }, + { + "address": 63268, + "name": "ram_F724", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48955, + "last_access": 48967, + "accesses": [ + { + "address": 63268, + "instruction_address": 48955, + "instruction": "TST.B @H'F724", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F724", + "operand_index": 0 + }, + { + "address": 63268, + "instruction_address": 48961, + "instruction": "ADD:Q.B #-1, @H'F724", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F724", + "operand_index": 1 + }, + { + "address": 63268, + "instruction_address": 48967, + "instruction": "MOV:G.B #H'03, @H'F724", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F724", + "operand_index": 1 + } + ] + }, + { + "address": 63270, + "name": "ram_F726", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 23050, + "last_access": 49031, + "accesses": [ + { + "address": 63270, + "instruction_address": 23050, + "instruction": "CLR.B @H'F726", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F726", + "operand_index": 0 + }, + { + "address": 63270, + "instruction_address": 23162, + "instruction": "TST.B @H'F726", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F726", + "operand_index": 0 + }, + { + "address": 63270, + "instruction_address": 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"first_access": null, + "last_access": null, + "accesses": [], + "xref_count": 2, + "xrefs": [ + { + "source": "pointer_table", + "address": 7856, + "target": 63271 + }, + { + "source": "pointer_table", + "address": 13432, + "target": 63271 + } + ] + }, + { + "address": 63278, + "name": "ram_F72E", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 23298, + "last_access": 23298, + "accesses": [ + { + "address": 63278, + "instruction_address": 23298, + "instruction": "MOV:G.B @H'F72E, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F72E", + "operand_index": 0 + } + ] + }, + { + "address": 63280, + "name": "ram_F730", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 4, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + 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"mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F730", + "operand_index": 1 + } + ], + "xref_count": 1, + "xrefs": [ + { + "source": "pointer_table", + "address": 7856, + "target": 63280 + } + ] + }, + { + "address": 63281, + "name": "ram_F731", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 23, + "read_count": 23, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 5893, + "last_access": 49087, + "accesses": [ + { + "address": 63281, + "instruction_address": 5893, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 5965, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 6037, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 6089, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 6139, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 6195, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 6245, + "instruction": "CMP:G.B #H'02, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + 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"address": 63281, + "instruction_address": 17495, + "instruction": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 17690, + "instruction": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 28725, + "instruction": "BSET.B #7, @H'F731", + "mnemonic": "BSET.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 48532, + "instruction": "BTST.B #7, @H'F731", + "mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F731", + "operand_index": 1 + }, + { + "address": 63281, + "instruction_address": 48565, + "instruction": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "direction": 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"instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 5926, + "instruction": "MOV:G.W #H'1C07, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 5990, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + "operand_index": 0 + }, + { + "address": 63282, + "instruction_address": 5998, + "instruction": "MOV:G.W #H'1C06, @H'F732", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F732", + "operand_index": 1 + }, + { + "address": 63282, + "instruction_address": 8493, + "instruction": "MOV:G.W @H'F732, R1", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F732", + 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"MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F85A", + "operand_index": 1 + }, + { + "address": 63578, + "instruction_address": 47704, + "instruction": "XOR.B @H'F85A, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F85A", + "operand_index": 0 + }, + { + "address": 63578, + "instruction_address": 48653, + "instruction": "MOV:G.W @H'F85A, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F85A", + "operand_index": 0 + } + ] + }, + { + "address": 63579, + "name": "ram_F85B", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47708, + "last_access": 47708, + "accesses": [ + { + "address": 63579, + "instruction_address": 47708, + "instruction": "XOR.B @H'F85B, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F85B", + "operand_index": 0 + } + ] + }, + { + "address": 63580, + "name": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 47690, + "last_access": 48661, + "accesses": [ + { + "address": 63580, + "instruction_address": 47690, + "instruction": "MOV:G.B R0, @H'F85C", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F85C", + "operand_index": 1 + }, + { + "address": 63580, + "instruction_address": 47712, + "instruction": "XOR.B @H'F85C, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F85C", + "operand_index": 0 + }, + { + "address": 63580, + "instruction_address": 48661, + "instruction": "MOV:G.W @H'F85C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F85C", + "operand_index": 0 + } + ] + }, + { + "address": 63581, + "name": "ram_F85D", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 0, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47716, + "last_access": 47716, + "accesses": [ + { + "address": 63581, + "instruction_address": 47716, + "instruction": "MOV:G.B R0, @H'F85D", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F85D", + "operand_index": 1 + } + ] + }, + { + "address": 63584, + "name": "ram_F860", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48055, + "last_access": 48136, + "accesses": [ + { + "address": 63584, + "instruction_address": 48055, + "instruction": "MOV:G.W R0, @H'F860", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F860", + 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48119, + "instruction": "MOV:G.B @H'F861, R5", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + }, + { + "address": 63585, + "instruction_address": 48153, + "instruction": "BTST.B #7, @H'F861", + "mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 1 + }, + { + "address": 63585, + "instruction_address": 48190, + "instruction": "BTST.B #7, @H'F861", + "mnemonic": "BTST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 1 + }, + { + "address": 63585, + "instruction_address": 48309, + "instruction": "MOV:G.B @H'F861, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + }, + { + "address": 63585, + "instruction_address": 48348, + "instruction": "MOV:G.B @H'F861, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + }, + { + "address": 63585, + "instruction_address": 48722, + "instruction": "MOV:G.B @H'F861, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F861", + "operand_index": 0 + } + ] + }, + { + "address": 63586, + "name": "ram_F862", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 5, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48063, + "last_access": 48730, + "accesses": [ + { + "address": 63586, + "instruction_address": 48063, + "instruction": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F862", + "operand_index": 1 + }, + { + "address": 63586, + "instruction_address": 48096, + "instruction": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48125, + "instruction": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48317, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48356, + "instruction": "MOV:G.B @H'F862, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F862", + "operand_index": 0 + }, + { + "address": 63586, + "instruction_address": 48730, + "instruction": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F862", + "operand_index": 0 + } + ] + }, + { + "address": 63587, + "name": "ram_F863", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 6, + "read_count": 6, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48100, + "last_access": 48603, + "accesses": [ + { + "address": 63587, + "instruction_address": 48100, + "instruction": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48237, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48267, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48402, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48427, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + }, + { + "address": 63587, + "instruction_address": 48603, + "instruction": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F863", + "operand_index": 0 + } + ] + }, + { + "address": 63588, + "name": "ram_F864", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 8, + "read_count": 6, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte", + "word" + ], + "width": "mixed", + "first_access": 48071, + "last_access": 48738, + "accesses": [ + { + "address": 63588, + "instruction_address": 48071, + "instruction": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "direction": "write", + "width": "word", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48104, + "instruction": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48253, + "instruction": "MOV:G.B #H'80, @H'F864", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F864", + "operand_index": 1 + }, + { + "address": 63588, + "instruction_address": 48273, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48325, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48433, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48609, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + }, + { + "address": 63588, + "instruction_address": 48738, + "instruction": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F864", + "operand_index": 0 + } + ] + }, + { + "address": 63589, + "name": "ram_F865", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 48108, + "last_access": 48108, + "accesses": [ + { + "address": 63589, + "instruction_address": 48108, + "instruction": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F865", + "operand_index": 0 + } + ] + }, + { + "address": 63592, + "name": "ram_F868", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48051, + "last_access": 48051, + "accesses": [ + { + "address": 63592, + "instruction_address": 48051, + "instruction": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F868", + "operand_index": 0 + } + ] + }, + { + "address": 63594, + "name": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48059, + "last_access": 48059, + "accesses": [ + { + "address": 63594, + "instruction_address": 48059, + "instruction": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86A", + "operand_index": 0 + } + ] + }, + { + "address": 63596, + "name": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 48067, + "last_access": 48067, + "accesses": [ + { + "address": 63596, + "instruction_address": 48067, + "instruction": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "direction": "read", + "width": "word", + "operand": "@H'F86C", + "operand_index": 0 + } + ] + }, + { + "address": 63920, + "name": "ram_F9B0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 9, + "read_count": 8, + "write_count": 5, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15968, + "last_access": 47864, + "accesses": [ + { + "address": 63920, + "instruction_address": 15968, + "instruction": "MOV:G.B @H'F9B0, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 15994, + "instruction": "ADD:Q.B #1, @H'F9B0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 15998, + "instruction": "BCLR.B #7, @H'F9B0", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 1 + }, + { + "address": 63920, + "instruction_address": 16002, + "instruction": "MOV:G.B @H'F9B0, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16377, + "instruction": "CLR.B @H'F9B0", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B0", + "operand_index": 0 + }, + { + "address": 63920, + "instruction_address": 16473, + "instruction": "MOV:G.B @H'F9B0, R2", + "mnemonic": "MOV:G.B", + "direction": "read", + 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"direction": "read", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 0 + }, + { + "address": 63924, + "instruction_address": 48789, + "instruction": "ADD:Q.B #1, @H'F9B4", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + }, + { + "address": 63924, + "instruction_address": 48793, + "instruction": "BCLR.B #5, @H'F9B4", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B4", + "operand_index": 1 + } + ] + }, + { + "address": 63925, + "name": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 10, + "write_count": 7, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 15960, + "last_access": 48631, + "accesses": [ + { + "address": 63925, + "instruction_address": 15960, + "instruction": "MOV:G.B @H'F9B5, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16011, + "instruction": "CMP:G.B @H'F9B5, R0", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16373, + "instruction": "CLR.B @H'F9B5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 16479, + "instruction": "CMP:G.B @H'F9B5, R2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 47858, + "instruction": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 0 + }, + { + "address": 63925, + "instruction_address": 48493, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48497, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48584, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48588, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48627, + "instruction": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + }, + { + "address": 63925, + "instruction_address": 48631, + "instruction": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9B5", + "operand_index": 1 + } + ] + }, + { + "address": 63929, + "name": "ram_F9B9", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 1, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 10246, + "last_access": 48752, + "accesses": [ + { + "address": 63929, + "instruction_address": 10246, + "instruction": "MOV:G.B @H'F9B9, R1", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 10274, + "instruction": "MOV:G.B R1, @H'F9B9", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 1 + }, + { + "address": 63929, + "instruction_address": 16030, + "instruction": "MOV:G.B @H'F9B9, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + }, + { + "address": 63929, + "instruction_address": 48752, + "instruction": "MOV:G.B @H'F9B9, R3", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9B9", + "operand_index": 0 + } + ] + }, + { + "address": 63936, + "name": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 11, + "read_count": 4, + "write_count": 8, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16357, + "last_access": 48884, + "accesses": [ + { + "address": 63936, + "instruction_address": 16357, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47654, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 47660, + "instruction": "MOV:G.B #H'64, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47778, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47834, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47841, + "instruction": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 47848, + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48669, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48702, + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + }, + { + "address": 63936, + "instruction_address": 48878, + "instruction": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 0 + }, + { + "address": 63936, + "instruction_address": 48884, + "instruction": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C0", + "operand_index": 1 + } + ] + }, + { + "address": 63937, + "name": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47853, + "last_access": 48894, + "accesses": [ + { + "address": 63937, + "instruction_address": 47853, + "instruction": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 47985, + "instruction": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 48035, + "instruction": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 1 + }, + { + "address": 63937, + "instruction_address": 48888, + "instruction": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 0 + }, + { + "address": 63937, + "instruction_address": 48894, + "instruction": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C1", + "operand_index": 1 + } + ] + }, + { + "address": 63938, + "name": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 4, + "read_count": 3, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47734, + "last_access": 47811, + "accesses": [ + { + "address": 63938, + "instruction_address": 47734, + "instruction": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47787, + "instruction": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 0 + }, + { + "address": 63938, + "instruction_address": 47807, + "instruction": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + }, + { + "address": 63938, + "instruction_address": 47811, + "instruction": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C2", + "operand_index": 1 + } + ] + }, + { + "address": 63939, + "name": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 10, + "read_count": 6, + "write_count": 4, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16351, + "last_access": 48849, + "accesses": [ + { + "address": 63939, + "instruction_address": 16351, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 16466, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47760, + "instruction": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47991, + "instruction": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 0 + }, + { + "address": 63939, + "instruction_address": 47997, + "instruction": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C3", + "operand_index": 1 + }, + { + "address": 63939, + "instruction_address": 48010, + "instruction": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", 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"on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 16454, + "last_access": 48941, + "accesses": [ + { + "address": 63940, + "instruction_address": 16454, + "instruction": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 0 + }, + { + "address": 63940, + "instruction_address": 16608, + "instruction": "MOV:G.B #H'14, @H'F9C4", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + }, + { + "address": 63940, + "instruction_address": 47665, + "instruction": "MOV:G.B #H'07, @H'F9C4", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C4", + "operand_index": 1 + }, + { + "address": 63940, + "instruction_address": 48935, + "instruction": "TST.B @H'F9C4", + "mnemonic": "TST.B", + "direction": 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"operand_index": 1 + }, + { + "address": 63941, + "instruction_address": 48868, + "instruction": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48945, + "instruction": "TST.B @H'F9C5", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 0 + }, + { + "address": 63941, + "instruction_address": 48951, + "instruction": "ADD:Q.B #-1, @H'F9C5", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C5", + "operand_index": 1 + } + ] + }, + { + "address": 63942, + "name": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 5, + "read_count": 3, + "write_count": 3, + "unknown_count": 0, + "width_hints": [ + "word" + ], + "width": "word", + "first_access": 47942, + "last_access": 48904, + "accesses": [ + { + "address": 63942, + "instruction_address": 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"operand_index": 1 + } + ] + }, + { + "address": 63944, + "name": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram", + "access_count": 3, + "read_count": 2, + "write_count": 2, + "unknown_count": 0, + "width_hints": [ + "byte" + ], + "width": "byte", + "first_access": 47948, + "last_access": 48833, + "accesses": [ + { + "address": 63944, + "instruction_address": 47948, + "instruction": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "direction": "write", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 1 + }, + { + "address": 63944, + "instruction_address": 48827, + "instruction": "TST.B @H'F9C8", + "mnemonic": "TST.B", + "direction": "read", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 0 + }, + { + "address": 63944, + "instruction_address": 48833, + "instruction": "ADD:Q.B #-1, @H'F9C8", + "mnemonic": "ADD:Q.B", + "direction": "read_write", + "width": "byte", + "operand": "@H'F9C8", + "operand_index": 1 + } + ] + }, + { + "address": 63995, + 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STORE~X", + "CUR SEL CHR X" + ] + }, + { + "start": 52953, + "end": 52966, + "count": 2, + "samples": [ + "1234", + "8965.,-(" + ] + } + ], + "searches": [ + { + "term": "CONNECT", + "literal_hits": [], + "candidate_hits": [], + "near_matches": [ + { + "address": 40997, + "text": " COMPLETED ", + "trimmed": "COMPLETED", + "score": 0.5 + }, + { + "address": 36473, + "text": "ON CONT1 OFF~X", + "trimmed": "ON CONT1 OFF~X", + "score": 0.444 + }, + { + "address": 36693, + "text": "ON CONT2 OFF~X", + "trimmed": "ON CONT2 OFF~X", + "score": 0.444 + }, + { + "address": 38057, + "text": " ON ", + "trimmed": "ON", + "score": 0.444 + }, + { + "address": 38707, + "text": " ON ", + "trimmed": "ON", + "score": 0.444 + }, + { + "address": 40342, + "text": " AUTO SET ", + "trimmed": "AUTO SET", + "score": 0.429 + }, + { + "address": 40476, + "text": " AUTO SET ", + "trimmed": "AUTO SET", + "score": 0.429 + }, + { + "address": 46908, + "text": " SCENE F. STORE~X", + "trimmed": "SCENE F. STORE~X", + "score": 0.421 + }, + { + "address": 29733, + "text": " OTHERS Xt%", + "trimmed": "OTHERS Xt%", + "score": 0.4 + }, + { + "address": 29796, + "text": " SAFETY ZONE Xtd", + "trimmed": "SAFETY ZONE Xtd", + "score": 0.4 + }, + { + "address": 46424, + "text": "SCENE F. RECALL~X", + "trimmed": "SCENE F. RECALL~X", + "score": 0.4 + }, + { + "address": 26243, + "text": "POINT1 POINT2Xf", + "trimmed": "POINT1 POINT2Xf", + "score": 0.381 + } + ], + "status": "not_found" + } + ], + "notes": [ + "LCD text scan is byte-oriented and conservative; strings may be inline script fields.", + "Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes." + ] + }, + "lcd_driver": { + "addresses": [ + { + "address": 61952, + "name": "lcd_status_control", + "role": "status/control register inferred from busy polling and command writes" + }, + { + "address": 61953, + "name": "lcd_data", + "role": "data register inferred from paired data reads/writes" + } + ], + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "polling_loops": [ + { + "read_address": 16202, + "test_address": 16207, + "branch_address": 16209, + "register": "R0", + "bit": 7, + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear" + } + ], + "routines": [ + { + "start": 16192, + "end": 16244, + "accesses": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + }, + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + }, + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "roles": [ + "lcd_command_or_address_write", + "lcd_data_read", + "lcd_data_write", + "lcd_status_read" + ], + "role_hint": "lcd_wait_and_transfer" + } + ], + "instructions": { + "16202": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16219": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ], + "16226": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ], + "16237": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ], + "16207": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ], + "16209": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + } + }, + "instructions": [ + { + "address": 4096, + "address_region": "program_or_external", + "bytes": "5FFE80", + "text": "MOV:I.W #H'FE80, R7", + "mnemonic": "MOV:I.W", + "operands": "#H'FE80, R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R7 = 0xFE80" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + } + } + } + }, + { + "address": 4099, + "address_region": "program_or_external", + "bytes": "0C070088", + "text": "LDC.W #H'0700, SR", + "mnemonic": "LDC.W", + "operands": "#H'0700, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + ], + "notes": [ + "SR = 0x0700" + ], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4103, + "address_region": "program_or_external", + "bytes": "15FE8006FF", + "text": "MOV:G.B #H'FF, @P1DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @P1DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65152, + "name": "P1DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DDR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4108, + "address_region": "program_or_external", + "bytes": "15FE820600", + "text": "MOV:G.B #H'00, @P1DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P1DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4113, + "address_region": "program_or_external", + "bytes": "15FE8906F9", + "text": "MOV:G.B #H'F9, @P6DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'F9, @P6DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65161, + "name": "P6DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DDR = H'F9", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4118, + "address_region": "program_or_external", + "bytes": "15FE8B06F1", + "text": "MOV:G.B #H'F1, @P6DR", + "mnemonic": "MOV:G.B", + "operands": "#H'F1, @P6DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65163, + "name": "P6DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P6DR = H'F1", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4123, + "address_region": "program_or_external", + "bytes": "15FE8C0600", + "text": "MOV:G.B #H'00, @P7DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65164, + "name": "P7DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DDR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4128, + "address_region": "program_or_external", + "bytes": "15FE8E0600", + "text": "MOV:G.B #H'00, @P7DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P7DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4133, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65278, + "name": "P9DDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DDR = H'93", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4138, + "address_region": "program_or_external", + "bytes": "15FEFF0600", + "text": "MOV:G.B #H'00, @P9DR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "P9DR = H'00", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4143, + "address_region": "program_or_external", + "bytes": "15FEFC0687", + "text": "MOV:G.B #H'87, @SYSCR1", + "mnemonic": "MOV:G.B", + "operands": "#H'87, @SYSCR1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65276, + "name": "SYSCR1", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4148, + "address_region": "program_or_external", + "bytes": "15FEFD0684", + "text": "MOV:G.B #H'84, @SYSCR2", + "mnemonic": "MOV:G.B", + "operands": "#H'84, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM)", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 4148, + "instruction": "MOV:G.B #H'84, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 132, + "value_hex": "H'84" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4153, + "address_region": "program_or_external", + "bytes": "15FE900602", + "text": "MOV:G.B #H'02, @FRT1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4158, + "address_region": "program_or_external", + "bytes": "15FE910601", + "text": "MOV:G.B #H'01, @FRT1_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4163, + "address_region": "program_or_external", + "bytes": "1DFE920600", + "text": "MOV:G.W #H'00, @FRT1_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT1_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65170, + "name": "FRT1_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4163, + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "register": "FRT1_FRC", + "high_address": 65170, + "low_address": 65171, + "referenced_address": 65170, + "referenced_address_hex": "H'FE92", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4168, + "address_region": "program_or_external", + "bytes": "1DFE9407009C", + "text": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'009C, @FRT1_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65172, + "name": "FRT1_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT1_OCRA_H = H'9C", + "valid": true, + "peripheral_access": [ + { + "address": 4168, + "instruction": "MOV:G.W #H'009C, @FRT1_OCRA_H", + "register": "FRT1_OCRA", + "high_address": 65172, + "low_address": 65173, + "referenced_address": 65172, + "referenced_address_hex": "H'FE94", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4174, + "address_region": "program_or_external", + "bytes": "15FEA00602", + "text": "MOV:G.B #H'02, @FRT2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'02, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4179, + "address_region": "program_or_external", + "bytes": "15FEA10601", + "text": "MOV:G.B #H'01, @FRT2_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @FRT2_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65185, + "name": "FRT2_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4184, + "address_region": "program_or_external", + "bytes": "1DFEA20600", + "text": "MOV:G.W #H'00, @FRT2_FRC_H", + "mnemonic": "MOV:G.W", + "operands": "#H'00, @FRT2_FRC_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65186, + "name": "FRT2_FRC_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_FRC_H = H'00", + "valid": true, + "peripheral_access": [ + { + "address": 4184, + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "register": "FRT2_FRC", + "high_address": 65186, + "low_address": 65187, + "referenced_address": 65186, + "referenced_address_hex": "H'FEA2", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4189, + "address_region": "program_or_external", + "bytes": "1DFEA4077A12", + "text": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "mnemonic": "MOV:G.W", + "operands": "#H'7A12, @FRT2_OCRA_H", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65188, + "name": "FRT2_OCRA_H", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT2_OCRA_H = H'7A12", + "valid": true, + "peripheral_access": [ + { + "address": 4189, + "instruction": "MOV:G.W #H'7A12, @FRT2_OCRA_H", + "register": "FRT2_OCRA", + "high_address": 65188, + "low_address": 65189, + "referenced_address": 65188, + "referenced_address_hex": "H'FEA4", + "byte": "high", + "size": "W", + "direction": "write" + } + ], + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4195, + "address_region": "program_or_external", + "bytes": "15FEB00600", + "text": "MOV:G.B #H'00, @FRT3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65200, + "name": "FRT3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4200, + "address_region": "program_or_external", + "bytes": "15FEB10600", + "text": "MOV:G.B #H'00, @FRT3_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @FRT3_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65201, + "name": "FRT3_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4205, + "address_region": "program_or_external", + "bytes": "15FED00600", + "text": "MOV:G.B #H'00, @TMR_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @TMR_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65232, + "name": "TMR_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4210, + "address_region": "program_or_external", + "bytes": "15FED10610", + "text": "MOV:G.B #H'10, @TMR_TCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'10, @TMR_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65233, + "name": "TMR_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4215, + "address_region": "program_or_external", + "bytes": "15FEC00638", + "text": "MOV:G.B #H'38, @PWM1_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65216, + "name": "PWM1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4220, + "address_region": "program_or_external", + "bytes": "15FEC106FF", + "text": "MOV:G.B #H'FF, @PWM1_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM1_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65217, + "name": "PWM1_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM1_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4225, + "address_region": "program_or_external", + "bytes": "15FEC40638", + "text": "MOV:G.B #H'38, @PWM2_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'38, @PWM2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65220, + "name": "PWM2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4230, + "address_region": "program_or_external", + "bytes": "15FEC506FF", + "text": "MOV:G.B #H'FF, @PWM2_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @PWM2_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65221, + "name": "PWM2_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM2_DTR = H'FF", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4235, + "address_region": "program_or_external", + "bytes": "15FEC8063B", + "text": "MOV:G.B #H'3B, @PWM3_TCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3B, @PWM3_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65224, + "name": "PWM3_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4240, + "address_region": "program_or_external", + "bytes": "15FEC9067D", + "text": "MOV:G.B #H'7D, @PWM3_DTR", + "mnemonic": "MOV:G.B", + "operands": "#H'7D, @PWM3_DTR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65225, + "name": "PWM3_DTR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "PWM3_DTR = H'7D", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4245, + "address_region": "program_or_external", + "bytes": "15FED80624", + "text": "MOV:G.B #H'24, @SCI1_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI1_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65240, + "name": "SCI1_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4245, + "instruction": "MOV:G.B #H'24, @SCI1_SMR", + "channel": "SCI1", + "register": "SMR", + "register_address": 65240, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 36, + "value_hex": "H'24" + } + ], + "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4250, + "address_region": "program_or_external", + "bytes": "15FEDA063C", + "text": "MOV:G.B #H'3C, @SCI1_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'3C, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "MOV:G", + "value": 60, + "value_hex": "H'3C" + } + ] + }, + "sci_protocol": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_transmitter", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": true, + "interrupt_source": "TXD output", + "value": 60 + }, + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "action": "enable_receiver", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": true, + "interrupt_source": "RXD input", + "value": 60 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4250, + "instruction": "MOV:G.B #H'3C, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 60, + "value_hex": "H'3C", + "scr": { + "value": 60, + "value_hex": "H'3C", + "tie": false, + "rie": false, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4255, + "address_region": "program_or_external", + "bytes": "15FED90607", + "text": "MOV:G.B #H'07, @SCI1_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI1_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65241, + "name": "SCI1_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI1", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 60, + "scr_hex": "H'3C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4255, + "instruction": "MOV:G.B #H'07, @SCI1_BRR", + "channel": "SCI1", + "register": "BRR", + "register_address": 65241, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)", + "value": 7, + "value_hex": "H'07" + } + ], + "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4260, + "address_region": "program_or_external", + "bytes": "15FEF00624", + "text": "MOV:G.B #H'24, @SCI2_SMR", + "mnemonic": "MOV:G.B", + "operands": "#H'24, @SCI2_SMR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65264, + "name": "SCI2_SMR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "operation": "MOV:G", + "value": 36, + "value_hex": "H'24" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4260, + "instruction": "MOV:G.B #H'24, @SCI2_SMR", + "channel": "SCI2", + "register": "SMR", + "register_address": 65264, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 36, + "value_hex": "H'24", + "p9sci2e": false + } + ], + "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4265, + "address_region": "program_or_external", + "bytes": "15FEF2060C", + "text": "MOV:G.B #H'0C, @SCI2_SCR", + "mnemonic": "MOV:G.B", + "operands": "#H'0C, @SCI2_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65266, + "name": "SCI2_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock)", + "valid": true, + "sci": { + "writes": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "operation": "MOV:G", + "value": 12, + "value_hex": "H'0C" + } + ] + }, + "sci_protocol": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_rx_eri_interrupts", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": false, + "interrupt_source": "RXI and ERI", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_transmitter", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 transmitter (TE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "bit_name": "TE", + "enabled": false, + "interrupt_source": "TXD output", + "value": 12 + }, + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "action": "disable_receiver", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "register_address_hex": "H'FEF2", + "comment": "disable SCI2 receiver (RE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "bit_name": "RE", + "enabled": false, + "interrupt_source": "RXD input", + "value": 12 + } + ], + "board_profile": { + "accesses": [ + { + "address": 4265, + "instruction": "MOV:G.B #H'0C, @SCI2_SCR", + "channel": "SCI2", + "register": "SCR", + "register_address": 65266, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 12, + "value_hex": "H'0C", + "scr": { + "value": 12, + "value_hex": "H'0C", + "tie": false, + "rie": false, + "tx_enabled": false, + "rx_enabled": false + }, + "p9sci2e": false + } + ], + "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4270, + "address_region": "program_or_external", + "bytes": "15FEF10607", + "text": "MOV:G.B #H'07, @SCI2_BRR", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @SCI2_BRR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65265, + "name": "SCI2_BRR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI2_BRR = H'07", + "valid": true, + "sci": { + "writes": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "operation": "MOV:G", + "value": 7, + "value_hex": "H'07" + } + ], + "inferences": [ + { + "channel": "SCI2", + "mode": "async", + "mode_summary": "async 8-bit even parity 1 stop", + "smr": 36, + "smr_hex": "H'24", + "brr": 7, + "brr_hex": "H'07", + "scr": 12, + "scr_hex": "H'0C", + "cks_n": 0, + "cks_divisor": 1, + "denominator": 512, + "clock_source": "internal", + "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))", + "baud_bps": null, + "confidence": "partial", + "reason": "clock_hz_missing", + "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz", + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR" + } + ] + }, + "board_profile": { + "accesses": [ + { + "address": 4270, + "instruction": "MOV:G.B #H'07, @SCI2_BRR", + "channel": "SCI2", + "register": "BRR", + "register_address": 65265, + "access": "write", + "traced_to_max202": false, + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96", + "value": 7, + "value_hex": "H'07", + "p9sci2e": false + } + ], + "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96" + }, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4275, + "address_region": "program_or_external", + "bytes": "15FEE80619", + "text": "MOV:G.B #H'19, @ADCSR", + "mnemonic": "MOV:G.B", + "operands": "#H'19, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4280, + "address_region": "program_or_external", + "bytes": "15FEE9067F", + "text": "MOV:G.B #H'7F, @H'FEE9", + "mnemonic": "MOV:G.B", + "operands": "#H'7F, @H'FEE9", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65257, + "name": null, + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4285, + "address_region": "program_or_external", + "bytes": "15FF1006F0", + "text": "MOV:G.B #H'F0, @WCR", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @WCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65296, + "name": "WCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4290, + "address_region": "program_or_external", + "bytes": "15FF1106FF", + "text": "MOV:G.B #H'FF, @RAMCR", + "mnemonic": "MOV:G.B", + "operands": "#H'FF, @RAMCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65297, + "name": "RAMCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "RAMCR = H'FF (RAME=1; on-chip RAM enabled)", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4295, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P1DR", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4299, + "address_region": "program_or_external", + "bytes": "302EA8", + "text": "BRA loc_3F76", + "mnemonic": "BRA", + "operands": "loc_3F76", + "kind": "jump", + "targets": [ + 16246 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4096, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R7": { + "known": true, + "value": 65152, + "hex": "0xFE80", + "width": 16, + "source": "MOV:I.W #H'FE80, R7" + } + }, + "control": { + "SR": { + "known": true, + "value": 1792, + "hex": "0x0700", + "width": 16, + "source": "LDC.W #H'0700, SR" + } + } + } + } + }, + { + "address": 4302, + "address_region": "program_or_external", + "bytes": "5C0040", + "text": "MOV:I.W #H'0040, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0040, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0040" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + } + } + } + } + }, + { + "address": 4305, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 4308, + "address_region": "program_or_external", + "bytes": "1E2DF5", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 64, + "hex": "0x0040", + "width": 16, + "source": "MOV:I.W #H'0040, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 4311, + "address_region": "program_or_external", + "bytes": "5C0200", + "text": "MOV:I.W #H'0200, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0200, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 4302, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 512, + "hex": "0x0200", + "width": 16, + "source": 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"text": "CMP:I #H'000F, R4", + "mnemonic": "CMP:I", + "operands": "#H'000F, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6582, + "changes": [], + "notes": [] + } + }, + { + "address": 6589, + "address_region": "program_or_external", + "bytes": "2314", + "text": "BLS loc_19D3", + "mnemonic": "BLS", + "operands": "loc_19D3", + "kind": "branch", + "targets": [ + 6611 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6582, + "changes": [], + "notes": [] + } + }, + { + "address": 6591, + "address_region": "program_or_external", + "bytes": "4CFFF0", + "text": "CMP:I #H'FFF0, R4", + "mnemonic": "CMP:I", + "operands": "#H'FFF0, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6591, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 6594, + "address_region": "program_or_external", + "bytes": "240F", + "text": "BCC loc_19D3", + "mnemonic": "BCC", + "operands": "loc_19D3", + "kind": "branch", + "targets": [ + 6611 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": 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"before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0xFF1C" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 65308, + "hex": "0xFF1C", + "width": 16, + "source": "MOV:I.W #H'FF1C, R4" + } + } + } + } + }, + { + "address": 6609, + "address_region": "program_or_external", + "bytes": "2004", + "text": "BRA loc_19D7", + "mnemonic": "BRA", + "operands": "loc_19D7", + "kind": "jump", + "targets": [ + 6615 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6606, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 65308, + "hex": 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"address": 6615, + "address_region": "program_or_external", + "bytes": "ACA8", + "text": "MULXU.W R4, R0", + "mnemonic": "MULXU.W", + "operands": "R4, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 25, + "base_cycles": 25, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6615, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:MULXU.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 6617, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA 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"assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6642, + "address_region": "program_or_external", + "bytes": "230F", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6637, + "changes": [], + "notes": [] + } + }, + { + "address": 6644, + "address_region": "program_or_external", + "bytes": "590000", + "text": "MOV:I.W #H'0000, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'0000, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + 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"address_region": "program_or_external", + "bytes": "2303", + "text": "BLS loc_1A03", + "mnemonic": "BLS", + "operands": "loc_1A03", + "kind": "branch", + "targets": [ + 6659 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6649, + "changes": [], + "notes": [] + } + }, + { + "address": 6656, + "address_region": "program_or_external", + "bytes": "59FFFF", + "text": "MOV:I.W #H'FFFF, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'FFFF, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6656, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 65535, + "hex": "0xFFFF", + "width": 16, + "source": "MOV:I.W #H'FFFF, R1" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 = 0xFFFF" + ], + "known_after": { + "registers": { + "R1": { + "known": true, + "value": 65535, + "hex": "0xFFFF", + "width": 16, + "source": "MOV:I.W #H'FFFF, R1" + } + } + } + } + }, + { + "address": 6659, + "address_region": "program_or_external", + "bytes": "FBE00071", + "text": "CMP:G.W @(-H'2000,R3), R1", + "mnemonic": "CMP:G.W", + "operands": "@(-H'2000,R3), R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"program_or_external", + "bytes": "AB85", + "text": "MOV:G.W R3, R5", + "mnemonic": "MOV:G.W", + "operands": "R3, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 6709, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 unknown after MOV source" + ] + } + }, + { + "address": 6711, + "address_region": "program_or_external", + "bytes": "0C01FF53", + "text": "AND.W #H'01FF, R3", + "mnemonic": "AND.W", + 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+ "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 10482, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 39, + "entry_address": 10484, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 40, + "entry_address": 10486, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 41, + "entry_address": 10488, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 42, + "entry_address": 10490, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 43, + "entry_address": 10492, + "target": 11430, + "target_label": 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"entry_address": 10578, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 87, + "entry_address": 10580, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 88, + "entry_address": 10582, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 89, + "entry_address": 10584, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 90, + "entry_address": 10586, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 91, + "entry_address": 10588, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 92, + "entry_address": 10590, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 93, + "entry_address": 10592, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 94, + "entry_address": 10594, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 95, + "entry_address": 10596, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 96, + "entry_address": 10598, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 97, + "entry_address": 10600, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 98, + "entry_address": 10602, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 99, + "entry_address": 10604, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 100, + "entry_address": 10606, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 101, + "entry_address": 10608, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 102, + "entry_address": 10610, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 103, + "entry_address": 10612, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 104, + "entry_address": 10614, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 105, + "entry_address": 10616, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 106, + "entry_address": 10618, + "target": 12124, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 107, + "entry_address": 10620, + "target": 12146, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 108, + "entry_address": 10622, + "target": 12207, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 109, + "entry_address": 10624, + "target": 12309, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 110, + "entry_address": 10626, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 111, + "entry_address": 10628, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 112, + "entry_address": 10630, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 113, + "entry_address": 10632, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 114, + "entry_address": 10634, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 115, + "entry_address": 10636, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 116, + "entry_address": 10638, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 117, + "entry_address": 10640, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 118, + "entry_address": 10642, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 119, + "entry_address": 10644, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 120, + "entry_address": 10646, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 121, + "entry_address": 10648, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 122, + "entry_address": 10650, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 123, + "entry_address": 10652, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 124, + "entry_address": 10654, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 125, + "entry_address": 10656, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 126, + "entry_address": 10658, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + }, + { + "index": 127, + "entry_address": 10660, + "target": 11430, + "target_label": "loc_2CA6", + "target_region": "program_or_external", + "decoded_code": true + } + ] + }, + "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)" + }, + "dataflow": { + "block": 10399, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "indirect_jump" + } + } + ], + "notes": [ + "indirect jump ends known register state" + ] + } + }, + { + "address": 11430, + "address_region": "program_or_external", + "bytes": "15F769D7", + "text": "BCLR.B #7, @H'F769", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11434, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11430, + "changes": [], + "notes": [] + } + }, + { + "address": 11435, + "address_region": "program_or_external", + "bytes": "1231", + "text": "STM.W {R0,R4,R5}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R4,R5}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 15, + "note": "6+3n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 11437, + "address_region": "program_or_external", + "bytes": "1E1C4A", + "text": "BSR loc_48FA", + "mnemonic": "BSR", + "operands": "loc_48FA", + "kind": "call", + "targets": [ + 18682 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 11440, + "address_region": "program_or_external", + "bytes": "0231", + "text": "LDM.W @SP+, {R0,R4,R5}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R4,R5}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 18, + "note": "6+4n, n=3", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R4, R5" + ] + } + }, + { + "address": 11442, + "address_region": "program_or_external", + "bytes": "15F769C7", + "text": "BSET.B #7, @H'F769", + "mnemonic": "BSET.B", + "operands": "#7, @H'F769", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63337, + "name": null, + "symbol": "ram_F769", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 11446, + "address_region": "program_or_external", + "bytes": "30FBE6", + "text": "BRA loc_289F", + "mnemonic": "BRA", + "operands": "loc_289F", + "kind": "jump", + "targets": [ + 10399 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 11435, + "changes": [], + "notes": [] + } + }, + { + "address": 14640, + "address_region": "program_or_external", + "bytes": "580007", + "text": "MOV:I.W #H'0007, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14640, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x0007" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + } + } + } + }, + { + "address": 14643, + "address_region": "program_or_external", + "bytes": "15FE8E78", + "text": "BTST.B R0, @P7DR", + "mnemonic": "BTST.B", + "operands": "R0, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 14643, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14647, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_3943", + "mnemonic": "BEQ", + "operands": "loc_3943", + "kind": "branch", + "targets": [ + 14659 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14643, + "changes": [], + "notes": [] + } + }, + { + "address": 14649, + "address_region": "program_or_external", + "bytes": "F0F6801A", + "text": "SHLL.B @(-H'0980,R0)", + "mnemonic": "SHLL.B", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14653, + "address_region": "program_or_external", + "bytes": "F0F680C0", + "text": "BSET.B #0, @(-H'0980,R0)", + "mnemonic": "BSET.B", + "operands": "#0, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [], + "notes": [] + } + }, + { + "address": 14657, + "address_region": "program_or_external", + "bytes": "2004", + "text": "BRA loc_3947", + "mnemonic": "BRA", + "operands": "loc_3947", + "kind": "jump", + "targets": [ + 14663 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14649, + "changes": [], + "notes": [] + } + }, + { + "address": 14659, + "address_region": "program_or_external", + "bytes": "F0F6801A", + "text": "SHLL.B @(-H'0980,R0)", + "mnemonic": "SHLL.B", + "operands": "@(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14659, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14663, + "address_region": "program_or_external", + "bytes": "F0F68004FF", + "text": "CMP:G.B #H'FF, @(-H'0980,R0)", + "mnemonic": "CMP:G.B", + "operands": "#H'FF, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14663, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14668, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_3954", + "mnemonic": "BNE", + "operands": "loc_3954", + "kind": "branch", + "targets": [ + 14676 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14663, + "changes": [], + "notes": [] + } + }, + { + "address": 14670, + "address_region": "program_or_external", + "bytes": "15F68848", + "text": "BSET.B R0, @H'F688", + "mnemonic": "BSET.B", + "operands": "R0, @H'F688", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63112, + "name": null, + "symbol": "ram_F688", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 14670, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 14674, + "address_region": "program_or_external", + "bytes": "200B", + "text": "BRA loc_395F", + "mnemonic": "BRA", + "operands": "loc_395F", + "kind": "jump", + "targets": [ + 14687 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 14670, + "changes": [], + "notes": [] + } + }, + { + "address": 14676, + "address_region": "program_or_external", + "bytes": "F0F6800400", + "text": "CMP:G.B #H'00, @(-H'0980,R0)", + "mnemonic": "CMP:G.B", + "operands": "#H'00, @(-H'0980,R0)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait 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"after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x00C0" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + } + } + } + }, + { + "address": 16113, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA loc_3EFB", + "mnemonic": "BRA", + "operands": "loc_3EFB", + "kind": "jump", + "targets": [ + 16123 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16110, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 192, + "hex": "0x00C0", + "width": 16, + "source": "MOV:I.W #H'00C0, R5" + } + } + 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"normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16120, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 208, + "hex": "0x00D0", + "width": 16, + "source": "MOV:I.W #H'00D0, R5" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R5 = 0x00D0" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 208, + "hex": "0x00D0", + "width": 16, + "source": "MOV:I.W #H'00D0, R5" + } + } + } + } + }, + { + "address": 16123, + "address_region": "program_or_external", + "bytes": "0410AB", + "text": "MULXU.B #H'10, R3", + "mnemonic": "MULXU.B", + "operands": "#H'10, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 19, + "base_cycles": 19, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16123, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:MULXU.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 16126, + "address_region": "program_or_external", + "bytes": "0CFAB023", + "text": "ADD:G.W #H'FAB0, R3", + "mnemonic": "ADD:G.W", + "operands": "#H'FAB0, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16123, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "unsupported:MULXU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R3 unknown after arithmetic" + ] + } + }, + { + "address": 16130, + "address_region": "program_or_external", + "bytes": "A913", + "text": "CLR.W R1", + "mnemonic": "CLR.W", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": 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"changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after memory load" + ] + } + }, + { + "address": 16136, + "address_region": "program_or_external", + "bytes": "D372", + "text": "CMP:G.B @R3, R2", + "mnemonic": "CMP:G.B", + "operands": "@R3, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16138, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_3F10", + "mnemonic": "BEQ", + "operands": "loc_3F10", + "kind": "branch", + "targets": [ + 16144 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16132, + "changes": [], + "notes": [] + } + }, + { + "address": 16140, + "address_region": "program_or_external", + "bytes": "D392", + "text": "MOV:G.B R2, @R3", + "mnemonic": "MOV:G.B", + "operands": "R2, @R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16140, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16142, + "address_region": "program_or_external", + "bytes": "0E18", + "text": "BSR loc_3F28", + "mnemonic": "BSR", + "operands": "loc_3F28", + "kind": "call", + "targets": [ + 16168 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16140, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": 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"before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": 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], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 16146, + "address_region": "program_or_external", + "bytes": "A308", + "text": "ADD:Q.B #1, R3", + "mnemonic": "ADD:Q.B", + "operands": "#1, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R3 unknown after arithmetic" + ] + } + }, + { + "address": 16148, + "address_region": "program_or_external", + "bytes": "4110", + "text": "CMP:E #H'10, R1", + "mnemonic": "CMP:E", + "operands": "#H'10, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [], + "notes": [] + } + }, + { + "address": 16150, + "address_region": "program_or_external", + "bytes": "2702", + "text": "BEQ loc_3F1A", + "mnemonic": "BEQ", + "operands": "loc_3F1A", + "kind": "branch", + "targets": [ + 16154 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16144, + "changes": [], + "notes": [] + } + }, + { + "address": 16152, + "address_region": "program_or_external", + "bytes": "20EA", + "text": "BRA loc_3F04", + "mnemonic": "BRA", + "operands": "loc_3F04", + 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"control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16202, + "instruction": "MOVFPE.B @H'F200, R0", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "read", + "role": "lcd_status_read", + "register": "R0", + "summary": "LCD status read from E-clock H'F200" + }, + { + "address": 16202, + "kind": "lcd_busy_status_read", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16207, + "address_region": "program_or_external", + "bytes": "A0F7", + "text": "BTST.B #7, R0", + "mnemonic": "BTST.B", + "operands": "#7, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16207, + "kind": "lcd_busy_flag_test", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16209, + "address_region": "program_or_external", + "bytes": "26F7", + "text": "BNE loc_3F4A", + "mnemonic": "BNE", + "operands": "loc_3F4A", + "kind": "branch", + "targets": [ + 16202 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16202, + "changes": [], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16209, + "kind": "lcd_busy_wait_branch", + "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear", + "loop_start": 16202 + } + ] + }, + { + "address": 16211, + "address_region": "program_or_external", + "bytes": "ACF8", + "text": "BTST.W #8, R4", + "mnemonic": "BTST.W", + "operands": "#8, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16213, + "address_region": "program_or_external", + "bytes": "2616", + "text": "BNE loc_3F6D", + "mnemonic": "BNE", + "operands": "loc_3F6D", + "kind": "branch", + "targets": [ + 16237 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16211, + "changes": [], + "notes": [] + } + }, + { + "address": 16215, + "address_region": "program_or_external", + "bytes": "ACF9", + "text": "BTST.W #9, R4", + "mnemonic": "BTST.W", + "operands": "#9, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 16217, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_3F62", + "mnemonic": "BNE", + "operands": "loc_3F62", + "kind": "branch", + "targets": [ + 16226 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16215, + "changes": [], + "notes": [] + } + }, + { + "address": 16219, + "address_region": "program_or_external", + "bytes": "15F2000094", + "text": "MOVTPE.B R4, @H'F200", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F200", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61952, + "name": null, + "symbol": "mem_F200", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16219, + "instruction": "MOVTPE.B R4, @H'F200", + "lcd_address": 61952, + "lcd_name": "lcd_status_control", + "direction": "write", + "role": "lcd_command_or_address_write", + "register": "R4", + "summary": "LCD command/address write to E-clock H'F200" + } + ] + }, + { + "address": 16224, + "address_region": "program_or_external", + "bytes": "2010", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16219, + "changes": [], + "notes": [] + } + }, + { + "address": 16226, + "address_region": "program_or_external", + "bytes": "15F2010094", + "text": "MOVTPE.B R4, @H'F201", + "mnemonic": "MOVTPE.B", + "operands": "R4, @H'F201", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + }, + "lcd_driver": [ + { + "address": 16226, + "instruction": "MOVTPE.B R4, @H'F201", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "write", + "role": "lcd_data_write", + "register": "R4", + "summary": "LCD data write to E-clock H'F201" + } + ] + }, + { + "address": 16231, + "address_region": "program_or_external", + "bytes": "1DFB0008", + "text": "ADD:Q.W #1, @H'FB00", + "mnemonic": "ADD:Q.W", + "operands": "#1, @H'FB00", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64256, + "name": null, + "symbol": "ram_FB00", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16235, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_3F72", + "mnemonic": "BRA", + "operands": "loc_3F72", + "kind": "jump", + "targets": [ + 16242 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16226, + "changes": [], + "notes": [] + } + }, + { + "address": 16237, + "address_region": "program_or_external", + "bytes": "15F2010084", + "text": "MOVFPE.B @H'F201, R4", + "mnemonic": "MOVFPE.B", + "operands": "@H'F201, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 13, + "note": "E-clock peripheral transfer", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 61953, + "name": null, + "symbol": "mem_F201", + "region": "program_or_external", + "kind": "program" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 16237, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + }, + "lcd_driver": [ + { + "address": 16237, + "instruction": "MOVFPE.B @H'F201, R4", + "lcd_address": 61953, + "lcd_name": "lcd_data", + "direction": "read", + "role": "lcd_data_read", + "register": "R4", + "summary": "LCD data read from E-clock H'F201" + } + ] + }, + { + "address": 16242, + "address_region": "program_or_external", + "bytes": "CF88", + "text": "LDC.W @R7+, SR", + "mnemonic": "LDC.W", + "operands": "@R7+, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "SR unknown after memory load" + ] + } + }, + { + "address": 16244, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16242, + "changes": [], + "notes": [] + } + }, + { + "address": 16246, + "address_region": "program_or_external", + "bytes": "582710", + "text": "MOV:I.W #H'2710, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'2710, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x2710" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + } + } + } + } + }, + { + "address": 16249, + "address_region": "program_or_external", + "bytes": "59C350", + "text": "MOV:I.W #H'C350, R1", + "mnemonic": "MOV:I.W", + "operands": "#H'C350, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16246, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + ], + "notes": [ + "R1 = 0xC350" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 10000, + "hex": "0x2710", + "width": 16, + "source": "MOV:I.W #H'2710, R0" + }, + "R1": { + "known": true, + "value": 50000, + "hex": "0xC350", + "width": 16, + "source": "MOV:I.W #H'C350, R1" + } + } + } + } + }, + { + "address": 16252, + "address_region": "program_or_external", + "bytes": "15FE82D7", + "text": "BCLR.B #7, @P1DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P1DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65154, + "name": "P1DR", + "symbol": null, + "region": "register_field", + "kind": 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+ "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16259, + "changes": [], + "notes": [] + } + }, + { + "address": 16266, + "address_region": "program_or_external", + "bytes": "A813", + "text": "CLR.W R0", + "mnemonic": "CLR.W", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 16266, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 0, + "hex": "0x0000", + "width": 16, + "source": "CLR.W R0" + } + }, + { + "kind": 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register state" + ] + } + }, + { + "address": 17197, + "address_region": "program_or_external", + "bytes": "5C0001", + "text": "MOV:I.W #H'0001, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0001, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0001" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + } + } + }, + { + "address": 17200, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17203, + "address_region": "program_or_external", + "bytes": "1EFB96", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17206, + "address_region": "program_or_external", + "bytes": "5C000E", + "text": "MOV:I.W #H'000E, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'000E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x000E" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + } + } + } + } + }, + { + "address": 17209, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17212, + "address_region": "program_or_external", + "bytes": "1EFB8D", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 14, + "hex": "0x000E", + "width": 16, + "source": "MOV:I.W #H'000E, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17215, + "address_region": "program_or_external", + "bytes": "5C0006", + "text": "MOV:I.W #H'0006, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0006, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0006" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + } + } + } + } + }, + { + "address": 17218, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 17221, + "address_region": "program_or_external", + "bytes": "1EFB84", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": true, + "value": 6, + "hex": "0x0006", + "width": 16, + "source": "MOV:I.W #H'0006, R4" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17224, + "address_region": "program_or_external", + "bytes": "1ECD83", + "text": "BSR loc_10CE", + "mnemonic": "BSR", + "operands": "loc_10CE", + "kind": "call", + "targets": [ + 4302 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 17227, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17188, + "changes": [], + "notes": [] + } + }, + { + "address": 17228, + "address_region": "program_or_external", + "bytes": "15FF000670", + "text": "MOV:G.B #H'70, @IPRA", + "mnemonic": "MOV:G.B", + "operands": "#H'70, @IPRA", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65280, + "name": "IPRA", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRA = H'70 (irq0 priority=7; irq1 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17233, + "address_region": "program_or_external", + "bytes": "15FF010644", + "text": "MOV:G.B #H'44, @IPRB", + "mnemonic": "MOV:G.B", + "operands": "#H'44, @IPRB", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65281, + "name": "IPRB", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17238, + "address_region": "program_or_external", + "bytes": "15FF020666", + "text": "MOV:G.B #H'66, @IPRC", + "mnemonic": "MOV:G.B", + "operands": "#H'66, @IPRC", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65282, + "name": "IPRC", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRC = H'66 (FRT1 priority=6; FRT2 priority=6)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17243, + "address_region": "program_or_external", + "bytes": "15FF030600", + "text": "MOV:G.B #H'00, @IPRD", + "mnemonic": "MOV:G.B", + "operands": "#H'00, @IPRD", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65283, + "name": "IPRD", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17248, + "address_region": "program_or_external", + "bytes": "15FF040650", + "text": "MOV:G.B #H'50, @IPRE", + "mnemonic": "MOV:G.B", + "operands": "#H'50, @IPRE", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65284, + "name": "IPRE", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRE = H'50 (SCI1 priority=5; SCI2 priority=0)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17253, + "address_region": "program_or_external", + "bytes": "15FF050640", + "text": "MOV:G.B #H'40, @IPRF", + "mnemonic": "MOV:G.B", + "operands": "#H'40, @IPRF", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65285, + "name": "IPRF", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "IPRF = H'40 (A/D priority=4)", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17258, + "address_region": "program_or_external", + "bytes": "15FEDAC6", + "text": "BSET.B #6, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#6, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set RIE (bit 6) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "action": "enable_rx_eri_interrupts", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 receive and receive-error interrupts (RIE)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "bit_name": "RIE", + "enabled": true, + "interrupt_source": "RXI and ERI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 17258, + "instruction": "BSET.B #6, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17262, + "address_region": "program_or_external", + "bytes": "15FE90C5", + "text": "BSET.B #5, @FRT1_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT1_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65168, + "name": "FRT1_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT1_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17266, + "address_region": "program_or_external", + "bytes": "15FEA0C5", + "text": "BSET.B #5, @FRT2_TCR", + "mnemonic": "BSET.B", + "operands": "#5, @FRT2_TCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65184, + "name": "FRT2_TCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set OCIEA (bit 5) of FRT2_TCR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17270, + "address_region": "program_or_external", + "bytes": "15FEE8C6", + "text": "BSET.B #6, @ADCSR", + "mnemonic": "BSET.B", + "operands": "#6, @ADCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65256, + "name": "ADCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set ADIE (bit 6) of ADCSR", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17274, + "address_region": "program_or_external", + "bytes": "15FEFDC4", + "text": "BSET.B #4, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#4, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ3E (bit 4) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17274, + "instruction": "BSET.B #4, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 148, + "value_hex": "H'94" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17278, + "address_region": "program_or_external", + "bytes": "15FEFDC5", + "text": "BSET.B #5, @SYSCR2", + "mnemonic": "BSET.B", + "operands": "#5, @SYSCR2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65277, + "name": "SYSCR2", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set IRQ4E (bit 5) of SYSCR2", + "valid": true, + "board_profile": { + "accesses": [ + { + "address": 17278, + "instruction": "BSET.B #5, @SYSCR2", + "register": "SYSCR2", + "register_address": 65277, + "access": "write", + "p9sci2e": false, + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96", + "value": 180, + "value_hex": "H'B4" + } + ], + "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96" + }, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17282, + "address_region": "program_or_external", + "bytes": "15FE8EF6", + "text": "BTST.B #6, @P7DR", + "mnemonic": "BTST.B", + "operands": "#6, @P7DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65166, + "name": "P7DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17286, + "address_region": "program_or_external", + "bytes": "2706", + "text": "BEQ loc_438E", + "mnemonic": "BEQ", + "operands": "loc_438E", + "kind": "branch", + "targets": [ + 17294 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17228, + "changes": [], + "notes": [] + } + }, + { + "address": 17288, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 17288, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17294, + "address_region": "program_or_external", + "bytes": "0C030088", + "text": "LDC.W #H'0300, SR", + "mnemonic": "LDC.W", + "operands": "#H'0300, SR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [ + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + ], + "notes": [ + "SR = 0x0300" + ], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17298, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17294, + "changes": [], + "notes": [], + "known_after": { + "control": { + "SR": { + "known": true, + "value": 768, + "hex": "0x0300", + "width": 16, + "source": "LDC.W #H'0300, SR" + } + } + } + } + }, + { + "address": 17299, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17299, + "changes": [], + "notes": [] + } + }, + { + "address": 17300, + "address_region": "program_or_external", + "bytes": "15F7310401", + "text": "CMP:G.B #H'01, @H'F731", + "mnemonic": "CMP:G.B", + "operands": "#H'01, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17305, + "address_region": "program_or_external", + "bytes": "320086", + "text": "BHI loc_4422", + "mnemonic": "BHI", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17300, + "changes": [], + "notes": [] + } + }, + { + "address": 17308, + "address_region": "program_or_external", + "bytes": "15FB03F7", + "text": "BTST.B #7, @H'FB03", + "mnemonic": "BTST.B", + "operands": "#7, @H'FB03", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64259, + "name": null, + "symbol": "ram_FB03", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17308, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17312, + "address_region": "program_or_external", + "bytes": "36007F", + "text": "BNE loc_4422", + "mnemonic": "BNE", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17308, + "changes": [], + "notes": [] + } + }, + { + "address": 17315, + "address_region": "program_or_external", + "bytes": "1DF73683", + "text": "MOV:G.W @H'F736, R3", + "mnemonic": "MOV:G.W", + "operands": "@H'F736, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63286, + "name": null, + "symbol": "ram_F736", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17315, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R3 unknown after memory load" + ] + } + }, + { + "address": 17319, + "address_region": "program_or_external", + "bytes": "370078", + "text": "BEQ loc_4422", + "mnemonic": "BEQ", + "operands": "loc_4422", + "kind": "branch", + "targets": [ + 17442 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17315, + "changes": [], + "notes": [] + } + }, + { + "address": 17322, + "address_region": "program_or_external", + "bytes": "1DF69E84", + "text": "MOV:G.W @H'F69E, R4", + "mnemonic": "MOV:G.W", + "operands": "@H'F69E, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63134, + "name": null, + "symbol": "ram_F69E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 17326, + "address_region": "program_or_external", + "bytes": "1DF6BE34", + "text": "SUB.W @H'F6BE, R4", + "mnemonic": "SUB.W", + "operands": "@H'F6BE, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63166, + "name": null, + "symbol": "ram_F6BE", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 17330, + "address_region": "program_or_external", + "bytes": "ABDF", + "text": "BCLR.W #15, R3", + "mnemonic": "BCLR.W", + "operands": "#15, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17332, + "address_region": "program_or_external", + "bytes": "2619", + "text": "BNE loc_43CF", + "mnemonic": "BNE", + "operands": "loc_43CF", + "kind": "branch", + "targets": [ + 17359 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17322, + "changes": [], + "notes": [] + } + }, + { + "address": 17334, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17334, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17336, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_43DB", + "mnemonic": "BNE", + "operands": "loc_43DB", + "kind": "branch", + "targets": [ + 17371 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17334, + "changes": [], + "notes": [] + } + }, + { + "address": 17338, + "address_region": "program_or_external", + "bytes": "ABDD", + "text": "BCLR.W #13, R3", + "mnemonic": "BCLR.W", + "operands": "#13, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17338, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17340, + "address_region": "program_or_external", + "bytes": "2629", + "text": "BNE loc_43E7", + "mnemonic": "BNE", + "operands": "loc_43E7", + "kind": "branch", + "targets": [ + 17383 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17338, + "changes": [], + "notes": [] + } + }, + { + "address": 17342, + "address_region": "program_or_external", + "bytes": "ABDC", + "text": "BCLR.W #12, R3", + "mnemonic": "BCLR.W", + "operands": "#12, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17342, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17344, + "address_region": "program_or_external", + "bytes": "2631", + "text": "BNE loc_43F3", + "mnemonic": "BNE", + "operands": "loc_43F3", + "kind": "branch", + "targets": [ + 17395 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17342, + "changes": [], + "notes": [] + } + }, + { + "address": 17346, + "address_region": "program_or_external", + "bytes": "ABDB", + "text": "BCLR.W #11, R3", + "mnemonic": "BCLR.W", + "operands": "#11, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17346, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17348, + "address_region": "program_or_external", + "bytes": "2639", + "text": "BNE loc_43FF", + "mnemonic": "BNE", + "operands": "loc_43FF", + "kind": "branch", + "targets": [ + 17407 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand 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"kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 17491, + "address_region": "program_or_external", + "bytes": "5C0001", + "text": "MOV:I.W #H'0001, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0001, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17486, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 1, + "hex": "0x0001", + "width": 16, + "source": "MOV:I.W #H'0001, R4" + } + } + ], + "notes": [ + "R4 = 0x0001" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + 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"changes": [], + "notes": [] + } + }, + { + "address": 17529, + "address_region": "program_or_external", + "bytes": "ABDE", + "text": "BCLR.W #14, R3", + "mnemonic": "BCLR.W", + "operands": "#14, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [ + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17531, + "address_region": "program_or_external", + "bytes": "2621", + "text": "BNE loc_449E", + "mnemonic": "BNE", + "operands": "loc_449E", + "kind": "branch", + "targets": [ + 17566 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17529, + "changes": [], + "notes": [] + } + }, + { + "address": 17533, + "address_region": "program_or_external", + "bytes": "ABDD", + "text": "BCLR.W #13, R3", + "mnemonic": "BCLR.W", + "operands": "#13, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 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"kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.W" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R3" + ] + } + }, + { + "address": 17543, + "address_region": "program_or_external", + "bytes": "2639", + "text": "BNE loc_44C2", + "mnemonic": "BNE", + "operands": "loc_44C2", + "kind": "branch", + "targets": [ + 17602 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 17541, + "changes": [], + "notes": [] + } + }, + { + "address": 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"reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + 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"comment": "", + "valid": true, + "dataflow": { + "block": 18729, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 18733, + "address_region": "program_or_external", + "bytes": "260E", + "text": "BNE loc_493D", + "mnemonic": "BNE", + "operands": "loc_493D", + "kind": "branch", + "targets": [ + 18749 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18729, + "changes": [], + "notes": [] + } + }, + { + "address": 18735, + "address_region": "program_or_external", + "bytes": "15F73280", + "text": "MOV:G.B @H'F732, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F732, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63282, + "name": null, + "symbol": "ram_F732", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 18739, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 18741, + "address_region": "program_or_external", + "bytes": "A01A", + "text": "SHLL.B R0", + "mnemonic": "SHLL.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 18743, + "address_region": "program_or_external", + "bytes": "F8493E80", + "text": "MOV:G.W @(H'493E,R0), R0", + "mnemonic": "MOV:G.W", + "operands": "@(H'493E,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 18747, + "address_region": "program_or_external", + "bytes": "11D8", + "text": "JSR @R0", + "mnemonic": "JSR", + "operands": "@R0", + "kind": "call", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "indirect_flow": { + "address": 18747, + "instruction": "JSR @R0", + "kind": "call", + "target_register": "R0", + "confidence": "table_load", + "table": { + "base": 18750, + "index_register": "R0", + "target_register": "R0", + "load_address": 18743, + "load_instruction": "MOV:G.W @(H'493E,R0), R0", + "entry_size": 2, + "entry_count": 52, + "decoded_target_count": 0, + "entries": [ + { + "index": 0, + "entry_address": 18750, + "target": 25193, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 1, + "entry_address": 18752, + "target": 25372, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 2, + "entry_address": 18754, + "target": 25318, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 3, + "entry_address": 18756, + "target": 25292, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 4, + "entry_address": 18758, + "target": 25268, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 5, + "entry_address": 18760, + "target": 25248, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 6, + "entry_address": 18762, + "target": 25224, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 7, + "entry_address": 18764, + "target": 25205, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 8, + "entry_address": 18766, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 9, + "entry_address": 18768, + "target": 33086, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 10, + "entry_address": 18770, + "target": 33062, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 11, + "entry_address": 18772, + "target": 33042, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 12, + "entry_address": 18774, + "target": 33022, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 13, + "entry_address": 18776, + "target": 33002, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 14, + "entry_address": 18778, + "target": 32974, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 15, + "entry_address": 18780, + "target": 32938, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 16, + "entry_address": 18782, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 17, + "entry_address": 18784, + "target": 37844, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 18, + "entry_address": 18786, + "target": 37822, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 19, + "entry_address": 18788, + "target": 25192, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 20, + "entry_address": 18790, + "target": 37802, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 21, + "entry_address": 18792, + "target": 37778, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 22, + "entry_address": 18794, + "target": 37756, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 23, + "entry_address": 18796, + "target": 37722, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 24, + "entry_address": 18798, + "target": 37670, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 25, + "entry_address": 18800, + "target": 37642, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 26, + "entry_address": 18802, + "target": 37618, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 27, + "entry_address": 18804, + "target": 37614, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 28, + "entry_address": 18806, + "target": 37580, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 29, + "entry_address": 18808, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 30, + "entry_address": 18810, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 31, + "entry_address": 18812, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 32, + "entry_address": 18814, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 33, + "entry_address": 18816, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 34, + "entry_address": 18818, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 35, + "entry_address": 18820, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 36, + "entry_address": 18822, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 37, + "entry_address": 18824, + "target": 12807, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 38, + "entry_address": 18826, + "target": 6912, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 39, + "entry_address": 18828, + "target": 7935, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 40, + "entry_address": 18830, + "target": 27417, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 41, + "entry_address": 18832, + "target": 5627, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 42, + "entry_address": 18834, + "target": 983, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 43, + "entry_address": 18836, + "target": 9736, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 44, + "entry_address": 18838, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 45, + "entry_address": 18840, + "target": 12928, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 46, + "entry_address": 18842, + "target": 7671, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 47, + "entry_address": 18844, + "target": 13456, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 48, + "entry_address": 18846, + "target": 5623, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 49, + "entry_address": 18848, + "target": 12804, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 50, + "entry_address": 18850, + "target": 6695, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + }, + { + "index": 51, + "entry_address": 18852, + "target": 1565, + "target_label": null, + "target_region": "program_or_external", + "decoded_code": false + } + ] + }, + "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (0/52 decoded targets)" + }, + "dataflow": { + "block": 18735, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 18749, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 18749, + "changes": [], + "notes": [] + } + }, + { + "address": 21760, + "address_region": "program_or_external", + "bytes": "15F795F7", + "text": "BTST.B #7, @H'F795", + "mnemonic": "BTST.B", + "operands": "#7, @H'F795", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63381, + "name": null, + "symbol": "ram_F795", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 21760, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 21764, + "address_region": "program_or_external", + "bytes": "3600A6", + "text": "BNE loc_55AD", + "mnemonic": "BNE", + "operands": "loc_55AD", + "kind": "branch", + "targets": [ + 21933 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21760, + "changes": [], + "notes": [] + } + }, + { + "address": 21767, + "address_region": "program_or_external", + "bytes": "15F76E82", + "text": "MOV:G.B @H'F76E, R2", + "mnemonic": "MOV:G.B", + "operands": "@H'F76E, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63342, + "name": null, + "symbol": "ram_F76E", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R2 unknown after memory load" + ] + } + }, + { + "address": 21771, + "address_region": "program_or_external", + "bytes": "0C000F52", + "text": "AND.W #H'000F, R2", + "mnemonic": "AND.W", + "operands": "#H'000F, R2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 21767, + "changes": [ + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:AND.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R2" + ] + } + }, + { + "address": 21775, + "address_region": "program_or_external", + "bytes": "AA83", + "text": "MOV:G.W R2, R3", + "mnemonic": "MOV:G.W", + "operands": "R2, R3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + 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"dataflow": { + "block": 22904, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 131, + "hex": "0x0083", + "width": 16, + "source": "MOV:I.W #H'0083, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0083" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 131, + "hex": "0x0083", + "width": 16, + "source": "MOV:I.W #H'0083, R4" + } + } + } + } + }, + { + "address": 22907, + "address_region": "program_or_external", + "bytes": "200D", + "text": "BRA loc_598A", + "mnemonic": "BRA", + "operands": "loc_598A", + "kind": "jump", + "targets": [ + 22922 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22904, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 131, + "hex": "0x0083", + "width": 16, + "source": "MOV:I.W #H'0083, R4" + } + } + } + } + }, + { + "address": 22909, + "address_region": "program_or_external", + "bytes": "5C00C3", + "text": "MOV:I.W #H'00C3, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'00C3, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22909, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 195, + "hex": "0x00C3", + "width": 16, + "source": "MOV:I.W #H'00C3, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x00C3" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 195, + "hex": "0x00C3", + "width": 16, + "source": "MOV:I.W #H'00C3, R4" + } + } + } + } + }, + { + "address": 22912, + "address_region": "program_or_external", + "bytes": "2008", + "text": "BRA loc_598A", + "mnemonic": "BRA", + "operands": "loc_598A", + "kind": "jump", + "targets": [ + 22922 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22909, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 195, + "hex": "0x00C3", + "width": 16, + "source": "MOV:I.W #H'00C3, R4" + } + } + } + } + }, + { + "address": 22914, + "address_region": "program_or_external", + "bytes": "5C0093", + "text": "MOV:I.W #H'0093, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'0093, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22914, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x0093" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + } + } + } + }, + { + "address": 22917, + "address_region": "program_or_external", + "bytes": "2003", + "text": "BRA loc_598A", + "mnemonic": "BRA", + "operands": "loc_598A", + "kind": "jump", + "targets": [ + 22922 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22914, + "changes": [], + "notes": [], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 147, + "hex": "0x0093", + "width": 16, + "source": "MOV:I.W #H'0093, R4" + } + } + } + } + }, + { + "address": 22919, + "address_region": "program_or_external", + "bytes": "5C00D3", + "text": "MOV:I.W #H'00D3, R4", + "mnemonic": "MOV:I.W", + "operands": "#H'00D3, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22919, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 211, + "hex": "0x00D3", + "width": 16, + "source": "MOV:I.W #H'00D3, R4" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 = 0x00D3" + ], + "known_after": { + "registers": { + "R4": { + "known": true, + "value": 211, + "hex": "0x00D3", + "width": 16, + "source": "MOV:I.W #H'00D3, R4" + } + } + } + } + }, + { + "address": 22922, + "address_region": "program_or_external", + "bytes": "15F75B24", + "text": "ADD:G.B @H'F75B, R4", + "mnemonic": "ADD:G.B", + "operands": "@H'F75B, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63323, + "name": null, + "symbol": "ram_F75B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after arithmetic memory source" + ] + } + }, + { + "address": 22926, + "address_region": "program_or_external", + "bytes": "5D0004", + "text": "MOV:I.W #H'0004, R5", + "mnemonic": "MOV:I.W", + "operands": "#H'0004, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + ], + "notes": [ + "R5 = 0x0004" + ], + "known_after": { + "registers": { + "R5": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + } + } + } + } + }, + { + "address": 22929, + "address_region": "program_or_external", + "bytes": "1EE538", + "text": "BSR loc_3ECC", + "mnemonic": "BSR", + "operands": "loc_3ECC", + "kind": "call", + "targets": [ + 16076 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": true, + "value": 4, + "hex": "0x0004", + "width": 16, + "source": "MOV:I.W #H'0004, R5" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 22932, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 22922, + "changes": [], + "notes": [] + } + }, + { + "address": 23044, + "address_region": "program_or_external", + "bytes": "15F713F6", + "text": "BTST.B #6, @H'F713", + "mnemonic": "BTST.B", + "operands": "#6, @H'F713", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63251, + "name": null, + "symbol": "ram_F713", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 23044, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 23048, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_5A0E", + "mnemonic": "BNE", + "operands": "loc_5A0E", + "kind": "branch", + "targets": [ + 23054 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 23044, + "changes": [], + "notes": [] + } + }, + { + "address": 23050, + "address_region": "program_or_external", + "bytes": "15F72613", + "text": "CLR.B @H'F726", + "mnemonic": "CLR.B", + "operands": "@H'F726", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63270, + "name": null, + "symbol": "ram_F726", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 23050, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 23054, + "address_region": "program_or_external", + "bytes": "580007", + "text": "MOV:I.W #H'0007, R0", + "mnemonic": "MOV:I.W", + "operands": "#H'0007, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 23054, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x0007" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 7, + "hex": "0x0007", + "width": 16, + "source": "MOV:I.W #H'0007, R0" + } + } + } + } + }, + { + "address": 23057, + "address_region": "program_or_external", + "bytes": "A80C", + "text": "ADD:Q.W #-1, R0", + "mnemonic": "ADD:Q.W", + "operands": "#-1, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 23057, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after arithmetic" + ] + } + }, + { + "address": 23059, + "address_region": "program_or_external", + "bytes": "F8F73C81", + "text": "MOV:G.W @(-H'08C4,R0), R1", + "mnemonic": "MOV:G.W", + "operands": "@(-H'08C4,R0), R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 23057, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 23063, + "address_region": "program_or_external", + "bytes": "274C", + "text": "BEQ loc_5A65", + "mnemonic": "BEQ", + "operands": "loc_5A65", + "kind": "branch", + "targets": [ + 23141 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": 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+ "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47670, + "address_region": "program_or_external", + "bytes": "1DF85080", + "text": "MOV:G.W @H'F850, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F850, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47674, + "address_region": "program_or_external", + "bytes": "1DF85890", + "text": "MOV:G.W R0, @H'F858", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F858", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47674, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47678, + "address_region": "program_or_external", + "bytes": "1DF85280", + "text": "MOV:G.W @H'F852, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F852, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47682, + "address_region": "program_or_external", + "bytes": "1DF85A90", + "text": "MOV:G.W R0, @H'F85A", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F85A", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47682, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47686, + "address_region": "program_or_external", + "bytes": "15F85480", + "text": "MOV:G.B @H'F854, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F854, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47690, + "address_region": "program_or_external", + "bytes": "15F85C90", + "text": "MOV:G.B R0, @H'F85C", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85C", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47690, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47694, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47694, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_checksum_seed", + "evidence_summary": "candidate TX checksum starts from seed H'005A", + "evidence_addresses": [ + 47694 + ], + "evidence_addresses_hex": [ + "H'BA4E" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 47696, + "address_region": "program_or_external", + "bytes": "15F85860", + "text": "XOR.B @H'F858, R0", + "mnemonic": "XOR.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47696, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47700, + "address_region": "program_or_external", + "bytes": "15F85960", + "text": "XOR.B @H'F859, R0", + "mnemonic": "XOR.B", + "operands": "@H'F859, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63577, + "name": null, + "symbol": "ram_F859", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47700, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47704, + "address_region": "program_or_external", + "bytes": "15F85A60", + "text": "XOR.B @H'F85A, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47704, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47708, + "address_region": "program_or_external", + "bytes": "15F85B60", + "text": "XOR.B @H'F85B, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85B, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63579, + "name": null, + "symbol": "ram_F85B", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47708, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47712, + "address_region": "program_or_external", + "bytes": "15F85C60", + "text": "XOR.B @H'F85C, R0", + "mnemonic": "XOR.B", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47712, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47716, + "address_region": "program_or_external", + "bytes": "15F85D90", + "text": "MOV:G.B R0, @H'F85D", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F85D", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63581, + "name": null, + "symbol": "ram_F85D", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "checksum_byte", + "evidence_summary": "candidate checksum byte write targets H'F85D", + "evidence_addresses": [ + 47716 + ], + "evidence_addresses_hex": [ + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high" + }, + { + "address": 47716, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "xor_checksum_chain", + "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte", + "evidence_addresses": [ + 47696, + 47700, + 47704, + 47708, + 47712, + 47716 + ], + "evidence_addresses_hex": [ + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high" + } + ], + "dataflow": { + "block": 47660, + "changes": [], + "notes": [] + } + }, + { + "address": 47720, + "address_region": "program_or_external", + "bytes": "15FEDCF7", + "text": "BTST.B #7, @SCI1_SSR", + "mnemonic": "BTST.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "action": "wait_for_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "wait for SCI1 transmit data register empty (TDRE=1)", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "branch_address": 47724, + "branch_target": 47720 + } + ], + "board_profile": { + "accesses": [ + { + "address": 47720, + "instruction": "BTST.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47720, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47724, + "address_region": "program_or_external", + "bytes": "27FA", + "text": "BEQ loc_BA68", + "mnemonic": "BEQ", + "operands": "loc_BA68", + "kind": "branch", + "targets": [ + 47720 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47724, + "instruction": "BEQ loc_BA68", + "action": "tdre_wait_branch", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "repeat SCI1 transmit-empty wait while TDRE=0", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "test_address": 47720, + "branch_target": 47720 + } + ], + "dataflow": { + "block": 47720, + "changes": [], + "notes": [] + } + }, + { + "address": 47726, + "address_region": "program_or_external", + "bytes": "15F85880", + "text": "MOV:G.B @H'F858, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + }, + { + "address": 47726, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47730, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47730, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "initial_send_from_buffer_start", + "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858", + "evidence_addresses": [ + 47726, + 47730 + ], + "evidence_addresses_hex": [ + "H'BA6E", + "H'BA72" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47730, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47734, + "address_region": "program_or_external", + "bytes": "15F9C20601", + "text": "MOV:G.B #H'01, @H'F9C2", + "mnemonic": "MOV:G.B", + "operands": "#H'01, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47734, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_initialized_to_one", + "evidence_summary": "write evidence supports TX index H'F9C2 being initialized to 1", + "evidence_addresses": [ + 47734 + ], + "evidence_addresses_hex": [ + "H'BA76" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high" + } + ], + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47739, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47739, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47743, + "address_region": "program_or_external", + "bytes": "15FEDAC7", + "text": "BSET.B #7, @SCI1_SCR", + "mnemonic": "BSET.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BSET", + "value": 252, + "value_hex": "H'FC" + } + ] + }, + "sci_protocol": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "action": "enable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": true, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47743, + "instruction": "BSET.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 252, + "value_hex": "H'FC", + "scr": { + "value": 252, + "value_hex": "H'FC", + "tie": true, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47747, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47726, + "changes": [], + "notes": [] + } + }, + { + "address": 47748, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47752, + "address_region": "program_or_external", + "bytes": "271F", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47748, + "changes": [], + "notes": [] + } + }, + { + "address": 47754, + "address_region": "program_or_external", + "bytes": "15FAA5F7", + "text": "BTST.B #7, @H'FAA5", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64165, + "name": null, + "symbol": "ram_FAA5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47758, + "address_region": "program_or_external", + "bytes": "2719", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47754, + "changes": [], + "notes": [] + } + }, + { + "address": 47760, + "address_region": "program_or_external", + "bytes": "15F9C316", + "text": "TST.B @H'F9C3", + "mnemonic": "TST.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47764, + "address_region": "program_or_external", + "bytes": "2713", + "text": "BEQ loc_BAA9", + "mnemonic": "BEQ", + "operands": "loc_BAA9", + "kind": "branch", + "targets": [ + 47785 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47760, + "changes": [], + "notes": [] + } + }, + { + "address": 47766, + "address_region": "program_or_external", + "bytes": "15FAA2D3", + "text": "BCLR.B #3, @H'FAA2", + "mnemonic": "BCLR.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47770, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47774, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47774, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47778, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47783, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BAF1", + "mnemonic": "BRA", + "operands": "loc_BAF1", + "kind": "jump", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47766, + "changes": [], + "notes": [] + } + }, + { + "address": 47785, + "address_region": "program_or_external", + "bytes": "BF90", + "text": "MOV:G.W R0, @-R7", + "mnemonic": "MOV:G.W", + "operands": "R0, @-R7", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 5, + "base_cycles": 5, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "addressing_side_effect" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47787, + "address_region": "program_or_external", + "bytes": "15F9C280", + "text": "MOV:G.B @H'F9C2, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C2, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47787, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47791, + "address_region": "program_or_external", + "bytes": "A012", + "text": "EXTU.B R0", + "mnemonic": "EXTU.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47793, + "address_region": "program_or_external", + "bytes": "F0F85880", + "text": "MOV:G.B @(-H'07A8,R0), R0", + "mnemonic": "MOV:G.B", + "operands": "@(-H'07A8,R0), R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47793, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47797, + "address_region": "program_or_external", + "bytes": "15FEDB90", + "text": "MOV:G.B R0, @SCI1_TDR", + "mnemonic": "MOV:G.B", + "operands": "R0, @SCI1_TDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65243, + "name": "SCI1_TDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "SCI1_TDR", + "valid": true, + "sci_protocol": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "action": "write_tdr", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "register_address_hex": "H'FEDB", + "comment": "write RS232/SCI byte to SCI1 TDR for transmission", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47797, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_isr_indexed_send", + "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer", + "evidence_addresses": [ + 47787, + 47793, + 47797 + ], + "evidence_addresses_hex": [ + "H'BAAB", + "H'BAB1", + "H'BAB5" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47797, + "instruction": "MOV:G.B R0, @SCI1_TDR", + "channel": "SCI1", + "register": "TDR", + "register_address": 65243, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + } + ], + "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47801, + "address_region": "program_or_external", + "bytes": "CF80", + "text": "MOV:G.W @R7+, R0", + "mnemonic": "MOV:G.W", + "operands": "@R7+, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 5, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47803, + "address_region": "program_or_external", + "bytes": "15FEDCD7", + "text": "BCLR.B #7, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TDRE (bit 7) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "action": "clear_tdre", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "flag": "TDRE", + "description": "transmit data register empty" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47803, + "instruction": "BCLR.B #7, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47807, + "address_region": "program_or_external", + "bytes": "15F9C208", + "text": "ADD:Q.B #1, @H'F9C2", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47807, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_increment", + "evidence_summary": "candidate TX ISR increments TX index H'F9C2", + "evidence_addresses": [ + 47807 + ], + "evidence_addresses_hex": [ + "H'BABF" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47811, + "address_region": "program_or_external", + "bytes": "15F9C20406", + "text": "CMP:G.B #H'06, @H'F9C2", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63938, + "name": null, + "symbol": "ram_F9C2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47811, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_index_compare_frame_length", + "evidence_summary": "candidate TX ISR compares TX index to frame length 6", + "evidence_addresses": [ + 47811 + ], + "evidence_addresses_hex": [ + "H'BAC3" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high" + } + ], + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47816, + "address_region": "program_or_external", + "bytes": "2627", + "text": "BNE loc_BAF1", + "mnemonic": "BNE", + "operands": "loc_BAF1", + "kind": "branch", + "targets": [ + 47857 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47785, + "changes": [], + "notes": [] + } + }, + { + "address": 47818, + "address_region": "program_or_external", + "bytes": "15FEDAD7", + "text": "BCLR.B #7, @SCI1_SCR", + "mnemonic": "BCLR.B", + "operands": "#7, @SCI1_SCR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65242, + "name": "SCI1_SCR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear TIE (bit 7) of SCI1_SCR", + "valid": true, + "sci": { + "writes": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "operation": "BCLR", + "value": 124, + "value_hex": "H'7C" + } + ] + }, + "sci_protocol": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "action": "disable_tx_interrupt", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "register_address_hex": "H'FEDA", + "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 7, + "bit_name": "TIE", + "enabled": false, + "interrupt_source": "TXI" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47818, + "instruction": "BCLR.B #7, @SCI1_SCR", + "channel": "SCI1", + "register": "SCR", + "register_address": 65242, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)", + "value": 124, + "value_hex": "H'7C", + "scr": { + "value": 124, + "value_hex": "H'7C", + "tie": false, + "rie": true, + "tx_enabled": true, + "rx_enabled": true + } + } + ], + "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)" + }, + "dataflow": { + "block": 47818, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47822, + "address_region": "program_or_external", + "bytes": "15F795F6", + "text": "BTST.B #6, @H'F795", + "mnemonic": "BTST.B", + "operands": "#6, @H'F795", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63381, + "name": null, + "symbol": "ram_F795", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47826, + "address_region": "program_or_external", + "bytes": "2614", + "text": "BNE loc_BAE8", + "mnemonic": "BNE", + "operands": "loc_BAE8", + "kind": "branch", + "targets": [ + 47848 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47818, + "changes": [], + "notes": [] + } + }, + { + "address": 47828, + "address_region": "program_or_external", + "bytes": "15F791F7", + "text": "BTST.B #7, @H'F791", + "mnemonic": "BTST.B", + "operands": "#7, @H'F791", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63377, + "name": null, + "symbol": "ram_F791", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47832, + "address_region": "program_or_external", + "bytes": "2607", + "text": "BNE loc_BAE1", + "mnemonic": "BNE", + "operands": "loc_BAE1", + "kind": "branch", + "targets": [ + 47841 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47828, + "changes": [], + "notes": [] + } + }, + { + "address": 47834, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47839, + "address_region": "program_or_external", + "bytes": "200C", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47834, + "changes": [], + "notes": [] + } + }, + { + "address": 47841, + "address_region": "program_or_external", + "bytes": "15F9C00609", + "text": "MOV:G.B #H'09, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'09, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47846, + "address_region": "program_or_external", + "bytes": "2005", + "text": "BRA loc_BAED", + "mnemonic": "BRA", + "operands": "loc_BAED", + "kind": "jump", + "targets": [ + 47853 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47841, + "changes": [], + "notes": [] + } + }, + { + "address": 47848, + "address_region": "program_or_external", + "bytes": "15F9C006F0", + "text": "MOV:G.B #H'F0, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'F0, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47848, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47853, + "address_region": "program_or_external", + "bytes": "15F9C113", + "text": "CLR.B @H'F9C1", + "mnemonic": "CLR.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47853, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47857, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47857, + "changes": [], + "notes": [] + } + }, + { + "address": 47858, + "address_region": "program_or_external", + "bytes": "15F9B581", + "text": "MOV:G.B @H'F9B5, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9B5, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 47862, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47858, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + 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"before": { + "known": false, + "reason": "unsupported:AND.W" + }, + "after": { + "known": false, + "reason": "unsupported:SHLL.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 47925, + "address_region": "program_or_external", + "bytes": "F8E80084", + "text": "MOV:G.W @(-H'1800,R0), R4", + "mnemonic": "MOV:G.W", + "operands": "@(-H'1800,R0), R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R4 unknown after memory load" + ] + } + }, + { + "address": 47929, + "address_region": "program_or_external", + "bytes": "15F85494", + "text": "MOV:G.B R4, @H'F854", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47933, + "address_region": "program_or_external", + "bytes": "A410", + "text": "SWAP.B R4", + "mnemonic": "SWAP.B", + "operands": "R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R4" + ] + } + }, + { + "address": 47935, + "address_region": "program_or_external", + "bytes": "15F85394", + "text": "MOV:G.B R4, @H'F853", + "mnemonic": "MOV:G.B", + "operands": "R4, @H'F853", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63571, + "name": null, + "symbol": "ram_F853", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47939, + "address_region": "program_or_external", + "bytes": "1EFEE0", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SHLL.W" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "unsupported:AND.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:OR.B" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 47942, + "address_region": "program_or_external", + "bytes": "1DF9C60701F4", + "text": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "operands": "#H'01F4, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47948, + "address_region": "program_or_external", + "bytes": "15F9C80614", + "text": "MOV:G.B #H'14, @H'F9C8", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47953, + "address_region": "program_or_external", + "bytes": "15FAA30680", + "text": "MOV:G.B #H'80, @H'FAA3", + "mnemonic": "MOV:G.B", + "operands": "#H'80, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47872, + "changes": [], + "notes": [] + } + }, + { + "address": 47958, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47958, + "changes": [], + "notes": [] + } + }, + { + "address": 47959, + "address_region": "program_or_external", + "bytes": "15FAA4C7", + "text": "BSET.B #7, @H'FAA4", + "mnemonic": "BSET.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 47959, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "dataflow": { + "block": 47959, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47963, + "address_region": "program_or_external", + "bytes": "15FEDCD5", + "text": "BCLR.B #5, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#5, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear ORER (bit 5) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "action": "clear_orer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 5, + "flag": "ORER", + "description": "overrun error" + } + ], + "serial_reconstruction": [ + { + "address": 47963, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47963, + "instruction": "BCLR.B #5, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47967, + "address_region": "program_or_external", + "bytes": "15FEDCD4", + "text": "BCLR.B #4, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#4, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear FER (bit 4) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "action": "clear_fer", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 4, + "flag": "FER", + "description": "framing error" + } + ], + "serial_reconstruction": [ + { + "address": 47967, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47967, + "instruction": "BCLR.B #4, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47971, + "address_region": "program_or_external", + "bytes": "15FEDCD3", + "text": "BCLR.B #3, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#3, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear PER (bit 3) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "action": "clear_per", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 3, + "flag": "PER", + "description": "parity error" + } + ], + "serial_reconstruction": [ + { + "address": 47971, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47971, + "instruction": "BCLR.B #3, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47959, + "changes": [], + "notes": [] + } + }, + { + "address": 47975, + "address_region": "program_or_external", + "bytes": "1203", + "text": "STM.W {R0,R1}, @-SP", + "mnemonic": "STM.W", + "operands": "{R0,R1}, @-SP", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 12, + "note": "6+3n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47977, + "address_region": "program_or_external", + "bytes": "15FEDCD6", + "text": "BCLR.B #6, @SCI1_SSR", + "mnemonic": "BCLR.B", + "operands": "#6, @SCI1_SSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65244, + "name": "SCI1_SSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear RDRF (bit 6) of SCI1_SSR", + "valid": true, + "sci_protocol": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "action": "clear_rdrf", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "register_address_hex": "H'FEDC", + "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ], + "bit": 6, + "flag": "RDRF", + "description": "receive-data-full" + } + ], + "serial_reconstruction": [ + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47977, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47977, + "instruction": "BCLR.B #6, @SCI1_SSR", + "channel": "SCI1", + "register": "SSR", + "register_address": 65244, + "access": "write", + "traced_to_max202": true, + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + } + ], + "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47981, + "address_region": "program_or_external", + "bytes": "15FEDD80", + "text": "MOV:G.B @SCI1_RDR, R0", + "mnemonic": "MOV:G.B", + "operands": "@SCI1_RDR, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65245, + "name": "SCI1_RDR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "sci_protocol": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "action": "read_rdr", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "register_address_hex": "H'FEDD", + "comment": "read SCI1 received byte from RDR", + "manual": [ + "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR", + "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable", + "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit", + "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE", + "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI", + "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter", + "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver", + "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero", + "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte", + "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR", + "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun", + "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors", + "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors" + ] + } + ], + "serial_reconstruction": [ + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdr_read", + "evidence_summary": "SCI1 RX ISR reads a byte from SCI1_RDR", + "evidence_addresses": [ + 47981 + ], + "evidence_addresses_hex": [ + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_rdrf_clear_before_rdr_read", + "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence", + "evidence_addresses": [ + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high" + }, + { + "address": 47981, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_eri_falls_through_to_rxi", + "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path", + "evidence_addresses": [ + 47959, + 47963, + 47967, + 47971, + 47977, + 47981 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB5B", + "H'BB5F", + "H'BB63", + "H'BB69", + "H'BB6D" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high" + } + ], + "board_profile": { + "accesses": [ + { + "address": 47981, + "instruction": "MOV:G.B @SCI1_RDR, R0", + "channel": "SCI1", + "register": "RDR", + "register_address": 65245, + "access": "read", + "traced_to_max202": true, + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + } + ], + "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD" + }, + "dataflow": { + "block": 47975, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 47985, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47989, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BB7D", + "mnemonic": "BNE", + "operands": "loc_BB7D", + "kind": "branch", + "targets": [ + 47997 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47975, + "changes": [], + "notes": [] + } + }, + { + "address": 47991, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 47995, + "address_region": "program_or_external", + "bytes": "200D", + "text": "BRA loc_BB8A", + "mnemonic": "BRA", + "operands": "loc_BB8A", + "kind": "jump", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47991, + "changes": [], + "notes": [] + } + }, + { + "address": 47997, + "address_region": "program_or_external", + "bytes": "15F9C30405", + "text": "CMP:G.B #H'05, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'05, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48002, + "address_region": "program_or_external", + "bytes": "2306", + "text": "BLS loc_BB8A", + "mnemonic": "BLS", + "operands": "loc_BB8A", + "kind": "branch", + "targets": [ + 48010 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 47997, + "changes": [], + "notes": [] + } + }, + { + "address": 48004, + "address_region": "program_or_external", + "bytes": "15FAA413", + "text": "CLR.B @H'FAA4", + "mnemonic": "CLR.B", + "operands": "@H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48008, + "address_region": "program_or_external", + "bytes": "2019", + "text": "BRA loc_BBA3", + "mnemonic": "BRA", + "operands": "loc_BBA3", + "kind": "jump", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48004, + "changes": [], + "notes": [] + } + }, + { + "address": 48010, + "address_region": "program_or_external", + "bytes": "15F9C381", + "text": "MOV:G.B @H'F9C3, R1", + "mnemonic": "MOV:G.B", + "operands": "@H'F9C3, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R1 unknown after memory load" + ] + } + }, + { + "address": 48014, + "address_region": "program_or_external", + "bytes": "A112", + "text": "EXTU.B R1", + "mnemonic": "EXTU.B", + "operands": "R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:EXTU.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R1" + ] + } + }, + { + "address": 48016, + "address_region": "program_or_external", + "bytes": "F1F86890", + "text": "MOV:G.B R0, @(-H'0798,R1)", + "mnemonic": "MOV:G.B", + "operands": "R0, @(-H'0798,R1)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48016, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_indexed_store", + "evidence_summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D", + "evidence_addresses": [ + 48016 + ], + "evidence_addresses_hex": [ + "H'BB90" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48020, + "address_region": "program_or_external", + "bytes": "A108", + "text": "ADD:Q.B #1, R1", + "mnemonic": "ADD:Q.B", + "operands": "#1, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 4, + "base_cycles": 4, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48020, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [ + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "unsupported:EXTU.B" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + } + ], + "notes": [ + "R1 unknown after arithmetic" + ] + } + }, + { + "address": 48022, + "address_region": "program_or_external", + "bytes": "15F9C391", + "text": "MOV:G.B R1, @H'F9C3", + "mnemonic": "MOV:G.B", + "operands": "R1, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48022, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_index_increment_store", + "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3", + "evidence_addresses": [ + 48020, + 48022 + ], + "evidence_addresses_hex": [ + "H'BB94", + "H'BB96" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48026, + "address_region": "program_or_external", + "bytes": "4106", + "text": "CMP:E #H'06, R1", + "mnemonic": "CMP:E", + "operands": "#H'06, R1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48026, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_isr_compare_frame_length", + "evidence_summary": "RX ISR compares incremented count to candidate frame length 6", + "evidence_addresses": [ + 48026 + ], + "evidence_addresses_hex": [ + "H'BB9A" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high" + } + ], + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48028, + "address_region": "program_or_external", + "bytes": "2605", + "text": "BNE loc_BBA3", + "mnemonic": "BNE", + "operands": "loc_BBA3", + "kind": "branch", + "targets": [ + 48035 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48010, + "changes": [], + "notes": [] + } + }, + { + "address": 48030, + "address_region": "program_or_external", + "bytes": "15F9C50614", + "text": "MOV:G.B #H'14, @H'F9C5", + "mnemonic": "MOV:G.B", + "operands": "#H'14, @H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48030, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_complete_timer", + "evidence_summary": "RX ISR sets H'F9C5 after count reaches 6", + "evidence_addresses": [ + 48030 + ], + "evidence_addresses_hex": [ + "H'BB9E" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high" + } + ], + "dataflow": { + "block": 48030, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48035, + "address_region": "program_or_external", + "bytes": "15F9C10605", + "text": "MOV:G.B #H'05, @H'F9C1", + "mnemonic": "MOV:G.B", + "operands": "#H'05, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48040, + "address_region": "program_or_external", + "bytes": "0203", + "text": "LDM.W @SP+, {R0,R1}", + "mnemonic": "LDM.W", + "operands": "@SP+, {R0,R1}", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 14, + "note": "6+4n, n=2", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:LDM.W" + } + } + ], + "notes": [ + "unsupported operation invalidated R0, R1" + ] + } + }, + { + "address": 48042, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 13, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48035, + "changes": [], + "notes": [] + } + }, + { + "address": 48043, + "address_region": "program_or_external", + "bytes": "15F9C30406", + "text": "CMP:G.B #H'06, @H'F9C3", + "mnemonic": "CMP:G.B", + "operands": "#H'06, @H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48043, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_processor_requires_six_bytes", + "evidence_summary": "RX processing path requires H'F9C3 to equal 6", + "evidence_addresses": [ + 48043 + ], + "evidence_addresses_hex": [ + "H'BBAB" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high" + } + ], + "dataflow": { + "block": 48043, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48048, + "address_region": "program_or_external", + "bytes": "3602BC", + "text": "BNE loc_BE6F", + "mnemonic": "BNE", + "operands": "loc_BE6F", + "kind": "branch", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48043, + "changes": [], + "notes": [] + } + }, + { + "address": 48051, + "address_region": "program_or_external", + "bytes": "1DF86880", + "text": "MOV:G.W @H'F868, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F868, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63592, + "name": null, + "symbol": "ram_F868", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48051, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48055, + "address_region": "program_or_external", + "bytes": "1DF86090", + "text": "MOV:G.W R0, @H'F860", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F860", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48055, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48059, + "address_region": "program_or_external", + "bytes": "1DF86A80", + "text": "MOV:G.W @H'F86A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63594, + "name": null, + "symbol": "ram_F86A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48059, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48063, + "address_region": "program_or_external", + "bytes": "1DF86290", + "text": "MOV:G.W R0, @H'F862", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F862", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48063, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48067, + "address_region": "program_or_external", + "bytes": "1DF86C80", + "text": "MOV:G.W @H'F86C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F86C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63596, + "name": null, + "symbol": "ram_F86C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48067, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48071, + "address_region": "program_or_external", + "bytes": "1DF86490", + "text": "MOV:G.W R0, @H'F864", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F864", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48071, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_copy_capture_to_frame_buffer", + "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865", + "evidence_addresses": [ + 48051, + 48059, + 48067, + 48055, + 48063, + 48071 + ], + "evidence_addresses_hex": [ + "H'BBB3", + "H'BBBB", + "H'BBC3", + "H'BBB7", + "H'BBBF", + "H'BBC7" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high" + } + ], + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48075, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48079, + "address_region": "program_or_external", + "bytes": "15FAA4F7", + "text": "BTST.B #7, @H'FAA4", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48083, + "address_region": "program_or_external", + "bytes": "360253", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48051, + "changes": [], + "notes": [] + } + }, + { + "address": 48086, + "address_region": "program_or_external", + "bytes": "505A", + "text": "MOV:E.B #H'5A, R0", + "mnemonic": "MOV:E.B", + "operands": "#H'5A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_checksum_seed", + "evidence_summary": "candidate RX checksum validation starts from seed H'005A", + "evidence_addresses": [ + 48086 + ], + "evidence_addresses_hex": [ + "H'BBD6" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high" + }, + { + "address": 48086, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 = 0x5A" + ], + "known_after": { + "registers": { + "R0": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + } + } + } + } + }, + { + "address": 48088, + "address_region": "program_or_external", + "bytes": "15F86060", + "text": "XOR.B @H'F860, R0", + "mnemonic": "XOR.B", + "operands": "@H'F860, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63584, + "name": null, + "symbol": "ram_F860", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48088, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": true, + "value": 90, + "hex": "0x5A", + "width": 8, + "source": "MOV:E.B #H'5A, R0" + }, + "after": { + "known": false, + "reason": "unsupported:XOR.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48092, + "address_region": "program_or_external", + "bytes": "15F86160", + "text": "XOR.B @H'F861, R0", + "mnemonic": "XOR.B", + "operands": "@H'F861, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48092, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48096, + "address_region": "program_or_external", + "bytes": "15F86260", + "text": "XOR.B @H'F862, R0", + "mnemonic": "XOR.B", + "operands": "@H'F862, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48096, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48100, + "address_region": "program_or_external", + "bytes": "15F86360", + "text": "XOR.B @H'F863, R0", + "mnemonic": "XOR.B", + "operands": "@H'F863, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63587, + "name": null, + "symbol": "ram_F863", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48100, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48104, + "address_region": "program_or_external", + "bytes": "15F86460", + "text": "XOR.B @H'F864, R0", + "mnemonic": "XOR.B", + "operands": "@H'F864, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48104, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48108, + "address_region": "program_or_external", + "bytes": "15F86570", + "text": "CMP:G.B @H'F865, R0", + "mnemonic": "CMP:G.B", + "operands": "@H'F865, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63589, + "name": null, + "symbol": "ram_F865", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48108, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_rx_frame_f868_len6_candidate", + "candidate_kind": "candidate_sci1_rx_frame", + "evidence": "rx_xor_checksum_validation", + "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865", + "evidence_addresses": [ + 48086, + 48088, + 48092, + 48096, + 48100, + 48104, + 48108 + ], + "evidence_addresses_hex": [ + "H'BBD6", + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC" + ], + "confidence": "high", + "confidence_score": 0.9, + "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high" + } + ], + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48112, + "address_region": "program_or_external", + "bytes": "360236", + "text": "BNE loc_BE29", + "mnemonic": "BNE", + "operands": "loc_BE29", + "kind": "branch", + "targets": [ + 48681 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48086, + "changes": [], + "notes": [] + } + }, + { + "address": 48115, + "address_region": "program_or_external", + "bytes": "15FAA613", + "text": "CLR.B @H'FAA6", + "mnemonic": "CLR.B", + "operands": "@H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48119, + "address_region": "program_or_external", + "bytes": "15F86185", + "text": "MOV:G.B @H'F861, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F861, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48123, + "address_region": "program_or_external", + "bytes": "A510", + "text": "SWAP.B R5", + "mnemonic": "SWAP.B", + "operands": "R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 48125, + "address_region": "program_or_external", + "bytes": "15F86285", + "text": "MOV:G.B @H'F862, R5", + "mnemonic": "MOV:G.B", + "operands": "@H'F862, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R5 unknown after memory load" + ] + } + }, + { + "address": 48129, + "address_region": "program_or_external", + "bytes": "1EA627", + "text": "BSR loc_622B", + "mnemonic": "BSR", + "operands": "loc_622B", + "kind": "call", + "targets": [ + 25131 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48132, + "address_region": "program_or_external", + "bytes": "AD84", + "text": "MOV:G.W R5, R4", + "mnemonic": "MOV:G.W", + "operands": "R5, R4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48115, + "changes": [ + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "unknown_operand" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "call" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R4 unknown after MOV source" + ] + } + }, + { + "address": 48134, + "address_region": "program_or_external", + "bytes": "AC1A", + "text": "SHLL.W R4", + "mnemonic": "SHLL.W", + "operands": "R4", + "kind": "normal", + "targets": [], + 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+ "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48578, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48582, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_BDD0", + "mnemonic": "BEQ", + "operands": "loc_BDD0", + "kind": "branch", + "targets": [ + 48592 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48578, + "changes": [], + "notes": [] + } + }, + { + "address": 48584, + "address_region": "program_or_external", + "bytes": "15F9B508", + "text": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48584, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48588, + "address_region": "program_or_external", + "bytes": "15F9B5D7", + "text": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48584, + "changes": [], + "notes": [] + } + }, + { + "address": 48592, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48592, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48596, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48592, + "changes": [], + "notes": [] + } + }, + { + "address": 48600, + "address_region": "program_or_external", + "bytes": "300094", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48592, + "changes": [], + "notes": [] + } + }, + { + "address": 48603, + "address_region": "program_or_external", + "bytes": "15F86380", + "text": "MOV:G.B @H'F863, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F863, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63587, + "name": null, + "symbol": "ram_F863", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48607, + "address_region": "program_or_external", + "bytes": "A010", + "text": "SWAP.B R0", + "mnemonic": "SWAP.B", + "operands": "R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 3, + "base_cycles": 3, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "unsupported:SWAP.B" + } + } + ], + "notes": [ + "unsupported operation invalidated R0" + ] + } + }, + { + "address": 48609, + "address_region": "program_or_external", + "bytes": "15F86480", + "text": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F864, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63588, + "name": null, + "symbol": "ram_F864", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "unsupported:SWAP.B" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48613, + "address_region": "program_or_external", + "bytes": "FCE40090", + "text": "MOV:G.W R0, @(-H'1C00,R4)", + "mnemonic": "MOV:G.W", + "operands": "R0, @(-H'1C00,R4)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48617, + "address_region": "program_or_external", + "bytes": "F5EC00C6", + "text": "BSET.B #6, @(-H'1400,R5)", + "mnemonic": "BSET.B", + "operands": "#6, @(-H'1400,R5)", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48621, + "address_region": "program_or_external", + "bytes": "15FAA2F3", + "text": "BTST.B #3, @H'FAA2", + "mnemonic": "BTST.B", + "operands": "#3, @H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48625, + "address_region": "program_or_external", + "bytes": "2708", + "text": "BEQ loc_BDFB", + "mnemonic": "BEQ", + "operands": "loc_BDFB", + "kind": "branch", + "targets": [ + 48635 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48603, + "changes": [], + "notes": [] + } + }, + { + "address": 48627, + "address_region": "program_or_external", + "bytes": "15F9B508", + "text": "ADD:Q.B #1, @H'F9B5", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48631, + "address_region": "program_or_external", + "bytes": "15F9B5D7", + "text": "BCLR.B #7, @H'F9B5", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F9B5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63925, + "name": null, + "symbol": "ram_F9B5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48627, + "changes": [], + "notes": [] + } + }, + { + "address": 48635, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48639, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64162, + "name": null, + "symbol": "ram_FAA2", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48643, + "address_region": "program_or_external", + "bytes": "206A", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48635, + "changes": [], + "notes": [] + } + }, + { + "address": 48645, + "address_region": "program_or_external", + "bytes": "1DF85880", + "text": "MOV:G.W @H'F858, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F858, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63576, + "name": null, + "symbol": "ram_F858", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48645, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48649, + "address_region": "program_or_external", + "bytes": "1DF85090", + "text": "MOV:G.W R0, @H'F850", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48653, + "address_region": "program_or_external", + "bytes": "1DF85A80", + "text": "MOV:G.W @H'F85A, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85A, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63578, + "name": null, + "symbol": "ram_F85A", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48653, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48657, + "address_region": "program_or_external", + "bytes": "1DF85290", + "text": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48661, + "address_region": "program_or_external", + "bytes": "1DF85C80", + "text": "MOV:G.W @H'F85C, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F85C, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63580, + "name": null, + "symbol": "ram_F85C", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48661, + "action": "serial_reconstruction_evidence", + "candidate_id": "sci1_tx_frame_f858_len6_candidate", + "candidate_kind": "candidate_sci1_tx_frame", + "evidence": "tx_buffer_region", + "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 48645, + 48653, + 48661 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BE05", + "H'BE0D", + "H'BE15" + ], + "confidence": "high", + "confidence_score": 0.95, + "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high" + } + ], + "dataflow": { + "block": 48645, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48665, + "address_region": "program_or_external", + "bytes": "1DF85490", + "text": "MOV:G.W R0, @H'F854", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F854", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63572, + "name": null, + "symbol": "ram_F854", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48669, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48674, + "address_region": "program_or_external", + "bytes": "1EFC01", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 13, + "base_cycles": 9, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "memory_load" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48677, + "address_region": "program_or_external", + "bytes": "2048", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48645, + "changes": [], + "notes": [] + } + }, + { + "address": 48679, + "address_region": "program_or_external", + "bytes": "2046", + "text": "BRA loc_BE6F", + "mnemonic": "BRA", + "operands": "loc_BE6F", + "kind": "jump", + "targets": [ + 48751 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48679, + "changes": [], + "notes": [] + } + }, + { + "address": 48681, + "address_region": "program_or_external", + "bytes": "15FAA4D7", + "text": "BCLR.B #7, @H'FAA4", + "mnemonic": "BCLR.B", + "operands": "#7, @H'FAA4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64164, + "name": null, + "symbol": "ram_FAA4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48685, + "address_region": "program_or_external", + "bytes": "15FAA5F7", + "text": "BTST.B #7, @H'FAA5", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64165, + "name": null, + "symbol": "ram_FAA5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [], + "notes": [] + } + }, + { + "address": 48689, + "address_region": "program_or_external", + "bytes": "273A", + "text": "BEQ loc_BE6D", + "mnemonic": "BEQ", + "operands": "loc_BE6D", + "kind": "branch", + "targets": [ + 48749 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48681, + "changes": [], + "notes": [] + } + }, + { + "address": 48691, + "address_region": "program_or_external", + "bytes": "15FAA608", + "text": "ADD:Q.B #1, @H'FAA6", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48691, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48695, + "address_region": "program_or_external", + "bytes": "15FAA60402", + "text": "CMP:G.B #H'02, @H'FAA6", + "mnemonic": "CMP:G.B", + "operands": "#H'02, @H'FAA6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64166, + "name": null, + "symbol": "ram_FAA6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48691, + "changes": [], + "notes": [] + } + }, + { + "address": 48700, + "address_region": "program_or_external", + "bytes": "250F", + "text": "BCS loc_BE4D", + "mnemonic": "BCS", + "operands": "loc_BE4D", + "kind": "branch", + "targets": [ + 48717 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48691, + "changes": [], + "notes": [] + } + }, + { + "address": 48702, + "address_region": "program_or_external", + "bytes": "15F9C0061F", + "text": "MOV:G.B #H'1F, @H'F9C0", + "mnemonic": "MOV:G.B", + "operands": "#H'1F, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48702, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48707, + "address_region": "program_or_external", + "bytes": "15FAA313", + "text": "CLR.B @H'FAA3", + "mnemonic": "CLR.B", + "operands": "@H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48702, + "changes": [], + "notes": [] + } + }, + { + "address": 48711, + "address_region": "program_or_external", + "bytes": "15FAA213", + "text": "CLR.B @H'FAA2", + "mnemonic": "CLR.B", + "operands": "@H'FAA2", + "kind": "normal", + "targets": [], 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"notes": [] + } + }, + { + "address": 48717, + "address_region": "program_or_external", + "bytes": "15F8500607", + "text": "MOV:G.B #H'07, @H'F850", + "mnemonic": "MOV:G.B", + "operands": "#H'07, @H'F850", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63568, + "name": null, + "symbol": "ram_F850", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48722, + "address_region": "program_or_external", + "bytes": "15F86180", + "text": "MOV:G.B @H'F861, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F861, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63585, + "name": null, + "symbol": "ram_F861", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "memory_load" + } + } + ], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48726, + "address_region": "program_or_external", + "bytes": "15F85190", + "text": "MOV:G.B R0, @H'F851", + "mnemonic": "MOV:G.B", + "operands": "R0, @H'F851", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63569, + "name": null, + "symbol": "ram_F851", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [], + "notes": [] + } + }, + { + "address": 48730, + "address_region": "program_or_external", + "bytes": "1DF86280", + "text": "MOV:G.W @H'F862, R0", + "mnemonic": "MOV:G.W", + "operands": "@H'F862, R0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63586, + "name": null, + "symbol": "ram_F862", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [], + "notes": [ + "R0 unknown after memory load" + ] + } + }, + { + "address": 48734, + "address_region": "program_or_external", + "bytes": "1DF85290", + "text": "MOV:G.W R0, @H'F852", + "mnemonic": "MOV:G.W", + "operands": "R0, @H'F852", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63570, + "name": null, + "symbol": "ram_F852", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48717, + "changes": [], + "notes": [] + } + }, + { + "address": 48738, + "address_region": "program_or_external", + "bytes": "15F86480", + "text": "MOV:G.B @H'F864, R0", + "mnemonic": "MOV:G.B", + "operands": "@H'F864, R0", + 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"reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48819, + "address_region": "program_or_external", + "bytes": "2033", + "text": "BRA loc_BEE8", + "mnemonic": "BRA", + "operands": "loc_BEE8", + "kind": "jump", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48815, + "changes": [], + "notes": [] + } + }, + { + "address": 48821, + "address_region": "program_or_external", + "bytes": "1DF9C616", + "text": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "operands": "@H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48821, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48825, + "address_region": "program_or_external", + "bytes": "262D", + "text": "BNE loc_BEE8", + "mnemonic": "BNE", + "operands": "loc_BEE8", + "kind": "branch", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48821, + "changes": [], + "notes": [] + } + }, + { + "address": 48827, + "address_region": "program_or_external", + "bytes": "15F9C816", + "text": "TST.B @H'F9C8", + "mnemonic": "TST.B", + "operands": "@H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48827, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48831, + "address_region": "program_or_external", + "bytes": "2723", + "text": "BEQ loc_BEE4", + "mnemonic": "BEQ", + "operands": "loc_BEE4", + "kind": "branch", + "targets": [ + 48868 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48827, + "changes": [], + "notes": [] + } + }, + { + "address": 48833, + "address_region": "program_or_external", + "bytes": "15F9C80C", + "text": "ADD:Q.B #-1, @H'F9C8", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C8", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63944, + "name": null, + "symbol": "ram_F9C8", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48837, + "address_region": "program_or_external", + "bytes": "1DF9C60701F4", + "text": "MOV:G.W #H'01F4, @H'F9C6", + "mnemonic": "MOV:G.W", + "operands": "#H'01F4, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [], + "notes": [] + } + }, + { + "address": 48843, + "address_region": "program_or_external", + "bytes": "15FAA3F7", + "text": "BTST.B #7, @H'FAA3", + "mnemonic": "BTST.B", + "operands": "#7, @H'FAA3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 64163, + "name": null, + "symbol": "ram_FAA3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [], + "notes": [] + } + }, + { + "address": 48847, + "address_region": "program_or_external", + "bytes": "2717", + "text": "BEQ loc_BEE8", + "mnemonic": "BEQ", + "operands": "loc_BEE8", + "kind": "branch", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48833, + "changes": [], + "notes": [] + } + }, + { + "address": 48849, + "address_region": "program_or_external", + "bytes": "15F9C313", + "text": "CLR.B @H'F9C3", + "mnemonic": "CLR.B", + "operands": "@H'F9C3", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63939, + "name": null, + "symbol": "ram_F9C3", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48853, + "address_region": "program_or_external", + "bytes": "1EFB4E", + "text": "BSR loc_BA26", + "mnemonic": "BSR", + "operands": "loc_BA26", + "kind": "call", + "targets": [ + 47654 + ], + "cycles": { + "cycles": 14, + "base_cycles": 9, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word push to stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [ + { + "kind": "register", + "name": "R0", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R1", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R2", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R3", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R4", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R6", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "register", + "name": "R7", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "flags" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "BR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "EP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "DP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "TP", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + }, + { + "kind": "control", + "name": "SR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "call" + } + } + ], + "notes": [ + "call clobbers tracked register state" + ] + } + }, + { + "address": 48856, + "address_region": "program_or_external", + "bytes": "200E", + "text": "BRA loc_BEE8", + "mnemonic": "BRA", + "operands": "loc_BEE8", + "kind": "jump", + "targets": [ + 48872 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48849, + "changes": [], + "notes": [] + } + }, + { + "address": 48868, + "address_region": "program_or_external", + "bytes": "15F9C513", + "text": "CLR.B @H'F9C5", + "mnemonic": "CLR.B", + "operands": "@H'F9C5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63941, + "name": null, + "symbol": "ram_F9C5", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48868, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48872, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48872, + "changes": [], + "notes": [] + } + }, + { + "address": 48874, + "address_region": "program_or_external", + "bytes": "15FE91D5", + "text": "BCLR.B #5, @FRT1_TCSR", + "mnemonic": "BCLR.B", + "operands": "#5, @FRT1_TCSR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65169, + "name": "FRT1_TCSR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear OCFA (bit 5) of FRT1_TCSR", + "valid": true, + "serial_reconstruction": [ + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + }, + { + "address": 48874, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "frt1_ocia_periodic_tick_isr", + "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA", + "evidence_addresses": [ + 48874 + ], + "evidence_addresses_hex": [ + "H'BEEA" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48878, + "address_region": "program_or_external", + "bytes": "15F9C016", + "text": "TST.B @H'F9C0", + "mnemonic": "TST.B", + "operands": "@H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48878, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48882, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BEF8", + "mnemonic": "BEQ", + "operands": "loc_BEF8", + "kind": "branch", + "targets": [ + 48888 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48874, + "changes": [], + "notes": [] + } + }, + { + "address": 48884, + "address_region": "program_or_external", + "bytes": "15F9C00C", + "text": "ADD:Q.B #-1, @H'F9C0", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C0", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63936, + "name": null, + "symbol": "ram_F9C0", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48884, + "action": "serial_reconstruction_ram_role", + "role_name": "post_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63936, + "role_address_hex": "H'F9C0", + "evidence": "post_tx_report_delay_tick_decrement", + "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48884, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48888, + "address_region": "program_or_external", + "bytes": "15F9C116", + "text": "TST.B @H'F9C1", + "mnemonic": "TST.B", + "operands": "@H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48888, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48888, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48892, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF02", + "mnemonic": "BEQ", + "operands": "loc_BF02", + "kind": "branch", + "targets": [ + 48898 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48888, + "changes": [], + "notes": [] + } + }, + { + "address": 48894, + "address_region": "program_or_external", + "bytes": "15F9C10C", + "text": "ADD:Q.B #-1, @H'F9C1", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F9C1", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63937, + "name": null, + "symbol": "ram_F9C1", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48894, + "action": "serial_reconstruction_ram_role", + "role_name": "secondary_tx_report_delay", + "role_kind": "candidate_ram_role", + "role_address": 63937, + "role_address_hex": "H'F9C1", + "evidence": "secondary_tx_report_delay_tick_decrement", + "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48888, + 48894 + ], + "evidence_addresses_hex": [ + "H'BEF8", + "H'BEFE" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48894, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48898, + "address_region": "program_or_external", + "bytes": "1DF9C616", + "text": "TST.W @H'F9C6", + "mnemonic": "TST.W", + "operands": "@H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48898, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48898, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48902, + "address_region": "program_or_external", + "bytes": "2704", + "text": "BEQ loc_BF0C", + "mnemonic": "BEQ", + "operands": "loc_BF0C", + "kind": "branch", + "targets": [ + 48908 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48898, + "changes": [], + "notes": [] + } + }, + { + "address": 48904, + "address_region": "program_or_external", + "bytes": "1DF9C60C", + "text": "ADD:Q.W #-1, @H'F9C6", + "mnemonic": "ADD:Q.W", + "operands": "#-1, @H'F9C6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63942, + "name": null, + "symbol": "ram_F9C6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "serial_reconstruction": [ + { + "address": 48904, + "action": "serial_reconstruction_ram_role", + "role_name": "periodic_report_countdown", + "role_kind": "candidate_ram_role", + "role_address": 63942, + "role_address_hex": "H'F9C6", + "evidence": "periodic_report_countdown_tick_decrement", + "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR", + "evidence_addresses": [ + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BF02", + "H'BF08" + ], + "confidence": "candidate/evidence-supported", + "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported" + } + ], + "dataflow": { + "block": 48904, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48908, + "address_region": "program_or_external", + "bytes": "15F6F6F7", + "text": "BTST.B #7, @H'F6F6", + "mnemonic": "BTST.B", + "operands": "#7, @H'F6F6", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63222, + "name": null, + "symbol": "ram_F6F6", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48908, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 48912, + "address_region": "program_or_external", + "bytes": "2710", + "text": "BEQ loc_BF22", + "mnemonic": "BEQ", + "operands": "loc_BF22", + "kind": "branch", + "targets": [ + 48930 + ], + "cycles": { + "not_taken": 3, + "taken": 7, + "base_taken": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48908, + "changes": [], + "notes": [] + } + }, + { + "address": 48914, + "address_region": "program_or_external", + "bytes": "1DF6F416", + "text": "TST.W @H'F6F4", + "mnemonic": "TST.W", + "operands": "@H'F6F4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 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"taken": 7, + "base_taken": 7, + "cycles": 7, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 48920, + "changes": [], + "notes": [] + } + }, + { + "address": 48926, + "address_region": "program_or_external", + "bytes": "1DF6F40C", + "text": "ADD:Q.W #-1, @H'F6F4", + "mnemonic": "ADD:Q.W", + "operands": "#-1, @H'F6F4", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63220, + "name": null, + "symbol": "ram_F6F4", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 48926, + "changes": [ + { + "kind": "control", + "name": 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"name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49041, + "address_region": "program_or_external", + "bytes": "2610", + "text": "BNE loc_BFA3", + "mnemonic": "BNE", + "operands": "loc_BFA3", + "kind": "branch", + "targets": [ + 49059 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49037, + "changes": [], + "notes": [] + } + }, + { + "address": 49043, + "address_region": "program_or_external", + "bytes": "15F711D7", + "text": "BCLR.B #7, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49047, + "address_region": "program_or_external", + "bytes": "15F711D6", + "text": "BCLR.B #6, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#6, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [], + "notes": [] + } + }, + { + "address": 49051, + "address_region": "program_or_external", + "bytes": "15F711D5", + "text": "BCLR.B #5, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#5, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [], + "notes": [] + } + }, + { + "address": 49055, + "address_region": "program_or_external", + "bytes": "15F711D4", + "text": "BCLR.B #4, @H'F711", + "mnemonic": "BCLR.B", + "operands": "#4, @H'F711", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63249, + "name": null, + "symbol": "ram_F711", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49043, + "changes": [], + "notes": [] + } + }, + { + "address": 49059, + "address_region": "program_or_external", + "bytes": "15F79716", + "text": "TST.B @H'F797", + "mnemonic": "TST.B", + "operands": "@H'F797", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63383, + "name": null, + "symbol": "ram_F797", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49059, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49063, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_BFB3", + "mnemonic": "BEQ", + "operands": "loc_BFB3", + "kind": "branch", + "targets": [ + 49075 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49059, + "changes": [], + "notes": [] + } + }, + { + "address": 49065, + "address_region": "program_or_external", + "bytes": "15F7970C", + "text": "ADD:Q.B #-1, @H'F797", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F797", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63383, + "name": null, + "symbol": "ram_F797", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49065, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49069, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_BFB3", + "mnemonic": "BNE", + "operands": "loc_BFB3", + "kind": "branch", + "targets": [ + 49075 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49065, + "changes": [], + "notes": [] + } + }, + { + "address": 49071, + "address_region": "program_or_external", + "bytes": "15F731D7", + "text": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49071, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49075, + "address_region": "program_or_external", + "bytes": "15F79816", + "text": "TST.B @H'F798", + "mnemonic": "TST.B", + "operands": "@H'F798", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 6, + "base_cycles": 6, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63384, + "name": null, + "symbol": "ram_F798", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49075, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49079, + "address_region": "program_or_external", + "bytes": "270A", + "text": "BEQ loc_BFC3", + "mnemonic": "BEQ", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49075, + "changes": [], + "notes": [] + } + }, + { + "address": 49081, + "address_region": "program_or_external", + "bytes": "15F7980C", + "text": "ADD:Q.B #-1, @H'F798", + "mnemonic": "ADD:Q.B", + "operands": "#-1, @H'F798", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63384, + "name": null, + "symbol": "ram_F798", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49085, + "address_region": "program_or_external", + "bytes": "2604", + "text": "BNE loc_BFC3", + "mnemonic": "BNE", + "operands": "loc_BFC3", + "kind": "branch", + "targets": [ + 49091 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49081, + "changes": [], + "notes": [] + } + }, + { + "address": 49087, + "address_region": "program_or_external", + "bytes": "15F731D7", + "text": "BCLR.B #7, @H'F731", + "mnemonic": "BCLR.B", + "operands": "#7, @H'F731", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63281, + "name": null, + "symbol": "ram_F731", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49087, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49091, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49091, + "changes": [], + "notes": [] + } + }, + { + "address": 49092, + "address_region": "program_or_external", + "bytes": "15FEECF7", + "text": "BTST.B #7, @WDT_TCSR_R", + "mnemonic": "BTST.B", + "operands": "#7, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49096, + "address_region": "program_or_external", + "bytes": "1DFEEC07A53F", + "text": "MOV:G.W #H'A53F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A53F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 11, + "base_cycles": 9, + "alignment_adjustment": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49102, + "address_region": "program_or_external", + "bytes": "15F79408", + "text": "ADD:Q.B #1, @H'F794", + "mnemonic": "ADD:Q.B", + "operands": "#1, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49106, + "address_region": "program_or_external", + "bytes": "15F794040A", + "text": "CMP:G.B #H'0A, @H'F794", + "mnemonic": "CMP:G.B", + "operands": "#H'0A, @H'F794", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 7, + "base_cycles": 6, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63380, + "name": null, + "symbol": "ram_F794", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49111, + "address_region": "program_or_external", + "bytes": "2606", + "text": "BNE loc_BFDF", + "mnemonic": "BNE", + "operands": "loc_BFDF", + "kind": "branch", + "targets": [ + 49119 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49092, + "changes": [], + "notes": [] + } + }, + { + "address": 49113, + "address_region": "program_or_external", + "bytes": "1DFEEC07A57F", + "text": "MOV:G.W #H'A57F, @WDT_TCSR_R", + "mnemonic": "MOV:G.W", + "operands": "#H'A57F, @WDT_TCSR_R", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 9, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65260, + "name": "WDT_TCSR_R", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096)", + "valid": true, + "dataflow": { + "block": 49113, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49119, + "address_region": "program_or_external", + "bytes": "0A", + "text": "RTE", + "mnemonic": "RTE", + "operands": "", + "kind": "rte", + "targets": [], + "cycles": { + "cycles": 14, + "base_cycles": 13, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49119, + "changes": [], + "notes": [] + } + }, + { + "address": 49120, + "address_region": "program_or_external", + "bytes": "15F840060A", + "text": "MOV:G.B #H'0A, @H'F840", + "mnemonic": "MOV:G.B", + "operands": "#H'0A, @H'F840", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 63552, + "name": null, + "symbol": "ram_F840", + "region": "on_chip_ram", + "kind": "ram" + } + ], + "comment": "", + "valid": true, + "dataflow": { + "block": 49120, + "changes": [ + { + "kind": "control", + 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"text": "BEQ loc_C0F5", + "mnemonic": "BEQ", + "operands": "loc_C0F5", + "kind": "branch", + "targets": [ + 49397 + ], + "cycles": { + "not_taken": 3, + "taken": 8, + "base_taken": 7, + "alignment_adjustment_taken": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49379, + "changes": [], + "notes": [] + } + }, + { + "address": 49393, + "address_region": "program_or_external", + "bytes": "A549", + "text": "BSET.B R1, R5", + "mnemonic": "BSET.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49393, + "changes": [ + { + "kind": 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"address": 49397, + "address_region": "program_or_external", + "bytes": "A559", + "text": "BCLR.B R1, R5", + "mnemonic": "BCLR.B", + "operands": "R1, R5", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 2, + "base_cycles": 2, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49397, + "changes": [ + { + "kind": "register", + "name": "R5", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "unsupported:BCLR.B" + } + }, + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [ + "unsupported operation invalidated R5" + ] + } + }, + { + "address": 49399, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": 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"block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49411, + "address_region": "program_or_external", + "bytes": "01B9DD", + "text": "SCB/F R1, loc_C0E3", + "mnemonic": "SCB/F", + "operands": "R1, loc_C0E3", + "kind": "branch", + "targets": [ + 49379 + ], + "cycles": { + "false": 3, + "count_minus_1": 4, + "taken": 9, + "base_taken": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49399, + "changes": [], + "notes": [] + } + }, + { + "address": 49414, + "address_region": "program_or_external", + "bytes": "15FEFE0693", + "text": "MOV:G.B #H'93, @P9DDR", + "mnemonic": "MOV:G.B", + "operands": "#H'93, @P9DDR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": 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"base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49465, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49469, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 8, + "base_cycles": 8, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49473, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 13, + "base_cycles": 8, + "alignment_adjustment": 1, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49441, + "changes": [], + "notes": [] + } + }, + { + "address": 49474, + "address_region": "program_or_external", + "bytes": "15FEFFD7", + "text": "BCLR.B #7, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [ + { + "kind": "control", + "name": "CCR", + "before": { + "known": false, + "reason": "block_entry" + }, + "after": { + "known": false, + "reason": "flags" + } + } + ], + "notes": [] + } + }, + { + "address": 49478, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49482, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49486, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49490, + "address_region": "program_or_external", + "bytes": "15FEFFC7", + "text": "BSET.B #7, @P9DR", + "mnemonic": "BSET.B", + "operands": "#7, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 7 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49494, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49498, + "address_region": "program_or_external", + "bytes": "15FEFFC1", + "text": "BSET.B #1, @P9DR", + "mnemonic": "BSET.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "set bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49502, + "address_region": "program_or_external", + "bytes": "15FEFFD1", + "text": "BCLR.B #1, @P9DR", + "mnemonic": "BCLR.B", + "operands": "#1, @P9DR", + "kind": "normal", + "targets": [], + "cycles": { + "cycles": 9, + "base_cycles": 8, + "alignment_adjustment": 1, + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [ + { + "address": 65279, + "name": "P9DR", + "symbol": null, + "region": "register_field", + "kind": "registers" + } + ], + "comment": "clear bit 1 of P9DR", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + }, + { + "address": 49506, + "address_region": "program_or_external", + "bytes": "19", + "text": "RTS", + "mnemonic": "RTS", + "operands": "", + "kind": "return", + "targets": [], + "cycles": { + "cycles": 12, + "base_cycles": 8, + "stack_adjustment": 4, + "note": "PC word pop from stack", + "source": "manual Appendix A.4, tables A-7/A-8", + "assumption": "on-chip instruction fetch/operand access, no external wait states" + }, + "references": [], + "comment": "", + "valid": true, + "dataflow": { + "block": 49474, + "changes": [], + "notes": [] + } + } + ], + "decompiler_consistency": { + "kind": "decompiler_pseudocode_consistency", + "summary": "58 byte-immediate-to-word destination case(s) require explicit zero-extension in pseudocode.", + "checks": [ + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4163, + "address_hex": "H'1043", + "instruction": "MOV:G.W #H'00, @FRT1_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 4184, + "address_hex": "H'1058", + "instruction": "MOV:G.W #H'00, @FRT2_FRC_H", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 16487, + "address_hex": "H'4067", + "instruction": "MOV:G.W #H'00, @(-H'0790,R2)", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 24838, + "address_hex": "H'6106", + "instruction": "MOV:G.W #H'01, @H'FAF0", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0001", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28388, + "address_hex": "H'6EE4", + "instruction": "MOV:G.W #H'00, @H'F736", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28393, + "address_hex": "H'6EE9", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28398, + "address_hex": "H'6EEE", + "instruction": "MOV:G.W #H'00, @H'F73A", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28403, + "address_hex": "H'6EF3", + "instruction": "MOV:G.W #H'00, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28408, + "address_hex": "H'6EF8", + "instruction": "MOV:G.W #H'00, @H'F740", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28449, + "address_hex": "H'6F21", + "instruction": "MOV:G.W #H'00, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28656, + "address_hex": "H'6FF0", + "instruction": "MOV:G.W #H'00, @H'F736", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28661, + "address_hex": "H'6FF5", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28666, + "address_hex": "H'6FFA", + "instruction": "MOV:G.W #H'00, @H'F73A", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28671, + "address_hex": "H'6FFF", + "instruction": "MOV:G.W #H'00, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28682, + "address_hex": "H'700A", + "instruction": "MOV:G.W #H'00, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28687, + "address_hex": "H'700F", + "instruction": "MOV:G.W #H'00, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28692, + "address_hex": "H'7014", + "instruction": "MOV:G.W #H'00, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28924, + "address_hex": "H'70FC", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28935, + "address_hex": "H'7107", + "instruction": "MOV:G.W #H'00, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28946, + "address_hex": "H'7112", + "instruction": "MOV:G.W #H'00, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28951, + "address_hex": "H'7117", + "instruction": "MOV:G.W #H'00, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 28956, + "address_hex": "H'711C", + "instruction": "MOV:G.W #H'46, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0046", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29064, + "address_hex": "H'7188", + "instruction": "MOV:G.W #H'00, @H'F736", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29069, + "address_hex": "H'718D", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29074, + "address_hex": "H'7192", + "instruction": "MOV:G.W #H'00, @H'F73A", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29079, + "address_hex": "H'7197", + "instruction": "MOV:G.W #H'00, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29084, + "address_hex": "H'719C", + "instruction": "MOV:G.W #H'00, @H'F740", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29089, + "address_hex": "H'71A1", + "instruction": "MOV:G.W #H'37, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0037", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29106, + "address_hex": "H'71B2", + "instruction": "MOV:G.W #H'37, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0037", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29117, + "address_hex": "H'71BD", + "instruction": "MOV:G.W #H'00, @H'F752", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29122, + "address_hex": "H'71C2", + "instruction": "MOV:G.W #H'00, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29272, + "address_hex": "H'7258", + "instruction": "MOV:G.W #H'00, @H'F736", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29277, + "address_hex": "H'725D", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29282, + "address_hex": "H'7262", + "instruction": "MOV:G.W #H'00, @H'F73A", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29287, + "address_hex": "H'7267", + "instruction": "MOV:G.W #H'38, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0038", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29304, + "address_hex": "H'7278", + "instruction": "MOV:G.W #H'38, @H'F740", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0038", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29321, + "address_hex": "H'7289", + "instruction": "MOV:G.W #H'00, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29326, + "address_hex": "H'728E", + "instruction": "MOV:G.W #H'38, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0038", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29337, + "address_hex": "H'7299", + "instruction": "MOV:G.W #H'00, @H'F752", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29342, + "address_hex": "H'729E", + "instruction": "MOV:G.W #H'00, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29480, + "address_hex": "H'7328", + "instruction": "MOV:G.W #H'00, @H'F736", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29485, + "address_hex": "H'732D", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29490, + "address_hex": "H'7332", + "instruction": "MOV:G.W #H'00, @H'F73A", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29495, + "address_hex": "H'7337", + "instruction": "MOV:G.W #H'00, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29500, + "address_hex": "H'733C", + "instruction": "MOV:G.W #H'00, @H'F740", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29505, + "address_hex": "H'7341", + "instruction": "MOV:G.W #H'27, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0027", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29522, + "address_hex": "H'7352", + "instruction": "MOV:G.W #H'27, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0027", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29533, + "address_hex": "H'735D", + "instruction": "MOV:G.W #H'00, @H'F752", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29538, + "address_hex": "H'7362", + "instruction": "MOV:G.W #H'00, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29656, + "address_hex": "H'73D8", + "instruction": "MOV:G.W #H'00, @H'F736", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29661, + "address_hex": "H'73DD", + "instruction": "MOV:G.W #H'00, @H'F738", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29666, + "address_hex": "H'73E2", + "instruction": "MOV:G.W #H'00, @H'F73A", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29671, + "address_hex": "H'73E7", + "instruction": "MOV:G.W #H'27, @H'F73C", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0027", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29688, + "address_hex": "H'73F8", + "instruction": "MOV:G.W #H'27, @H'F740", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0027", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29705, + "address_hex": "H'7409", + "instruction": "MOV:G.W #H'00, @H'F73E", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29710, + "address_hex": "H'740E", + "instruction": "MOV:G.W #H'27, @H'F742", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0027", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29721, + "address_hex": "H'7419", + "instruction": "MOV:G.W #H'00, @H'F752", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + }, + { + "kind": "byte_immediate_to_word_destination", + "status": "requires_zero_extend8_to16_pseudocode", + "address": 29726, + "address_hex": "H'741E", + "instruction": "MOV:G.W #H'00, @H'F754", + "expected_pseudocode_hint": "zero_extend8_to16", + "zero_extended_value_hex": "0x0000", + "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte." + } + ] + }, + "serial_semantics": { + "kind": "serial_semantics", + "protocol_semantics": [ + { + "kind": "serial_semantics", + "scope": "evidence_supported_sci1_6_byte_frame", + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation.", + "frame_candidate": { + "channel": "SCI1", + "rx_frame_start": 63584, + "rx_frame_start_hex": "H'F860", + "rx_frame_end": 63589, + "rx_frame_end_hex": "H'F865", + "tx_staging_start": 63568, + "tx_staging_start_hex": "H'F850", + "tx_staging_end": 63572, + "tx_staging_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "frame_length": 6, + "tx_staging_length": 5, + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "serial_reconstruction_supported": true, + "rx_reconstruction_candidate_id": "sci1_rx_frame_f868_len6_candidate", + "tx_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + "byte_layout": [ + { + "offset": 0, + "rx_address": 63584, + "tx_staging_address": 63568, + "name_candidate": "op_flags", + "semantic": "low three bits select a command; upper bits are preserved or gated in some paths", + "confidence": "medium-high" + }, + { + "offset": 1, + "rx_address": 63585, + "tx_staging_address": 63569, + "name_candidate": "addr_page_flags", + "semantic": "candidate high/page byte for logical point/index; bit 7 is tested as a control flag", + "confidence": "medium" + }, + { + "offset": 2, + "rx_address": 63586, + "tx_staging_address": 63570, + "name_candidate": "addr_offset", + "semantic": "candidate low/offset byte for logical point/index", + "confidence": "medium" + }, + { + "offset": 3, + "rx_address": 63587, + "tx_staging_address": 63571, + "name_candidate": "value_hi", + "semantic": "candidate high byte of a word value", + "confidence": "medium" + }, + { + "offset": 4, + "rx_address": 63588, + "tx_staging_address": 63572, + "name_candidate": "value_lo", + "semantic": "candidate low byte of a word value", + "confidence": "medium" + }, + { + "offset": 5, + "rx_address": 63589, + "tx_staging_address": null, + "name_candidate": "checksum", + "semantic": "0x5A-seeded XOR of bytes 0..4", + "confidence": "high" + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2899 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2931 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2943 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 3027 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2946 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2983 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 3015 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 3027 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "index_decoder": { + "kind": "logical_index_decoder_candidate", + "label": "loc_622B", + "address": 25131, + "address_hex": "H'622B", + "input_fields": [ + "addr_page_flags", + "addr_offset" + ], + "output_register": "R5", + "post_scale_register": "R4", + "post_scale": "R4 = R5 << 1", + "mapping_candidate": [ + { + "page": 0, + "offset_range": "0x00-0x7F", + "index_range": "0x000-0x07F" + }, + { + "page": 1, + "offset_range": "0x00-0xFF", + "index_range": "0x080-0x17F" + }, + { + "page": 2, + "offset_range": "0x00-0x7F", + "index_range": "0x180-0x1FF" + }, + { + "page": "other/overflow", + "index": "0x1FF" + } + ], + "evidence_addresses": [ + 48129 + ], + "evidence_addresses_hex": [ + "H'BC01" + ], + "confidence": "medium", + "caveat": "Mapping is inferred from loc_622B behavior and the nearby R4 = R5 << 1 table-index use." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 23113, + "instruction_address_hex": "H'5A49", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R1), R1" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 23113, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'5A49", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": 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"instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23081, + "instruction_address_hex": "H'5A29", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23097, + "instruction_address_hex": "H'5A39", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23105, + "instruction_address_hex": "H'5A41", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23450, + "instruction_address_hex": "H'5B9A", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23466, + "instruction_address_hex": "H'5BAA", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23474, + "instruction_address_hex": "H'5BB2", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23582, + "instruction_address_hex": "H'5C1E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23598, + "instruction_address_hex": "H'5C2E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23606, + "instruction_address_hex": "H'5C36", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23081, + 23097, + 23105, + 23450, + 23466, + 23474, + 23582, + 23598, + 23606, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5A29", + "H'5A39", + "H'5A41", + "H'5B9A", + "H'5BAA", + "H'5BB2", + "H'5C1E", + "H'5C2E", + "H'5C36", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, 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base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 23113, + "instruction_address_hex": "H'5A49", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R1), R1" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 23113, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'5A49", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23081, + "instruction_address_hex": "H'5A29", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23097, + "instruction_address_hex": "H'5A39", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23105, + "instruction_address_hex": "H'5A41", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23450, + "instruction_address_hex": "H'5B9A", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23466, + "instruction_address_hex": "H'5BAA", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23474, + "instruction_address_hex": "H'5BB2", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23582, + "instruction_address_hex": "H'5C1E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23598, + "instruction_address_hex": "H'5C2E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23606, + "instruction_address_hex": "H'5C36", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23081, + 23097, + 23105, + 23450, + 23466, + 23474, + 23582, + 23598, + 23606, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5A29", + "H'5A39", + "H'5A41", + "H'5B9A", + "H'5BAA", + "H'5BB2", + "H'5C1E", + "H'5C2E", + "H'5C36", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, 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"access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "rx_fields": [ + { + "kind": "rx_field_semantic_candidate", + "offset": 0, + "name": "command_low3", + "address": 63584, + "address_hex": "H'F860", + "confidence": "candidate-high", + "caveat": "RX[0] is masked with 0x07 before command comparisons", + "evidence_addresses": [ + 48088, + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "mask": 7, + "mask_hex": "H'07" + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 1, + "name": "likely_id_or_index", + "address": 63585, + "address_hex": "H'F861", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 2, + "name": "likely_id_or_index", + "address": 63586, + "address_hex": "H'F862", + "confidence": "candidate-medium", + "caveat": "RX[1:2] are read near logical point/index and response-echo handling", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 3, + "name": "likely_value", + "address": 63587, + "address_hex": "H'F863", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 4, + "name": "likely_value", + "address": 63588, + "address_hex": "H'F864", + "confidence": "candidate-medium", + "caveat": "RX[3:4] are read near table-value write/read response handling", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62" + ] + }, + { + "kind": "rx_field_semantic_candidate", + "offset": 5, + "name": "checksum", + "address": 63589, + "address_hex": "H'F865", + "confidence": "candidate-high", + "caveat": "RX[5] is validated by the serial reconstruction checksum evidence", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ] + } + ], + "response_builders": [ + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 47939, + "call_address_hex": "H'BB43", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48674, + "call_address_hex": "H'BE22", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + }, + { + "kind": "response_builder_candidate", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "send_call_target": 47654, + "send_call_target_hex": "H'BA26", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "writes": [ + { + "address": 63568, + "address_hex": "H'F850", + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "address": 63569, + "address_hex": "H'F851", + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "address": 63570, + "address_hex": "H'F852", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63571, + "address_hex": "H'F853", + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "address": 63572, + "address_hex": "H'F854", + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "evidence": [ + { + "kind": "rx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 RX frame candidate", + "candidate_id": "sci1_rx_frame_f868_len6_candidate" + }, + { + "kind": "tx_frame_reconstruction_present", + "summary": "serial_reconstruction contains an evidence-supported SCI1 TX frame candidate", + "candidate_id": "sci1_tx_frame_f858_len6_candidate" + }, + { + "kind": "rx0_masked_command_dispatch", + "summary": "RX[0] is read, masked with 0x07, and compared against command values", + "addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + { + "kind": "responses_stage_f850_f854_before_send", + "summary": "F850-F854 writes are observed before calls to loc_BA26", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378, + 48649, + 48657, + 48665, + 48674, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "response_count": 5 + }, + { + "kind": "bb43_autonomous_tx_report_path", + "summary": "BB43 stages a candidate device-to-host report before loc_BA26; this is separate from RX command dispatch.", + "addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + { + "kind": "rx_payload_bytes_read", + "summary": "RX[1..4] are read in the command-processing region", + "addresses": [ + 48092, + 48096, + 48100, + 48104, + 48119, + 48125, + 48153, + 48190, + 48237, + 48267, + 48273, + 48309, + 48317, + 48325, + 48348, + 48356, + 48402, + 48427, + 48433, + 48603, + 48609, + 48722, + 48730, + 48738 + ], + "addresses_hex": [ + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBF7", + "H'BBFD", + "H'BC19", + "H'BC3E", + "H'BC6D", + "H'BC8B", + "H'BC91", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCDC", + "H'BCE4", + "H'BD12", + "H'BD2B", + "H'BD31", + "H'BDDB", + "H'BDE1", + "H'BE52", + "H'BE5A", + "H'BE62" + ] + } + ] + } + ], + "fields": [ + { + "id": "rx_0", + "kind": "rx_frame_field_candidate", + "offset": 0, + "address": 63584, + "address_hex": "H'F860", + "role_candidate": "command_selector_candidate", + "evidence_addresses": [ + 48088, + 48136, + 48055, + 48160, + 48162, + 48164, + 48197, + 48166, + 48199, + 48169, + 48202, + 48171, + 48140, + 48204, + 48174, + 48207, + 48176, + 48209, + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BC08", + "H'BBB7", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC45", + "H'BC26", + "H'BC47", + "H'BC29", + "H'BC4A", + "H'BC2B", + "H'BC0C", + "H'BC4C", + "H'BC2E", + "H'BC4F", + "H'BC30", + "H'BC51", + "H'BC54", + "H'BC56" + ], + "read_count": 2, + "write_count": 2, + "confidence": "medium", + "caveat": "RX[0] is masked with 0x07 before command comparisons." + }, + { + "id": "rx_1", + "kind": "rx_frame_field_candidate", + "offset": 1, + "address": 63585, + "address_hex": "H'F861", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48092, + 48119, + 48153, + 48190, + 48309, + 48348, + 48722 + ], + "evidence_addresses_hex": [ + "H'BBDC", + "H'BBF7", + "H'BC19", + "H'BC3E", + "H'BCB5", + "H'BCDC", + "H'BE52" + ], + "read_count": 7, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_2", + "kind": "rx_frame_field_candidate", + "offset": 2, + "address": 63586, + "address_hex": "H'F862", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48096, + 48125, + 48317, + 48356, + 48730, + 48063 + ], + "evidence_addresses_hex": [ + "H'BBE0", + "H'BBFD", + "H'BCBD", + "H'BCE4", + "H'BE5A", + "H'BBBF" + ], + "read_count": 5, + "write_count": 2, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_3", + "kind": "rx_frame_field_candidate", + "offset": 3, + "address": 63587, + "address_hex": "H'F863", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48100, + 48237, + 48267, + 48402, + 48427, + 48603 + ], + "evidence_addresses_hex": [ + "H'BBE4", + "H'BC6D", + "H'BC8B", + "H'BD12", + "H'BD2B", + "H'BDDB" + ], + "read_count": 6, + "write_count": 1, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_4", + "kind": "rx_frame_field_candidate", + "offset": 4, + "address": 63588, + "address_hex": "H'F864", + "role_candidate": "payload_byte_candidate", + "evidence_addresses": [ + 48104, + 48273, + 48325, + 48433, + 48609, + 48738, + 48071, + 48253 + ], + "evidence_addresses_hex": [ + "H'BBE8", + "H'BC91", + "H'BCC5", + "H'BD31", + "H'BDE1", + "H'BE62", + "H'BBC7", + "H'BC7D" + ], + "read_count": 6, + "write_count": 3, + "confidence": "medium", + "caveat": "Role is inferred from reads in command processing." + }, + { + "id": "rx_5", + "kind": "rx_frame_field_candidate", + "offset": 5, + "address": 63589, + "address_hex": "H'F865", + "role_candidate": "checksum_byte_candidate", + "evidence_addresses": [ + 48108 + ], + "evidence_addresses_hex": [ + "H'BBEC" + ], + "read_count": 1, + "write_count": 0, + "confidence": "medium", + "caveat": "RX[5] is compared with a checksum over RX[0..4]." + }, + { + "id": "tx_staging_0", + "kind": "tx_staging_field_candidate", + "offset": 0, + "address": 63568, + "address_hex": "H'F850", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47900, + 48304, + 48343, + 48649, + 48717 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BCB0", + "H'BCD7", + "H'BE09", + "H'BE4D" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_1", + "kind": "tx_staging_field_candidate", + "offset": 1, + "address": 63569, + "address_hex": "H'F851", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47915, + 48313, + 48352, + 48360, + 48649, + 48726 + ], + "evidence_addresses_hex": [ + "H'BB2B", + "H'BCB9", + "H'BCE0", + "H'BCE8", + "H'BE09", + "H'BE56" + ], + "write_count": 6, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_2", + "kind": "tx_staging_field_candidate", + "offset": 2, + "address": 63570, + "address_hex": "H'F852", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47904, + 48321, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB20", + "H'BCC1", + "H'BE11", + "H'BE5E" + ], + "write_count": 4, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_3", + "kind": "tx_staging_field_candidate", + "offset": 3, + "address": 63571, + "address_hex": "H'F853", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47935, + 48321, + 48374, + 48657, + 48734 + ], + "evidence_addresses_hex": [ + "H'BB3F", + "H'BCC1", + "H'BCF6", + "H'BE11", + "H'BE5E" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + }, + { + "id": "tx_staging_4", + "kind": "tx_staging_field_candidate", + "offset": 4, + "address": 63572, + "address_hex": "H'F854", + "role_candidate": "response_staging_byte_candidate", + "evidence_addresses": [ + 47929, + 48329, + 48368, + 48665, + 48742 + ], + "evidence_addresses_hex": [ + "H'BB39", + "H'BCC9", + "H'BCF0", + "H'BE19", + "H'BE66" + ], + "write_count": 5, + "confidence": "medium", + "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position." + } + ], + "command_dispatch": { + "kind": "command_dispatch_candidate", + "selector": "rx0_low3_bits", + "field": "command_low3", + "rx_offset": 0, + "rx_address": 63584, + "rx_address_hex": "H'F860", + "source_address": 63584, + "source_address_hex": "H'F860", + "source_field": "byte0", + "mask": 7, + "mask_hex": "H'0007", + "selector_register": "R0", + "read_address": 48136, + "read_address_hex": "H'BC08", + "mask_address": 48140, + "mask_address_hex": "H'BC0C", + "command_values": [ + 0, + 1, + 2, + 4, + 5, + 6, + 7 + ], + "command_values_hex": [ + "H'00", + "H'01", + "H'02", + "H'04", + "H'05", + "H'06", + "H'07" + ], + "comparisons": [ + { + "command_value": 0, + "command_value_hex": "H'00", + "compare_address": 48160, + "compare_address_hex": "H'BC20", + "branch_address": 48162, + "branch_address_hex": "H'BC22", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "evidence_addresses": [ + 48160, + 48162 + ], + "evidence_addresses_hex": [ + "H'BC20", + "H'BC22" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2899 + }, + { + "command_value": 1, + "command_value_hex": "H'01", + "compare_address": 48164, + "compare_address_hex": "H'BC24", + "branch_address": 48166, + "branch_address_hex": "H'BC26", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "evidence_addresses": [ + 48164, + 48166 + ], + "evidence_addresses_hex": [ + "H'BC24", + "H'BC26" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "handler_start_index": 2931 + }, + { + "command_value": 2, + "command_value_hex": "H'02", + "compare_address": 48169, + "compare_address_hex": "H'BC29", + "branch_address": 48171, + "branch_address_hex": "H'BC2B", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "evidence_addresses": [ + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC29", + "H'BC2B" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 2943 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48174, + "compare_address_hex": "H'BC2E", + "branch_address": 48176, + "branch_address_hex": "H'BC30", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48174, + 48176 + ], + "evidence_addresses_hex": [ + "H'BC2E", + "H'BC30" + ], + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "handler_start_index": 3027 + }, + { + "command_value": 4, + "command_value_hex": "H'04", + "compare_address": 48197, + "compare_address_hex": "H'BC45", + "branch_address": 48199, + "branch_address_hex": "H'BC47", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "evidence_addresses": [ + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC45", + "H'BC47" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2946 + }, + { + "command_value": 5, + "command_value_hex": "H'05", + "compare_address": 48202, + "compare_address_hex": "H'BC4A", + "branch_address": 48204, + "branch_address_hex": "H'BC4C", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "evidence_addresses": [ + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC4A", + "H'BC4C" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 2983 + }, + { + "command_value": 6, + "command_value_hex": "H'06", + "compare_address": 48207, + "compare_address_hex": "H'BC4F", + "branch_address": 48209, + "branch_address_hex": "H'BC51", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "evidence_addresses": [ + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC4F", + "H'BC51" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 3015 + }, + { + "command_value": 7, + "command_value_hex": "H'07", + "compare_address": 48212, + "compare_address_hex": "H'BC54", + "branch_address": 48214, + "branch_address_hex": "H'BC56", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "evidence_addresses": [ + 48212, + 48214 + ], + "evidence_addresses_hex": [ + "H'BC54", + "H'BC56" + ], + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "handler_start_index": 3027 + } + ], + "state_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "dispatcher_split": { + "kind": "serial_command_dispatch_state_split", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "test_address": 48143, + "test_address_hex": "H'BC0F", + "branch_address": 48147, + "branch_address_hex": "H'BC13", + "continuation_target": 48186, + "continuation_target_hex": "H'BC3A", + "initial_idle_commands": [ + 0, + 1, + 2, + 7 + ], + "initial_idle_commands_hex": [ + "H'00", + "H'01", + "H'02", + "H'07" + ], + "continuation_commands": [ + 4, + 5, + 6, + 7 + ], + "continuation_commands_hex": [ + "H'04", + "H'05", + "H'06", + "H'07" + ], + "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.", + "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.", + "evidence_addresses": [ + 48143, + 48147 + ], + "evidence_addresses_hex": [ + "H'BC0F", + "H'BC13" + ] + }, + "cases": [ + { + "value": 0, + "value_hex": "H'00", + "target": 48233, + "target_hex": "H'BC69", + "compare_address": 48160, + "branch_address": 48162, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 1, + "value_hex": "H'01", + "target": 48343, + "target_hex": "H'BCD7", + "compare_address": 48164, + "branch_address": 48166, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + }, + { + "value": 2, + "value_hex": "H'02", + "target": 48388, + "target_hex": "H'BD04", + "compare_address": 48169, + "branch_address": 48171, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48174, + "branch_address": 48176, + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "value": 4, + "value_hex": "H'04", + "target": 48398, + "target_hex": "H'BD0E", + "compare_address": 48197, + "branch_address": 48199, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 5, + "value_hex": "H'05", + "target": 48512, + "target_hex": "H'BD80", + "compare_address": 48202, + "branch_address": 48204, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 6, + "value_hex": "H'06", + "target": 48603, + "target_hex": "H'BDDB", + "compare_address": 48207, + "branch_address": 48209, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + }, + { + "value": 7, + "value_hex": "H'07", + "target": 48645, + "target_hex": "H'BE05", + "compare_address": 48212, + "branch_address": 48214, + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48164, + 48166, + 48169, + 48171, + 48174, + 48176, + 48197, + 48199, + 48202, + 48204, + 48207, + 48209, + 48212, + 48214 + ], + "confidence": "medium", + "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BC24", + "H'BC26", + "H'BC29", + "H'BC2B", + "H'BC2E", + "H'BC30", + "H'BC45", + "H'BC47", + "H'BC4A", + "H'BC4C", + "H'BC4F", + "H'BC51", + "H'BC54", + "H'BC56" + ] + }, + "commands": [ + { + "kind": "command_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response", + "handler_alternatives": [ + { + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "dispatch_compare_address": 48160, + "dispatch_compare_address_hex": "H'BC20", + "dispatch_branch_address": 48162, + "dispatch_branch_address_hex": "H'BC22", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "response_candidates": [ + "response_at_BCCD" + ], + "rx_reads": [ + { + "instruction_address": 48237, + "instruction_address_hex": "H'BC6D", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48267, + "instruction_address_hex": "H'BC8B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48273, + "instruction_address_hex": "H'BC91", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + }, + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48233, + "handler_start_hex": "H'BC69", + "handler_end": 48340, + "handler_end_hex": "H'BCD4", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ] + }, + { + "kind": "command_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence", + "handler_alternatives": [ + { + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "dispatch_compare_address": 48164, + "dispatch_compare_address_hex": "H'BC24", + "dispatch_branch_address": 48166, + "dispatch_branch_address_hex": "H'BC26", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "response_candidates": [ + "response_at_BCFA" + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48343, + "handler_start_hex": "H'BCD7", + "handler_end": 48385, + "handler_end_hex": "H'BD01", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ] + }, + { + "kind": "command_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "candidate clear/abort path with no immediate response builder", + "handler_alternatives": [ + { + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "dispatch_compare_address": 48169, + "dispatch_compare_address_hex": "H'BC29", + "dispatch_branch_address": 48171, + "dispatch_branch_address_hex": "H'BC2B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48388, + "handler_start_hex": "H'BD04", + "handler_end": 48395, + "handler_end_hex": "H'BD0B", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ] + }, + { + "kind": "command_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "candidate write/update path that stores a value without an immediate serial response", + "handler_alternatives": [ + { + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "dispatch_compare_address": 48197, + "dispatch_compare_address_hex": "H'BC45", + "dispatch_branch_address": 48199, + "dispatch_branch_address_hex": "H'BC47", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48402, + "instruction_address_hex": "H'BD12", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48427, + "instruction_address_hex": "H'BD2B", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48433, + "instruction_address_hex": "H'BD31", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48398, + "handler_start_hex": "H'BD0E", + "handler_end": 48509, + "handler_end_hex": "H'BD7D", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ] + }, + { + "kind": "command_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "continuation-only conditional acknowledgement/session clear path", + "handler_alternatives": [ + { + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "dispatch_compare_address": 48202, + "dispatch_compare_address_hex": "H'BC4A", + "dispatch_branch_address": 48204, + "dispatch_branch_address_hex": "H'BC4C", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "response_candidates": [], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48512, + "handler_start_hex": "H'BD80", + "handler_end": 48600, + "handler_end_hex": "H'BDD8", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ] + }, + { + "kind": "command_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "candidate secondary-table value write path", + "handler_alternatives": [ + { + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "dispatch_compare_address": 48207, + "dispatch_compare_address_hex": "H'BC4F", + "dispatch_branch_address": 48209, + "dispatch_branch_address_hex": "H'BC51", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "response_candidates": [], + "rx_reads": [ + { + "instruction_address": 48603, + "instruction_address_hex": "H'BDDB", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "instruction": "MOV:G.B @H'F863, R0" + }, + { + "instruction_address": 48609, + "instruction_address_hex": "H'BDE1", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48603, + "handler_start_hex": "H'BDDB", + "handler_end": 48643, + "handler_end_hex": "H'BE03", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ] + }, + { + "kind": "command_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo", + "handler_alternatives": [ + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48174, + "dispatch_compare_address_hex": "H'BC2E", + "dispatch_branch_address": 48176, + "dispatch_branch_address_hex": "H'BC30", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ] + }, + { + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "dispatch_compare_address": 48212, + "dispatch_compare_address_hex": "H'BC54", + "dispatch_branch_address": 48214, + "dispatch_branch_address_hex": "H'BC56", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ] + } + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "response_candidates": [ + "response_at_BE22" + ], + "rx_reads": [], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.", + "handler_start": 48645, + "handler_start_hex": "H'BE05", + "handler_end": 48677, + "handler_end_hex": "H'BE25", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ] + } + ], + "command_effects": [ + { + "kind": "command_effects_candidate", + "command_value": 0, + "command_value_hex": "H'00", + "name_candidate": "set_value_acked", + "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48245, + 48277 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC75", + "H'BC95" + ] + }, + { + "kind": "table_write_candidate", + "target_candidate": "current_value_table_candidate", + "source_candidate": "same candidate value written to the primary table", + "table_base": 59392, + "table_base_hex": "H'E800", + "evidence_addresses": [ + 48249, + 48281 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC79", + "H'BC99" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48258, + 48285 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BC82", + "H'BC9D" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCCD" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48333 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCCD" + ] + } + ], + "response_candidates": [ + "response_at_BCCD" + ], + "evidence_addresses": [ + 48136, + 48140, + 48160, + 48162, + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC20", + "H'BC22", + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 1, + "command_value_hex": "H'01", + "name_candidate": "read_value", + "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "F861.bit7 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0", + "semantic_notes": [ + "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.", + "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.", + "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.", + "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame." + ], + "effects": [ + { + "kind": "table_read_candidate", + "target_candidate": "primary_value_table_candidate", + "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7", + "table_base": 57344, + "table_base_hex": "H'E000", + "address_expression_candidate": "E000 + 2*selector", + "evidence_addresses": [ + 48364 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCEC" + ] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BCFA" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48378 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BCFA" + ] + } + ], + "response_candidates": [ + "response_at_BCFA" + ], + "evidence_addresses": [ + 48136, + 48140, + 48164, + 48166, + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC24", + "H'BC26", + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 2, + "command_value_hex": "H'02", + "name_candidate": "clear_or_abort", + "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.", + "availability": "initial_idle_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0", + "semantic_notes": [], + "effects": [ + { + "kind": "state_clear_candidate", + "target_candidate": "serial_session_flags_candidate", + "state_address": 64162, + "state_address_hex": "H'FAA2", + "operation_candidate": "clear bit 7", + "evidence_addresses": [ + 48388 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD04" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48169, + 48171 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC29", + "H'BC2B" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 4, + "command_value_hex": "H'04", + "name_candidate": "set_value_no_immediate_reply", + "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "primary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero", + "table_base": 57344, + "table_base_hex": "H'E000", + "evidence_addresses": [ + 48410, + 48437 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD1A", + "H'BD35" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 7", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48418, + 48441 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BD22", + "H'BD39" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48197, + 48199 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC45", + "H'BC47" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 5, + "command_value_hex": "H'05", + "name_candidate": "ack_or_clear_pending", + "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "Only accepted on the continuation dispatcher path when FAA2 != 0.", + "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.", + "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.", + "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work." + ], + "effects": [ + { + "kind": "conditional_ack_session_clear_candidate", + "target_candidate": "selected event/pending state", + "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response", + "selector_without_response_hex": "H'0040", + "requires": [ + "FAA2 != 0" + ], + "fallthrough_when": "FAA2 == 0", + "evidence_addresses": [ + 48578, + 48596, + 48592, + 48584, + 48588 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDC2", + "H'BDD4", + "H'BDD0", + "H'BDC8", + "H'BDCC" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4A", + "H'BC4C" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 6, + "command_value_hex": "H'06", + "name_candidate": "set_secondary_value", + "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.", + "availability": "continuation_dispatch", + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [], + "effects": [ + { + "kind": "table_write_candidate", + "target_candidate": "secondary_value_table_candidate", + "source_candidate": "RX[3:4] value bytes", + "table_base": 58368, + "table_base_hex": "H'E400", + "evidence_addresses": [ + 48613 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE5" + ] + }, + { + "kind": "flag_update_candidate", + "target_candidate": "per_index_flag_table_candidate", + "operation_candidate": "set bit 6", + "table_base": 60416, + "table_base_hex": "H'EC00", + "evidence_addresses": [ + 48617 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BDE9" + ] + } + ], + "response_candidates": [], + "evidence_addresses": [ + 48136, + 48140, + 48207, + 48209 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC4F", + "H'BC51" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + }, + { + "kind": "command_effects_candidate", + "command_value": 7, + "command_value_hex": "H'07", + "name_candidate": "retransmit_or_error_reply", + "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.", + "availability": [ + "initial_idle_dispatch", + "continuation_dispatch" + ], + "availability_conditions": [ + "valid checksum/no RX physical error", + "FAA2 == 0", + "FAA2 != 0" + ], + "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0", + "semantic_notes": [ + "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.", + "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value." + ], + "effects": [ + { + "kind": "retransmit_candidate", + "source_candidate": "previous TX frame bytes H'F858-H'F85C", + "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26", + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48645, + 48649, + 48653, + 48657, + 48661, + 48665, + 48669, + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE05", + "H'BE09", + "H'BE0D", + "H'BE11", + "H'BE15", + "H'BE19", + "H'BE1D", + "H'BE22" + ] + }, + { + "kind": "retry_error_echo_candidate", + "source_candidate": "RX payload bytes F861-F864", + "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value", + "response_candidates": [], + "evidence_addresses": [], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [] + }, + { + "kind": "response_staging_candidate", + "response_candidates": [ + "response_at_BE22" + ], + "operation_candidate": "stage F850-F854 and call loc_BA26", + "evidence_addresses": [ + 48674 + ], + "confidence": "candidate-medium", + "caveat": "Effect is inferred from local data movement and remains a protocol candidate.", + "evidence_addresses_hex": [ + "H'BE22" + ] + } + ], + "response_candidates": [ + "response_at_BE22" + ], + "evidence_addresses": [ + 48136, + 48140, + 48174, + 48176, + 48212, + 48214, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BC08", + "H'BC0C", + "H'BC2E", + "H'BC30", + "H'BC54", + "H'BC56", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted." + } + ], + "response_candidates": [ + { + "id": "response_at_BB43", + "kind": "response_staging_candidate", + "call_address": 47939, + "call_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 47872, + "window_start_hex": "H'BB00", + "writes": [ + { + "instruction_address": 47900, + "instruction_address_hex": "H'BB1C", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "R1", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1" + }, + "instruction": "MOV:G.B R1, @H'F850" + }, + { + "instruction_address": 47904, + "instruction_address_hex": "H'BB20", + "addresses": [ + 63570 + ], + "addresses_hex": [ + "H'F852" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0" + }, + "instruction": "MOV:G.B R5, @H'F852" + }, + { + "instruction_address": 47915, + "instruction_address_hex": "H'BB2B", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R5", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5" + }, + "instruction": "MOV:G.B R5, @H'F851" + }, + { + "instruction_address": 47929, + "instruction_address_hex": "H'BB39", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + "instruction": "MOV:G.B R4, @H'F854" + }, + { + "instruction_address": 47935, + "instruction_address_hex": "H'BB3F", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R4", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R4, @H'F853" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCCD", + "kind": "response_staging_candidate", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48297, + "window_start_hex": "H'BCA9", + "writes": [ + { + "instruction_address": 48304, + "instruction_address_hex": "H'BCB0", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48313, + "instruction_address_hex": "H'BCB9", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48321, + "instruction_address_hex": "H'BCC1", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48329, + "instruction_address_hex": "H'BCC9", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48309, + "instruction_address_hex": "H'BCB5", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48317, + "instruction_address_hex": "H'BCBD", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48325, + "instruction_address_hex": "H'BCC5", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329, + 48309, + 48317, + 48325, + 48333 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9", + "H'BCB5", + "H'BCBD", + "H'BCC5", + "H'BCCD" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BCFA", + "kind": "response_staging_candidate", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48343, + "window_start_hex": "H'BCD7", + "writes": [ + { + "instruction_address": 48343, + "instruction_address_hex": "H'BCD7", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04" + }, + "instruction": "MOV:G.B #H'04, @H'F850" + }, + { + "instruction_address": 48352, + "instruction_address_hex": "H'BCE0", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48348, + "evidence_address_hex": "H'BCDC", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48360, + "instruction_address_hex": "H'BCE8", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48368, + "instruction_address_hex": "H'BCF0", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + }, + { + "instruction_address": 48374, + "instruction_address_hex": "H'BCF6", + "addresses": [ + 63571 + ], + "addresses_hex": [ + "H'F853" + ], + "source_operand": "R0", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ] + }, + "instruction": "MOV:G.B R0, @H'F853" + } + ], + "rx_reads": [ + { + "instruction_address": 48348, + "instruction_address_hex": "H'BCDC", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48356, + "instruction_address_hex": "H'BCE4", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.B @H'F862, R0" + } + ], + "evidence_addresses": [ + 48343, + 48352, + 48360, + 48368, + 48374, + 48348, + 48356, + 48378 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE0", + "H'BCE8", + "H'BCF0", + "H'BCF6", + "H'BCDC", + "H'BCE4", + "H'BCFA" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ] + }, + { + "id": "response_at_BE22", + "kind": "response_staging_candidate", + "call_address": 48674, + "call_address_hex": "H'BE22", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48645, + "window_start_hex": "H'BE05", + "writes": [ + { + "instruction_address": 48649, + "instruction_address_hex": "H'BE09", + "addresses": [ + 63568, + 63569 + ], + "addresses_hex": [ + "H'F850", + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + }, + "instruction": "MOV:G.W R0, @H'F850" + }, + { + "instruction_address": 48657, + "instruction_address_hex": "H'BE11", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48665, + "instruction_address_hex": "H'BE19", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + }, + "instruction": "MOV:G.W R0, @H'F854" + } + ], + "rx_reads": [], + "evidence_addresses": [ + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [] + }, + { + "id": "response_at_BE6A", + "kind": "response_staging_candidate", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "window_start": 48717, + "window_start_hex": "H'BE4D", + "writes": [ + { + "instruction_address": 48717, + "instruction_address_hex": "H'BE4D", + "addresses": [ + 63568 + ], + "addresses_hex": [ + "H'F850" + ], + "source_operand": "#H'07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07" + }, + "instruction": "MOV:G.B #H'07, @H'F850" + }, + { + "instruction_address": 48726, + "instruction_address_hex": "H'BE56", + "addresses": [ + 63569 + ], + "addresses_hex": [ + "H'F851" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + }, + "instruction": "MOV:G.B R0, @H'F851" + }, + { + "instruction_address": 48734, + "instruction_address_hex": "H'BE5E", + "addresses": [ + 63570, + 63571 + ], + "addresses_hex": [ + "H'F852", + "H'F853" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + }, + "instruction": "MOV:G.W R0, @H'F852" + }, + { + "instruction_address": 48742, + "instruction_address_hex": "H'BE66", + "addresses": [ + 63572 + ], + "addresses_hex": [ + "H'F854" + ], + "source_operand": "R0", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + }, + "instruction": "MOV:G.B R0, @H'F854" + } + ], + "rx_reads": [ + { + "instruction_address": 48722, + "instruction_address_hex": "H'BE52", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "instruction": "MOV:G.B @H'F861, R0" + }, + { + "instruction_address": 48730, + "instruction_address_hex": "H'BE5A", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "instruction": "MOV:G.W @H'F862, R0" + }, + { + "instruction_address": 48738, + "instruction_address_hex": "H'BE62", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "instruction": "MOV:G.B @H'F864, R0" + } + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "medium", + "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.", + "schema": { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + "byte_schema": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ] + } + ], + "response_schemas": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "response_schema": [ + { + "kind": "response_schema_candidate", + "response_id": "response_at_BB43", + "call_address": 47939, + "call_address_hex": "H'BB43", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R1", + "source_category": "computed", + "operation": "AND", + "evidence_address": 47897, + "evidence_address_hex": "H'BB19", + "instruction": "AND.B #H'07, R1", + "byte_index": 0 + }, + "write_instruction_address": 47900, + "write_instruction_address_hex": "H'BB1C", + "instruction": "MOV:G.B R1, @H'F850", + "evidence_addresses": [ + 47900 + ], + "evidence_addresses_hex": [ + "H'BB1C" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "R5", + "source_category": "computed", + "operation": "OR", + "evidence_address": 47913, + "evidence_address_hex": "H'BB29", + "instruction": "OR.B R2, R5", + "byte_index": 0 + }, + "write_instruction_address": 47915, + "write_instruction_address_hex": "H'BB2B", + "instruction": "MOV:G.B R5, @H'F851", + "evidence_addresses": [ + 47915 + ], + "evidence_addresses_hex": [ + "H'BB2B" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "computed", + "source_expression": "computed", + "source": { + "kind": "register_or_computed", + "operand": "@(-H'0790,R0)", + "source_category": "computed", + "evidence_address": 47880, + "evidence_address_hex": "H'BB08", + "instruction": "MOV:G.W @(-H'0790,R0), R0", + "byte_index": 0 + }, + "write_instruction_address": 47904, + "write_instruction_address_hex": "H'BB20", + "instruction": "MOV:G.B R5, @H'F852", + "evidence_addresses": [ + 47904 + ], + "evidence_addresses_hex": [ + "H'BB20" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 47935, + "write_instruction_address_hex": "H'BB3F", + "instruction": "MOV:G.B R4, @H'F853", + "evidence_addresses": [ + 47935 + ], + "evidence_addresses_hex": [ + "H'BB3F" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "current_value_table_candidate", + "source": { + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "operand": "@(-H'1800,R0)", + "kind": "table", + "access_width": 2, + "evidence_address": 47925, + "evidence_address_hex": "H'BB35", + "instruction": "MOV:G.W @(-H'1800,R0), R4", + "byte_index": 0 + }, + "write_instruction_address": 47929, + "write_instruction_address_hex": "H'BB39", + "instruction": "MOV:G.B R4, @H'F854", + "evidence_addresses": [ + 47929 + ], + "evidence_addresses_hex": [ + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 47900, + 47915, + 47904, + 47935, + 47929 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB2B", + "H'BB20", + "H'BB3F", + "H'BB39" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCCD", + "call_address": 48333, + "call_address_hex": "H'BCCD", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48304, + "write_instruction_address_hex": "H'BCB0", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48304 + ], + "evidence_addresses_hex": [ + "H'BCB0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48309, + "evidence_address_hex": "H'BCB5", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48313, + "write_instruction_address_hex": "H'BCB9", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48313 + ], + "evidence_addresses_hex": [ + "H'BCB9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48317, + "evidence_address_hex": "H'BCBD", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48321, + "write_instruction_address_hex": "H'BCC1", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48321 + ], + "evidence_addresses_hex": [ + "H'BCC1" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48325, + "evidence_address_hex": "H'BCC5", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48329, + "write_instruction_address_hex": "H'BCC9", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48329 + ], + "evidence_addresses_hex": [ + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48304, + 48313, + 48321, + 48329 + ], + "evidence_addresses_hex": [ + "H'BCB0", + "H'BCB9", + "H'BCC1", + "H'BCC9" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BCFA", + "call_address": 48378, + "call_address_hex": "H'BCFA", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x04", + "source": { + "kind": "immediate", + "value": 4, + "value_hex": "H'04", + "byte_index": 0 + }, + "write_instruction_address": 48343, + "write_instruction_address_hex": "H'BCD7", + "instruction": "MOV:G.B #H'04, @H'F850", + "evidence_addresses": [ + 48343 + ], + "evidence_addresses_hex": [ + "H'BCD7" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_offsets": [ + 2 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48356, + "evidence_address_hex": "H'BCE4", + "instruction": "MOV:G.B @H'F862, R0" + } + }, + "write_instruction_address": 48360, + "write_instruction_address_hex": "H'BCE8", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48360 + ], + "evidence_addresses_hex": [ + "H'BCE8" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "stale_or_unchanged", + "source_expression": "stale/unchanged", + "source": { + "kind": "unknown" + }, + "evidence_addresses": [], + "evidence_addresses_hex": [], + "confidence": "candidate-low", + "caveat": "BCD7 does not freshly write F852 before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "transforms": [ + "swap_bytes" + ], + "byte_index": 0 + }, + "write_instruction_address": 48374, + "write_instruction_address_hex": "H'BCF6", + "instruction": "MOV:G.B R0, @H'F853", + "evidence_addresses": [ + 48374 + ], + "evidence_addresses_hex": [ + "H'BCF6" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "table", + "source_expression": "primary_value_table_candidate", + "source": { + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "operand": "@(-H'2000,R4)", + "kind": "table", + "access_width": 2, + "evidence_address": 48364, + "evidence_address_hex": "H'BCEC", + "instruction": "MOV:G.W @(-H'2000,R4), R0", + "byte_index": 0 + }, + "write_instruction_address": 48368, + "write_instruction_address_hex": "H'BCF0", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48368 + ], + "evidence_addresses_hex": [ + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.", + "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.", + "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape." + ], + "evidence_addresses": [ + 48343, + 48360, + 48374, + 48368 + ], + "evidence_addresses_hex": [ + "H'BCD7", + "H'BCE8", + "H'BCF6", + "H'BCF0" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE22", + "call_address": 48674, + "call_address_hex": "H'BE22", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "tx_frame_byte", + "source_expression": "tx[0]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 0, + "tx_address": 63576, + "tx_address_hex": "H'F858", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "tx_frame_byte", + "source_expression": "tx[1]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 1, + "tx_address": 63577, + "tx_address_hex": "H'F859", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 0, + "tx_offsets": [ + 0, + 1 + ], + "tx_address": 63576, + "tx_address_hex": "H'F858", + "evidence_address": 48645, + "evidence_address_hex": "H'BE05", + "instruction": "MOV:G.W @H'F858, R0" + } + }, + "write_instruction_address": 48649, + "write_instruction_address_hex": "H'BE09", + "instruction": "MOV:G.W R0, @H'F850", + "evidence_addresses": [ + 48649 + ], + "evidence_addresses_hex": [ + "H'BE09" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "tx_frame_byte", + "source_expression": "tx[2]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 2, + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "tx_frame_byte", + "source_expression": "tx[3]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 3, + "tx_address": 63579, + "tx_address_hex": "H'F85B", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 2, + "tx_offsets": [ + 2, + 3 + ], + "tx_address": 63578, + "tx_address_hex": "H'F85A", + "evidence_address": 48653, + "evidence_address_hex": "H'BE0D", + "instruction": "MOV:G.W @H'F85A, R0" + } + }, + "write_instruction_address": 48657, + "write_instruction_address_hex": "H'BE11", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48657 + ], + "evidence_addresses_hex": [ + "H'BE11" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "tx_frame_byte", + "source_expression": "tx[4]", + "source": { + "kind": "tx_frame_byte", + "tx_offset": 4, + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "derived_from": { + "kind": "tx_frame_word", + "tx_offset": 4, + "tx_offsets": [ + 4, + 5 + ], + "tx_address": 63580, + "tx_address_hex": "H'F85C", + "evidence_address": 48661, + "evidence_address_hex": "H'BE15", + "instruction": "MOV:G.W @H'F85C, R0" + } + }, + "write_instruction_address": 48665, + "write_instruction_address_hex": "H'BE19", + "instruction": "MOV:G.W R0, @H'F854", + "evidence_addresses": [ + 48665 + ], + "evidence_addresses_hex": [ + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [], + "evidence_addresses": [ + 48649, + 48657, + 48665 + ], + "evidence_addresses_hex": [ + "H'BE09", + "H'BE11", + "H'BE19" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + }, + { + "kind": "response_schema_candidate", + "response_id": "response_at_BE6A", + "call_address": 48746, + "call_address_hex": "H'BE6A", + "buffer_start": 63568, + "buffer_start_hex": "H'F850", + "buffer_end": 63572, + "buffer_end_hex": "H'F854", + "bytes": [ + { + "offset": 0, + "byte": "byte0", + "tx_byte": "TX[0]", + "tx_staging_byte": "TX[0]", + "address": 63568, + "address_hex": "H'F850", + "source_kind": "immediate", + "source_expression": "0x07", + "source": { + "kind": "immediate", + "value": 7, + "value_hex": "H'07", + "byte_index": 0 + }, + "write_instruction_address": 48717, + "write_instruction_address_hex": "H'BE4D", + "instruction": "MOV:G.B #H'07, @H'F850", + "evidence_addresses": [ + 48717 + ], + "evidence_addresses_hex": [ + "H'BE4D" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 1, + "byte": "byte1", + "tx_byte": "TX[1]", + "tx_staging_byte": "TX[1]", + "address": 63569, + "address_hex": "H'F851", + "source_kind": "rx_frame_byte", + "source_expression": "rx[1]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_address": 63585, + "rx_address_hex": "H'F861", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 1, + "rx_offsets": [ + 1 + ], + "rx_address": 63585, + "rx_address_hex": "H'F861", + "evidence_address": 48722, + "evidence_address_hex": "H'BE52", + "instruction": "MOV:G.B @H'F861, R0" + } + }, + "write_instruction_address": 48726, + "write_instruction_address_hex": "H'BE56", + "instruction": "MOV:G.B R0, @H'F851", + "evidence_addresses": [ + 48726 + ], + "evidence_addresses_hex": [ + "H'BE56" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 2, + "byte": "byte2", + "tx_byte": "TX[2]", + "tx_staging_byte": "TX[2]", + "address": 63570, + "address_hex": "H'F852", + "source_kind": "rx_frame_byte", + "source_expression": "rx[2]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 2, + "rx_address": 63586, + "rx_address_hex": "H'F862", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 3, + "byte": "byte3", + "tx_byte": "TX[3]", + "tx_staging_byte": "TX[3]", + "address": 63571, + "address_hex": "H'F853", + "source_kind": "rx_frame_byte", + "source_expression": "rx[3]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 3, + "rx_address": 63587, + "rx_address_hex": "H'F863", + "derived_from": { + "kind": "rx_frame_word", + "rx_offset": 2, + "rx_offsets": [ + 2, + 3 + ], + "rx_address": 63586, + "rx_address_hex": "H'F862", + "evidence_address": 48730, + "evidence_address_hex": "H'BE5A", + "instruction": "MOV:G.W @H'F862, R0" + } + }, + "write_instruction_address": 48734, + "write_instruction_address_hex": "H'BE5E", + "instruction": "MOV:G.W R0, @H'F852", + "evidence_addresses": [ + 48734 + ], + "evidence_addresses_hex": [ + "H'BE5E" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + }, + { + "offset": 4, + "byte": "byte4", + "tx_byte": "TX[4]", + "tx_staging_byte": "TX[4]", + "address": 63572, + "address_hex": "H'F854", + "source_kind": "rx_frame_byte", + "source_expression": "rx[4]", + "source": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_address": 63588, + "rx_address_hex": "H'F864", + "derived_from": { + "kind": "rx_frame_byte", + "rx_offset": 4, + "rx_offsets": [ + 4 + ], + "rx_address": 63588, + "rx_address_hex": "H'F864", + "evidence_address": 48738, + "evidence_address_hex": "H'BE62", + "instruction": "MOV:G.B @H'F864, R0" + } + }, + "write_instruction_address": 48742, + "write_instruction_address_hex": "H'BE66", + "instruction": "MOV:G.B R0, @H'F854", + "evidence_addresses": [ + 48742 + ], + "evidence_addresses_hex": [ + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26." + } + ], + "semantic_notes": [ + "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.", + "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value." + ], + "evidence_addresses": [ + 48717, + 48726, + 48734, + 48742 + ], + "evidence_addresses_hex": [ + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66" + ], + "confidence": "candidate-medium", + "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call." + } + ], + "send_builder": { + "kind": "tx_send_builder_candidate", + "label": "loc_BA26", + "address": 47654, + "address_hex": "H'BA26", + "staging_buffer_start": 63568, + "staging_buffer_start_hex": "H'F850", + "staging_buffer_end": 63572, + "staging_buffer_end_hex": "H'F854", + "tx_frame_start": 63576, + "tx_frame_start_hex": "H'F858", + "tx_frame_end": 63581, + "tx_frame_end_hex": "H'F85D", + "checksum_address": 63581, + "checksum_address_hex": "H'F85D", + "checksum_seed": 90, + "checksum_seed_hex": "H'005A", + "staging_to_frame_copies": [], + "response_call_addresses": [ + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "response_call_addresses_hex": [ + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate", + "evidence_addresses": [ + 47674, + 47682, + 47690, + 47696, + 47700, + 47704, + 47708, + 47712, + 47716, + 47726, + 47939, + 48333, + 48378, + 48674, + 48746 + ], + "evidence_addresses_hex": [ + "H'BA3A", + "H'BA42", + "H'BA4A", + "H'BA50", + "H'BA54", + "H'BA58", + "H'BA5C", + "H'BA60", + "H'BA64", + "H'BA6E", + "H'BB43", + "H'BCCD", + "H'BCFA", + "H'BE22", + "H'BE6A" + ], + "confidence": "low", + "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission." + }, + "logical_table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 23113, + "instruction_address_hex": "H'5A49", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R1), R1" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 23113, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'5A49", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23081, + "instruction_address_hex": "H'5A29", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23097, + "instruction_address_hex": "H'5A39", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23105, + "instruction_address_hex": "H'5A41", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23450, + "instruction_address_hex": "H'5B9A", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23466, + "instruction_address_hex": "H'5BAA", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23474, + "instruction_address_hex": "H'5BB2", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23582, + "instruction_address_hex": "H'5C1E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23598, + "instruction_address_hex": "H'5C2E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23606, + "instruction_address_hex": "H'5C36", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23081, + 23097, + 23105, + 23450, + 23466, + 23474, + 23582, + 23598, + 23606, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5A29", + "H'5A39", + "H'5A41", + "H'5B9A", + "H'5BAA", + "H'5BB2", + "H'5C1E", + "H'5C2E", + "H'5C36", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "table_map_candidates": [ + { + "kind": "logical_table_map_candidate", + "name_candidate": "primary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 57344, + "logical_base_address_hex": "H'E000", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 6627, + "instruction_address_hex": "H'19E3", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6659, + "instruction_address_hex": "H'1A03", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R1" + }, + { + "instruction_address": 6717, + "instruction_address_hex": "H'1A3D", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 6763, + "instruction_address_hex": "H'1A6B", + "operand": "@(-H'2000,R3)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'2000,R3), R0" + }, + { + "instruction_address": 16268, + "instruction_address_hex": "H'3F8C", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 16503, + "instruction_address_hex": "H'4077", + "operand": "@(-H'2000,R0)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'2000,R0)" + }, + { + "instruction_address": 23113, + "instruction_address_hex": "H'5A49", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R1), R1" + }, + { + "instruction_address": 24701, + "instruction_address_hex": "H'607D", + "operand": "@(-H'2000,R1)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R1", + "access": "read", + "width": 1, + "instruction": "MOV:G.B @(-H'2000,R1), R0" + }, + { + "instruction_address": 48245, + "instruction_address_hex": "H'BC75", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48277, + "instruction_address_hex": "H'BC95", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48364, + "instruction_address_hex": "H'BCEC", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'2000,R4), R0" + }, + { + "instruction_address": 48410, + "instruction_address_hex": "H'BD1A", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + }, + { + "instruction_address": 48437, + "instruction_address_hex": "H'BD35", + "operand": "@(-H'2000,R4)", + "negative_offset": 8192, + "negative_offset_hex": "H'2000", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'2000,R4)" + } + ], + "evidence_addresses": [ + 6627, + 6659, + 6717, + 6763, + 16268, + 16503, + 23113, + 24701, + 48245, + 48277, + 48364, + 48410, + 48437 + ], + "evidence_addresses_hex": [ + "H'19E3", + "H'1A03", + "H'1A3D", + "H'1A6B", + "H'3F8C", + "H'4077", + "H'5A49", + "H'607D", + "H'BC75", + "H'BC95", + "H'BCEC", + "H'BD1A", + "H'BD35" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "secondary_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 58368, + "logical_base_address_hex": "H'E400", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "observed_index_registers": [ + "R0", + "R1", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6570, + "instruction_address_hex": "H'19AA", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R0" + }, + { + "instruction_address": 6731, + "instruction_address_hex": "H'1A4B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6747, + "instruction_address_hex": "H'1A5B", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6785, + "instruction_address_hex": "H'1A81", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "AND.W @(-H'1C00,R3), R1" + }, + { + "instruction_address": 6836, + "instruction_address_hex": "H'1AB4", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 6849, + "instruction_address_hex": "H'1AC1", + "operand": "@(-H'1C00,R3)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R3", + "access": "read", + "width": 2, + "instruction": "BTST.W R0, @(-H'1C00,R3)" + }, + { + "instruction_address": 16507, + "instruction_address_hex": "H'407B", + "operand": "@(-H'1C00,R0)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1C00,R0)" + }, + { + "instruction_address": 23081, + "instruction_address_hex": "H'5A29", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23097, + "instruction_address_hex": "H'5A39", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23105, + "instruction_address_hex": "H'5A41", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23450, + "instruction_address_hex": "H'5B9A", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23466, + "instruction_address_hex": "H'5BAA", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23474, + "instruction_address_hex": "H'5BB2", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23582, + "instruction_address_hex": "H'5C1E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23598, + "instruction_address_hex": "H'5C2E", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23606, + "instruction_address_hex": "H'5C36", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23715, + "instruction_address_hex": "H'5CA3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23731, + "instruction_address_hex": "H'5CB3", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23739, + "instruction_address_hex": "H'5CBB", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23847, + "instruction_address_hex": "H'5D27", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23863, + "instruction_address_hex": "H'5D37", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 23871, + "instruction_address_hex": "H'5D3F", + "operand": "@(-H'1C00,R1)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R1", + "access": "read", + "width": 2, + "instruction": "CMP:G.W @(-H'1C00,R1), R2" + }, + { + "instruction_address": 48613, + "instruction_address_hex": "H'BDE5", + "operand": "@(-H'1C00,R4)", + "negative_offset": 7168, + "negative_offset_hex": "H'1C00", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1C00,R4)" + } + ], + "evidence_addresses": [ + 6570, + 6731, + 6747, + 6785, + 6836, + 6849, + 16507, + 23081, + 23097, + 23105, + 23450, + 23466, + 23474, + 23582, + 23598, + 23606, + 23715, + 23731, + 23739, + 23847, + 23863, + 23871, + 48613 + ], + "evidence_addresses_hex": [ + "H'19AA", + "H'1A4B", + "H'1A5B", + "H'1A81", + "H'1AB4", + "H'1AC1", + "H'407B", + "H'5A29", + "H'5A39", + "H'5A41", + "H'5B9A", + "H'5BAA", + "H'5BB2", + "H'5C1E", + "H'5C2E", + "H'5C36", + "H'5CA3", + "H'5CB3", + "H'5CBB", + "H'5D27", + "H'5D37", + "H'5D3F", + "H'BDE5" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "current_value_table_candidate", + "element_candidate": "word_value", + "logical_base_address": 59392, + "logical_base_address_hex": "H'E800", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "observed_index_registers": [ + "R0", + "R3", + "R4" + ], + "observed_accesses": [ + "read", + "write" + ], + "observed_widths": [ + 2 + ], + "accesses": [ + { + "instruction_address": 6665, + "instruction_address_hex": "H'1A09", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R1, @(-H'1800,R3)" + }, + { + "instruction_address": 6769, + "instruction_address_hex": "H'1A71", + "operand": "@(-H'1800,R3)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R3", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R3)" + }, + { + "instruction_address": 16272, + "instruction_address_hex": "H'3F90", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 16511, + "instruction_address_hex": "H'407F", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1800,R0)" + }, + { + "instruction_address": 47925, + "instruction_address_hex": "H'BB35", + "operand": "@(-H'1800,R0)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R0", + "access": "read", + "width": 2, + "instruction": "MOV:G.W @(-H'1800,R0), R4" + }, + { + "instruction_address": 48249, + "instruction_address_hex": "H'BC79", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48281, + "instruction_address_hex": "H'BC99", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + }, + { + "instruction_address": 48414, + "instruction_address_hex": "H'BD1E", + "operand": "@(-H'1800,R4)", + "negative_offset": 6144, + "negative_offset_hex": "H'1800", + "index_register": "R4", + "access": "write", + "width": 2, + "instruction": "MOV:G.W R0, @(-H'1800,R4)" + } + ], + "evidence_addresses": [ + 6665, + 6769, + 16272, + 16511, + 47925, + 48249, + 48281, + 48414 + ], + "evidence_addresses_hex": [ + "H'1A09", + "H'1A71", + "H'3F90", + "H'407F", + "H'BB35", + "H'BC79", + "H'BC99", + "H'BD1E" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + }, + { + "kind": "logical_table_map_candidate", + "name_candidate": "flag_table_candidate", + "element_candidate": "bit_flags", + "logical_base_address": 60416, + "logical_base_address_hex": "H'EC00", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "observed_index_registers": [ + "R0", + "R5" + ], + "observed_accesses": [ + "write" + ], + "observed_widths": [ + 1, + 2 + ], + "accesses": [ + { + "instruction_address": 16520, + "instruction_address_hex": "H'4088", + "operand": "@(-H'1400,R0)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R0", + "access": "write", + "width": 2, + "instruction": "CLR.W @(-H'1400,R0)" + }, + { + "instruction_address": 48258, + "instruction_address_hex": "H'BC82", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48285, + "instruction_address_hex": "H'BC9D", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48418, + "instruction_address_hex": "H'BD22", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48441, + "instruction_address_hex": "H'BD39", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #7, @(-H'1400,R5)" + }, + { + "instruction_address": 48617, + "instruction_address_hex": "H'BDE9", + "operand": "@(-H'1400,R5)", + "negative_offset": 5120, + "negative_offset_hex": "H'1400", + "index_register": "R5", + "access": "write", + "width": 1, + "instruction": "BSET.B #6, @(-H'1400,R5)" + } + ], + "evidence_addresses": [ + 16520, + 48258, + 48285, + 48418, + 48441, + 48617 + ], + "evidence_addresses_hex": [ + "H'4088", + "H'BC82", + "H'BC9D", + "H'BD22", + "H'BD39", + "H'BDE9" + ], + "confidence": "candidate-medium", + "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate." + } + ], + "state_variable_candidates": [ + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_session_flags_candidate", + "address": 64162, + "address_hex": "H'FAA2", + "access_count": 18, + "read_count": 5, + "write_count": 13, + "bit_candidates": [ + 3, + 7 + ], + "immediate_values": [ + 3, + 7 + ], + "immediate_values_hex": [ + "H'0003", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47748, + "instruction_address_hex": "H'BA84", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47766, + "instruction_address_hex": "H'BA96", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 47872, + "instruction_address_hex": "H'BB00", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48143, + "instruction_address_hex": "H'BC0F", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'FAA2" + }, + { + "instruction_address": 48149, + "instruction_address_hex": "H'BC15", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48179, + "instruction_address_hex": "H'BC33", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48220, + "instruction_address_hex": "H'BC5C", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48336, + "instruction_address_hex": "H'BCD0", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48381, + "instruction_address_hex": "H'BCFD", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48388, + "instruction_address_hex": "H'BD04", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA2", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48487, + "instruction_address_hex": "H'BD67", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48505, + "instruction_address_hex": "H'BD79", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48578, + "instruction_address_hex": "H'BDC2", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48596, + "instruction_address_hex": "H'BDD4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48621, + "instruction_address_hex": "H'BDED", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #3, @H'FAA2", + "bit": 3, + "immediate": 3, + "immediate_hex": "H'03" + }, + { + "instruction_address": 48639, + "instruction_address_hex": "H'BDFF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48711, + "instruction_address_hex": "H'BE47", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + }, + { + "instruction_address": 48815, + "instruction_address_hex": "H'BEAF", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA2" + } + ], + "evidence_addresses": [ + 47748, + 47766, + 47872, + 48143, + 48149, + 48179, + 48220, + 48336, + 48381, + 48388, + 48487, + 48505, + 48578, + 48596, + 48621, + 48639, + 48711, + 48815 + ], + "evidence_addresses_hex": [ + "H'BA84", + "H'BA96", + "H'BB00", + "H'BC0F", + "H'BC15", + "H'BC33", + "H'BC5C", + "H'BCD0", + "H'BCFD", + "H'BD04", + "H'BD67", + "H'BD79", + "H'BDC2", + "H'BDD4", + "H'BDED", + "H'BDFF", + "H'BE47", + "H'BEAF" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_pending_mask_candidate", + "address": 64163, + "address_hex": "H'FAA3", + "access_count": 10, + "read_count": 1, + "write_count": 9, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 128, + 7 + ], + "immediate_values_hex": [ + "H'0080", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47770, + "instruction_address_hex": "H'BA9A", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 47953, + "instruction_address_hex": "H'BB51", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'80, @H'FAA3", + "immediate": 128, + "immediate_hex": "H'80" + }, + { + "instruction_address": 48227, + "instruction_address_hex": "H'BC63", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48501, + "instruction_address_hex": "H'BD75", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48592, + "instruction_address_hex": "H'BDD0", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48635, + "instruction_address_hex": "H'BDFB", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48707, + "instruction_address_hex": "H'BE43", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA3" + }, + { + "instruction_address": 48805, + "instruction_address_hex": "H'BEA5", + "access": "write", + "mnemonic": "AND.B", + "instruction": "AND.B @H'FAA3, R0" + }, + { + "instruction_address": 48809, + "instruction_address_hex": "H'BEA9", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B R0, @H'FAA3" + }, + { + "instruction_address": 48843, + "instruction_address_hex": "H'BECB", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA3", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47770, + 47953, + 48227, + 48501, + 48592, + 48635, + 48707, + 48805, + 48809, + 48843 + ], + "evidence_addresses_hex": [ + "H'BA9A", + "H'BB51", + "H'BC63", + "H'BD75", + "H'BDD0", + "H'BDFB", + "H'BE43", + "H'BEA5", + "H'BEA9", + "H'BECB" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_rx_error_or_retry_gate_candidate", + "address": 64164, + "address_hex": "H'FAA4", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 47959, + "instruction_address_hex": "H'BB57", + "access": "write", + "mnemonic": "BSET.B", + "instruction": "BSET.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48004, + "instruction_address_hex": "H'BB84", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA4" + }, + { + "instruction_address": 48079, + "instruction_address_hex": "H'BBCF", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48681, + "instruction_address_hex": "H'BE29", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'FAA4", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 47959, + 48004, + 48079, + 48681 + ], + "evidence_addresses_hex": [ + "H'BB57", + "H'BB84", + "H'BBCF", + "H'BE29" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_enable_or_mode_flags_candidate", + "address": 64165, + "address_hex": "H'FAA5", + "access_count": 4, + "read_count": 4, + "write_count": 0, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 7 + ], + "immediate_values_hex": [ + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16460, + "instruction_address_hex": "H'404C", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 47754, + "instruction_address_hex": "H'BA8A", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48685, + "instruction_address_hex": "H'BE2D", + "access": "read", + "mnemonic": "BTST.B", + "instruction": "BTST.B #7, @H'FAA5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48798, + "instruction_address_hex": "H'BE9E", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'FAA5, R0" + } + ], + "evidence_addresses": [ + 16460, + 47754, + 48685, + 48798 + ], + "evidence_addresses_hex": [ + "H'404C", + "H'BA8A", + "H'BE2D", + "H'BE9E" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_retry_counter_candidate", + "address": 64166, + "address_hex": "H'FAA6", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 1, + 2 + ], + "immediate_values_hex": [ + "H'0001", + "H'0002" + ], + "accesses": [ + { + "instruction_address": 48115, + "instruction_address_hex": "H'BBF3", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'FAA6" + }, + { + "instruction_address": 48691, + "instruction_address_hex": "H'BE33", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'FAA6", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48695, + "instruction_address_hex": "H'BE37", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B #H'02, @H'FAA6", + "immediate": 2, + "immediate_hex": "H'02" + } + ], + "evidence_addresses": [ + 48115, + 48691, + 48695 + ], + "evidence_addresses_hex": [ + "H'BBF3", + "H'BE33", + "H'BE37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_read_cursor_candidate", + "address": 63924, + "address_hex": "H'F9B4", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [ + 5 + ], + "immediate_values": [ + 1, + 5 + ], + "immediate_values_hex": [ + "H'0001", + "H'0005" + ], + "accesses": [ + { + "instruction_address": 48760, + "instruction_address_hex": "H'BE78", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B4, R1" + }, + { + "instruction_address": 48789, + "instruction_address_hex": "H'BE95", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B4", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48793, + "instruction_address_hex": "H'BE99", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #5, @H'F9B4", + "bit": 5, + "immediate": 5, + "immediate_hex": "H'05" + } + ], + "evidence_addresses": [ + 48760, + 48789, + 48793 + ], + "evidence_addresses_hex": [ + "H'BE78", + "H'BE95", + "H'BE99" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_write_or_pending_cursor_candidate", + "address": 63925, + "address_hex": "H'F9B5", + "access_count": 8, + "read_count": 2, + "write_count": 6, + "bit_candidates": [ + 7 + ], + "immediate_values": [ + 1, + 7 + ], + "immediate_values_hex": [ + "H'0001", + "H'0007" + ], + "accesses": [ + { + "instruction_address": 16479, + "instruction_address_hex": "H'405F", + "access": "read", + "mnemonic": "CMP:G.B", + "instruction": "CMP:G.B @H'F9B5, R2" + }, + { + "instruction_address": 47858, + "instruction_address_hex": "H'BAF2", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B5, R1" + }, + { + "instruction_address": 48493, + "instruction_address_hex": "H'BD6D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48497, + "instruction_address_hex": "H'BD71", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48584, + "instruction_address_hex": "H'BDC8", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48588, + "instruction_address_hex": "H'BDCC", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48627, + "instruction_address_hex": "H'BDF3", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #1, @H'F9B5", + "immediate": 1, + "immediate_hex": "H'01" + }, + { + "instruction_address": 48631, + "instruction_address_hex": "H'BDF7", + "access": "write", + "mnemonic": "BCLR.B", + "instruction": "BCLR.B #7, @H'F9B5", + "bit": 7, + "immediate": 7, + "immediate_hex": "H'07" + } + ], + "evidence_addresses": [ + 16479, + 47858, + 48493, + 48497, + 48584, + 48588, + 48627, + 48631 + ], + "evidence_addresses_hex": [ + "H'405F", + "H'BAF2", + "H'BD6D", + "H'BD71", + "H'BDC8", + "H'BDCC", + "H'BDF3", + "H'BDF7" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "event_queue_base_or_current_slot_candidate", + "address": 63929, + "address_hex": "H'F9B9", + "access_count": 1, + "read_count": 1, + "write_count": 0, + "bit_candidates": [], + "immediate_values": [], + "immediate_values_hex": [], + "accesses": [ + { + "instruction_address": 48752, + "instruction_address_hex": "H'BE70", + "access": "read", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B @H'F9B9, R3" + } + ], + "evidence_addresses": [ + 48752 + ], + "evidence_addresses_hex": [ + "H'BE70" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "serial_tx_busy_timer_candidate", + "address": 63936, + "address_hex": "H'F9C0", + "access_count": 10, + "read_count": 2, + "write_count": 8, + "bit_candidates": [], + "immediate_values": [ + 100, + 31, + 9, + 240, + 65535 + ], + "immediate_values_hex": [ + "H'0064", + "H'001F", + "H'0009", + "H'00F0", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47654, + "instruction_address_hex": "H'BA26", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 47660, + "instruction_address_hex": "H'BA2C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'64, @H'F9C0", + "immediate": 100, + "immediate_hex": "H'64" + }, + { + "instruction_address": 47778, + "instruction_address_hex": "H'BAA2", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 47834, + "instruction_address_hex": "H'BADA", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47841, + "instruction_address_hex": "H'BAE1", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'09, @H'F9C0", + "immediate": 9, + "immediate_hex": "H'09" + }, + { + "instruction_address": 47848, + "instruction_address_hex": "H'BAE8", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'F0, @H'F9C0", + "immediate": 240, + "immediate_hex": "H'F0" + }, + { + "instruction_address": 48669, + "instruction_address_hex": "H'BE1D", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48702, + "instruction_address_hex": "H'BE3E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'1F, @H'F9C0", + "immediate": 31, + "immediate_hex": "H'1F" + }, + { + "instruction_address": 48878, + "instruction_address_hex": "H'BEEE", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C0" + }, + { + "instruction_address": 48884, + "instruction_address_hex": "H'BEF4", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C0", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47654, + 47660, + 47778, + 47834, + 47841, + 47848, + 48669, + 48702, + 48878, + 48884 + ], + "evidence_addresses_hex": [ + "H'BA26", + "H'BA2C", + "H'BAA2", + "H'BADA", + "H'BAE1", + "H'BAE8", + "H'BE1D", + "H'BE3E", + "H'BEEE", + "H'BEF4" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "address": 63940, + "address_hex": "H'F9C4", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 7, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'0007", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 16454, + "instruction_address_hex": "H'4046", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 16608, + "instruction_address_hex": "H'40E0", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C4", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 47665, + "instruction_address_hex": "H'BA31", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'07, @H'F9C4", + "immediate": 7, + "immediate_hex": "H'07" + }, + { + "instruction_address": 48935, + "instruction_address_hex": "H'BF27", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C4" + }, + { + "instruction_address": 48941, + "instruction_address_hex": "H'BF2D", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C4", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 16454, + 16608, + 47665, + 48935, + 48941 + ], + "evidence_addresses_hex": [ + "H'4046", + "H'40E0", + "H'BA31", + "H'BF27", + "H'BF2D" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "rx_session_timeout_candidate", + "address": 63941, + "address_hex": "H'F9C5", + "access_count": 4, + "read_count": 1, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 48030, + "instruction_address_hex": "H'BB9E", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C5", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48868, + "instruction_address_hex": "H'BEE4", + "access": "write", + "mnemonic": "CLR.B", + "instruction": "CLR.B @H'F9C5" + }, + { + "instruction_address": 48945, + "instruction_address_hex": "H'BF31", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C5" + }, + { + "instruction_address": 48951, + "instruction_address_hex": "H'BF37", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C5", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 48030, + 48868, + 48945, + 48951 + ], + "evidence_addresses_hex": [ + "H'BB9E", + "H'BEE4", + "H'BF31", + "H'BF37" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_period_timer_candidate", + "address": 63942, + "address_hex": "H'F9C6", + "access_count": 5, + "read_count": 2, + "write_count": 3, + "bit_candidates": [], + "immediate_values": [ + 500, + 65535 + ], + "immediate_values_hex": [ + "H'01F4", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47942, + "instruction_address_hex": "H'BB46", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48821, + "instruction_address_hex": "H'BEB5", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48837, + "instruction_address_hex": "H'BEC5", + "access": "write", + "mnemonic": "MOV:G.W", + "instruction": "MOV:G.W #H'01F4, @H'F9C6", + "immediate": 500, + "immediate_hex": "H'01F4" + }, + { + "instruction_address": 48898, + "instruction_address_hex": "H'BF02", + "access": "read", + "mnemonic": "TST.W", + "instruction": "TST.W @H'F9C6" + }, + { + "instruction_address": 48904, + "instruction_address_hex": "H'BF08", + "access": "write", + "mnemonic": "ADD:Q.W", + "instruction": "ADD:Q.W #-1, @H'F9C6", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47942, + 48821, + 48837, + 48898, + 48904 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEB5", + "H'BEC5", + "H'BF02", + "H'BF08" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + }, + { + "kind": "serial_state_variable_candidate", + "name_candidate": "autonomous_report_resend_countdown_candidate", + "address": 63944, + "address_hex": "H'F9C8", + "access_count": 3, + "read_count": 1, + "write_count": 2, + "bit_candidates": [], + "immediate_values": [ + 20, + 65535 + ], + "immediate_values_hex": [ + "H'0014", + "H'FFFF" + ], + "accesses": [ + { + "instruction_address": 47948, + "instruction_address_hex": "H'BB4C", + "access": "write", + "mnemonic": "MOV:G.B", + "instruction": "MOV:G.B #H'14, @H'F9C8", + "immediate": 20, + "immediate_hex": "H'14" + }, + { + "instruction_address": 48827, + "instruction_address_hex": "H'BEBB", + "access": "read", + "mnemonic": "TST.B", + "instruction": "TST.B @H'F9C8" + }, + { + "instruction_address": 48833, + "instruction_address_hex": "H'BEC1", + "access": "write", + "mnemonic": "ADD:Q.B", + "instruction": "ADD:Q.B #-1, @H'F9C8", + "immediate": 65535, + "immediate_hex": "H'FFFF" + } + ], + "evidence_addresses": [ + 47948, + 48827, + 48833 + ], + "evidence_addresses_hex": [ + "H'BB4C", + "H'BEBB", + "H'BEC1" + ], + "confidence": "candidate-medium", + "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate." + } + ], + "retry_error_model": { + "kind": "serial_retry_error_model_candidate", + "checksum_failure_path": { + "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]", + "error_target": "loc_BE29", + "error_target_address": 48681, + "error_target_address_hex": "H'BE29", + "checksum_error_response_candidates": [ + "response_at_BE6A" + ], + "branch_evidence_addresses": [ + 48112 + ], + "branch_evidence_addresses_hex": [ + "H'BBF0" + ], + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-high" + }, + "retry_path": { + "entry_label": "loc_BE29", + "entry_address": 48681, + "entry_address_hex": "H'BE29", + "counter_address": 64166, + "counter_address_hex": "H'FAA6", + "threshold_candidate": 2, + "response_candidates": [ + "response_at_BE6A" + ], + "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.", + "echo_response_candidate": { + "entry_label": "loc_BE4D", + "entry_address": 48717, + "entry_address_hex": "H'BE4D", + "staging_candidate": "F850=0x07; F851-F854=F861-F864", + "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value." + }, + "evidence_addresses": [ + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746 + ], + "evidence_addresses_hex": [ + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A" + ], + "confidence": "candidate-medium" + }, + "command_0x07_path": { + "entry_label": "loc_BE05", + "entry_address": 48645, + "entry_address_hex": "H'BE05", + "response_candidates": [ + "response_at_BE22" + ], + "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.", + "evidence_addresses": [ + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium" + }, + "evidence_addresses": [ + 48088, + 48092, + 48096, + 48100, + 48104, + 48108, + 48112, + 48717, + 48726, + 48734, + 48742, + 48722, + 48730, + 48738, + 48746, + 48681, + 48685, + 48691, + 48695, + 48707, + 48711, + 48645, + 48653, + 48661, + 48649, + 48657, + 48665, + 48674 + ], + "evidence_addresses_hex": [ + "H'BBD8", + "H'BBDC", + "H'BBE0", + "H'BBE4", + "H'BBE8", + "H'BBEC", + "H'BBF0", + "H'BE4D", + "H'BE56", + "H'BE5E", + "H'BE66", + "H'BE52", + "H'BE5A", + "H'BE62", + "H'BE6A", + "H'BE29", + "H'BE2D", + "H'BE33", + "H'BE37", + "H'BE43", + "H'BE47", + "H'BE05", + "H'BE0D", + "H'BE15", + "H'BE09", + "H'BE11", + "H'BE19", + "H'BE22" + ], + "confidence": "candidate-medium", + "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing." + }, + "gate_queue_model": { + "kind": "serial_gate_queue_state_machine_candidate", + "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.", + "predicates": [ + { + "name": "main_loop_may_enter_report_builder", + "entry_label": "loc_3FD3", + "target_label": "loc_BAF2", + "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))", + "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.", + "state_addresses_hex": [ + "H'FAA2", + "H'FAA5", + "H'F9C3", + "H'F9C0" + ], + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363 + ] + }, + { + "name": "idle_heartbeat_report_may_enqueue", + "entry_label": "loc_4046", + "target_label": "loc_4067", + "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5", + "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.", + "state_addresses_hex": [ + "H'F9C4", + "H'FAA5", + "H'F9C3", + "H'F9B0", + "H'F9B5" + ], + "enqueued_report_candidate_hex": "H'0000", + "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.", + "runtime_trace_confirmation": { + "source": "h8536_emulator_probe target-frame run", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF", + "dequeue_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_seed_hex": "H'5A", + "checksum_hex": "H'DA" + }, + "evidence_addresses": [ + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496 + ] + }, + { + "name": "queue_has_pending_report", + "entry_label": "loc_BAF2", + "condition_candidate": "F9B5 != F9B0", + "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.", + "state_addresses_hex": [ + "H'F9B5", + "H'F9B0" + ], + "staging_path": [ + "loc_BAF2", + "loc_BB43", + "loc_BA26" + ], + "evidence_addresses": [ + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939 + ] + }, + { + "name": "periodic_resend_may_fire", + "entry_label": "loc_BE9E", + "target_label": "loc_BED5", + "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown", + "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.", + "state_addresses_hex": [ + "H'FAA5", + "H'FAA3", + "H'F9C6", + "H'F9C8" + ], + "evidence_addresses": [ + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ] + } + ], + "session_effects": [ + { + "name": "rx_completion_sets_session_timer", + "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.", + "state_addresses_hex": [ + "H'F9C5" + ], + "evidence_addresses": [ + 48030 + ] + }, + { + "name": "session_timeout_clears_gate_and_queue", + "entry_label": "loc_3FEF", + "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.", + "state_addresses_hex": [ + "H'F9C5", + "H'F9B5", + "H'F9B0", + "H'FAA5" + ], + "evidence_addresses": [ + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391 + ] + }, + { + "name": "idle_heartbeat_gate_initial_delay_loaded", + "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'14", + "evidence_addresses": [ + 16608 + ] + }, + { + "name": "idle_heartbeat_gate_post_send_delay_loaded", + "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.", + "state_addresses_hex": [ + "H'F9C4" + ], + "reload_value_hex": "H'07", + "evidence_addresses": [ + 47665 + ] + }, + { + "name": "host_ack_can_advance_queue", + "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.", + "command_values_hex": [ + "H'05" + ], + "state_addresses_hex": [ + "H'FAA2", + "H'FAA3", + "H'F9B5" + ], + "evidence_addresses": [ + 48136, + 48140, + 48202, + 48204 + ] + } + ], + "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.", + "confidence": "candidate-medium", + "evidence_addresses": [ + 16339, + 16343, + 16345, + 16349, + 16351, + 16355, + 16357, + 16361, + 16363, + 16367, + 16371, + 16373, + 16377, + 16381, + 16385, + 16387, + 16389, + 16391, + 16454, + 16458, + 16460, + 16464, + 16466, + 16470, + 16472, + 16473, + 16477, + 16479, + 16483, + 16485, + 16487, + 16492, + 16496, + 47858, + 47862, + 47864, + 47868, + 47870, + 47872, + 47876, + 47878, + 47880, + 47884, + 47886, + 47889, + 47891, + 47893, + 47895, + 47897, + 47900, + 47904, + 47908, + 47910, + 47913, + 47915, + 47919, + 47923, + 47925, + 47929, + 47933, + 47935, + 47939, + 48798, + 48802, + 48805, + 48809, + 48813, + 48815, + 48819, + 48821, + 48825, + 48827, + 48831, + 48833, + 48837, + 48843, + 48847, + 48849, + 48853 + ], + "evidence_addresses_hex": [ + "H'3FD3", + "H'3FD7", + "H'3FD9", + "H'3FDD", + "H'3FDF", + "H'3FE3", + "H'3FE5", + "H'3FE9", + "H'3FEB", + "H'3FEF", + "H'3FF3", + "H'3FF5", + "H'3FF9", + "H'3FFD", + "H'4001", + "H'4003", + "H'4005", + "H'4007", + "H'4046", + "H'404A", + "H'404C", + "H'4050", + "H'4052", + "H'4056", + "H'4058", + "H'4059", + "H'405D", + "H'405F", + "H'4063", + "H'4065", + "H'4067", + "H'406C", + "H'4070", + "H'BAF2", + "H'BAF6", + "H'BAF8", + "H'BAFC", + "H'BAFE", + "H'BB00", + "H'BB04", + "H'BB06", + "H'BB08", + "H'BB0C", + "H'BB0E", + "H'BB11", + "H'BB13", + "H'BB15", + "H'BB17", + "H'BB19", + "H'BB1C", + "H'BB20", + "H'BB24", + "H'BB26", + "H'BB29", + "H'BB2B", + "H'BB2F", + "H'BB33", + "H'BB35", + "H'BB39", + "H'BB3D", + "H'BB3F", + "H'BB43", + "H'BE9E", + "H'BEA2", + "H'BEA5", + "H'BEA9", + "H'BEAD", + "H'BEAF", + "H'BEB3", + "H'BEB5", + "H'BEB9", + "H'BEBB", + "H'BEBF", + "H'BEC1", + "H'BEC5", + "H'BECB", + "H'BECF", + "H'BED1", + "H'BED5" + ] + }, + "tx_report_model": { + "kind": "bb43_to_ba26_tx_report_model_candidate", + "direction": "device_to_host_autonomous_report_candidate", + "entry_label": "loc_BB43", + "entry_address": 47939, + "entry_address_hex": "H'BB43", + "send_builder": "loc_BA26", + "send_builder_address": 47654, + "send_builder_address_hex": "H'BA26", + "response_candidates": [ + "response_at_BB43" + ], + "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.", + "byte_roles": [ + { + "offset": 0, + "field_candidate": "encoded_logical_index_or_report_id_byte0", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 1, + "field_candidate": "encoded_logical_index_or_report_id_byte1", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 2, + "field_candidate": "encoded_logical_index_or_report_id_byte2", + "source_candidate": "computed from candidate logical index/report id" + }, + { + "offset": 3, + "field_candidate": "current_value_hi", + "source_candidate": "current_value_table_candidate high byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 4, + "field_candidate": "current_value_lo", + "source_candidate": "current_value_table_candidate low byte", + "table_candidate": "current_value_table_candidate" + }, + { + "offset": 5, + "field_candidate": "checksum", + "source_candidate": "0x5A XOR TX[0..4]" + } + ], + "value_source_candidate": "current_value_table_candidate", + "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4", + "observed_capture_overlay_candidates": [ + { + "logical_index": 0, + "name_candidate": "heartbeat_or_idle_report_candidate", + "observed_frames_hex": [ + "00 00 00 00 80 DA" + ], + "observed_period_ms_candidate": 700 + }, + { + "logical_index": 21, + "name_candidate": "call_button_report_candidate", + "observed_frames_hex": [ + "00 00 15 80 00 CF", + "00 00 15 00 00 4F" + ] + }, + { + "logical_index": 7, + "name_candidate": "camera_power_report_candidate", + "observed_frames_hex": [ + "00 00 07 80 00 DD" + ] + } + ], + "runtime_confirmed_paths": [ + { + "name": "idle_heartbeat_report_runtime_confirmation", + "report_id_hex": "H'0000", + "queue_write_address_hex": "H'4067", + "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot", + "staging_path": [ + "loc_4046", + "loc_BAF2", + "loc_BB08", + "loc_BB1C", + "loc_BB20", + "loc_BB2B", + "loc_BA26" + ], + "emitted_frame_hex": "00 00 00 00 80 DA", + "checksum_hex": "H'DA" + } + ], + "consistency_checks": [ + { + "name": "idle_heartbeat_report_id_width", + "status": "pass", + "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000." + } + ], + "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.", + "confidence": "candidate-medium", + "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.", + "evidence_addresses": [ + 47900, + 47904, + 47915, + 47929, + 47935, + 47939 + ], + "evidence_addresses_hex": [ + "H'BB1C", + "H'BB20", + "H'BB2B", + "H'BB39", + "H'BB3F", + "H'BB43" + ] + }, + "periodic_resend_model": { + "kind": "autonomous_periodic_resend_model_candidate", + "period_timer": { + "address": 63942, + "address_hex": "H'F9C6", + "reload_value_candidate": 500, + "reload_value_hex": "H'01F4", + "summary": "Candidate periodic report/heartbeat timer reload.", + "evidence_addresses": [ + 47942, + 48837 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5" + ] + }, + "resend_countdown": { + "address": 63944, + "address_hex": "H'F9C8", + "reload_value_candidate": 20, + "reload_value_hex": "H'14", + "summary": "Candidate periodic resend countdown/retry spacing value.", + "evidence_addresses": [ + 47948 + ], + "evidence_addresses_hex": [ + "H'BB4C" + ] + }, + "pending_mask": { + "address": 64163, + "address_hex": "H'FAA3", + "mask_candidate": 128, + "mask_hex": "H'80", + "summary": "Candidate bit/mask that marks an autonomous report pending.", + "evidence_addresses": [ + 47953, + 48843 + ], + "evidence_addresses_hex": [ + "H'BB51", + "H'BECB" + ] + }, + "resend_path": { + "entry_label": "loc_BED5", + "entry_address": 48853, + "entry_address_hex": "H'BED5", + "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.", + "evidence_addresses": [ + 48853 + ], + "evidence_addresses_hex": [ + "H'BED5" + ] + }, + "evidence_addresses": [ + 47942, + 48837, + 47948, + 47953, + 48843, + 48853 + ], + "evidence_addresses_hex": [ + "H'BB46", + "H'BEC5", + "H'BB4C", + "H'BB51", + "H'BECB", + "H'BED5" + ], + "confidence": "candidate-medium", + "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing." + }, + "timer_interrupt_model": { + "kind": "timer_interrupt_model_candidate", + "source": "FRT1 OCIA / FRT2 OCIA", + "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.", + "sources": [ + { + "source": "FRT1 OCIA", + "vector_address_hex": "H'0062", + "handler_address": 48874, + "handler_address_hex": "H'BEEA", + "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.", + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08" + ] + }, + { + "source": "FRT2 OCIA", + "vector_address_hex": "H'006A", + "handler_address": 48931, + "handler_address_hex": "H'BF23", + "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.", + "clock_select": "CKS1=1 CKS0=0 => phi/32", + "ocra_value_hex": "H'7A12", + "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select", + "counters": [ + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ] + } + ], + "counters": [ + { + "address": 63936, + "address_hex": "H'F9C0", + "name_candidate": "tx_report_gate_counter_candidate", + "role": "candidate gate counter used before entering the report builder.", + "evidence_address": 48884, + "evidence_address_hex": "H'BEF4" + }, + { + "address": 63937, + "address_hex": "H'F9C1", + "name_candidate": "rx_interbyte_timeout_candidate", + "role": "candidate RX interbyte timeout counter.", + "evidence_address": 48894, + "evidence_address_hex": "H'BEFE" + }, + { + "address": 63942, + "address_hex": "H'F9C6", + "name_candidate": "periodic_resend_cadence_counter_candidate", + "role": "candidate periodic resend/heartbeat cadence counter.", + "evidence_address": 48904, + "evidence_address_hex": "H'BF08" + }, + { + "address": 63940, + "address_hex": "H'F9C4", + "name_candidate": "idle_heartbeat_gate_countdown_candidate", + "role": "candidate idle/default report enqueue countdown.", + "evidence_address": 48941, + "evidence_address_hex": "H'BF2D" + }, + { + "address": 63941, + "address_hex": "H'F9C5", + "name_candidate": "rx_session_timeout_candidate", + "role": "candidate RX/session maintenance timeout counter.", + "evidence_address": 48951, + "evidence_address_hex": "H'BF37" + } + ], + "evidence_addresses": [ + 48874, + 48878, + 48882, + 48884, + 48888, + 48892, + 48894, + 48898, + 48902, + 48904, + 48931, + 48935, + 48939, + 48941, + 48945, + 48949, + 48951 + ], + "evidence_addresses_hex": [ + "H'BEEA", + "H'BEEE", + "H'BEF2", + "H'BEF4", + "H'BEF8", + "H'BEFC", + "H'BEFE", + "H'BF02", + "H'BF06", + "H'BF08", + "H'BF23", + "H'BF27", + "H'BF2B", + "H'BF2D", + "H'BF31", + "H'BF35", + "H'BF37" + ], + "confidence": "candidate-medium" + }, + "confidence": "medium-high", + "confidence_score": 0.9, + "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation." + } +} \ No newline at end of file diff --git a/docs/pt2-copy-state-machine.md b/docs/pt2-copy-state-machine.md new file mode 100644 index 0000000..4058f0a --- /dev/null +++ b/docs/pt2-copy-state-machine.md @@ -0,0 +1,125 @@ +# PT2 Copy State Machine + +This is a focused reference for the COPY behavior seen on the RCP LCD and traced in the ROM. + +## Known Entry Points + +### Serial Start / Progress + +Frame: + +```text +05 00 6D 00 00 32 +``` + +ROM path: + +- Command 5 accepts selector `0x006D` at `BD80-BDBF`. +- The selector is queued through `BE70`. +- Selector `0x006D` dispatches to `H'3015`. + +Observed effects from forced decode: + +- Sets `F731.7`. +- Sets `F795.6/F795.7`. +- Loads `F798=H'C8`. +- Sets display selector `F732=H'1903`. +- Sets `FB02=H'64`. +- Calls the display/report bridge at `48FA`. +- Sets `F76E.6`. + +LCD dispatch: + +- `F732` high byte `0x19` selects `493E[0x19] -> H'930A`. +- The local table at `H'931C` maps substate `0x03` to `H'9F6A`. +- `H'9F6A` builds `COPY` / `IN PROGRESS`. + +### Serial Complete / Exit + +Frame: + +```text +05 00 6C 00 00 33 +``` + +ROM path: + +- Command 5 accepts selector `0x006C` at `BD80-BDBF`. +- The selector is queued through `BE70`. +- Selector `0x006C` dispatches to `H'2FAF`. + +Observed effects from forced decode: + +- Manipulates `F76E`, `F795`, `F797`, and `F799`. +- Can set display selector `F732=H'1904`. +- Sets `FB02=H'14`. +- Calls the display/report bridge at `48FA`. + +LCD dispatch: + +- `F732` high byte `0x19` selects `493E[0x19] -> H'930A`. +- The local table at `H'931C` maps substate `0x04` to `H'9FDA`. +- `H'9FDA` builds `COPY` / `COMPLETED`. + +### RCP-Side Menu Start + +ROM path: + +- OTHERS menu page: `493E[0x01] -> H'631C`. +- Local page table: `H'632E`. +- `COPY TO SLAVES` entry handler: `H'6FF0`. + +Required gates: + +- The entry descriptor before `H'6FF0` requires `E400[0x0015] != 0`. +- The local COPY action branch requires `F770.2` and `F791.7`. + +Local branch effects: + +- Sets `F76E.6`. +- Sets `F795.7`. +- Sets `F731.7`. +- Loads `F798=H'C8`. +- Sets `F711.7`. +- Loads `F726=H'64`. +- Calls `loc_5500`. +- Displays `COPY TO SLAVES`. + +If `F770.2` is set while `F791.7` is clear, the ROM diverts through `H'704C` to a `SET RCP` / `MASTER` display path instead of starting copy. + +## Working State Model + +| State | Likely indicators | Entry | Exit | +| --- | --- | --- | --- | +| Idle / no copy | `F731.7` clear | Boot, timeout, or completion cleanup | `0x006D` or local COPY branch | +| Copy in progress | `F731.7`, `F795.6/F795.7`, `F798` live, `F732=H'1903` | `05 00 6D 00 00 32` or local COPY branch | `0x006C` in the live window, or timer expiry | +| Copy completed | `F732=H'1904` | `05 00 6C 00 00 33` while copy flags are live | Display/session timeout or next state update | +| Timeout / not active | `F731.7` cleared by timer path | `F797` or `F798` reaches zero | Normal CONNECT recovery traffic | + +## Bench Results + +Observed on the real panel: + +```text +006C alone -> CONNECT OK -> blank +006D alone -> CONNECT OK -> COPY IN PROGRESS -> CONNECT NOT ACT +006D -> 006C after 250 ms -> COPY IN PROGRESS -> COPY COMPLETED +006D -> 006C after 1.0-1.5 s -> COPY IN PROGRESS -> COPY COMPLETED +006D -> 006C after 2.0-2.5 s -> COPY IN PROGRESS -> CONNECT NOT ACT +006D repeated, then 006C -> COPY IN PROGRESS held longer -> COPY COMPLETED +006D repeated without 006C -> COPY IN PROGRESS -> CONNECT NOT ACT +``` + +Current interpretation: + +- `0x006D` is a copy-start/progress-window refresh selector. +- `0x006C` is a completion/exit selector that only behaves cleanly while the copy window is live. +- The copy window is transient and timer-controlled. +- The panel does not treat `0x006C` as a stateless "show completed" command. + +## Open Questions + +- What sets `F791.7` during normal CCU/RCP operation? +- What exact official PT2 name belongs to selectors `0x006C`, `0x006D`, and `0x006E`? +- Whether `0x006E` is a copy cancel/error sibling or an unrelated special selector. +- Whether the CCU sends repeated progress refreshes during a real COPY TO SLAVES operation. diff --git a/docs/pt2-menu-state-machine.md b/docs/pt2-menu-state-machine.md new file mode 100644 index 0000000..df839fe --- /dev/null +++ b/docs/pt2-menu-state-machine.md @@ -0,0 +1,124 @@ +# PT2 Menu State Machine + +This is a focused reference for the ROM menu/display selection machinery that drives LCD pages and panel soft-key activity. + +## Page Dispatch + +Primary display selector: + +- `F732` holds the current display/page selector. +- The high byte of `F732` selects a page wrapper through `493E`. +- The low byte is used as a page-local substate/selection, commonly through `F733`. + +Important dispatcher: + +- `48FA` bridges table/report state into LCD page dispatch. +- `493E[page]` points at a wrapper. +- Wrappers pass a local table pointer to `5FD2`. + +For COPY status: + +- `F732=H'1903` selects page `0x19`, substate `0x03`, `COPY IN PROGRESS`. +- `F732=H'1904` selects page `0x19`, substate `0x04`, `COPY COMPLETED`. + +For OTHERS: + +- `493E[0x01] -> H'631C`. +- Local table `H'632E` includes the OTHERS pages. + +## Local Entry Selection + +`loc_5FD2` is the local menu chooser. + +Important RAM: + +| RAM | Role | +| --- | --- | +| `F72C` | visible/selectable entry bitmask | +| `F72E` | count of visible/selectable entries | +| `F72F` | cached page high byte | +| `F733` | selected local entry index | +| `FB03.7` | no-entry/error/display suppression flag | +| `FB02` | display/session timer or message timer | + +Observed algorithm shape: + +1. If the page changed, clear `F72C/F72E` and cache the new page in `F72F`. +2. Walk the page-local handler table from the last entry down. +3. For each handler, read descriptor words immediately before the handler. +4. Compare the entry state descriptor against `F731`. +5. If the entry has required selector descriptors, test `E400 + selector*2`. +6. If requirements pass, set the entry bit in `F72C` and increment `F72E`. +7. Clamp or reset `F733` so it points at a visible entry. +8. If no entries are visible, set `FB03.7`, set `FB02=H'14`, clear `F72F`, and return `R4=H'FFFE`. + +Practical meaning: + +- A page can exist in ROM but be invisible/inactive until the CCU seeds the right `E400` feature/status selector. +- Command 6 writes the `E400-E7FF` secondary table, but only on the continuation side of the protocol. + +## OTHERS / COPY TO SLAVES Gates + +OTHERS page map: + +| Local entry | Handler | Visible text | Required secondary selector | +| --- | --- | --- | --- | +| 1 | `H'6FF0` | `OTHERS` / `COPY TO SLAVES` | `E400[0x0015] != 0` | +| 2 | `H'70F6` | `OTHERS` / `CAM ID SET` | `E400[0x0043] != 0` | +| 3 | `H'7188` | `OTHERS` / `CAM ID IND` | `E400[0x0037] != 0` | +| 4 | `H'7258` | `OTHERS` / `CAM BARS` | `E400[0x0038] != 0` | +| 5-6 | `H'7328/H'73D8` | marker/percentage pages | `E400[0x0027] != 0` | + +COPY TO SLAVES local action gate: + +- Handler `H'6FF0` watches `F770.2`. +- If `F770.2` is clear, it only displays the OTHERS/COPY page. +- If `F770.2` is set and `F791.7` is set, it enters the local copy-start branch. +- If `F770.2` is set and `F791.7` is clear, it diverts to `SET RCP` / `MASTER`. + +Root OTHERS soft-key bits: + +- Root handler `H'6EE4` tests `E000[0x008F]` at `H'E11E`. +- Bit 11 sets `F711.6`. +- Bit 12 sets `F711.4`. + +These look like CCU-provided OTHERS soft-key enable bits. If they are absent, some OTHERS controls can appear inactive even when the page table entry exists. + +## Button / Lamp Masks + +Important RAM: + +| RAM | Role | +| --- | --- | +| `F711-F718` | panel output masks used by external panel chips | +| `F711.4-F711.7` | soft-key/menu-related bits seen around OTHERS/COPY | +| `F726` | countdown that temporarily preserves some soft-key bits | +| `F770` | local panel action/change code | + +Relevant ROM behavior: + +- Init clears `F711-F717` and sets `F718=H'FF`. +- `5A7A` clears `F711.4-F711.7` if `F726 == 0`. +- The FRT timer path decrements `F726`; when it expires, it clears `F713.6` and `F711.4-F711.7`. +- The OTHERS/COPY branch sets `F711.7` and `F726=H'64` to keep the local key/display state alive briefly. + +## Bench Implications + +To make the local COPY path available from the panel, the fake CCU probably needs to: + +1. Recover to a live `CONNECT: OK` style session. +2. Seed root OTHERS soft-key bits: + +```text +00 01 0F 18 00 4C ; E000[0x008F] bits 11+12 +``` + +3. During a live continuation/report window, seed the COPY page visibility bit: + +```text +06 00 15 00 01 48 ; E400[0x0015] nonzero +``` + +4. Still satisfy the `F791.7` local copy-start gate. + +The current hardest unknown is step 4: the ROM uses `F791.7` in several places, but the source that sets it has not yet been identified. diff --git a/docs/pt2-protocol.md b/docs/pt2-protocol.md index 505cfb0..2d77c65 100644 --- a/docs/pt2-protocol.md +++ b/docs/pt2-protocol.md @@ -4,6 +4,11 @@ This document is the current working model for the serial protocol spoken by the A later RCP manual mentions a "PT2 compatibility mode" for controlling the same CCU family this panel was made for. We are using "PT2" here as a practical label for this six-byte SCI1 protocol model. It is not yet a claim that every field name matches Sony's official PT2 terminology. +Focused companion notes: + +- [PT2 Copy State Machine](pt2-copy-state-machine.md) +- [PT2 Menu State Machine](pt2-menu-state-machine.md) + ## Current High-Confidence Facts - The real bench link is `38400 8E1`, not `38400 8N1`. @@ -562,11 +567,27 @@ The `0x006D` copy path is now confirmed outside the earlier all-suite ordering c - Selector `0x006D` dispatches to `H'3015`. Forced decoding shows it sets `F731.7`, loads `F798=H'C8`, sets `F795.6/F795.7`, sets display selector `F732=H'1903`, sets `FB02=H'64`, calls `48FA`, then sets `F76E.6`. - The LCD dispatch for these states is now traced: `loc_48FA` reads the high byte at `F732`, so `F732=H'1903/H'1904` selects display page `0x19`, not direct page `0x03/0x04`. `493E[0x19] -> H'930A`; that page's local table at `H'931C` includes `H'9F6A` for `COPY` / `IN PROGRESS` and `H'9FDA` for `COPY` / `COMPLETED`. The low byte at `F733` is the substate selector: `0x03` is in-progress and `0x04` is completed. - This makes the likely copy handshake: `0x006D` starts copy and sets the `F795.6/F795.7` in-progress flags; `0x006C` is the completion/exit sibling only when those flags are live. Sending `0x006C` alone can therefore blank or clear state instead of displaying `COPY COMPLETED`. -- Bench step-through confirmed the sequence model: `006C` alone produced `CONNECT OK -> blank`; `006D` alone produced `CONNECT OK -> COPY IN PROGRESS`; `006D` followed by `006C` after 250 ms produced a brief `COPY IN PROGRESS` then `COPY COMPLETED`; the same after 1.0 s and 1.5 s produced a longer `COPY IN PROGRESS` then `COPY COMPLETED`; after 2.0 s or 2.5 s it fell to `CONNECT:NOT ACT` instead of completing. Repeating `006D` before `006C` also completed successfully in the 2x and 3x repeat tests. This points to an active completion window that can likely be refreshed/restarted by additional in-progress/progress traffic, rather than a stateless command. +- Bench step-through confirmed the sequence model: `006C` alone produced `CONNECT OK -> blank`; `006D` alone produced `CONNECT OK -> COPY IN PROGRESS`; `006D` followed by `006C` after 250 ms produced a brief `COPY IN PROGRESS` then `COPY COMPLETED`; the same after 1.0 s and 1.5 s produced a longer `COPY IN PROGRESS` then `COPY COMPLETED`; after 2.0 s or 2.5 s it fell to `CONNECT:NOT ACT` instead of completing. Repeating `006D` before `006C` also completed successfully in the 2x and 3x repeat tests. A longer `006D` hold test kept `COPY IN PROGRESS` active for several seconds and then completed when `006C` arrived, while the same hold without `006C` timed out from `COPY IN PROGRESS` to `CONNECT:NOT ACT`. This points to `006D` as an in-progress/progress-window refresh selector and `006C` as the explicit completion/exit selector, not a stateless command pair. - The FRT1 timer path decrements `F797` and `F798`; when either reaches zero, it clears `F731.7`. This matches the observed transient display modes falling back to `CONNECT:NOT ACT`. - The string `COPY IN PROGRESS` is present in the ROM LCD resources, so the `006D` result is not a generic serial artifact. - Manual interpretation: the RCP-TX7 operating manual describes `COPY IN PROGRESS` as the LCD state shown during the multi-camera `COPY TO SLAVES` data-transfer operation over the RS232C command-link system. During that state, all linked RCP units display the message and their buttons/knobs are locked until `COPY COMPLETED`. Therefore selector `0x006D` is best treated as entering a command-link copy/data-transfer state, not as a normal CCU connection ACK. +RCP-side OTHERS/COPY menu trace: + +- The OTHERS menu is page `0x01`: `493E[0x01] -> H'631C`, local table `H'632E`. +- Local table entry 1 points to `H'6FF0`, the page that renders `OTHERS` / `COPY TO SLAVES`. +- The entry descriptor immediately before `H'6FF0` requires selector `0x0015` in the secondary table: `E400[0x0015] != 0`. Because command 6 writes `E400`, this is probably a CCU-provided feature/visibility bit, and command 6 must be sent in a live continuation/report window to have an effect. +- When the page sees `F770.2` set, it only follows the local copy-start branch if `F791.7` is already set. That branch sets `F76E.6`, `F795.7`, `F731.7`, `F798=H'C8`, `F711.7`, `F726=H'64`, calls `loc_5500`, then displays `COPY TO SLAVES`. This is the RCP-side equivalent of the serial `0x006D` copy-start effect. +- If `F770.2` is set while `F791.7` is clear, the ROM diverts through `H'704C` to a `SET RCP` / `MASTER` display path instead of starting copy. That makes `F791.7` a second, likely master/link/session gate for the physical COPY operation. +- The OTHERS root handler at `H'6EE4` also tests primary selector `E000[0x008F]` (`H'E11E`) bits 11 and 12, and uses them to set `F711.6` and `F711.4`. If those bits are absent, some OTHERS soft keys can appear inactive even when the page exists. +- Candidate gate probes, not final protocol truth: + +```text +00 01 0F 18 00 4C ; command 0, set E000[0x008F] bits 11+12 +06 00 15 00 01 48 ; command 6, set E400[0x0015] nonzero; requires live continuation +06 00 15 80 00 C9 ; command 6, alternate nonzero visibility value; requires live continuation +``` + Read table state: ```powershell diff --git a/scenarios/others-copy-gate-probe.json b/scenarios/others-copy-gate-probe.json new file mode 100644 index 0000000..b7cf675 --- /dev/null +++ b/scenarios/others-copy-gate-probe.json @@ -0,0 +1,49 @@ +{ + "name": "others-copy-gate-probe", + "notes": [ + "Recover toward CONNECT OK, seed the OTHERS root soft-key bits, then try to set the page-1 COPY TO SLAVES visibility gate.", + "Press the panel OTHER/COPY controls during the final listen window and record the LCD/lamp result.", + "The command-6 E400 write only works if the ROM is in a live continuation/report window.", + "ROM trace also shows a second local COPY-start gate at F791.7; if that is clear, the panel can divert to SET RCP / MASTER instead of COPY." + ], + "steps": [ + { + "action": "power_cycle", + "off_seconds": 1.5 + }, + { + "action": "wait_ready", + "heartbeats": 2, + "timeout": 10.0, + "require": true + }, + { + "action": "drain", + "seconds": 0.25 + }, + { + "action": "send", + "label": "selector_zero_connect_ok_seed", + "frame": "00 00 00 80 00 DA", + "listen": 0.10 + }, + { + "action": "send", + "label": "others_root_e000_008f_bits11_12", + "frame": "00 01 0F 18 00 4C", + "listen": 0.15 + }, + { + "action": "wait_for", + "frame": "02 00 02 00 00 5A", + "timeout": 1.5, + "require": false + }, + { + "action": "send", + "label": "others_copy_e400_0015_gate", + "frame": "06 00 15 00 01 48", + "listen": 8.0 + } + ] +}