Emualtor improements

2026-05-25 18:55:50 +10:00
parent 05e1237acc
commit 1fabf6587d
10 changed files with 413 additions and 15 deletions
--- a/tests/test_emulator_sci_timing.py
+++ b/tests/test_emulator_sci_timing.py
@@ -0,0 +1,71 @@
+import unittest
+
+from h8536.emulator import (
+    HEARTBEAT_FRAME,
+    SCI1_SCR,
+    SCI1_SSR,
+    SCI1_TDR,
+    SCI_SCR_TE,
+    SCI_SSR_FER,
+    SCI_SSR_ORER,
+    SCI_SSR_PER,
+    SCI_SSR_RDRF,
+    SCI_SSR_TDRE,
+    SCI1,
+)
+
+
+class SciTimingTest(unittest.TestCase):
+    def test_ssr_write_one_does_not_set_hardware_flags(self):
+        sci = SCI1()
+        sci.ssr = 0x00
+
+        sci.write(SCI1_SSR, SCI_SSR_TDRE | SCI_SSR_RDRF | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER)
+
+        self.assertEqual(sci.read(SCI1_SSR) & 0xF8, 0x00)
+
+    def test_ssr_write_zero_clears_selected_writable_flags(self):
+        sci = SCI1()
+        sci.ssr = SCI_SSR_TDRE | SCI_SSR_RDRF | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER | 0x07
+
+        sci.write(SCI1_SSR, sci.ssr & ~SCI_SSR_RDRF)
+
+        self.assertEqual(sci.read(SCI1_SSR) & SCI_SSR_RDRF, 0x00)
+        self.assertEqual(
+            sci.read(SCI1_SSR) & (SCI_SSR_TDRE | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER),
+            SCI_SSR_TDRE | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER,
+        )
+
+    def test_tdr_write_then_ssr_clear_delays_tdre_until_ticks(self):
+        sci = SCI1(tx_ready_ticks=2)
+        sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
+        self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+
+        sci.write(SCI1_TDR, 0x42)
+        sci.write(SCI1_SSR, sci.read(SCI1_SSR) & ~SCI_SSR_TDRE)
+        self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+
+        sci.tick()
+        self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+
+        sci.tick()
+        self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
+
+    def test_transmit_capture_requires_te_enabled(self):
+        sci = SCI1()
+
+        sci.write(SCI1_TDR, 0x33)
+        self.assertEqual(sci.tx_bytes, [])
+        self.assertFalse(sci.tx_events[-1].emitted)
+
+        sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
+        for byte in HEARTBEAT_FRAME:
+            sci.write(SCI1_TDR, byte)
+
+        self.assertEqual(bytes(sci.tx_bytes), HEARTBEAT_FRAME)
+        self.assertEqual(sci.tx_frames, [HEARTBEAT_FRAME])
+        self.assertTrue(sci.saw_heartbeat())
+
+
+if __name__ == "__main__":
+    unittest.main()