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Emualtor improements

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This commit is contained in:
Aiden
2026-05-25 18:55:50 +10:00
parent 05e1237acc
commit 1fabf6587d
10 changed files with 413 additions and 15 deletions
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104
tests/test_emulator_probe_sci.py Normal file
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@@ -0,0 +1,104 @@
import unittest
from collections import Counter
from h8536.emulator.constants import IPRE, SCI1_SCR, SCI1_TDR, SCI_SCR_TE
from h8536.emulator.probe import ProbeReport, SCI1Snapshot, SCI1TXISummary, run_probe
def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1040) -> bytearray:
rom = bytearray([0xFF] * size)
rom[0:2] = reset.to_bytes(2, "big")
return rom
class EmulatorProbeSciTest(unittest.TestCase):
def test_report_lines_include_compact_sci_state_and_txi_summary(self):
report = ProbeReport(
steps=12,
pc=0xBA68,
stopped_reason="max_steps",
hot_pcs=Counter({0xBA68: 7}),
tx_bytes=b"\x00\x03",
sci_accesses=[
"old write SCR=00",
"H'BA60 read SSR=00",
"H'BA64 write SCR=A0",
"H'BA68 write TDR=03",
],
sci1=SCI1Snapshot(
smr=0x00,
brr=0x07,
scr=0xA0,
ssr=0x80,
tdr=0x03,
rdr=0x00,
tx_ready_delay=1,
),
sci1_txi=SCI1TXISummary(
tie=True,
te=True,
tdre=True,
vector_target=0xBA68,
priority=6,
interrupt_mask=2,
interrupt_depth=0,
),
)
lines = report.lines()
self.assertIn("sci1=SMR=00 BRR=07 SCR=A0 SSR=80 TDR=03 RDR=00 tx_ready_delay=1", lines)
self.assertIn(
"sci1_txi=TIE=1 TE=1 TDRE=1 vector=H'BA68 priority=6 mask=2 depth=0 pending=1 serviceable=1",
lines,
)
self.assertIn("recent_sci:", lines)
self.assertIn(" H'BA60 read SSR=00", lines)
self.assertIn(" H'BA68 write TDR=03", lines)
def test_report_lines_bound_recent_sci_accesses(self):
report = ProbeReport(
steps=1,
pc=0x1000,
stopped_reason="max_steps",
sci_accesses=[f"H'{idx:04X} read SSR={idx:02X}" for idx in range(20)],
)
lines = report.lines()
self.assertNotIn(" H'0000 read SSR=00", lines)
self.assertIn(" H'0004 read SSR=04", lines)
self.assertIn(" H'0013 read SSR=13", lines)
def test_run_probe_tracks_sci_register_accesses_and_final_txi_state(self):
rom = rom_with_reset()
rom[0x0084:0x0086] = (0x1010).to_bytes(2, "big")
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
rom[0x1003:0x1008] = bytes([0x15, (IPRE >> 8) & 0xFF, IPRE & 0xFF, 0x06, 0x50])
rom[0x1008:0x100D] = bytes([0x15, (SCI1_SCR >> 8) & 0xFF, SCI1_SCR & 0xFF, 0x06, 0xA0])
rom[0x100D] = 0x00
rom[0x1010:0x1015] = bytes([0x15, (SCI1_SCR >> 8) & 0xFF, SCI1_SCR & 0xFF, 0x06, SCI_SCR_TE])
rom[0x1015:0x101A] = bytes([0x15, (SCI1_TDR >> 8) & 0xFF, SCI1_TDR & 0xFF, 0x06, 0x42])
rom[0x101A] = 0x0A
report = run_probe(
bytes(rom),
max_steps=8,
interval_steps=512,
stop_on_tx=False,
p9_log_limit=8,
sci_log_limit=8,
watch_pcs=(),
)
self.assertEqual(report.tx_bytes, b"\x42")
self.assertIsNotNone(report.sci1)
self.assertIsNotNone(report.sci1_txi)
self.assertTrue(any("write SCR=A0" in line for line in report.sci_accesses))
self.assertTrue(any("write SCR=20" in line for line in report.sci_accesses))
self.assertTrue(any("write TDR=42" in line for line in report.sci_accesses))
self.assertTrue(any(line.startswith("sci1=SMR=00") for line in report.lines()))
if __name__ == "__main__":
unittest.main()

71
tests/test_emulator_sci_timing.py Normal file
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@@ -0,0 +1,71 @@
import unittest
from h8536.emulator import (
HEARTBEAT_FRAME,
SCI1_SCR,
SCI1_SSR,
SCI1_TDR,
SCI_SCR_TE,
SCI_SSR_FER,
SCI_SSR_ORER,
SCI_SSR_PER,
SCI_SSR_RDRF,
SCI_SSR_TDRE,
SCI1,
)
class SciTimingTest(unittest.TestCase):
def test_ssr_write_one_does_not_set_hardware_flags(self):
sci = SCI1()
sci.ssr = 0x00
sci.write(SCI1_SSR, SCI_SSR_TDRE | SCI_SSR_RDRF | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER)
self.assertEqual(sci.read(SCI1_SSR) & 0xF8, 0x00)
def test_ssr_write_zero_clears_selected_writable_flags(self):
sci = SCI1()
sci.ssr = SCI_SSR_TDRE | SCI_SSR_RDRF | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER | 0x07
sci.write(SCI1_SSR, sci.ssr & ~SCI_SSR_RDRF)
self.assertEqual(sci.read(SCI1_SSR) & SCI_SSR_RDRF, 0x00)
self.assertEqual(
sci.read(SCI1_SSR) & (SCI_SSR_TDRE | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER),
SCI_SSR_TDRE | SCI_SSR_ORER | SCI_SSR_FER | SCI_SSR_PER,
)
def test_tdr_write_then_ssr_clear_delays_tdre_until_ticks(self):
sci = SCI1(tx_ready_ticks=2)
sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
sci.write(SCI1_TDR, 0x42)
sci.write(SCI1_SSR, sci.read(SCI1_SSR) & ~SCI_SSR_TDRE)
self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
sci.tick()
self.assertFalse(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
sci.tick()
self.assertTrue(sci.read(SCI1_SSR) & SCI_SSR_TDRE)
def test_transmit_capture_requires_te_enabled(self):
sci = SCI1()
sci.write(SCI1_TDR, 0x33)
self.assertEqual(sci.tx_bytes, [])
self.assertFalse(sci.tx_events[-1].emitted)
sci.write(SCI1_SCR, sci.read(SCI1_SCR) | SCI_SCR_TE)
for byte in HEARTBEAT_FRAME:
sci.write(SCI1_TDR, byte)
self.assertEqual(bytes(sci.tx_bytes), HEARTBEAT_FRAME)
self.assertEqual(sci.tx_frames, [HEARTBEAT_FRAME])
self.assertTrue(sci.saw_heartbeat())
if __name__ == "__main__":
unittest.main()

53
tests/test_emulator_timers.py
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@@ -4,9 +4,12 @@ from h8536.emulator import H8536Emulator, ON_CHIP_RAM_START
from h8536.emulator.constants import (
FRT_TCR_OCIEA,
FRT_TCSR_OCFA,
FRT1_TCR,
FRT1_TCSR,
FRT2_TCR,
FRT2_TCSR,
IPRC,
VECTOR_FRT1_OCIA,
VECTOR_FRT2_OCIA,
)
@@ -23,6 +26,56 @@ def write_mov_b_abs_imm(rom: bytearray, address: int, target: int, value: int) -
class Frt2OciaTimerTest(unittest.TestCase):
def test_frt1_ocia_vector_can_fire_and_decrement_ram(self):
rom = rom_with_reset()
rom[VECTOR_FRT1_OCIA : VECTOR_FRT1_OCIA + 2] = (0x1020).to_bytes(2, "big")
pc = 0x1000
rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
pc += 3
# IPRC bits 6..4 are FRT1 and bits 2..0 are FRT2, so H'60 makes
# only the FRT1 priority field high enough to pass interrupt mask 0.
pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x60)
pc = write_mov_b_abs_imm(rom, pc, FRT1_TCR, FRT_TCR_OCIEA)
rom[pc : pc + 2] = b"\x20\xFE" # BRA self
isr = 0x1020
rom[isr : isr + 4] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C])
isr += 4
rom[isr : isr + 4] = bytes([0x15, (FRT1_TCSR >> 8) & 0xFF, FRT1_TCSR & 0xFF, 0xD5])
rom[isr + 4] = 0x0A # RTE
emulator = H8536Emulator(bytes(rom), frt1_ocia_steps=2)
emulator.memory.write8(ON_CHIP_RAM_START, 3)
emulator.run(max_steps=5)
self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 2)
self.assertFalse(emulator.memory.read8(FRT1_TCSR) & FRT_TCSR_OCFA)
self.assertEqual(emulator.cpu.pc, isr + 4)
def test_frt1_ocia_does_not_fire_when_ociea_disabled(self):
rom = rom_with_reset()
rom[VECTOR_FRT1_OCIA : VECTOR_FRT1_OCIA + 2] = (0x1020).to_bytes(2, "big")
pc = 0x1000
rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
pc += 3
pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x60)
rom[pc : pc + 2] = b"\x20\xFE" # BRA self
rom[0x1020 : 0x1024] = bytes(
[0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C]
)
rom[0x1024] = 0x0A # RTE
emulator = H8536Emulator(bytes(rom), frt1_ocia_steps=1)
emulator.memory.write8(ON_CHIP_RAM_START, 3)
emulator.run(max_steps=8)
self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 3)
self.assertEqual(emulator.memory.read8(FRT1_TCSR) & FRT_TCSR_OCFA, 0)
self.assertEqual(emulator.cpu.pc, pc)
def test_frt2_ocia_vector_can_fire_and_decrement_ram(self):
rom = rom_with_reset()
rom[VECTOR_FRT2_OCIA : VECTOR_FRT2_OCIA + 2] = (0x1020).to_bytes(2, "big")