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Emualtor improements

This commit is contained in:
Aiden
2026-05-25 18:55:50 +10:00
parent 05e1237acc
commit 1fabf6587d
10 changed files with 413 additions and 15 deletions

View File

@@ -9,6 +9,8 @@ from ..vectors import read_vectors_min
from .constants import (
FRT_TCR_OCIEA,
FRT_TCSR_OCFA,
FRT1_TCR,
FRT1_TCSR,
FRT2_TCR,
FRT2_TCSR,
IPRA,
@@ -16,6 +18,7 @@ from .constants import (
IPRE,
SCI_SCR_TIE,
SCI_SSR_TDRE,
VECTOR_FRT1_OCIA,
VECTOR_FRT2_OCIA,
VECTOR_INTERVAL_TIMER,
VECTOR_SCI1_TXI,
@@ -63,6 +66,7 @@ class H8536Emulator:
rom_bytes: bytes,
*,
interval_steps: int = 2048,
frt1_ocia_steps: int = 1024,
frt2_ocia_steps: int = 1024,
p9_fast_path: P9FastPath | None = None,
p9_fast_path_enabled: bool = False,
@@ -78,8 +82,10 @@ class H8536Emulator:
self.cpu = CPUState()
self.vectors = read_vectors_min(self.memory.rom)
self.interval_steps = max(1, interval_steps)
self.frt1_ocia_steps = max(1, frt1_ocia_steps)
self.frt2_ocia_steps = max(1, frt2_ocia_steps)
self._interval_counter = 0
self._frt1_ocia_counter = 0
self._frt2_ocia_counter = 0
self.reset()
@@ -372,6 +378,7 @@ class H8536Emulator:
def _tick_peripherals(self) -> None:
self.sci1.tick()
self._interval_counter += 1
self._frt1_ocia_counter += 1
self._frt2_ocia_counter += 1
self._service_pending_interrupt()
@@ -387,6 +394,10 @@ class H8536Emulator:
target = self._vector_target(VECTOR_INTERVAL_TIMER)
if target is not None:
candidates.append((self._interval_priority(), target, "interval_timer"))
if self._frt1_ocia_pending():
target = self._vector_target(VECTOR_FRT1_OCIA)
if target is not None:
candidates.append((self._frt1_priority(), target, "frt1_ocia"))
if self._frt2_ocia_pending():
target = self._vector_target(VECTOR_FRT2_OCIA)
if target is not None:
@@ -399,6 +410,9 @@ class H8536Emulator:
return
if source == "interval_timer":
self._interval_counter = 0
elif source == "frt1_ocia":
self._frt1_ocia_counter = 0
self.memory.write8(FRT1_TCSR, self.memory.read8(FRT1_TCSR) | FRT_TCSR_OCFA)
elif source == "frt2_ocia":
self._frt2_ocia_counter = 0
self.memory.write8(FRT2_TCSR, self.memory.read8(FRT2_TCSR) | FRT_TCSR_OCFA)
@@ -430,6 +444,14 @@ class H8536Emulator:
def _interval_priority(self) -> int:
return (self.memory.read8(IPRA) >> 4) & 0x07
def _frt1_ocia_pending(self) -> bool:
if self._frt1_ocia_counter < self.frt1_ocia_steps:
return False
return bool(self.memory.read8(FRT1_TCR) & FRT_TCR_OCIEA)
def _frt1_priority(self) -> int:
return (self.memory.read8(IPRC) >> 4) & 0x07
def _frt2_ocia_pending(self) -> bool:
if self._frt2_ocia_counter < self.frt2_ocia_steps:
return False