Emualtor improements
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@@ -9,6 +9,8 @@ from ..vectors import read_vectors_min
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from .constants import (
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FRT_TCR_OCIEA,
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FRT_TCSR_OCFA,
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FRT1_TCR,
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FRT1_TCSR,
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FRT2_TCR,
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FRT2_TCSR,
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IPRA,
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@@ -16,6 +18,7 @@ from .constants import (
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IPRE,
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SCI_SCR_TIE,
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SCI_SSR_TDRE,
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VECTOR_FRT1_OCIA,
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VECTOR_FRT2_OCIA,
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VECTOR_INTERVAL_TIMER,
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VECTOR_SCI1_TXI,
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@@ -63,6 +66,7 @@ class H8536Emulator:
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rom_bytes: bytes,
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*,
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interval_steps: int = 2048,
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frt1_ocia_steps: int = 1024,
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frt2_ocia_steps: int = 1024,
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p9_fast_path: P9FastPath | None = None,
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p9_fast_path_enabled: bool = False,
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@@ -78,8 +82,10 @@ class H8536Emulator:
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self.cpu = CPUState()
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self.vectors = read_vectors_min(self.memory.rom)
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self.interval_steps = max(1, interval_steps)
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self.frt1_ocia_steps = max(1, frt1_ocia_steps)
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self.frt2_ocia_steps = max(1, frt2_ocia_steps)
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self._interval_counter = 0
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self._frt1_ocia_counter = 0
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self._frt2_ocia_counter = 0
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self.reset()
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@@ -372,6 +378,7 @@ class H8536Emulator:
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def _tick_peripherals(self) -> None:
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self.sci1.tick()
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self._interval_counter += 1
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self._frt1_ocia_counter += 1
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self._frt2_ocia_counter += 1
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self._service_pending_interrupt()
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@@ -387,6 +394,10 @@ class H8536Emulator:
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target = self._vector_target(VECTOR_INTERVAL_TIMER)
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if target is not None:
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candidates.append((self._interval_priority(), target, "interval_timer"))
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if self._frt1_ocia_pending():
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target = self._vector_target(VECTOR_FRT1_OCIA)
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if target is not None:
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candidates.append((self._frt1_priority(), target, "frt1_ocia"))
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if self._frt2_ocia_pending():
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target = self._vector_target(VECTOR_FRT2_OCIA)
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if target is not None:
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@@ -399,6 +410,9 @@ class H8536Emulator:
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return
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if source == "interval_timer":
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self._interval_counter = 0
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elif source == "frt1_ocia":
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self._frt1_ocia_counter = 0
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self.memory.write8(FRT1_TCSR, self.memory.read8(FRT1_TCSR) | FRT_TCSR_OCFA)
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elif source == "frt2_ocia":
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self._frt2_ocia_counter = 0
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self.memory.write8(FRT2_TCSR, self.memory.read8(FRT2_TCSR) | FRT_TCSR_OCFA)
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@@ -430,6 +444,14 @@ class H8536Emulator:
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def _interval_priority(self) -> int:
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return (self.memory.read8(IPRA) >> 4) & 0x07
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def _frt1_ocia_pending(self) -> bool:
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if self._frt1_ocia_counter < self.frt1_ocia_steps:
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return False
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return bool(self.memory.read8(FRT1_TCR) & FRT_TCR_OCIEA)
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def _frt1_priority(self) -> int:
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return (self.memory.read8(IPRC) >> 4) & 0x07
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def _frt2_ocia_pending(self) -> bool:
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if self._frt2_ocia_counter < self.frt2_ocia_steps:
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return False
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