non-volatile storage emulation

tests/test_p9_bus.py

@@ -4,6 +4,55 @@ from h8536.emulator import MemoryMap, P9DDR, P9DR
 from h8536.emulator.peripherals import P9Bus
 
 
+def p9_start(bus: P9Bus) -> None:
+    bus.write_ddr(0x93)
+    bus.write_dr(0x80)
+    bus.write_dr(0x82)
+    bus.write_dr(0x02)
+    bus.write_dr(0x00)
+
+
+def p9_stop(bus: P9Bus) -> None:
+    bus.write_ddr(0x93)
+    bus.write_dr(0x00)
+    bus.write_dr(0x02)
+    bus.write_dr(0x82)
+    bus.write_dr(0x80)
+
+
+def p9_write_byte(bus: P9Bus, value: int) -> bool:
+    bus.write_ddr(0x93)
+    for bit_index in range(7, -1, -1):
+        bit = (value >> bit_index) & 1
+        low = 0x80 if bit else 0x00
+        bus.write_dr(low)
+        bus.write_dr(low | 0x02)
+        bus.write_dr(low)
+    bus.write_ddr(0x13)
+    bus.write_dr(bus.dr_latch | 0x02)
+    ack_low = not bool(bus.read_dr() & 0x80)
+    bus.write_dr(bus.dr_latch & ~0x02)
+    bus.write_ddr(0x93)
+    return ack_low
+
+
+def p9_read_byte(bus: P9Bus, *, master_ack: bool) -> int:
+    value = 0
+    bus.write_ddr(0x13)
+    for _ in range(8):
+        bus.write_dr(bus.dr_latch | 0x02)
+        value = (value << 1) | (1 if bus.read_dr() & 0x80 else 0)
+        bus.write_dr(bus.dr_latch & ~0x02)
+    bus.write_ddr(0x93)
+    if master_ack:
+        bus.write_dr(bus.dr_latch & ~0x80)
+    else:
+        bus.write_dr(bus.dr_latch | 0x80)
+    bus.write_dr(bus.dr_latch | 0x02)
+    bus.write_dr(bus.dr_latch & ~0x02)
+    return value
+
+
 class P9BusTest(unittest.TestCase):
     def test_bit7_input_uses_queued_then_default_low_response(self):
         memory = MemoryMap(b"\x00" * 4)
@@ -47,6 +96,44 @@ class P9BusTest(unittest.TestCase):
         self.assertIn("wrapper_result ddr=00 dr=00 value=01 success=1 source=panel-script queued=0", bus.trace_lines())
         self.assertIn("wrapper_result ddr=00 dr=00 value=00 success=0 source=default_timeout queued=0", bus.trace_lines())
 
+    def test_x24164_bit_banged_write_acknowledges_and_stores_data(self):
+        bus = P9Bus()
+
+        p9_start(bus)
+        self.assertTrue(p9_write_byte(bus, 0xA0))
+        self.assertTrue(p9_write_byte(bus, 0x12))
+        self.assertTrue(p9_write_byte(bus, 0x34))
+        p9_stop(bus)
+
+        device = bus.x24164_bus.devices[0]
+        self.assertEqual(device.read(0x12), 0x34)
+        self.assertTrue(any("x24164_write_data" in line and "addr=012" in line for line in bus.trace_lines()))
+
+    def test_x24164_bit_banged_random_read_uses_p91_p97_lines(self):
+        bus = P9Bus()
+        bus.x24164_bus.devices[0].write(0x12, 0xAB)
+
+        p9_start(bus)
+        self.assertTrue(p9_write_byte(bus, 0xA0))
+        self.assertTrue(p9_write_byte(bus, 0x12))
+        p9_start(bus)
+        self.assertTrue(p9_write_byte(bus, 0xA1))
+        self.assertEqual(p9_read_byte(bus, master_ack=False), 0xAB)
+        p9_stop(bus)
+
+        self.assertTrue(any("x24164_prepare_read" in line and "value=AB" in line for line in bus.trace_lines()))
+
+    def test_x24164_fast_word_mapping_matches_rom_address_banks(self):
+        bus = P9Bus()
+
+        self.assertTrue(bus.fast_write_word(0x0012, 0x3456))
+        self.assertTrue(bus.fast_write_word(0x0812, 0xABCD))
+
+        self.assertEqual(bus.fast_read_word(0x0012), (True, 0x3456))
+        self.assertEqual(bus.fast_read_word(0x0812), (True, 0xABCD))
+        self.assertEqual(bus.x24164_bus.devices[0].read(0x12), 0x34)
+        self.assertEqual(bus.x24164_bus.devices[1].read(0x12), 0xAB)
+
 
 if __name__ == "__main__":
     unittest.main()