1
0

EMualtor im

This commit is contained in:
Aiden
2026-05-25 18:43:36 +10:00
parent 81f5d7a150
commit 05e1237acc
18 changed files with 993 additions and 20 deletions

42
tests/test_p9_bus.py Normal file
View File

@@ -0,0 +1,42 @@
import unittest
from h8536.emulator import MemoryMap, P9DDR, P9DR
from h8536.emulator.peripherals import P9Bus
class P9BusTest(unittest.TestCase):
def test_bit7_input_uses_queued_then_default_low_response(self):
memory = MemoryMap(b"\x00" * 4)
memory.write8(P9DDR, 0x13)
memory.write8(P9DR, 0x80)
memory.p9_bus.queue_input_bits([1])
self.assertEqual(memory.read8(P9DDR), 0x13)
self.assertEqual(memory.read8(P9DR) & 0x80, 0x80)
self.assertEqual(memory.read8(P9DR) & 0x80, 0x00)
self.assertEqual(memory.registers[P9DR - 0xFE80], 0x80)
def test_bit7_output_reads_latch(self):
memory = MemoryMap(b"\x00" * 4)
memory.write8(P9DDR, 0x93)
memory.write8(P9DR, 0x80)
self.assertEqual(memory.read8(P9DDR), 0x93)
self.assertEqual(memory.read8(P9DR) & 0x80, 0x80)
self.assertEqual(memory.registers[P9DR - 0xFE80], 0x80)
def test_strobe_rising_edges_capture_output_bits_and_byte_candidates(self):
bus = P9Bus()
bus.write_ddr(0x93)
for bit in (1, 0, 1, 0, 0, 1, 0, 1):
bus.write_dr(0x80 if bit else 0x00)
bus.write_dr((0x80 if bit else 0x00) | 0x02)
bus.write_dr(0x80 if bit else 0x00)
self.assertEqual(bus.transmitted_bits, [1, 0, 1, 0, 0, 1, 0, 1])
self.assertEqual(bus.byte_candidates, [0xA5])
self.assertEqual([event.edge for event in bus.strobe_edges[:2]], ["rising", "falling"])
if __name__ == "__main__":
unittest.main()