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Aiden
2026-05-25 18:43:36 +10:00
parent 81f5d7a150
commit 05e1237acc
18 changed files with 993 additions and 20 deletions
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87
tests/test_emulator_fast_paths.py Normal file
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import unittest
from h8536.emulator.fast_paths import (
LOC_C08B_P9_WRITE_BYTE,
LOC_C0DB_P9_READ_BYTE,
P9FastPath,
P9FastPathConfig,
)
from h8536.emulator.runner import H8536Emulator
def rom_with_reset(*, reset: int = 0x1000, size: int = 0xD000) -> bytearray:
rom = bytearray([0xFF] * size)
rom[0:2] = reset.to_bytes(2, "big")
return rom
class P9FastPathTest(unittest.TestCase):
def test_disabled_fast_path_does_not_handle_known_pc(self):
emulator = H8536Emulator(bytes(rom_with_reset()))
emulator.cpu.pc = LOC_C08B_P9_WRITE_BYTE
fast_path = P9FastPath()
self.assertFalse(fast_path.try_handle(emulator))
self.assertEqual(emulator.cpu.pc, LOC_C08B_P9_WRITE_BYTE)
def test_c08b_write_byte_logs_r0_sets_success_and_returns_to_caller(self):
emulator = H8536Emulator(bytes(rom_with_reset()))
emulator.cpu.pc = LOC_C08B_P9_WRITE_BYTE
emulator.cpu.regs[0] = 0x12A5
emulator.cpu.regs[7] = 0xFE7E
emulator.cpu.c = True
emulator.cpu.v = True
emulator.memory.write16(0xFE7E, 0x3456)
fast_path = P9FastPath(P9FastPathConfig(enabled=True))
self.assertTrue(fast_path.try_handle(emulator))
self.assertEqual(fast_path.output_bytes, [0xA5])
self.assertEqual(fast_path.events[-1].kind, "write_byte")
self.assertEqual(fast_path.events[-1].value, 0xA5)
self.assertEqual(emulator.cpu.regs[0], 1)
self.assertEqual(emulator.cpu.pc, 0x3456)
self.assertEqual(emulator.cpu.regs[7], 0xFE80)
self.assertFalse(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertTrue(emulator.cpu.c)
self.assertEqual(emulator.cpu.steps, 1)
def test_c0db_read_byte_puts_queued_byte_in_r5_low_and_returns(self):
emulator = H8536Emulator(bytes(rom_with_reset()))
emulator.cpu.pc = LOC_C0DB_P9_READ_BYTE
emulator.cpu.regs[5] = 0xBE00
emulator.cpu.regs[7] = 0xFE7C
emulator.memory.write16(0xFE7C, 0x4567)
fast_path = P9FastPath(P9FastPathConfig(enabled=True), input_bytes=[0x3C])
self.assertTrue(fast_path.try_handle(emulator))
self.assertEqual(emulator.cpu.regs[5], 0xBE3C)
self.assertEqual(emulator.cpu.pc, 0x4567)
self.assertEqual(emulator.cpu.regs[7], 0xFE7E)
self.assertEqual(fast_path.events[-1].kind, "read_byte")
self.assertEqual(fast_path.events[-1].value, 0x3C)
self.assertFalse(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
def test_c0db_read_byte_uses_default_when_queue_is_empty(self):
emulator = H8536Emulator(bytes(rom_with_reset()))
emulator.cpu.pc = LOC_C0DB_P9_READ_BYTE
emulator.cpu.regs[7] = 0xFE80
emulator.memory.write16(0xFE80, 0x5678)
fast_path = P9FastPath(P9FastPathConfig(enabled=True, default_input_byte=0x81))
self.assertTrue(fast_path.try_handle(emulator))
self.assertEqual(emulator.cpu.regs[5], 0x0081)
self.assertEqual(emulator.cpu.pc, 0x5678)
self.assertFalse(emulator.cpu.z)
self.assertTrue(emulator.cpu.n)
if __name__ == "__main__":
unittest.main()

116
tests/test_emulator_flags.py Normal file
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import unittest
from h8536.emulator import H8536Emulator
def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1100) -> bytearray:
rom = bytearray([0xFF] * size)
rom[0:2] = reset.to_bytes(2, "big")
return rom
class EmulatorMovFlagTest(unittest.TestCase):
def test_mov_e_byte_zero_sets_z_for_beq_and_preserves_c(self):
rom = rom_with_reset()
rom[0x1000:0x1002] = b"\x50\x00" # MOV:E.B #H'00, R0
rom[0x1002:0x1004] = b"\x27\x02" # BEQ H'1006
rom[0x1004:0x1006] = b"\x51\x01" # MOV:E.B #H'01, R1
rom[0x1006:0x1008] = b"\x52\x02" # MOV:E.B #H'02, R2
emulator = H8536Emulator(bytes(rom))
emulator.cpu.c = True
emulator.cpu.v = True
emulator.step()
self.assertTrue(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertTrue(emulator.cpu.c)
emulator.run(max_steps=2)
self.assertEqual(emulator.cpu.regs[1], 0)
self.assertEqual(emulator.cpu.regs[2], 2)
self.assertEqual(emulator.cpu.pc, 0x1008)
def test_mov_e_byte_one_clears_z_for_beq_and_preserves_c(self):
rom = rom_with_reset()
rom[0x1000:0x1002] = b"\x50\x01" # MOV:E.B #H'01, R0
rom[0x1002:0x1004] = b"\x27\x02" # BEQ H'1006
rom[0x1004:0x1006] = b"\x51\x01" # MOV:E.B #H'01, R1
rom[0x1006:0x1008] = b"\x52\x02" # MOV:E.B #H'02, R2
emulator = H8536Emulator(bytes(rom))
emulator.cpu.c = True
emulator.cpu.v = True
emulator.step()
self.assertFalse(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertTrue(emulator.cpu.c)
emulator.run(max_steps=2)
self.assertEqual(emulator.cpu.regs[1], 1)
self.assertEqual(emulator.cpu.regs[2], 0)
self.assertEqual(emulator.cpu.pc, 0x1006)
def test_mov_i_word_immediate_sets_word_flags_and_preserves_c(self):
rom = rom_with_reset()
rom[0x1000:0x1003] = b"\x58\x80\x00" # MOV:I.W #H'8000, R0
rom[0x1003:0x1006] = b"\x59\x00\x00" # MOV:I.W #H'0000, R1
emulator = H8536Emulator(bytes(rom))
emulator.cpu.c = True
emulator.cpu.v = True
emulator.step()
self.assertEqual(emulator.cpu.regs[0], 0x8000)
self.assertFalse(emulator.cpu.z)
self.assertTrue(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertTrue(emulator.cpu.c)
emulator.step()
self.assertEqual(emulator.cpu.regs[1], 0)
self.assertTrue(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertTrue(emulator.cpu.c)
def test_mulxu_byte_immediate_writes_word_result_and_clears_carry(self):
rom = rom_with_reset()
rom[0x1000:0x1002] = b"\x53\x12" # MOV:E.B #H'12, R3
rom[0x1002:0x1005] = b"\x04\x10\xAB" # MULXU.B #H'10, R3
emulator = H8536Emulator(bytes(rom))
emulator.cpu.c = True
emulator.run(max_steps=2)
self.assertEqual(emulator.cpu.regs[3], 0x0120)
self.assertFalse(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertFalse(emulator.cpu.c)
def test_not_byte_memory_updates_logic_flags_and_preserves_carry(self):
rom = rom_with_reset()
rom[0x1000:0x1005] = b"\x15\xF6\x80\x15\x00" # NOT.B @H'F680, then NOP
emulator = H8536Emulator(bytes(rom))
emulator.memory.write8(0xF680, 0xFF)
emulator.cpu.c = True
emulator.cpu.v = True
emulator.step()
self.assertEqual(emulator.memory.read8(0xF680), 0x00)
self.assertTrue(emulator.cpu.z)
self.assertFalse(emulator.cpu.n)
self.assertFalse(emulator.cpu.v)
self.assertTrue(emulator.cpu.c)
if __name__ == "__main__":
unittest.main()

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tests/test_emulator_lcd.py Normal file
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import unittest
from h8536.emulator import MemoryMap
from h8536.emulator.peripherals import LCD_E_CLOCK_DATA, LCD_E_CLOCK_STATUS
class EmulatorLcdBusTest(unittest.TestCase):
def test_status_read_reports_ready_even_after_command_write(self):
memory = MemoryMap(b"\x00" * 4)
memory.write8(LCD_E_CLOCK_STATUS, 0x80)
self.assertEqual(memory.read8(LCD_E_CLOCK_STATUS), 0x00)
def test_data_read_returns_data_latch_defaulting_to_zero(self):
memory = MemoryMap(b"\x00" * 4)
self.assertEqual(memory.read8(LCD_E_CLOCK_DATA), 0x00)
memory.write8(LCD_E_CLOCK_DATA, 0x41)
self.assertEqual(memory.read8(LCD_E_CLOCK_DATA), 0x41)
if __name__ == "__main__":
unittest.main()

56
tests/test_emulator_probe.py Normal file
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import unittest
from h8536.emulator.probe import DEFAULT_WATCH_PCS, parse_watch_pc, run_probe
def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1100) -> bytearray:
rom = bytearray([0xFF] * size)
rom[0:2] = reset.to_bytes(2, "big")
return rom
class EmulatorProbeTest(unittest.TestCase):
def test_parse_watch_pc_accepts_h8_hex_forms(self):
self.assertEqual(parse_watch_pc("C08B"), 0xC08B)
self.assertEqual(parse_watch_pc("0xC08B"), 0xC08B)
self.assertEqual(parse_watch_pc("H'C08B"), 0xC08B)
def test_default_watch_pcs_include_bit_bang_transfer_path(self):
self.assertIn(0xC08B, DEFAULT_WATCH_PCS)
self.assertIn(0xC0DB, DEFAULT_WATCH_PCS)
self.assertIn(0xC121, DEFAULT_WATCH_PCS)
self.assertIn(0xBFE0, DEFAULT_WATCH_PCS)
self.assertIn(0xBFFE, DEFAULT_WATCH_PCS)
self.assertIn(0xC059, DEFAULT_WATCH_PCS)
def test_watch_snapshot_includes_bsr_return_address_on_stack(self):
rom = rom_with_reset()
rom[0x1000:0x1003] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
rom[0x1003:0x1005] = b"\x0E\x03" # BSR H'1008, return H'1005
rom[0x1005:0x1008] = b"\x59\x12\x34" # MOV:I.W #H'1234, R1
rom[0x1008] = 0x19 # RTS
report = run_probe(
bytes(rom),
max_steps=4,
interval_steps=512,
stop_on_tx=False,
p9_log_limit=8,
watch_pcs=(0x1008,),
watch_snapshot_limit=4,
watch_pc_limit=2,
watch_min_interval=0,
)
self.assertEqual(len(report.watch_snapshots), 1)
snapshot = report.watch_snapshots[0]
self.assertEqual(snapshot.pc, 0x1008)
self.assertEqual(snapshot.sp, 0xFE7E)
self.assertIn((0xFE7E, 0x1005), snapshot.stack_words)
self.assertIn((0x1005, 0x1003), snapshot.callers)
self.assertIn("H'1005<-H'1003", snapshot.line())
self.assertTrue(any("recent_watch_snapshots:" == line for line in report.lines()))
if __name__ == "__main__":
unittest.main()

78
tests/test_emulator_timers.py Normal file
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import unittest
from h8536.emulator import H8536Emulator, ON_CHIP_RAM_START
from h8536.emulator.constants import (
FRT_TCR_OCIEA,
FRT_TCSR_OCFA,
FRT2_TCR,
FRT2_TCSR,
IPRC,
VECTOR_FRT2_OCIA,
)
def rom_with_reset(*, reset: int = 0x1000, size: int = 0x1040) -> bytearray:
rom = bytearray([0xFF] * size)
rom[0:2] = reset.to_bytes(2, "big")
return rom
def write_mov_b_abs_imm(rom: bytearray, address: int, target: int, value: int) -> int:
rom[address : address + 5] = bytes([0x15, (target >> 8) & 0xFF, target & 0xFF, 0x06, value & 0xFF])
return address + 5
class Frt2OciaTimerTest(unittest.TestCase):
def test_frt2_ocia_vector_can_fire_and_decrement_ram(self):
rom = rom_with_reset()
rom[VECTOR_FRT2_OCIA : VECTOR_FRT2_OCIA + 2] = (0x1020).to_bytes(2, "big")
pc = 0x1000
rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
pc += 3
# IPRC bits 6..4 are FRT1 and bits 2..0 are FRT2, so H'06 makes
# only the FRT2 priority field high enough to pass interrupt mask 0.
pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x06)
pc = write_mov_b_abs_imm(rom, pc, FRT2_TCR, FRT_TCR_OCIEA)
rom[pc : pc + 2] = b"\x20\xFE" # BRA self
isr = 0x1020
rom[isr : isr + 4] = bytes([0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C])
isr += 4
rom[isr : isr + 4] = bytes([0x15, (FRT2_TCSR >> 8) & 0xFF, FRT2_TCSR & 0xFF, 0xD5])
rom[isr + 4] = 0x0A # RTE
emulator = H8536Emulator(bytes(rom), frt2_ocia_steps=2)
emulator.memory.write8(ON_CHIP_RAM_START, 3)
emulator.run(max_steps=5)
self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 2)
self.assertFalse(emulator.memory.read8(FRT2_TCSR) & FRT_TCSR_OCFA)
self.assertEqual(emulator.cpu.pc, isr + 4)
def test_frt2_ocia_does_not_fire_when_ociea_disabled(self):
rom = rom_with_reset()
rom[VECTOR_FRT2_OCIA : VECTOR_FRT2_OCIA + 2] = (0x1020).to_bytes(2, "big")
pc = 0x1000
rom[pc : pc + 3] = b"\x5F\xFE\x80" # MOV:I.W #H'FE80, R7
pc += 3
pc = write_mov_b_abs_imm(rom, pc, IPRC, 0x06)
rom[pc : pc + 2] = b"\x20\xFE" # BRA self
rom[0x1020 : 0x1024] = bytes(
[0x15, (ON_CHIP_RAM_START >> 8) & 0xFF, ON_CHIP_RAM_START & 0xFF, 0x0C]
)
rom[0x1024] = 0x0A # RTE
emulator = H8536Emulator(bytes(rom), frt2_ocia_steps=1)
emulator.memory.write8(ON_CHIP_RAM_START, 3)
emulator.run(max_steps=8)
self.assertEqual(emulator.memory.read8(ON_CHIP_RAM_START), 3)
self.assertEqual(emulator.memory.read8(FRT2_TCSR) & FRT_TCSR_OCFA, 0)
self.assertEqual(emulator.cpu.pc, pc)
if __name__ == "__main__":
unittest.main()

42
tests/test_p9_bus.py Normal file
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import unittest
from h8536.emulator import MemoryMap, P9DDR, P9DR
from h8536.emulator.peripherals import P9Bus
class P9BusTest(unittest.TestCase):
def test_bit7_input_uses_queued_then_default_low_response(self):
memory = MemoryMap(b"\x00" * 4)
memory.write8(P9DDR, 0x13)
memory.write8(P9DR, 0x80)
memory.p9_bus.queue_input_bits([1])
self.assertEqual(memory.read8(P9DDR), 0x13)
self.assertEqual(memory.read8(P9DR) & 0x80, 0x80)
self.assertEqual(memory.read8(P9DR) & 0x80, 0x00)
self.assertEqual(memory.registers[P9DR - 0xFE80], 0x80)
def test_bit7_output_reads_latch(self):
memory = MemoryMap(b"\x00" * 4)
memory.write8(P9DDR, 0x93)
memory.write8(P9DR, 0x80)
self.assertEqual(memory.read8(P9DDR), 0x93)
self.assertEqual(memory.read8(P9DR) & 0x80, 0x80)
self.assertEqual(memory.registers[P9DR - 0xFE80], 0x80)
def test_strobe_rising_edges_capture_output_bits_and_byte_candidates(self):
bus = P9Bus()
bus.write_ddr(0x93)
for bit in (1, 0, 1, 0, 0, 1, 0, 1):
bus.write_dr(0x80 if bit else 0x00)
bus.write_dr((0x80 if bit else 0x00) | 0x02)
bus.write_dr(0x80 if bit else 0x00)
self.assertEqual(bus.transmitted_bits, [1, 0, 1, 0, 0, 1, 0, 1])
self.assertEqual(bus.byte_candidates, [0xA5])
self.assertEqual([event.edge for event in bus.strobe_edges[:2]], ["rising", "falling"])
if __name__ == "__main__":
unittest.main()